mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_usart.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 184:08ed48f1de7f
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | ****************************************************************************** |
<> | 149:156823d33999 | 3 | * @file stm32l1xx_ll_usart.c |
<> | 149:156823d33999 | 4 | * @author MCD Application Team |
<> | 149:156823d33999 | 5 | * @brief USART LL module driver. |
<> | 149:156823d33999 | 6 | ****************************************************************************** |
<> | 149:156823d33999 | 7 | * @attention |
<> | 149:156823d33999 | 8 | * |
AnnaBridge | 184:08ed48f1de7f | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 149:156823d33999 | 10 | * |
<> | 149:156823d33999 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 149:156823d33999 | 12 | * are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 149:156823d33999 | 14 | * this list of conditions and the following disclaimer. |
<> | 149:156823d33999 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 149:156823d33999 | 16 | * this list of conditions and the following disclaimer in the documentation |
<> | 149:156823d33999 | 17 | * and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 149:156823d33999 | 19 | * may be used to endorse or promote products derived from this software |
<> | 149:156823d33999 | 20 | * without specific prior written permission. |
<> | 149:156823d33999 | 21 | * |
<> | 149:156823d33999 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 149:156823d33999 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 149:156823d33999 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 149:156823d33999 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 149:156823d33999 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 149:156823d33999 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 149:156823d33999 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 149:156823d33999 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 149:156823d33999 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 149:156823d33999 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 32 | * |
<> | 149:156823d33999 | 33 | ****************************************************************************** |
<> | 149:156823d33999 | 34 | */ |
<> | 149:156823d33999 | 35 | #if defined(USE_FULL_LL_DRIVER) |
<> | 149:156823d33999 | 36 | |
<> | 149:156823d33999 | 37 | /* Includes ------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 38 | #include "stm32l1xx_ll_usart.h" |
<> | 149:156823d33999 | 39 | #include "stm32l1xx_ll_rcc.h" |
<> | 149:156823d33999 | 40 | #include "stm32l1xx_ll_bus.h" |
<> | 149:156823d33999 | 41 | #ifdef USE_FULL_ASSERT |
<> | 149:156823d33999 | 42 | #include "stm32_assert.h" |
<> | 149:156823d33999 | 43 | #else |
<> | 149:156823d33999 | 44 | #define assert_param(expr) ((void)0U) |
<> | 149:156823d33999 | 45 | #endif |
<> | 149:156823d33999 | 46 | |
<> | 149:156823d33999 | 47 | /** @addtogroup STM32L1xx_LL_Driver |
<> | 149:156823d33999 | 48 | * @{ |
<> | 149:156823d33999 | 49 | */ |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) |
<> | 149:156823d33999 | 52 | |
<> | 149:156823d33999 | 53 | /** @addtogroup USART_LL |
<> | 149:156823d33999 | 54 | * @{ |
<> | 149:156823d33999 | 55 | */ |
<> | 149:156823d33999 | 56 | |
<> | 149:156823d33999 | 57 | /* Private types -------------------------------------------------------------*/ |
<> | 149:156823d33999 | 58 | /* Private variables ---------------------------------------------------------*/ |
<> | 149:156823d33999 | 59 | /* Private constants ---------------------------------------------------------*/ |
<> | 149:156823d33999 | 60 | /** @addtogroup USART_LL_Private_Constants |
<> | 149:156823d33999 | 61 | * @{ |
<> | 149:156823d33999 | 62 | */ |
<> | 149:156823d33999 | 63 | |
<> | 149:156823d33999 | 64 | /** |
<> | 149:156823d33999 | 65 | * @} |
<> | 149:156823d33999 | 66 | */ |
<> | 149:156823d33999 | 67 | |
<> | 149:156823d33999 | 68 | |
<> | 149:156823d33999 | 69 | /* Private macros ------------------------------------------------------------*/ |
<> | 149:156823d33999 | 70 | /** @addtogroup USART_LL_Private_Macros |
<> | 149:156823d33999 | 71 | * @{ |
<> | 149:156823d33999 | 72 | */ |
<> | 149:156823d33999 | 73 | |
<> | 149:156823d33999 | 74 | /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available |
<> | 149:156823d33999 | 75 | * divided by the smallest oversampling used on the USART (i.e. 8) */ |
<> | 149:156823d33999 | 76 | #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) |
<> | 149:156823d33999 | 77 | |
<> | 149:156823d33999 | 78 | #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ |
<> | 149:156823d33999 | 79 | || ((__VALUE__) == LL_USART_DIRECTION_RX) \ |
<> | 149:156823d33999 | 80 | || ((__VALUE__) == LL_USART_DIRECTION_TX) \ |
<> | 149:156823d33999 | 81 | || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) |
<> | 149:156823d33999 | 82 | |
<> | 149:156823d33999 | 83 | #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ |
<> | 149:156823d33999 | 84 | || ((__VALUE__) == LL_USART_PARITY_EVEN) \ |
<> | 149:156823d33999 | 85 | || ((__VALUE__) == LL_USART_PARITY_ODD)) |
<> | 149:156823d33999 | 86 | |
<> | 149:156823d33999 | 87 | #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ |
<> | 149:156823d33999 | 88 | || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) |
<> | 149:156823d33999 | 89 | |
<> | 149:156823d33999 | 90 | #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ |
<> | 149:156823d33999 | 91 | || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) |
<> | 149:156823d33999 | 92 | |
<> | 149:156823d33999 | 93 | #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ |
<> | 149:156823d33999 | 94 | || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) |
<> | 149:156823d33999 | 95 | |
<> | 149:156823d33999 | 96 | #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ |
<> | 149:156823d33999 | 97 | || ((__VALUE__) == LL_USART_PHASE_2EDGE)) |
<> | 149:156823d33999 | 98 | |
<> | 149:156823d33999 | 99 | #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ |
<> | 149:156823d33999 | 100 | || ((__VALUE__) == LL_USART_POLARITY_HIGH)) |
<> | 149:156823d33999 | 101 | |
<> | 149:156823d33999 | 102 | #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ |
<> | 149:156823d33999 | 103 | || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) |
<> | 149:156823d33999 | 104 | |
<> | 149:156823d33999 | 105 | #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ |
<> | 149:156823d33999 | 106 | || ((__VALUE__) == LL_USART_STOPBITS_1) \ |
<> | 149:156823d33999 | 107 | || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ |
<> | 149:156823d33999 | 108 | || ((__VALUE__) == LL_USART_STOPBITS_2)) |
<> | 149:156823d33999 | 109 | |
<> | 149:156823d33999 | 110 | #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ |
<> | 149:156823d33999 | 111 | || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ |
<> | 149:156823d33999 | 112 | || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ |
<> | 149:156823d33999 | 113 | || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) |
<> | 149:156823d33999 | 114 | |
<> | 149:156823d33999 | 115 | /** |
<> | 149:156823d33999 | 116 | * @} |
<> | 149:156823d33999 | 117 | */ |
<> | 149:156823d33999 | 118 | |
<> | 149:156823d33999 | 119 | /* Private function prototypes -----------------------------------------------*/ |
<> | 149:156823d33999 | 120 | |
<> | 149:156823d33999 | 121 | /* Exported functions --------------------------------------------------------*/ |
<> | 149:156823d33999 | 122 | /** @addtogroup USART_LL_Exported_Functions |
<> | 149:156823d33999 | 123 | * @{ |
<> | 149:156823d33999 | 124 | */ |
<> | 149:156823d33999 | 125 | |
<> | 149:156823d33999 | 126 | /** @addtogroup USART_LL_EF_Init |
<> | 149:156823d33999 | 127 | * @{ |
<> | 149:156823d33999 | 128 | */ |
<> | 149:156823d33999 | 129 | |
<> | 149:156823d33999 | 130 | /** |
<> | 149:156823d33999 | 131 | * @brief De-initialize USART registers (Registers restored to their default values). |
<> | 149:156823d33999 | 132 | * @param USARTx USART Instance |
<> | 149:156823d33999 | 133 | * @retval An ErrorStatus enumeration value: |
<> | 149:156823d33999 | 134 | * - SUCCESS: USART registers are de-initialized |
<> | 149:156823d33999 | 135 | * - ERROR: USART registers are not de-initialized |
<> | 149:156823d33999 | 136 | */ |
<> | 149:156823d33999 | 137 | ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) |
<> | 149:156823d33999 | 138 | { |
<> | 149:156823d33999 | 139 | ErrorStatus status = SUCCESS; |
<> | 149:156823d33999 | 140 | |
<> | 149:156823d33999 | 141 | /* Check the parameters */ |
<> | 149:156823d33999 | 142 | assert_param(IS_UART_INSTANCE(USARTx)); |
<> | 149:156823d33999 | 143 | |
<> | 149:156823d33999 | 144 | if (USARTx == USART1) |
<> | 149:156823d33999 | 145 | { |
<> | 149:156823d33999 | 146 | /* Force reset of USART clock */ |
<> | 149:156823d33999 | 147 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); |
<> | 149:156823d33999 | 148 | |
<> | 149:156823d33999 | 149 | /* Release reset of USART clock */ |
<> | 149:156823d33999 | 150 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); |
<> | 149:156823d33999 | 151 | } |
<> | 149:156823d33999 | 152 | else if (USARTx == USART2) |
<> | 149:156823d33999 | 153 | { |
<> | 149:156823d33999 | 154 | /* Force reset of USART clock */ |
<> | 149:156823d33999 | 155 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); |
<> | 149:156823d33999 | 156 | |
<> | 149:156823d33999 | 157 | /* Release reset of USART clock */ |
<> | 149:156823d33999 | 158 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); |
<> | 149:156823d33999 | 159 | } |
<> | 149:156823d33999 | 160 | else if (USARTx == USART3) |
<> | 149:156823d33999 | 161 | { |
<> | 149:156823d33999 | 162 | /* Force reset of USART clock */ |
<> | 149:156823d33999 | 163 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); |
<> | 149:156823d33999 | 164 | |
<> | 149:156823d33999 | 165 | /* Release reset of USART clock */ |
<> | 149:156823d33999 | 166 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); |
<> | 149:156823d33999 | 167 | } |
<> | 149:156823d33999 | 168 | #if defined(UART4) |
<> | 149:156823d33999 | 169 | else if (USARTx == UART4) |
<> | 149:156823d33999 | 170 | { |
<> | 149:156823d33999 | 171 | /* Force reset of UART clock */ |
<> | 149:156823d33999 | 172 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); |
<> | 149:156823d33999 | 173 | |
<> | 149:156823d33999 | 174 | /* Release reset of UART clock */ |
<> | 149:156823d33999 | 175 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); |
<> | 149:156823d33999 | 176 | } |
<> | 149:156823d33999 | 177 | #endif /* UART4 */ |
<> | 149:156823d33999 | 178 | #if defined(UART5) |
<> | 149:156823d33999 | 179 | else if (USARTx == UART5) |
<> | 149:156823d33999 | 180 | { |
<> | 149:156823d33999 | 181 | /* Force reset of UART clock */ |
<> | 149:156823d33999 | 182 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); |
<> | 149:156823d33999 | 183 | |
<> | 149:156823d33999 | 184 | /* Release reset of UART clock */ |
<> | 149:156823d33999 | 185 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); |
<> | 149:156823d33999 | 186 | } |
<> | 149:156823d33999 | 187 | #endif /* UART5 */ |
<> | 149:156823d33999 | 188 | else |
<> | 149:156823d33999 | 189 | { |
<> | 149:156823d33999 | 190 | status = ERROR; |
<> | 149:156823d33999 | 191 | } |
<> | 149:156823d33999 | 192 | |
<> | 149:156823d33999 | 193 | return (status); |
<> | 149:156823d33999 | 194 | } |
<> | 149:156823d33999 | 195 | |
<> | 149:156823d33999 | 196 | /** |
<> | 149:156823d33999 | 197 | * @brief Initialize USART registers according to the specified |
<> | 149:156823d33999 | 198 | * parameters in USART_InitStruct. |
<> | 149:156823d33999 | 199 | * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), |
<> | 149:156823d33999 | 200 | * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. |
<> | 149:156823d33999 | 201 | * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). |
<> | 149:156823d33999 | 202 | * @param USARTx USART Instance |
<> | 149:156823d33999 | 203 | * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure |
<> | 149:156823d33999 | 204 | * that contains the configuration information for the specified USART peripheral. |
<> | 149:156823d33999 | 205 | * @retval An ErrorStatus enumeration value: |
<> | 149:156823d33999 | 206 | * - SUCCESS: USART registers are initialized according to USART_InitStruct content |
<> | 149:156823d33999 | 207 | * - ERROR: Problem occurred during USART Registers initialization |
<> | 149:156823d33999 | 208 | */ |
<> | 149:156823d33999 | 209 | ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) |
<> | 149:156823d33999 | 210 | { |
<> | 149:156823d33999 | 211 | ErrorStatus status = ERROR; |
<> | 149:156823d33999 | 212 | uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; |
<> | 149:156823d33999 | 213 | LL_RCC_ClocksTypeDef rcc_clocks; |
<> | 149:156823d33999 | 214 | |
<> | 149:156823d33999 | 215 | /* Check the parameters */ |
<> | 149:156823d33999 | 216 | assert_param(IS_UART_INSTANCE(USARTx)); |
<> | 149:156823d33999 | 217 | assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); |
<> | 149:156823d33999 | 218 | assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); |
<> | 149:156823d33999 | 219 | assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); |
<> | 149:156823d33999 | 220 | assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); |
<> | 149:156823d33999 | 221 | assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); |
<> | 149:156823d33999 | 222 | assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); |
<> | 149:156823d33999 | 223 | assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); |
<> | 149:156823d33999 | 224 | |
<> | 149:156823d33999 | 225 | /* USART needs to be in disabled state, in order to be able to configure some bits in |
<> | 149:156823d33999 | 226 | CRx registers */ |
<> | 149:156823d33999 | 227 | if (LL_USART_IsEnabled(USARTx) == 0U) |
<> | 149:156823d33999 | 228 | { |
<> | 149:156823d33999 | 229 | /*---------------------------- USART CR1 Configuration ----------------------- |
<> | 149:156823d33999 | 230 | * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: |
<> | 149:156823d33999 | 231 | * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value |
<> | 149:156823d33999 | 232 | * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value |
<> | 149:156823d33999 | 233 | * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value |
<> | 149:156823d33999 | 234 | * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. |
<> | 149:156823d33999 | 235 | */ |
<> | 149:156823d33999 | 236 | MODIFY_REG(USARTx->CR1, |
<> | 149:156823d33999 | 237 | (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | |
<> | 149:156823d33999 | 238 | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), |
<> | 149:156823d33999 | 239 | (USART_InitStruct->DataWidth | USART_InitStruct->Parity | |
<> | 149:156823d33999 | 240 | USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); |
<> | 149:156823d33999 | 241 | |
<> | 149:156823d33999 | 242 | /*---------------------------- USART CR2 Configuration ----------------------- |
<> | 149:156823d33999 | 243 | * Configure USARTx CR2 (Stop bits) with parameters: |
<> | 149:156823d33999 | 244 | * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. |
<> | 149:156823d33999 | 245 | * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). |
<> | 149:156823d33999 | 246 | */ |
<> | 149:156823d33999 | 247 | LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); |
<> | 149:156823d33999 | 248 | |
<> | 149:156823d33999 | 249 | /*---------------------------- USART CR3 Configuration ----------------------- |
<> | 149:156823d33999 | 250 | * Configure USARTx CR3 (Hardware Flow Control) with parameters: |
<> | 149:156823d33999 | 251 | * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. |
<> | 149:156823d33999 | 252 | */ |
<> | 149:156823d33999 | 253 | LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); |
<> | 149:156823d33999 | 254 | |
<> | 149:156823d33999 | 255 | /*---------------------------- USART BRR Configuration ----------------------- |
<> | 149:156823d33999 | 256 | * Retrieve Clock frequency used for USART Peripheral |
<> | 149:156823d33999 | 257 | */ |
<> | 149:156823d33999 | 258 | LL_RCC_GetSystemClocksFreq(&rcc_clocks); |
<> | 149:156823d33999 | 259 | if (USARTx == USART1) |
<> | 149:156823d33999 | 260 | { |
<> | 149:156823d33999 | 261 | periphclk = rcc_clocks.PCLK2_Frequency; |
<> | 149:156823d33999 | 262 | } |
<> | 149:156823d33999 | 263 | else if (USARTx == USART2) |
<> | 149:156823d33999 | 264 | { |
<> | 149:156823d33999 | 265 | periphclk = rcc_clocks.PCLK1_Frequency; |
<> | 149:156823d33999 | 266 | } |
<> | 149:156823d33999 | 267 | else if (USARTx == USART3) |
<> | 149:156823d33999 | 268 | { |
<> | 149:156823d33999 | 269 | periphclk = rcc_clocks.PCLK1_Frequency; |
<> | 149:156823d33999 | 270 | } |
<> | 149:156823d33999 | 271 | #if defined(UART4) |
<> | 149:156823d33999 | 272 | else if (USARTx == UART4) |
<> | 149:156823d33999 | 273 | { |
<> | 149:156823d33999 | 274 | periphclk = rcc_clocks.PCLK1_Frequency; |
<> | 149:156823d33999 | 275 | } |
<> | 149:156823d33999 | 276 | #endif /* UART4 */ |
<> | 149:156823d33999 | 277 | #if defined(UART5) |
<> | 149:156823d33999 | 278 | else if (USARTx == UART5) |
<> | 149:156823d33999 | 279 | { |
<> | 149:156823d33999 | 280 | periphclk = rcc_clocks.PCLK1_Frequency; |
<> | 149:156823d33999 | 281 | } |
<> | 149:156823d33999 | 282 | #endif /* UART5 */ |
<> | 149:156823d33999 | 283 | else |
<> | 149:156823d33999 | 284 | { |
<> | 149:156823d33999 | 285 | /* Nothing to do, as error code is already assigned to ERROR value */ |
<> | 149:156823d33999 | 286 | } |
<> | 149:156823d33999 | 287 | |
<> | 149:156823d33999 | 288 | /* Configure the USART Baud Rate : |
<> | 149:156823d33999 | 289 | - valid baud rate value (different from 0) is required |
<> | 149:156823d33999 | 290 | - Peripheral clock as returned by RCC service, should be valid (different from 0). |
<> | 149:156823d33999 | 291 | */ |
<> | 149:156823d33999 | 292 | if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) |
<> | 149:156823d33999 | 293 | && (USART_InitStruct->BaudRate != 0U)) |
<> | 149:156823d33999 | 294 | { |
<> | 149:156823d33999 | 295 | status = SUCCESS; |
<> | 149:156823d33999 | 296 | LL_USART_SetBaudRate(USARTx, |
<> | 149:156823d33999 | 297 | periphclk, |
<> | 149:156823d33999 | 298 | USART_InitStruct->OverSampling, |
<> | 149:156823d33999 | 299 | USART_InitStruct->BaudRate); |
<> | 149:156823d33999 | 300 | } |
<> | 149:156823d33999 | 301 | } |
<> | 149:156823d33999 | 302 | /* Endif (=> USART not in Disabled state => return ERROR) */ |
<> | 149:156823d33999 | 303 | |
<> | 149:156823d33999 | 304 | return (status); |
<> | 149:156823d33999 | 305 | } |
<> | 149:156823d33999 | 306 | |
<> | 149:156823d33999 | 307 | /** |
<> | 149:156823d33999 | 308 | * @brief Set each @ref LL_USART_InitTypeDef field to default value. |
<> | 149:156823d33999 | 309 | * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure |
<> | 149:156823d33999 | 310 | * whose fields will be set to default values. |
<> | 149:156823d33999 | 311 | * @retval None |
<> | 149:156823d33999 | 312 | */ |
<> | 149:156823d33999 | 313 | |
<> | 149:156823d33999 | 314 | void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) |
<> | 149:156823d33999 | 315 | { |
<> | 149:156823d33999 | 316 | /* Set USART_InitStruct fields to default values */ |
<> | 149:156823d33999 | 317 | USART_InitStruct->BaudRate = 9600U; |
<> | 149:156823d33999 | 318 | USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; |
<> | 149:156823d33999 | 319 | USART_InitStruct->StopBits = LL_USART_STOPBITS_1; |
<> | 149:156823d33999 | 320 | USART_InitStruct->Parity = LL_USART_PARITY_NONE ; |
<> | 149:156823d33999 | 321 | USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; |
<> | 149:156823d33999 | 322 | USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; |
<> | 149:156823d33999 | 323 | USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; |
<> | 149:156823d33999 | 324 | } |
<> | 149:156823d33999 | 325 | |
<> | 149:156823d33999 | 326 | /** |
<> | 149:156823d33999 | 327 | * @brief Initialize USART Clock related settings according to the |
<> | 149:156823d33999 | 328 | * specified parameters in the USART_ClockInitStruct. |
<> | 149:156823d33999 | 329 | * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), |
<> | 149:156823d33999 | 330 | * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. |
<> | 149:156823d33999 | 331 | * @param USARTx USART Instance |
<> | 149:156823d33999 | 332 | * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure |
<> | 149:156823d33999 | 333 | * that contains the Clock configuration information for the specified USART peripheral. |
<> | 149:156823d33999 | 334 | * @retval An ErrorStatus enumeration value: |
<> | 149:156823d33999 | 335 | * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content |
<> | 149:156823d33999 | 336 | * - ERROR: Problem occurred during USART Registers initialization |
<> | 149:156823d33999 | 337 | */ |
<> | 149:156823d33999 | 338 | ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) |
<> | 149:156823d33999 | 339 | { |
<> | 149:156823d33999 | 340 | ErrorStatus status = SUCCESS; |
<> | 149:156823d33999 | 341 | |
<> | 149:156823d33999 | 342 | /* Check USART Instance and Clock signal output parameters */ |
<> | 149:156823d33999 | 343 | assert_param(IS_UART_INSTANCE(USARTx)); |
<> | 149:156823d33999 | 344 | assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); |
<> | 149:156823d33999 | 345 | |
<> | 149:156823d33999 | 346 | /* USART needs to be in disabled state, in order to be able to configure some bits in |
<> | 149:156823d33999 | 347 | CRx registers */ |
<> | 149:156823d33999 | 348 | if (LL_USART_IsEnabled(USARTx) == 0U) |
<> | 149:156823d33999 | 349 | { |
<> | 149:156823d33999 | 350 | /*---------------------------- USART CR2 Configuration -----------------------*/ |
<> | 149:156823d33999 | 351 | /* If Clock signal has to be output */ |
<> | 149:156823d33999 | 352 | if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) |
<> | 149:156823d33999 | 353 | { |
<> | 149:156823d33999 | 354 | /* Deactivate Clock signal delivery : |
<> | 149:156823d33999 | 355 | * - Disable Clock Output: USART_CR2_CLKEN cleared |
<> | 149:156823d33999 | 356 | */ |
<> | 149:156823d33999 | 357 | LL_USART_DisableSCLKOutput(USARTx); |
<> | 149:156823d33999 | 358 | } |
<> | 149:156823d33999 | 359 | else |
<> | 149:156823d33999 | 360 | { |
<> | 149:156823d33999 | 361 | /* Ensure USART instance is USART capable */ |
<> | 149:156823d33999 | 362 | assert_param(IS_USART_INSTANCE(USARTx)); |
<> | 149:156823d33999 | 363 | |
<> | 149:156823d33999 | 364 | /* Check clock related parameters */ |
<> | 149:156823d33999 | 365 | assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); |
<> | 149:156823d33999 | 366 | assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); |
<> | 149:156823d33999 | 367 | assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); |
<> | 149:156823d33999 | 368 | |
<> | 149:156823d33999 | 369 | /*---------------------------- USART CR2 Configuration ----------------------- |
<> | 149:156823d33999 | 370 | * Configure USARTx CR2 (Clock signal related bits) with parameters: |
<> | 149:156823d33999 | 371 | * - Enable Clock Output: USART_CR2_CLKEN set |
<> | 149:156823d33999 | 372 | * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value |
<> | 149:156823d33999 | 373 | * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value |
<> | 149:156823d33999 | 374 | * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. |
<> | 149:156823d33999 | 375 | */ |
<> | 149:156823d33999 | 376 | MODIFY_REG(USARTx->CR2, |
<> | 149:156823d33999 | 377 | USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, |
<> | 149:156823d33999 | 378 | USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | |
<> | 149:156823d33999 | 379 | USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); |
<> | 149:156823d33999 | 380 | } |
<> | 149:156823d33999 | 381 | } |
<> | 149:156823d33999 | 382 | /* Else (USART not in Disabled state => return ERROR */ |
<> | 149:156823d33999 | 383 | else |
<> | 149:156823d33999 | 384 | { |
<> | 149:156823d33999 | 385 | status = ERROR; |
<> | 149:156823d33999 | 386 | } |
<> | 149:156823d33999 | 387 | |
<> | 149:156823d33999 | 388 | return (status); |
<> | 149:156823d33999 | 389 | } |
<> | 149:156823d33999 | 390 | |
<> | 149:156823d33999 | 391 | /** |
<> | 149:156823d33999 | 392 | * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. |
<> | 149:156823d33999 | 393 | * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure |
<> | 149:156823d33999 | 394 | * whose fields will be set to default values. |
<> | 149:156823d33999 | 395 | * @retval None |
<> | 149:156823d33999 | 396 | */ |
<> | 149:156823d33999 | 397 | void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) |
<> | 149:156823d33999 | 398 | { |
<> | 149:156823d33999 | 399 | /* Set LL_USART_ClockInitStruct fields with default values */ |
<> | 149:156823d33999 | 400 | USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; |
<> | 149:156823d33999 | 401 | USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ |
<> | 149:156823d33999 | 402 | USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ |
<> | 149:156823d33999 | 403 | USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ |
<> | 149:156823d33999 | 404 | } |
<> | 149:156823d33999 | 405 | |
<> | 149:156823d33999 | 406 | /** |
<> | 149:156823d33999 | 407 | * @} |
<> | 149:156823d33999 | 408 | */ |
<> | 149:156823d33999 | 409 | |
<> | 149:156823d33999 | 410 | /** |
<> | 149:156823d33999 | 411 | * @} |
<> | 149:156823d33999 | 412 | */ |
<> | 149:156823d33999 | 413 | |
<> | 149:156823d33999 | 414 | /** |
<> | 149:156823d33999 | 415 | * @} |
<> | 149:156823d33999 | 416 | */ |
<> | 149:156823d33999 | 417 | |
<> | 149:156823d33999 | 418 | #endif /* USART1 || USART2|| USART3 || UART4 || UART5 */ |
<> | 149:156823d33999 | 419 | |
<> | 149:156823d33999 | 420 | /** |
<> | 149:156823d33999 | 421 | * @} |
<> | 149:156823d33999 | 422 | */ |
<> | 149:156823d33999 | 423 | |
<> | 149:156823d33999 | 424 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 149:156823d33999 | 425 | |
<> | 149:156823d33999 | 426 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
<> | 149:156823d33999 | 427 |