mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 184:08ed48f1de7f

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_ll_tim.h
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @brief Header file of TIM LL module.
<>	149:156823d33999	6	******************************************************************************
<>	149:156823d33999	7	* @attention
<>	149:156823d33999	8	*
AnnaBridge	184:08ed48f1de7f	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	149:156823d33999	10	*
<>	149:156823d33999	11	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	12	* are permitted provided that the following conditions are met:
<>	149:156823d33999	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	14	* this list of conditions and the following disclaimer.
<>	149:156823d33999	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	16	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	17	* and/or other materials provided with the distribution.
<>	149:156823d33999	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	19	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	20	* without specific prior written permission.
<>	149:156823d33999	21	*
<>	149:156823d33999	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	32	*
<>	149:156823d33999	33	******************************************************************************
<>	149:156823d33999	34	*/
<>	149:156823d33999	35
<>	149:156823d33999	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	149:156823d33999	37	#ifndef __STM32L1xx_LL_TIM_H
<>	149:156823d33999	38	#define __STM32L1xx_LL_TIM_H
<>	149:156823d33999	39
<>	149:156823d33999	40	#ifdef __cplusplus
<>	149:156823d33999	41	extern "C" {
<>	149:156823d33999	42	#endif
<>	149:156823d33999	43
<>	149:156823d33999	44	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	45	#include "stm32l1xx.h"
<>	149:156823d33999	46
<>	149:156823d33999	47	/** @addtogroup STM32L1xx_LL_Driver
<>	149:156823d33999	48	* @{
<>	149:156823d33999	49	*/
<>	149:156823d33999	50
<>	149:156823d33999	51	#if defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM6) \|\| defined (TIM7)
<>	149:156823d33999	52
<>	149:156823d33999	53	/** @defgroup TIM_LL TIM
<>	149:156823d33999	54	* @{
<>	149:156823d33999	55	*/
<>	149:156823d33999	56
<>	149:156823d33999	57	/* Private types -------------------------------------------------------------*/
<>	149:156823d33999	58	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
<>	149:156823d33999	60	* @{
<>	149:156823d33999	61	*/
<>	149:156823d33999	62	static const uint8_t OFFSET_TAB_CCMRx[] =
<>	149:156823d33999	63	{
<>	149:156823d33999	64	0x00U, /* 0: TIMx_CH1 */
<>	149:156823d33999	65	0x00U, /* 1: NA */
<>	149:156823d33999	66	0x00U, /* 2: TIMx_CH2 */
<>	149:156823d33999	67	0x00U, /* 3: NA */
<>	149:156823d33999	68	0x04U, /* 4: TIMx_CH3 */
<>	149:156823d33999	69	0x00U, /* 5: NA */
<>	149:156823d33999	70	0x04U /* 6: TIMx_CH4 */
<>	149:156823d33999	71	};
<>	149:156823d33999	72
<>	149:156823d33999	73	static const uint8_t SHIFT_TAB_OCxx[] =
<>	149:156823d33999	74	{
<>	149:156823d33999	75	0U, /* 0: OC1M, OC1FE, OC1PE */
<>	149:156823d33999	76	0U, /* 1: - NA */
<>	149:156823d33999	77	8U, /* 2: OC2M, OC2FE, OC2PE */
<>	149:156823d33999	78	0U, /* 3: - NA */
<>	149:156823d33999	79	0U, /* 4: OC3M, OC3FE, OC3PE */
<>	149:156823d33999	80	0U, /* 5: - NA */
<>	149:156823d33999	81	8U /* 6: OC4M, OC4FE, OC4PE */
<>	149:156823d33999	82	};
<>	149:156823d33999	83
<>	149:156823d33999	84	static const uint8_t SHIFT_TAB_ICxx[] =
<>	149:156823d33999	85	{
<>	149:156823d33999	86	0U, /* 0: CC1S, IC1PSC, IC1F */
<>	149:156823d33999	87	0U, /* 1: - NA */
<>	149:156823d33999	88	8U, /* 2: CC2S, IC2PSC, IC2F */
<>	149:156823d33999	89	0U, /* 3: - NA */
<>	149:156823d33999	90	0U, /* 4: CC3S, IC3PSC, IC3F */
<>	149:156823d33999	91	0U, /* 5: - NA */
<>	149:156823d33999	92	8U /* 6: CC4S, IC4PSC, IC4F */
<>	149:156823d33999	93	};
<>	149:156823d33999	94
<>	149:156823d33999	95	static const uint8_t SHIFT_TAB_CCxP[] =
<>	149:156823d33999	96	{
<>	149:156823d33999	97	0U, /* 0: CC1P */
<>	149:156823d33999	98	0U, /* 1: NA */
<>	149:156823d33999	99	4U, /* 2: CC2P */
<>	149:156823d33999	100	0U, /* 3: NA */
<>	149:156823d33999	101	8U, /* 4: CC3P */
<>	149:156823d33999	102	0U, /* 5: NA */
<>	149:156823d33999	103	12U /* 6: CC4P */
<>	149:156823d33999	104	};
<>	149:156823d33999	105
<>	149:156823d33999	106	/**
<>	149:156823d33999	107	* @}
<>	149:156823d33999	108	*/
<>	149:156823d33999	109
<>	149:156823d33999	110
<>	149:156823d33999	111	/* Private constants ---------------------------------------------------------*/
<>	149:156823d33999	112	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
<>	149:156823d33999	113	* @{
<>	149:156823d33999	114	*/
<>	149:156823d33999	115
<>	149:156823d33999	116
AnnaBridge	184:08ed48f1de7f	117	#define TIMx_OR_RMP_SHIFT 16U
AnnaBridge	184:08ed48f1de7f	118	#define TIMx_OR_RMP_MASK 0x0000FFFFU
AnnaBridge	184:08ed48f1de7f	119	#define TIM_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM_OR_ETR_RMP \| TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT)
AnnaBridge	184:08ed48f1de7f	120	#define TIM9_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
AnnaBridge	184:08ed48f1de7f	121	#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	184:08ed48f1de7f	122	#define TIM3_OR_RMP_MASK (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT)
<>	149:156823d33999	123
<>	149:156823d33999	124
<>	149:156823d33999	125
<>	149:156823d33999	126	/**
<>	149:156823d33999	127	* @}
<>	149:156823d33999	128	*/
<>	149:156823d33999	129
<>	149:156823d33999	130	/* Private macros ------------------------------------------------------------*/
<>	149:156823d33999	131	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
<>	149:156823d33999	132	* @{
<>	149:156823d33999	133	*/
<>	149:156823d33999	134	/** @brief Convert channel id into channel index.
<>	149:156823d33999	135	* @param __CHANNEL__ This parameter can be one of the following values:
<>	149:156823d33999	136	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	137	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	138	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	139	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	140	* @retval none
<>	149:156823d33999	141	*/
<>	149:156823d33999	142	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<>	149:156823d33999	143	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<>	149:156823d33999	144	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<>	149:156823d33999	145	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
<>	149:156823d33999	146
<>	149:156823d33999	147	/**
<>	149:156823d33999	148	* @}
<>	149:156823d33999	149	*/
<>	149:156823d33999	150
<>	149:156823d33999	151
<>	149:156823d33999	152	/* Exported types ------------------------------------------------------------*/
<>	149:156823d33999	153	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	154	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
<>	149:156823d33999	155	* @{
<>	149:156823d33999	156	*/
<>	149:156823d33999	157
<>	149:156823d33999	158	/**
<>	149:156823d33999	159	* @brief TIM Time Base configuration structure definition.
<>	149:156823d33999	160	*/
<>	149:156823d33999	161	typedef struct
<>	149:156823d33999	162	{
<>	149:156823d33999	163	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	149:156823d33999	164	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	149:156823d33999	165
<>	149:156823d33999	166	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
<>	149:156823d33999	167
<>	149:156823d33999	168	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	149:156823d33999	169	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
<>	149:156823d33999	170
<>	149:156823d33999	171	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
<>	149:156823d33999	172
AnnaBridge	184:08ed48f1de7f	173	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
<>	149:156823d33999	174	Auto-Reload Register at the next update event.
<>	149:156823d33999	175	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	149:156823d33999	176	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
<>	149:156823d33999	177
<>	149:156823d33999	178	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
<>	149:156823d33999	179
<>	149:156823d33999	180	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	149:156823d33999	181	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
<>	149:156823d33999	182
<>	149:156823d33999	183	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
<>	149:156823d33999	184	} LL_TIM_InitTypeDef;
<>	149:156823d33999	185
<>	149:156823d33999	186	/**
<>	149:156823d33999	187	* @brief TIM Output Compare configuration structure definition.
<>	149:156823d33999	188	*/
<>	149:156823d33999	189	typedef struct
<>	149:156823d33999	190	{
<>	149:156823d33999	191	uint32_t OCMode; /*!< Specifies the output mode.
<>	149:156823d33999	192	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
<>	149:156823d33999	193
<>	149:156823d33999	194	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
<>	149:156823d33999	195
<>	149:156823d33999	196	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
<>	149:156823d33999	197	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	149:156823d33999	198
<>	149:156823d33999	199	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	149:156823d33999	200
<>	149:156823d33999	201	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
<>	149:156823d33999	202	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	149:156823d33999	203
<>	149:156823d33999	204	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
<>	149:156823d33999	205
<>	149:156823d33999	206	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	149:156823d33999	207	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	149:156823d33999	208
<>	149:156823d33999	209	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	149:156823d33999	210
AnnaBridge	184:08ed48f1de7f	211
<>	149:156823d33999	212	} LL_TIM_OC_InitTypeDef;
<>	149:156823d33999	213
<>	149:156823d33999	214	/**
<>	149:156823d33999	215	* @brief TIM Input Capture configuration structure definition.
<>	149:156823d33999	216	*/
<>	149:156823d33999	217
<>	149:156823d33999	218	typedef struct
<>	149:156823d33999	219	{
<>	149:156823d33999	220
<>	149:156823d33999	221	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	149:156823d33999	222	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	149:156823d33999	223
<>	149:156823d33999	224	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	149:156823d33999	225
<>	149:156823d33999	226	uint32_t ICActiveInput; /*!< Specifies the input.
<>	149:156823d33999	227	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	149:156823d33999	228
<>	149:156823d33999	229	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	149:156823d33999	230
<>	149:156823d33999	231	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	149:156823d33999	232	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	149:156823d33999	233
<>	149:156823d33999	234	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	149:156823d33999	235
<>	149:156823d33999	236	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	149:156823d33999	237	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	149:156823d33999	238
<>	149:156823d33999	239	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	149:156823d33999	240	} LL_TIM_IC_InitTypeDef;
<>	149:156823d33999	241
<>	149:156823d33999	242
<>	149:156823d33999	243	/**
<>	149:156823d33999	244	* @brief TIM Encoder interface configuration structure definition.
<>	149:156823d33999	245	*/
<>	149:156823d33999	246	typedef struct
<>	149:156823d33999	247	{
<>	149:156823d33999	248	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
<>	149:156823d33999	249	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
<>	149:156823d33999	250
<>	149:156823d33999	251	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
<>	149:156823d33999	252
<>	149:156823d33999	253	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	149:156823d33999	254	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	149:156823d33999	255
<>	149:156823d33999	256	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	149:156823d33999	257
<>	149:156823d33999	258	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
<>	149:156823d33999	259	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	149:156823d33999	260
<>	149:156823d33999	261	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	149:156823d33999	262
<>	149:156823d33999	263	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	149:156823d33999	264	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	149:156823d33999	265
<>	149:156823d33999	266	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	149:156823d33999	267
<>	149:156823d33999	268	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	149:156823d33999	269	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	149:156823d33999	270
<>	149:156823d33999	271	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	149:156823d33999	272
<>	149:156823d33999	273	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
<>	149:156823d33999	274	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	149:156823d33999	275
<>	149:156823d33999	276	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	149:156823d33999	277
<>	149:156823d33999	278	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
<>	149:156823d33999	279	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	149:156823d33999	280
<>	149:156823d33999	281	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	149:156823d33999	282
<>	149:156823d33999	283	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
<>	149:156823d33999	284	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	149:156823d33999	285
<>	149:156823d33999	286	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	149:156823d33999	287
<>	149:156823d33999	288	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
<>	149:156823d33999	289	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	149:156823d33999	290
<>	149:156823d33999	291	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	149:156823d33999	292
<>	149:156823d33999	293	} LL_TIM_ENCODER_InitTypeDef;
<>	149:156823d33999	294
<>	149:156823d33999	295
<>	149:156823d33999	296	/**
<>	149:156823d33999	297	* @}
<>	149:156823d33999	298	*/
<>	149:156823d33999	299	#endif /* USE_FULL_LL_DRIVER */
<>	149:156823d33999	300
<>	149:156823d33999	301	/* Exported constants --------------------------------------------------------*/
<>	149:156823d33999	302	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
<>	149:156823d33999	303	* @{
<>	149:156823d33999	304	*/
<>	149:156823d33999	305
<>	149:156823d33999	306	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
<>	149:156823d33999	307	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
<>	149:156823d33999	308	* @{
<>	149:156823d33999	309	*/
<>	149:156823d33999	310	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
<>	149:156823d33999	311	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
<>	149:156823d33999	312	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
<>	149:156823d33999	313	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
<>	149:156823d33999	314	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
<>	149:156823d33999	315	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
<>	149:156823d33999	316	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
<>	149:156823d33999	317	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
<>	149:156823d33999	318	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
<>	149:156823d33999	319	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
<>	149:156823d33999	320	/**
<>	149:156823d33999	321	* @}
<>	149:156823d33999	322	*/
<>	149:156823d33999	323
<>	149:156823d33999	324	/** @defgroup TIM_LL_EC_IT IT Defines
<>	149:156823d33999	325	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
<>	149:156823d33999	326	* @{
<>	149:156823d33999	327	*/
<>	149:156823d33999	328	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
<>	149:156823d33999	329	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
<>	149:156823d33999	330	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
<>	149:156823d33999	331	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
<>	149:156823d33999	332	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
<>	149:156823d33999	333	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
<>	149:156823d33999	334	/**
<>	149:156823d33999	335	* @}
<>	149:156823d33999	336	*/
<>	149:156823d33999	337
<>	149:156823d33999	338	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
<>	149:156823d33999	339	* @{
<>	149:156823d33999	340	*/
AnnaBridge	184:08ed48f1de7f	341	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	184:08ed48f1de7f	342	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
<>	149:156823d33999	343	/**
<>	149:156823d33999	344	* @}
<>	149:156823d33999	345	*/
<>	149:156823d33999	346
<>	149:156823d33999	347	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
<>	149:156823d33999	348	* @{
<>	149:156823d33999	349	*/
AnnaBridge	184:08ed48f1de7f	350	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	184:08ed48f1de7f	351	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
<>	149:156823d33999	352	/**
<>	149:156823d33999	353	* @}
<>	149:156823d33999	354	*/
<>	149:156823d33999	355
<>	149:156823d33999	356	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
<>	149:156823d33999	357	* @{
<>	149:156823d33999	358	*/
AnnaBridge	184:08ed48f1de7f	359	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	184:08ed48f1de7f	360	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	184:08ed48f1de7f	361	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	184:08ed48f1de7f	362	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	184:08ed48f1de7f	363	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
<>	149:156823d33999	364	/**
<>	149:156823d33999	365	* @}
<>	149:156823d33999	366	*/
<>	149:156823d33999	367
<>	149:156823d33999	368	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
<>	149:156823d33999	369	* @{
<>	149:156823d33999	370	*/
AnnaBridge	184:08ed48f1de7f	371	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	184:08ed48f1de7f	372	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	184:08ed48f1de7f	373	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
<>	149:156823d33999	374	/**
<>	149:156823d33999	375	* @}
<>	149:156823d33999	376	*/
<>	149:156823d33999	377
<>	149:156823d33999	378	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
<>	149:156823d33999	379	* @{
<>	149:156823d33999	380	*/
AnnaBridge	184:08ed48f1de7f	381	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	184:08ed48f1de7f	382	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
<>	149:156823d33999	383	/**
<>	149:156823d33999	384	* @}
<>	149:156823d33999	385	*/
<>	149:156823d33999	386
<>	149:156823d33999	387
<>	149:156823d33999	388	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
<>	149:156823d33999	389	* @{
<>	149:156823d33999	390	*/
AnnaBridge	184:08ed48f1de7f	391	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	184:08ed48f1de7f	392	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
<>	149:156823d33999	393	/**
<>	149:156823d33999	394	* @}
<>	149:156823d33999	395	*/
<>	149:156823d33999	396
<>	149:156823d33999	397
<>	149:156823d33999	398	/** @defgroup TIM_LL_EC_CHANNEL Channel
<>	149:156823d33999	399	* @{
<>	149:156823d33999	400	*/
<>	149:156823d33999	401	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
<>	149:156823d33999	402	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
<>	149:156823d33999	403	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
<>	149:156823d33999	404	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
<>	149:156823d33999	405	/**
<>	149:156823d33999	406	* @}
<>	149:156823d33999	407	*/
<>	149:156823d33999	408
<>	149:156823d33999	409	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	410	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
<>	149:156823d33999	411	* @{
<>	149:156823d33999	412	*/
AnnaBridge	184:08ed48f1de7f	413	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
<>	149:156823d33999	414	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
<>	149:156823d33999	415	/**
<>	149:156823d33999	416	* @}
<>	149:156823d33999	417	*/
<>	149:156823d33999	418	#endif /* USE_FULL_LL_DRIVER */
<>	149:156823d33999	419
<>	149:156823d33999	420	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
<>	149:156823d33999	421	* @{
<>	149:156823d33999	422	*/
AnnaBridge	184:08ed48f1de7f	423	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
<>	149:156823d33999	424	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
<>	149:156823d33999	425	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
<>	149:156823d33999	426	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	184:08ed48f1de7f	427	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
<>	149:156823d33999	428	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
<>	149:156823d33999	429	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
<>	149:156823d33999	430	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
<>	149:156823d33999	431	/**
<>	149:156823d33999	432	* @}
<>	149:156823d33999	433	*/
<>	149:156823d33999	434
<>	149:156823d33999	435	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
<>	149:156823d33999	436	* @{
<>	149:156823d33999	437	*/
AnnaBridge	184:08ed48f1de7f	438	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
<>	149:156823d33999	439	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
<>	149:156823d33999	440	/**
<>	149:156823d33999	441	* @}
<>	149:156823d33999	442	*/
<>	149:156823d33999	443
<>	149:156823d33999	444
<>	149:156823d33999	445
<>	149:156823d33999	446	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
<>	149:156823d33999	447	* @{
<>	149:156823d33999	448	*/
AnnaBridge	184:08ed48f1de7f	449	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	184:08ed48f1de7f	450	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	184:08ed48f1de7f	451	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
<>	149:156823d33999	452	/**
<>	149:156823d33999	453	* @}
<>	149:156823d33999	454	*/
<>	149:156823d33999	455
<>	149:156823d33999	456	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
<>	149:156823d33999	457	* @{
<>	149:156823d33999	458	*/
AnnaBridge	184:08ed48f1de7f	459	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	184:08ed48f1de7f	460	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	184:08ed48f1de7f	461	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	184:08ed48f1de7f	462	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
<>	149:156823d33999	463	/**
<>	149:156823d33999	464	* @}
<>	149:156823d33999	465	*/
<>	149:156823d33999	466
<>	149:156823d33999	467	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
<>	149:156823d33999	468	* @{
<>	149:156823d33999	469	*/
AnnaBridge	184:08ed48f1de7f	470	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	184:08ed48f1de7f	471	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	184:08ed48f1de7f	472	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	184:08ed48f1de7f	473	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	184:08ed48f1de7f	474	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	184:08ed48f1de7f	475	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	184:08ed48f1de7f	476	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	184:08ed48f1de7f	477	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	184:08ed48f1de7f	478	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	184:08ed48f1de7f	479	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	184:08ed48f1de7f	480	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	184:08ed48f1de7f	481	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	184:08ed48f1de7f	482	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	184:08ed48f1de7f	483	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	184:08ed48f1de7f	484	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	184:08ed48f1de7f	485	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
<>	149:156823d33999	486	/**
<>	149:156823d33999	487	* @}
<>	149:156823d33999	488	*/
<>	149:156823d33999	489
<>	149:156823d33999	490	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
<>	149:156823d33999	491	* @{
<>	149:156823d33999	492	*/
AnnaBridge	184:08ed48f1de7f	493	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
<>	149:156823d33999	494	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
<>	149:156823d33999	495	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
<>	149:156823d33999	496	/**
<>	149:156823d33999	497	* @}
<>	149:156823d33999	498	*/
<>	149:156823d33999	499
<>	149:156823d33999	500	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
<>	149:156823d33999	501	* @{
<>	149:156823d33999	502	*/
AnnaBridge	184:08ed48f1de7f	503	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	184:08ed48f1de7f	504	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
AnnaBridge	184:08ed48f1de7f	505	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
<>	149:156823d33999	506	/**
<>	149:156823d33999	507	* @}
<>	149:156823d33999	508	*/
<>	149:156823d33999	509
<>	149:156823d33999	510	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
<>	149:156823d33999	511	* @{
<>	149:156823d33999	512	*/
<>	149:156823d33999	513	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
<>	149:156823d33999	514	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
<>	149:156823d33999	515	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
<>	149:156823d33999	516	/**
<>	149:156823d33999	517	* @}
<>	149:156823d33999	518	*/
<>	149:156823d33999	519
<>	149:156823d33999	520	/** @defgroup TIM_LL_EC_TRGO Trigger Output
<>	149:156823d33999	521	* @{
<>	149:156823d33999	522	*/
AnnaBridge	184:08ed48f1de7f	523	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
<>	149:156823d33999	524	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
<>	149:156823d33999	525	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
<>	149:156823d33999	526	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
<>	149:156823d33999	527	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
<>	149:156823d33999	528	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
<>	149:156823d33999	529	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
<>	149:156823d33999	530	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
<>	149:156823d33999	531	/**
<>	149:156823d33999	532	* @}
<>	149:156823d33999	533	*/
<>	149:156823d33999	534
<>	149:156823d33999	535
<>	149:156823d33999	536	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
<>	149:156823d33999	537	* @{
<>	149:156823d33999	538	*/
AnnaBridge	184:08ed48f1de7f	539	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
<>	149:156823d33999	540	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
<>	149:156823d33999	541	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
<>	149:156823d33999	542	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
<>	149:156823d33999	543	/**
<>	149:156823d33999	544	* @}
<>	149:156823d33999	545	*/
<>	149:156823d33999	546
<>	149:156823d33999	547	/** @defgroup TIM_LL_EC_TS Trigger Selection
<>	149:156823d33999	548	* @{
<>	149:156823d33999	549	*/
AnnaBridge	184:08ed48f1de7f	550	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	184:08ed48f1de7f	551	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	184:08ed48f1de7f	552	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	184:08ed48f1de7f	553	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	184:08ed48f1de7f	554	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	184:08ed48f1de7f	555	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	184:08ed48f1de7f	556	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	184:08ed48f1de7f	557	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
<>	149:156823d33999	558	/**
<>	149:156823d33999	559	* @}
<>	149:156823d33999	560	*/
<>	149:156823d33999	561
<>	149:156823d33999	562	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
<>	149:156823d33999	563	* @{
<>	149:156823d33999	564	*/
AnnaBridge	184:08ed48f1de7f	565	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
<>	149:156823d33999	566	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
<>	149:156823d33999	567	/**
<>	149:156823d33999	568	* @}
<>	149:156823d33999	569	*/
<>	149:156823d33999	570
<>	149:156823d33999	571	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
<>	149:156823d33999	572	* @{
<>	149:156823d33999	573	*/
AnnaBridge	184:08ed48f1de7f	574	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
<>	149:156823d33999	575	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
<>	149:156823d33999	576	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
<>	149:156823d33999	577	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
<>	149:156823d33999	578	/**
<>	149:156823d33999	579	* @}
<>	149:156823d33999	580	*/
<>	149:156823d33999	581
<>	149:156823d33999	582	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
<>	149:156823d33999	583	* @{
<>	149:156823d33999	584	*/
AnnaBridge	184:08ed48f1de7f	585	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
<>	149:156823d33999	586	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
<>	149:156823d33999	587	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
<>	149:156823d33999	588	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
<>	149:156823d33999	589	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
<>	149:156823d33999	590	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	184:08ed48f1de7f	591	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
<>	149:156823d33999	592	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
<>	149:156823d33999	593	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
<>	149:156823d33999	594	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	184:08ed48f1de7f	595	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
<>	149:156823d33999	596	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	184:08ed48f1de7f	597	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	184:08ed48f1de7f	598	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	184:08ed48f1de7f	599	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
<>	149:156823d33999	600	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
<>	149:156823d33999	601	/**
<>	149:156823d33999	602	* @}
<>	149:156823d33999	603	*/
<>	149:156823d33999	604
<>	149:156823d33999	605
<>	149:156823d33999	606
<>	149:156823d33999	607
<>	149:156823d33999	608
<>	149:156823d33999	609
<>	149:156823d33999	610
<>	149:156823d33999	611	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
<>	149:156823d33999	612	* @{
<>	149:156823d33999	613	*/
AnnaBridge	184:08ed48f1de7f	614	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
<>	149:156823d33999	615	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
<>	149:156823d33999	616	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
<>	149:156823d33999	617	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
<>	149:156823d33999	618	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
<>	149:156823d33999	619	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
<>	149:156823d33999	620	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
<>	149:156823d33999	621	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
<>	149:156823d33999	622	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
<>	149:156823d33999	623	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
<>	149:156823d33999	624	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
<>	149:156823d33999	625	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
<>	149:156823d33999	626	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
<>	149:156823d33999	627	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
<>	149:156823d33999	628	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
<>	149:156823d33999	629	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
<>	149:156823d33999	630	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR register is the DMA base address for DMA burst /
<>	149:156823d33999	631	/**
<>	149:156823d33999	632	* @}
<>	149:156823d33999	633	*/
<>	149:156823d33999	634
<>	149:156823d33999	635	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
<>	149:156823d33999	636	* @{
<>	149:156823d33999	637	*/
AnnaBridge	184:08ed48f1de7f	638	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
<>	149:156823d33999	639	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
<>	149:156823d33999	640	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
<>	149:156823d33999	641	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
<>	149:156823d33999	642	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
<>	149:156823d33999	643	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
<>	149:156823d33999	644	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
<>	149:156823d33999	645	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
<>	149:156823d33999	646	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
<>	149:156823d33999	647	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
<>	149:156823d33999	648	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
<>	149:156823d33999	649	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
<>	149:156823d33999	650	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
<>	149:156823d33999	651	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
<>	149:156823d33999	652	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
<>	149:156823d33999	653	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
<>	149:156823d33999	654	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
<>	149:156823d33999	655	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
<>	149:156823d33999	656	/**
<>	149:156823d33999	657	* @}
<>	149:156823d33999	658	*/
<>	149:156823d33999	659
<>	149:156823d33999	660	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability
AnnaBridge	184:08ed48f1de7f	661	* @{
AnnaBridge	184:08ed48f1de7f	662	*/
AnnaBridge	184:08ed48f1de7f	663	#define LL_TIM_TIM10_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM10 channel1 is connected to GPIO /
<>	149:156823d33999	664	#define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSI internal clock /
<>	149:156823d33999	665	#define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSE internal clock /
<>	149:156823d33999	666	#define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RTC wakeup interrupt signal /
<>	149:156823d33999	667	/**
<>	149:156823d33999	668	* @}
<>	149:156823d33999	669	*/
<>	149:156823d33999	670
<>	149:156823d33999	671	/** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap
AnnaBridge	184:08ed48f1de7f	672	* @{
AnnaBridge	184:08ed48f1de7f	673	*/
AnnaBridge	184:08ed48f1de7f	674	#define LL_TIM_TIM10_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM10 ETR input is connected to LSE /
<>	149:156823d33999	675	#define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM10 ETR input is connected to TIM9 TGO /
<>	149:156823d33999	676	/**
<>	149:156823d33999	677	* @}
<>	149:156823d33999	678	*/
<>	149:156823d33999	679
<>	149:156823d33999	680	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
<>	149:156823d33999	681	* @{
<>	149:156823d33999	682	*/
AnnaBridge	184:08ed48f1de7f	683	#define LL_TIM_TIM10_TI1_RMP TIM_OR_RMP_MASK /!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values /
<>	149:156823d33999	684	#define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RI /
<>	149:156823d33999	685	/**
<>	149:156823d33999	686	* @}
<>	149:156823d33999	687	*/
<>	149:156823d33999	688
<>	149:156823d33999	689	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability
AnnaBridge	184:08ed48f1de7f	690	* @{
AnnaBridge	184:08ed48f1de7f	691	*/
AnnaBridge	184:08ed48f1de7f	692	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM11 channel1 is connected to GPIO /
<>	149:156823d33999	693	#define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to MSI internal clock /
<>	149:156823d33999	694	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to HSE RTC clock /
<>	149:156823d33999	695	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to GPIO /
<>	149:156823d33999	696	/**
<>	149:156823d33999	697	* @}
<>	149:156823d33999	698	*/
<>	149:156823d33999	699
<>	149:156823d33999	700	/** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap
AnnaBridge	184:08ed48f1de7f	701	* @{
AnnaBridge	184:08ed48f1de7f	702	*/
AnnaBridge	184:08ed48f1de7f	703	#define LL_TIM_TIM11_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM11 ETR input is connected to LSE /
<>	149:156823d33999	704	#define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM11 ETR input is connected to TIM9 TGO clock /
<>	149:156823d33999	705	/**
<>	149:156823d33999	706	* @}
<>	149:156823d33999	707	*/
<>	149:156823d33999	708
<>	149:156823d33999	709	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
AnnaBridge	184:08ed48f1de7f	710	* @{
AnnaBridge	184:08ed48f1de7f	711	*/
AnnaBridge	184:08ed48f1de7f	712	#define LL_TIM_TIM11_TI1_RMP TIM_OR_RMP_MASK /!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values /
<>	149:156823d33999	713	#define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to RI /
<>	149:156823d33999	714	/**
<>	149:156823d33999	715	* @}
<>	149:156823d33999	716	*/
<>	149:156823d33999	717
<>	149:156823d33999	718	/** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
AnnaBridge	184:08ed48f1de7f	719	* @{
AnnaBridge	184:08ed48f1de7f	720	*/
AnnaBridge	184:08ed48f1de7f	721	#define LL_TIM_TIM9_TI1_RMP_GPIO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to GPIO /
<>	149:156823d33999	722	#define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to LSE internal clock /
<>	149:156823d33999	723	#define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
<>	149:156823d33999	724	#define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
<>	149:156823d33999	725	/**
<>	149:156823d33999	726	* @}
<>	149:156823d33999	727	*/
<>	149:156823d33999	728
<>	149:156823d33999	729	/** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap
AnnaBridge	184:08ed48f1de7f	730	* @{
AnnaBridge	184:08ed48f1de7f	731	*/
AnnaBridge	184:08ed48f1de7f	732	#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to TIM3 TGO signal /
<>	149:156823d33999	733	#define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to touch sensing I/O /
<>	149:156823d33999	734	/**
<>	149:156823d33999	735	* @}
<>	149:156823d33999	736	*/
<>	149:156823d33999	737
<>	149:156823d33999	738	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap
<>	149:156823d33999	739	* @{
<>	149:156823d33999	740	*/
AnnaBridge	184:08ed48f1de7f	741	#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC TIM9_OR_RMP_MASK /!< TIM2 ITR1 input is connected to TIM10 OC/
<>	149:156823d33999	742	#define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM2 ITR1 input is connected to TIM5 TGO /
<>	149:156823d33999	743	/**
<>	149:156823d33999	744	* @}
<>	149:156823d33999	745	*/
<>	149:156823d33999	746
<>	149:156823d33999	747	/** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap
AnnaBridge	184:08ed48f1de7f	748	* @{
AnnaBridge	184:08ed48f1de7f	749	*/
AnnaBridge	184:08ed48f1de7f	750	#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC TIM9_OR_RMP_MASK /!< TIM3 ITR2 input is connected to TIM11 OC /
<>	149:156823d33999	751	#define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP \| TIM9_OR_RMP_MASK) /!< TIM3 ITR2 input is connected to TIM5 TGO /
<>	149:156823d33999	752	/**
<>	149:156823d33999	753	* @}
<>	149:156823d33999	754	*/
<>	149:156823d33999	755
<>	149:156823d33999	756
<>	149:156823d33999	757	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
<>	149:156823d33999	758	* @{
<>	149:156823d33999	759	*/
AnnaBridge	184:08ed48f1de7f	760	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
AnnaBridge	184:08ed48f1de7f	761	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
<>	149:156823d33999	762	/**
<>	149:156823d33999	763	* @}
<>	149:156823d33999	764	*/
<>	149:156823d33999	765
<>	149:156823d33999	766	/**
<>	149:156823d33999	767	* @}
<>	149:156823d33999	768	*/
<>	149:156823d33999	769
<>	149:156823d33999	770	/* Exported macro ------------------------------------------------------------*/
<>	149:156823d33999	771	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
<>	149:156823d33999	772	* @{
<>	149:156823d33999	773	*/
<>	149:156823d33999	774
<>	149:156823d33999	775	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	149:156823d33999	776	* @{
<>	149:156823d33999	777	*/
<>	149:156823d33999	778	/**
<>	149:156823d33999	779	* @brief Write a value in TIM register.
<>	149:156823d33999	780	* @param __INSTANCE__ TIM Instance
<>	149:156823d33999	781	* @param __REG__ Register to be written
<>	149:156823d33999	782	* @param __VALUE__ Value to be written in the register
<>	149:156823d33999	783	* @retval None
<>	149:156823d33999	784	*/
<>	149:156823d33999	785	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	149:156823d33999	786
<>	149:156823d33999	787	/**
<>	149:156823d33999	788	* @brief Read a value in TIM register.
<>	149:156823d33999	789	* @param __INSTANCE__ TIM Instance
<>	149:156823d33999	790	* @param __REG__ Register to be read
<>	149:156823d33999	791	* @retval Register value
<>	149:156823d33999	792	*/
<>	149:156823d33999	793	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	149:156823d33999	794	/**
<>	149:156823d33999	795	* @}
<>	149:156823d33999	796	*/
<>	149:156823d33999	797
<>	149:156823d33999	798	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
<>	149:156823d33999	799	* @{
<>	149:156823d33999	800	*/
<>	149:156823d33999	801
<>	149:156823d33999	802
<>	149:156823d33999	803	/**
<>	149:156823d33999	804	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
<>	149:156823d33999	805	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
<>	149:156823d33999	806	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	149:156823d33999	807	* @param __CNTCLK__ counter clock frequency (in Hz)
<>	149:156823d33999	808	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	809	*/
<>	149:156823d33999	810	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
<>	149:156823d33999	811	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
<>	149:156823d33999	812
<>	149:156823d33999	813	/**
<>	149:156823d33999	814	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
<>	149:156823d33999	815	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
<>	149:156823d33999	816	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	149:156823d33999	817	* @param __PSC__ prescaler
<>	149:156823d33999	818	* @param __FREQ__ output signal frequency (in Hz)
<>	149:156823d33999	819	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	820	*/
<>	149:156823d33999	821	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
<>	149:156823d33999	822	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
<>	149:156823d33999	823
<>	149:156823d33999	824	/**
<>	149:156823d33999	825	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
<>	149:156823d33999	826	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
<>	149:156823d33999	827	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	149:156823d33999	828	* @param __PSC__ prescaler
<>	149:156823d33999	829	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	149:156823d33999	830	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	831	*/
<>	149:156823d33999	832	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
<>	149:156823d33999	833	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
<>	149:156823d33999	834	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
<>	149:156823d33999	835
<>	149:156823d33999	836	/**
<>	149:156823d33999	837	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
<>	149:156823d33999	838	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
<>	149:156823d33999	839	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	149:156823d33999	840	* @param __PSC__ prescaler
<>	149:156823d33999	841	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	149:156823d33999	842	* @param __PULSE__ pulse duration (in us)
<>	149:156823d33999	843	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	844	*/
<>	149:156823d33999	845	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
<>	149:156823d33999	846	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
<>	149:156823d33999	847	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
<>	149:156823d33999	848
<>	149:156823d33999	849	/**
<>	149:156823d33999	850	* @brief HELPER macro retrieving the ratio of the input capture prescaler
<>	149:156823d33999	851	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
<>	149:156823d33999	852	* @param __ICPSC__ This parameter can be one of the following values:
<>	149:156823d33999	853	* @arg @ref LL_TIM_ICPSC_DIV1
<>	149:156823d33999	854	* @arg @ref LL_TIM_ICPSC_DIV2
<>	149:156823d33999	855	* @arg @ref LL_TIM_ICPSC_DIV4
<>	149:156823d33999	856	* @arg @ref LL_TIM_ICPSC_DIV8
<>	149:156823d33999	857	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
<>	149:156823d33999	858	*/
<>	149:156823d33999	859	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	184:08ed48f1de7f	860	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
<>	149:156823d33999	861
<>	149:156823d33999	862
<>	149:156823d33999	863	/**
<>	149:156823d33999	864	* @}
<>	149:156823d33999	865	*/
<>	149:156823d33999	866
<>	149:156823d33999	867
<>	149:156823d33999	868	/**
<>	149:156823d33999	869	* @}
<>	149:156823d33999	870	*/
<>	149:156823d33999	871
<>	149:156823d33999	872	/* Exported functions --------------------------------------------------------*/
<>	149:156823d33999	873	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
<>	149:156823d33999	874	* @{
<>	149:156823d33999	875	*/
<>	149:156823d33999	876
<>	149:156823d33999	877	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
<>	149:156823d33999	878	* @{
<>	149:156823d33999	879	*/
<>	149:156823d33999	880	/**
<>	149:156823d33999	881	* @brief Enable timer counter.
<>	149:156823d33999	882	* @rmtoll CR1 CEN LL_TIM_EnableCounter
<>	149:156823d33999	883	* @param TIMx Timer instance
<>	149:156823d33999	884	* @retval None
<>	149:156823d33999	885	*/
<>	149:156823d33999	886	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
<>	149:156823d33999	887	{
<>	149:156823d33999	888	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	149:156823d33999	889	}
<>	149:156823d33999	890
<>	149:156823d33999	891	/**
<>	149:156823d33999	892	* @brief Disable timer counter.
<>	149:156823d33999	893	* @rmtoll CR1 CEN LL_TIM_DisableCounter
<>	149:156823d33999	894	* @param TIMx Timer instance
<>	149:156823d33999	895	* @retval None
<>	149:156823d33999	896	*/
<>	149:156823d33999	897	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
<>	149:156823d33999	898	{
<>	149:156823d33999	899	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	149:156823d33999	900	}
<>	149:156823d33999	901
<>	149:156823d33999	902	/**
<>	149:156823d33999	903	* @brief Indicates whether the timer counter is enabled.
<>	149:156823d33999	904	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
<>	149:156823d33999	905	* @param TIMx Timer instance
<>	149:156823d33999	906	* @retval State of bit (1 or 0).
<>	149:156823d33999	907	*/
<>	149:156823d33999	908	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
<>	149:156823d33999	909	{
<>	149:156823d33999	910	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
<>	149:156823d33999	911	}
<>	149:156823d33999	912
<>	149:156823d33999	913	/**
<>	149:156823d33999	914	* @brief Enable update event generation.
<>	149:156823d33999	915	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
<>	149:156823d33999	916	* @param TIMx Timer instance
<>	149:156823d33999	917	* @retval None
<>	149:156823d33999	918	*/
<>	149:156823d33999	919	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
<>	149:156823d33999	920	{
AnnaBridge	184:08ed48f1de7f	921	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	149:156823d33999	922	}
<>	149:156823d33999	923
<>	149:156823d33999	924	/**
<>	149:156823d33999	925	* @brief Disable update event generation.
<>	149:156823d33999	926	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
<>	149:156823d33999	927	* @param TIMx Timer instance
<>	149:156823d33999	928	* @retval None
<>	149:156823d33999	929	*/
<>	149:156823d33999	930	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
<>	149:156823d33999	931	{
AnnaBridge	184:08ed48f1de7f	932	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	149:156823d33999	933	}
<>	149:156823d33999	934
<>	149:156823d33999	935	/**
<>	149:156823d33999	936	* @brief Indicates whether update event generation is enabled.
<>	149:156823d33999	937	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
<>	149:156823d33999	938	* @param TIMx Timer instance
<>	149:156823d33999	939	* @retval State of bit (1 or 0).
<>	149:156823d33999	940	*/
<>	149:156823d33999	941	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
<>	149:156823d33999	942	{
<>	149:156823d33999	943	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
<>	149:156823d33999	944	}
<>	149:156823d33999	945
<>	149:156823d33999	946	/**
<>	149:156823d33999	947	* @brief Set update event source
<>	149:156823d33999	948	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
<>	149:156823d33999	949	* generate an update interrupt or DMA request if enabled:
<>	149:156823d33999	950	* - Counter overflow/underflow
<>	149:156823d33999	951	* - Setting the UG bit
<>	149:156823d33999	952	* - Update generation through the slave mode controller
<>	149:156823d33999	953	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
<>	149:156823d33999	954	* overflow/underflow generates an update interrupt or DMA request if enabled.
<>	149:156823d33999	955	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
<>	149:156823d33999	956	* @param TIMx Timer instance
<>	149:156823d33999	957	* @param UpdateSource This parameter can be one of the following values:
<>	149:156823d33999	958	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	149:156823d33999	959	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	149:156823d33999	960	* @retval None
<>	149:156823d33999	961	*/
<>	149:156823d33999	962	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
<>	149:156823d33999	963	{
<>	149:156823d33999	964	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
<>	149:156823d33999	965	}
<>	149:156823d33999	966
<>	149:156823d33999	967	/**
<>	149:156823d33999	968	* @brief Get actual event update source
<>	149:156823d33999	969	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
<>	149:156823d33999	970	* @param TIMx Timer instance
<>	149:156823d33999	971	* @retval Returned value can be one of the following values:
<>	149:156823d33999	972	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	149:156823d33999	973	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	149:156823d33999	974	*/
<>	149:156823d33999	975	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
<>	149:156823d33999	976	{
<>	149:156823d33999	977	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
<>	149:156823d33999	978	}
<>	149:156823d33999	979
<>	149:156823d33999	980	/**
<>	149:156823d33999	981	* @brief Set one pulse mode (one shot v.s. repetitive).
<>	149:156823d33999	982	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
<>	149:156823d33999	983	* @param TIMx Timer instance
<>	149:156823d33999	984	* @param OnePulseMode This parameter can be one of the following values:
<>	149:156823d33999	985	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	149:156823d33999	986	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	149:156823d33999	987	* @retval None
<>	149:156823d33999	988	*/
<>	149:156823d33999	989	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
<>	149:156823d33999	990	{
<>	149:156823d33999	991	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
<>	149:156823d33999	992	}
<>	149:156823d33999	993
<>	149:156823d33999	994	/**
<>	149:156823d33999	995	* @brief Get actual one pulse mode.
<>	149:156823d33999	996	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
<>	149:156823d33999	997	* @param TIMx Timer instance
<>	149:156823d33999	998	* @retval Returned value can be one of the following values:
<>	149:156823d33999	999	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	149:156823d33999	1000	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	149:156823d33999	1001	*/
<>	149:156823d33999	1002	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
<>	149:156823d33999	1003	{
<>	149:156823d33999	1004	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
<>	149:156823d33999	1005	}
<>	149:156823d33999	1006
<>	149:156823d33999	1007	/**
<>	149:156823d33999	1008	* @brief Set the timer counter counting mode.
<>	149:156823d33999	1009	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	149:156823d33999	1010	* check whether or not the counter mode selection feature is supported
<>	149:156823d33999	1011	* by a timer instance.
<>	149:156823d33999	1012	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
<>	149:156823d33999	1013	* CR1 CMS LL_TIM_SetCounterMode
<>	149:156823d33999	1014	* @param TIMx Timer instance
<>	149:156823d33999	1015	* @param CounterMode This parameter can be one of the following values:
<>	149:156823d33999	1016	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	149:156823d33999	1017	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	149:156823d33999	1018	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	149:156823d33999	1019	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	149:156823d33999	1020	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	149:156823d33999	1021	* @retval None
<>	149:156823d33999	1022	*/
<>	149:156823d33999	1023	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
<>	149:156823d33999	1024	{
<>	149:156823d33999	1025	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
<>	149:156823d33999	1026	}
<>	149:156823d33999	1027
<>	149:156823d33999	1028	/**
<>	149:156823d33999	1029	* @brief Get actual counter mode.
<>	149:156823d33999	1030	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	149:156823d33999	1031	* check whether or not the counter mode selection feature is supported
<>	149:156823d33999	1032	* by a timer instance.
<>	149:156823d33999	1033	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
<>	149:156823d33999	1034	* CR1 CMS LL_TIM_GetCounterMode
<>	149:156823d33999	1035	* @param TIMx Timer instance
<>	149:156823d33999	1036	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1037	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	149:156823d33999	1038	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	149:156823d33999	1039	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	149:156823d33999	1040	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	149:156823d33999	1041	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	149:156823d33999	1042	*/
<>	149:156823d33999	1043	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
<>	149:156823d33999	1044	{
<>	149:156823d33999	1045	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
<>	149:156823d33999	1046	}
<>	149:156823d33999	1047
<>	149:156823d33999	1048	/**
<>	149:156823d33999	1049	* @brief Enable auto-reload (ARR) preload.
<>	149:156823d33999	1050	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
<>	149:156823d33999	1051	* @param TIMx Timer instance
<>	149:156823d33999	1052	* @retval None
<>	149:156823d33999	1053	*/
<>	149:156823d33999	1054	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
<>	149:156823d33999	1055	{
<>	149:156823d33999	1056	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	149:156823d33999	1057	}
<>	149:156823d33999	1058
<>	149:156823d33999	1059	/**
<>	149:156823d33999	1060	* @brief Disable auto-reload (ARR) preload.
<>	149:156823d33999	1061	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
<>	149:156823d33999	1062	* @param TIMx Timer instance
<>	149:156823d33999	1063	* @retval None
<>	149:156823d33999	1064	*/
<>	149:156823d33999	1065	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
<>	149:156823d33999	1066	{
<>	149:156823d33999	1067	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	149:156823d33999	1068	}
<>	149:156823d33999	1069
<>	149:156823d33999	1070	/**
<>	149:156823d33999	1071	* @brief Indicates whether auto-reload (ARR) preload is enabled.
<>	149:156823d33999	1072	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
<>	149:156823d33999	1073	* @param TIMx Timer instance
<>	149:156823d33999	1074	* @retval State of bit (1 or 0).
<>	149:156823d33999	1075	*/
<>	149:156823d33999	1076	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
<>	149:156823d33999	1077	{
<>	149:156823d33999	1078	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
<>	149:156823d33999	1079	}
<>	149:156823d33999	1080
<>	149:156823d33999	1081	/**
<>	149:156823d33999	1082	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	149:156823d33999	1083	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1084	* whether or not the clock division feature is supported by the timer
<>	149:156823d33999	1085	* instance.
<>	149:156823d33999	1086	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
<>	149:156823d33999	1087	* @param TIMx Timer instance
<>	149:156823d33999	1088	* @param ClockDivision This parameter can be one of the following values:
<>	149:156823d33999	1089	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	149:156823d33999	1090	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	149:156823d33999	1091	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	149:156823d33999	1092	* @retval None
<>	149:156823d33999	1093	*/
<>	149:156823d33999	1094	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
<>	149:156823d33999	1095	{
<>	149:156823d33999	1096	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
<>	149:156823d33999	1097	}
<>	149:156823d33999	1098
<>	149:156823d33999	1099	/**
<>	149:156823d33999	1100	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	149:156823d33999	1101	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1102	* whether or not the clock division feature is supported by the timer
<>	149:156823d33999	1103	* instance.
<>	149:156823d33999	1104	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
<>	149:156823d33999	1105	* @param TIMx Timer instance
<>	149:156823d33999	1106	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1107	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	149:156823d33999	1108	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	149:156823d33999	1109	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	149:156823d33999	1110	*/
<>	149:156823d33999	1111	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
<>	149:156823d33999	1112	{
<>	149:156823d33999	1113	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
<>	149:156823d33999	1114	}
<>	149:156823d33999	1115
<>	149:156823d33999	1116	/**
<>	149:156823d33999	1117	* @brief Set the counter value.
<>	149:156823d33999	1118	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1119	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1120	* @rmtoll CNT CNT LL_TIM_SetCounter
<>	149:156823d33999	1121	* @param TIMx Timer instance
<>	149:156823d33999	1122	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	149:156823d33999	1123	* @retval None
<>	149:156823d33999	1124	*/
<>	149:156823d33999	1125	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
<>	149:156823d33999	1126	{
<>	149:156823d33999	1127	WRITE_REG(TIMx->CNT, Counter);
<>	149:156823d33999	1128	}
<>	149:156823d33999	1129
<>	149:156823d33999	1130	/**
<>	149:156823d33999	1131	* @brief Get the counter value.
<>	149:156823d33999	1132	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1133	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1134	* @rmtoll CNT CNT LL_TIM_GetCounter
<>	149:156823d33999	1135	* @param TIMx Timer instance
<>	149:156823d33999	1136	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	149:156823d33999	1137	*/
<>	149:156823d33999	1138	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
<>	149:156823d33999	1139	{
<>	149:156823d33999	1140	return (uint32_t)(READ_REG(TIMx->CNT));
<>	149:156823d33999	1141	}
<>	149:156823d33999	1142
<>	149:156823d33999	1143	/**
<>	149:156823d33999	1144	* @brief Get the current direction of the counter
<>	149:156823d33999	1145	* @rmtoll CR1 DIR LL_TIM_GetDirection
<>	149:156823d33999	1146	* @param TIMx Timer instance
<>	149:156823d33999	1147	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1148	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
<>	149:156823d33999	1149	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
<>	149:156823d33999	1150	*/
<>	149:156823d33999	1151	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
<>	149:156823d33999	1152	{
<>	149:156823d33999	1153	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
<>	149:156823d33999	1154	}
<>	149:156823d33999	1155
<>	149:156823d33999	1156	/**
<>	149:156823d33999	1157	* @brief Set the prescaler value.
<>	149:156823d33999	1158	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
<>	149:156823d33999	1159	* @note The prescaler can be changed on the fly as this control register is buffered. The new
<>	149:156823d33999	1160	* prescaler ratio is taken into account at the next update event.
<>	149:156823d33999	1161	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
<>	149:156823d33999	1162	* @rmtoll PSC PSC LL_TIM_SetPrescaler
<>	149:156823d33999	1163	* @param TIMx Timer instance
<>	149:156823d33999	1164	* @param Prescaler between Min_Data=0 and Max_Data=65535
<>	149:156823d33999	1165	* @retval None
<>	149:156823d33999	1166	*/
<>	149:156823d33999	1167	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
<>	149:156823d33999	1168	{
<>	149:156823d33999	1169	WRITE_REG(TIMx->PSC, Prescaler);
<>	149:156823d33999	1170	}
<>	149:156823d33999	1171
<>	149:156823d33999	1172	/**
<>	149:156823d33999	1173	* @brief Get the prescaler value.
<>	149:156823d33999	1174	* @rmtoll PSC PSC LL_TIM_GetPrescaler
<>	149:156823d33999	1175	* @param TIMx Timer instance
<>	149:156823d33999	1176	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
<>	149:156823d33999	1177	*/
<>	149:156823d33999	1178	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
<>	149:156823d33999	1179	{
<>	149:156823d33999	1180	return (uint32_t)(READ_REG(TIMx->PSC));
<>	149:156823d33999	1181	}
<>	149:156823d33999	1182
<>	149:156823d33999	1183	/**
<>	149:156823d33999	1184	* @brief Set the auto-reload value.
<>	149:156823d33999	1185	* @note The counter is blocked while the auto-reload value is null.
<>	149:156823d33999	1186	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1187	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1188	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
<>	149:156823d33999	1189	* @rmtoll ARR ARR LL_TIM_SetAutoReload
<>	149:156823d33999	1190	* @param TIMx Timer instance
<>	149:156823d33999	1191	* @param AutoReload between Min_Data=0 and Max_Data=65535
<>	149:156823d33999	1192	* @retval None
<>	149:156823d33999	1193	*/
<>	149:156823d33999	1194	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
<>	149:156823d33999	1195	{
<>	149:156823d33999	1196	WRITE_REG(TIMx->ARR, AutoReload);
<>	149:156823d33999	1197	}
<>	149:156823d33999	1198
<>	149:156823d33999	1199	/**
<>	149:156823d33999	1200	* @brief Get the auto-reload value.
<>	149:156823d33999	1201	* @rmtoll ARR ARR LL_TIM_GetAutoReload
<>	149:156823d33999	1202	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1203	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1204	* @param TIMx Timer instance
<>	149:156823d33999	1205	* @retval Auto-reload value
<>	149:156823d33999	1206	*/
<>	149:156823d33999	1207	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
<>	149:156823d33999	1208	{
<>	149:156823d33999	1209	return (uint32_t)(READ_REG(TIMx->ARR));
<>	149:156823d33999	1210	}
<>	149:156823d33999	1211
<>	149:156823d33999	1212	/**
<>	149:156823d33999	1213	* @}
<>	149:156823d33999	1214	*/
<>	149:156823d33999	1215
<>	149:156823d33999	1216	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
<>	149:156823d33999	1217	* @{
<>	149:156823d33999	1218	*/
<>	149:156823d33999	1219	/**
<>	149:156823d33999	1220	* @brief Set the trigger of the capture/compare DMA request.
<>	149:156823d33999	1221	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
<>	149:156823d33999	1222	* @param TIMx Timer instance
<>	149:156823d33999	1223	* @param DMAReqTrigger This parameter can be one of the following values:
<>	149:156823d33999	1224	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	149:156823d33999	1225	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	149:156823d33999	1226	* @retval None
<>	149:156823d33999	1227	*/
<>	149:156823d33999	1228	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
<>	149:156823d33999	1229	{
<>	149:156823d33999	1230	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
<>	149:156823d33999	1231	}
<>	149:156823d33999	1232
<>	149:156823d33999	1233	/**
<>	149:156823d33999	1234	* @brief Get actual trigger of the capture/compare DMA request.
<>	149:156823d33999	1235	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
<>	149:156823d33999	1236	* @param TIMx Timer instance
<>	149:156823d33999	1237	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1238	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	149:156823d33999	1239	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	149:156823d33999	1240	*/
<>	149:156823d33999	1241	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
<>	149:156823d33999	1242	{
<>	149:156823d33999	1243	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
<>	149:156823d33999	1244	}
<>	149:156823d33999	1245
<>	149:156823d33999	1246	/**
<>	149:156823d33999	1247	* @brief Enable capture/compare channels.
<>	149:156823d33999	1248	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
<>	149:156823d33999	1249	* CCER CC2E LL_TIM_CC_EnableChannel\n
<>	149:156823d33999	1250	* CCER CC3E LL_TIM_CC_EnableChannel\n
<>	149:156823d33999	1251	* CCER CC4E LL_TIM_CC_EnableChannel
<>	149:156823d33999	1252	* @param TIMx Timer instance
<>	149:156823d33999	1253	* @param Channels This parameter can be a combination of the following values:
<>	149:156823d33999	1254	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1255	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1256	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1257	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1258	* @retval None
<>	149:156823d33999	1259	*/
<>	149:156823d33999	1260	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	149:156823d33999	1261	{
<>	149:156823d33999	1262	SET_BIT(TIMx->CCER, Channels);
<>	149:156823d33999	1263	}
<>	149:156823d33999	1264
<>	149:156823d33999	1265	/**
<>	149:156823d33999	1266	* @brief Disable capture/compare channels.
<>	149:156823d33999	1267	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
<>	149:156823d33999	1268	* CCER CC2E LL_TIM_CC_DisableChannel\n
<>	149:156823d33999	1269	* CCER CC3E LL_TIM_CC_DisableChannel\n
<>	149:156823d33999	1270	* CCER CC4E LL_TIM_CC_DisableChannel
<>	149:156823d33999	1271	* @param TIMx Timer instance
<>	149:156823d33999	1272	* @param Channels This parameter can be a combination of the following values:
<>	149:156823d33999	1273	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1274	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1275	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1276	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1277	* @retval None
<>	149:156823d33999	1278	*/
<>	149:156823d33999	1279	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	149:156823d33999	1280	{
<>	149:156823d33999	1281	CLEAR_BIT(TIMx->CCER, Channels);
<>	149:156823d33999	1282	}
<>	149:156823d33999	1283
<>	149:156823d33999	1284	/**
<>	149:156823d33999	1285	* @brief Indicate whether channel(s) is(are) enabled.
<>	149:156823d33999	1286	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
<>	149:156823d33999	1287	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
<>	149:156823d33999	1288	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
<>	149:156823d33999	1289	* CCER CC4E LL_TIM_CC_IsEnabledChannel
<>	149:156823d33999	1290	* @param TIMx Timer instance
<>	149:156823d33999	1291	* @param Channels This parameter can be a combination of the following values:
<>	149:156823d33999	1292	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1293	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1294	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1295	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1296	* @retval State of bit (1 or 0).
<>	149:156823d33999	1297	*/
<>	149:156823d33999	1298	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	149:156823d33999	1299	{
<>	149:156823d33999	1300	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
<>	149:156823d33999	1301	}
<>	149:156823d33999	1302
<>	149:156823d33999	1303	/**
<>	149:156823d33999	1304	* @}
<>	149:156823d33999	1305	*/
<>	149:156823d33999	1306
<>	149:156823d33999	1307	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
<>	149:156823d33999	1308	* @{
<>	149:156823d33999	1309	*/
<>	149:156823d33999	1310	/**
<>	149:156823d33999	1311	* @brief Configure an output channel.
<>	149:156823d33999	1312	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1313	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1314	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1315	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1316	* CCER CC1P LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1317	* CCER CC2P LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1318	* CCER CC3P LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1319	* CCER CC4P LL_TIM_OC_ConfigOutput\n
<>	149:156823d33999	1320	* @param TIMx Timer instance
<>	149:156823d33999	1321	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1322	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1323	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1324	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1325	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1326	* @param Configuration This parameter must be a combination of all the following values:
<>	149:156823d33999	1327	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
<>	149:156823d33999	1328	* @retval None
<>	149:156823d33999	1329	*/
<>	149:156823d33999	1330	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	149:156823d33999	1331	{
<>	149:156823d33999	1332	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1333	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1334	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
<>	149:156823d33999	1335	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
<>	149:156823d33999	1336	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
<>	149:156823d33999	1337	}
<>	149:156823d33999	1338
<>	149:156823d33999	1339	/**
<>	149:156823d33999	1340	* @brief Define the behavior of the output reference signal OCxREF from which
<>	149:156823d33999	1341	* OCx and OCxN (when relevant) are derived.
<>	149:156823d33999	1342	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
<>	149:156823d33999	1343	* CCMR1 OC2M LL_TIM_OC_SetMode\n
<>	149:156823d33999	1344	* CCMR2 OC3M LL_TIM_OC_SetMode\n
<>	149:156823d33999	1345	* CCMR2 OC4M LL_TIM_OC_SetMode
<>	149:156823d33999	1346	* @param TIMx Timer instance
<>	149:156823d33999	1347	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1348	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1349	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1350	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1351	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1352	* @param Mode This parameter can be one of the following values:
<>	149:156823d33999	1353	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	149:156823d33999	1354	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	149:156823d33999	1355	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	149:156823d33999	1356	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	149:156823d33999	1357	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	149:156823d33999	1358	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	149:156823d33999	1359	* @arg @ref LL_TIM_OCMODE_PWM1
<>	149:156823d33999	1360	* @arg @ref LL_TIM_OCMODE_PWM2
<>	149:156823d33999	1361	* @retval None
<>	149:156823d33999	1362	*/
<>	149:156823d33999	1363	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
<>	149:156823d33999	1364	{
<>	149:156823d33999	1365	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1366	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1367	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
<>	149:156823d33999	1368	}
<>	149:156823d33999	1369
<>	149:156823d33999	1370	/**
<>	149:156823d33999	1371	* @brief Get the output compare mode of an output channel.
<>	149:156823d33999	1372	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
<>	149:156823d33999	1373	* CCMR1 OC2M LL_TIM_OC_GetMode\n
<>	149:156823d33999	1374	* CCMR2 OC3M LL_TIM_OC_GetMode\n
<>	149:156823d33999	1375	* CCMR2 OC4M LL_TIM_OC_GetMode
<>	149:156823d33999	1376	* @param TIMx Timer instance
<>	149:156823d33999	1377	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1378	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1379	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1380	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1381	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1382	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1383	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	149:156823d33999	1384	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	149:156823d33999	1385	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	149:156823d33999	1386	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	149:156823d33999	1387	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	149:156823d33999	1388	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	149:156823d33999	1389	* @arg @ref LL_TIM_OCMODE_PWM1
<>	149:156823d33999	1390	* @arg @ref LL_TIM_OCMODE_PWM2
<>	149:156823d33999	1391	*/
<>	149:156823d33999	1392	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1393	{
<>	149:156823d33999	1394	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1395	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1396	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
<>	149:156823d33999	1397	}
<>	149:156823d33999	1398
<>	149:156823d33999	1399	/**
<>	149:156823d33999	1400	* @brief Set the polarity of an output channel.
<>	149:156823d33999	1401	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
<>	149:156823d33999	1402	* CCER CC2P LL_TIM_OC_SetPolarity\n
<>	149:156823d33999	1403	* CCER CC3P LL_TIM_OC_SetPolarity\n
<>	149:156823d33999	1404	* CCER CC4P LL_TIM_OC_SetPolarity
<>	149:156823d33999	1405	* @param TIMx Timer instance
<>	149:156823d33999	1406	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1407	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1408	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1409	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1410	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1411	* @param Polarity This parameter can be one of the following values:
<>	149:156823d33999	1412	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	149:156823d33999	1413	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	149:156823d33999	1414	* @retval None
<>	149:156823d33999	1415	*/
<>	149:156823d33999	1416	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
<>	149:156823d33999	1417	{
<>	149:156823d33999	1418	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1419	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
<>	149:156823d33999	1420	}
<>	149:156823d33999	1421
<>	149:156823d33999	1422	/**
<>	149:156823d33999	1423	* @brief Get the polarity of an output channel.
<>	149:156823d33999	1424	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
<>	149:156823d33999	1425	* CCER CC2P LL_TIM_OC_GetPolarity\n
<>	149:156823d33999	1426	* CCER CC3P LL_TIM_OC_GetPolarity\n
<>	149:156823d33999	1427	* CCER CC4P LL_TIM_OC_GetPolarity
<>	149:156823d33999	1428	* @param TIMx Timer instance
<>	149:156823d33999	1429	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1430	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1431	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1432	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1433	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1434	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1435	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	149:156823d33999	1436	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	149:156823d33999	1437	*/
<>	149:156823d33999	1438	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1439	{
<>	149:156823d33999	1440	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1441	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<>	149:156823d33999	1442	}
<>	149:156823d33999	1443
<>	149:156823d33999	1444	/**
<>	149:156823d33999	1445	* @brief Enable fast mode for the output channel.
<>	149:156823d33999	1446	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
<>	149:156823d33999	1447	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
<>	149:156823d33999	1448	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
<>	149:156823d33999	1449	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
<>	149:156823d33999	1450	* CCMR2 OC4FE LL_TIM_OC_EnableFast
<>	149:156823d33999	1451	* @param TIMx Timer instance
<>	149:156823d33999	1452	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1453	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1454	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1455	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1456	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1457	* @retval None
<>	149:156823d33999	1458	*/
<>	149:156823d33999	1459	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1460	{
<>	149:156823d33999	1461	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1462	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1463	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	149:156823d33999	1464
<>	149:156823d33999	1465	}
<>	149:156823d33999	1466
<>	149:156823d33999	1467	/**
<>	149:156823d33999	1468	* @brief Disable fast mode for the output channel.
<>	149:156823d33999	1469	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
<>	149:156823d33999	1470	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
<>	149:156823d33999	1471	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
<>	149:156823d33999	1472	* CCMR2 OC4FE LL_TIM_OC_DisableFast
<>	149:156823d33999	1473	* @param TIMx Timer instance
<>	149:156823d33999	1474	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1475	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1476	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1477	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1478	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1479	* @retval None
<>	149:156823d33999	1480	*/
<>	149:156823d33999	1481	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1482	{
<>	149:156823d33999	1483	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1484	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1485	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	149:156823d33999	1486
<>	149:156823d33999	1487	}
<>	149:156823d33999	1488
<>	149:156823d33999	1489	/**
<>	149:156823d33999	1490	* @brief Indicates whether fast mode is enabled for the output channel.
<>	149:156823d33999	1491	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
<>	149:156823d33999	1492	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
<>	149:156823d33999	1493	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
<>	149:156823d33999	1494	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
<>	149:156823d33999	1495	* @param TIMx Timer instance
<>	149:156823d33999	1496	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1497	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1498	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1499	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1500	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1501	* @retval State of bit (1 or 0).
<>	149:156823d33999	1502	*/
<>	149:156823d33999	1503	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1504	{
<>	149:156823d33999	1505	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1506	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1507	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
<>	149:156823d33999	1508	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	149:156823d33999	1509	}
<>	149:156823d33999	1510
<>	149:156823d33999	1511	/**
<>	149:156823d33999	1512	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
<>	149:156823d33999	1513	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
<>	149:156823d33999	1514	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
<>	149:156823d33999	1515	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
<>	149:156823d33999	1516	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
<>	149:156823d33999	1517	* @param TIMx Timer instance
<>	149:156823d33999	1518	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1519	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1520	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1521	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1522	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1523	* @retval None
<>	149:156823d33999	1524	*/
<>	149:156823d33999	1525	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1526	{
<>	149:156823d33999	1527	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1528	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1529	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	149:156823d33999	1530	}
<>	149:156823d33999	1531
<>	149:156823d33999	1532	/**
<>	149:156823d33999	1533	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
<>	149:156823d33999	1534	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
<>	149:156823d33999	1535	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
<>	149:156823d33999	1536	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
<>	149:156823d33999	1537	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
<>	149:156823d33999	1538	* @param TIMx Timer instance
<>	149:156823d33999	1539	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1540	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1541	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1542	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1543	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1544	* @retval None
<>	149:156823d33999	1545	*/
<>	149:156823d33999	1546	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1547	{
<>	149:156823d33999	1548	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1549	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1550	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	149:156823d33999	1551	}
<>	149:156823d33999	1552
<>	149:156823d33999	1553	/**
<>	149:156823d33999	1554	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
<>	149:156823d33999	1555	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
<>	149:156823d33999	1556	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
<>	149:156823d33999	1557	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
<>	149:156823d33999	1558	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
<>	149:156823d33999	1559	* @param TIMx Timer instance
<>	149:156823d33999	1560	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1561	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1562	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1563	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1564	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1565	* @retval State of bit (1 or 0).
<>	149:156823d33999	1566	*/
<>	149:156823d33999	1567	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1568	{
<>	149:156823d33999	1569	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1570	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1571	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
<>	149:156823d33999	1572	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	149:156823d33999	1573	}
<>	149:156823d33999	1574
<>	149:156823d33999	1575	/**
<>	149:156823d33999	1576	* @brief Enable clearing the output channel on an external event.
<>	149:156823d33999	1577	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	149:156823d33999	1578	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	149:156823d33999	1579	* or not a timer instance can clear the OCxREF signal on an external event.
<>	149:156823d33999	1580	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
<>	149:156823d33999	1581	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
<>	149:156823d33999	1582	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
<>	149:156823d33999	1583	* CCMR2 OC4CE LL_TIM_OC_EnableClear
<>	149:156823d33999	1584	* @param TIMx Timer instance
<>	149:156823d33999	1585	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1586	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1587	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1588	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1589	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1590	* @retval None
<>	149:156823d33999	1591	*/
<>	149:156823d33999	1592	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1593	{
<>	149:156823d33999	1594	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1595	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1596	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	149:156823d33999	1597	}
<>	149:156823d33999	1598
<>	149:156823d33999	1599	/**
<>	149:156823d33999	1600	* @brief Disable clearing the output channel on an external event.
<>	149:156823d33999	1601	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	149:156823d33999	1602	* or not a timer instance can clear the OCxREF signal on an external event.
<>	149:156823d33999	1603	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
<>	149:156823d33999	1604	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
<>	149:156823d33999	1605	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
<>	149:156823d33999	1606	* CCMR2 OC4CE LL_TIM_OC_DisableClear
<>	149:156823d33999	1607	* @param TIMx Timer instance
<>	149:156823d33999	1608	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1609	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1610	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1611	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1612	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1613	* @retval None
<>	149:156823d33999	1614	*/
<>	149:156823d33999	1615	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1616	{
<>	149:156823d33999	1617	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1618	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1619	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	149:156823d33999	1620	}
<>	149:156823d33999	1621
<>	149:156823d33999	1622	/**
<>	149:156823d33999	1623	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
<>	149:156823d33999	1624	* @note This function enables clearing the output channel on an external event.
<>	149:156823d33999	1625	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	149:156823d33999	1626	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	149:156823d33999	1627	* or not a timer instance can clear the OCxREF signal on an external event.
<>	149:156823d33999	1628	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
<>	149:156823d33999	1629	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
<>	149:156823d33999	1630	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
<>	149:156823d33999	1631	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
<>	149:156823d33999	1632	* @param TIMx Timer instance
<>	149:156823d33999	1633	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1634	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1635	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1636	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1637	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1638	* @retval State of bit (1 or 0).
<>	149:156823d33999	1639	*/
<>	149:156823d33999	1640	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1641	{
<>	149:156823d33999	1642	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1643	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1644	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
<>	149:156823d33999	1645	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	149:156823d33999	1646	}
<>	149:156823d33999	1647
<>	149:156823d33999	1648	/**
<>	149:156823d33999	1649	* @brief Set compare value for output channel 1 (TIMx_CCR1).
<>	149:156823d33999	1650	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1651	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1652	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1653	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1654	* output channel 1 is supported by a timer instance.
<>	149:156823d33999	1655	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
<>	149:156823d33999	1656	* @param TIMx Timer instance
<>	149:156823d33999	1657	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	149:156823d33999	1658	* @retval None
<>	149:156823d33999	1659	*/
<>	149:156823d33999	1660	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	149:156823d33999	1661	{
<>	149:156823d33999	1662	WRITE_REG(TIMx->CCR1, CompareValue);
<>	149:156823d33999	1663	}
<>	149:156823d33999	1664
<>	149:156823d33999	1665	/**
<>	149:156823d33999	1666	* @brief Set compare value for output channel 2 (TIMx_CCR2).
<>	149:156823d33999	1667	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1668	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1669	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1670	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1671	* output channel 2 is supported by a timer instance.
<>	149:156823d33999	1672	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
<>	149:156823d33999	1673	* @param TIMx Timer instance
<>	149:156823d33999	1674	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	149:156823d33999	1675	* @retval None
<>	149:156823d33999	1676	*/
<>	149:156823d33999	1677	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	149:156823d33999	1678	{
<>	149:156823d33999	1679	WRITE_REG(TIMx->CCR2, CompareValue);
<>	149:156823d33999	1680	}
<>	149:156823d33999	1681
<>	149:156823d33999	1682	/**
<>	149:156823d33999	1683	* @brief Set compare value for output channel 3 (TIMx_CCR3).
<>	149:156823d33999	1684	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1685	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1686	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1687	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1688	* output channel is supported by a timer instance.
<>	149:156823d33999	1689	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
<>	149:156823d33999	1690	* @param TIMx Timer instance
<>	149:156823d33999	1691	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	149:156823d33999	1692	* @retval None
<>	149:156823d33999	1693	*/
<>	149:156823d33999	1694	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	149:156823d33999	1695	{
<>	149:156823d33999	1696	WRITE_REG(TIMx->CCR3, CompareValue);
<>	149:156823d33999	1697	}
<>	149:156823d33999	1698
<>	149:156823d33999	1699	/**
<>	149:156823d33999	1700	* @brief Set compare value for output channel 4 (TIMx_CCR4).
<>	149:156823d33999	1701	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1702	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1703	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1704	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1705	* output channel 4 is supported by a timer instance.
<>	149:156823d33999	1706	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
<>	149:156823d33999	1707	* @param TIMx Timer instance
<>	149:156823d33999	1708	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	149:156823d33999	1709	* @retval None
<>	149:156823d33999	1710	*/
<>	149:156823d33999	1711	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	149:156823d33999	1712	{
<>	149:156823d33999	1713	WRITE_REG(TIMx->CCR4, CompareValue);
<>	149:156823d33999	1714	}
<>	149:156823d33999	1715
<>	149:156823d33999	1716	/**
<>	149:156823d33999	1717	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
<>	149:156823d33999	1718	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1719	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1720	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1721	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1722	* output channel 1 is supported by a timer instance.
<>	149:156823d33999	1723	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
<>	149:156823d33999	1724	* @param TIMx Timer instance
<>	149:156823d33999	1725	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	1726	*/
<>	149:156823d33999	1727	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
<>	149:156823d33999	1728	{
<>	149:156823d33999	1729	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	149:156823d33999	1730	}
<>	149:156823d33999	1731
<>	149:156823d33999	1732	/**
<>	149:156823d33999	1733	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
<>	149:156823d33999	1734	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1735	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1736	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1737	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1738	* output channel 2 is supported by a timer instance.
<>	149:156823d33999	1739	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
<>	149:156823d33999	1740	* @param TIMx Timer instance
<>	149:156823d33999	1741	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	1742	*/
<>	149:156823d33999	1743	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
<>	149:156823d33999	1744	{
<>	149:156823d33999	1745	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	149:156823d33999	1746	}
<>	149:156823d33999	1747
<>	149:156823d33999	1748	/**
<>	149:156823d33999	1749	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
<>	149:156823d33999	1750	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1751	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1752	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1753	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1754	* output channel 3 is supported by a timer instance.
<>	149:156823d33999	1755	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
<>	149:156823d33999	1756	* @param TIMx Timer instance
<>	149:156823d33999	1757	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	1758	*/
<>	149:156823d33999	1759	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
<>	149:156823d33999	1760	{
<>	149:156823d33999	1761	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	149:156823d33999	1762	}
<>	149:156823d33999	1763
<>	149:156823d33999	1764	/**
<>	149:156823d33999	1765	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
<>	149:156823d33999	1766	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	1767	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	1768	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	1769	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	1770	* output channel 4 is supported by a timer instance.
<>	149:156823d33999	1771	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
<>	149:156823d33999	1772	* @param TIMx Timer instance
<>	149:156823d33999	1773	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	1774	*/
<>	149:156823d33999	1775	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
<>	149:156823d33999	1776	{
<>	149:156823d33999	1777	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	149:156823d33999	1778	}
<>	149:156823d33999	1779
<>	149:156823d33999	1780	/**
<>	149:156823d33999	1781	* @}
<>	149:156823d33999	1782	*/
<>	149:156823d33999	1783
<>	149:156823d33999	1784	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
<>	149:156823d33999	1785	* @{
<>	149:156823d33999	1786	*/
<>	149:156823d33999	1787	/**
<>	149:156823d33999	1788	* @brief Configure input channel.
<>	149:156823d33999	1789	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
<>	149:156823d33999	1790	* CCMR1 IC1PSC LL_TIM_IC_Config\n
<>	149:156823d33999	1791	* CCMR1 IC1F LL_TIM_IC_Config\n
<>	149:156823d33999	1792	* CCMR1 CC2S LL_TIM_IC_Config\n
<>	149:156823d33999	1793	* CCMR1 IC2PSC LL_TIM_IC_Config\n
<>	149:156823d33999	1794	* CCMR1 IC2F LL_TIM_IC_Config\n
<>	149:156823d33999	1795	* CCMR2 CC3S LL_TIM_IC_Config\n
<>	149:156823d33999	1796	* CCMR2 IC3PSC LL_TIM_IC_Config\n
<>	149:156823d33999	1797	* CCMR2 IC3F LL_TIM_IC_Config\n
<>	149:156823d33999	1798	* CCMR2 CC4S LL_TIM_IC_Config\n
<>	149:156823d33999	1799	* CCMR2 IC4PSC LL_TIM_IC_Config\n
<>	149:156823d33999	1800	* CCMR2 IC4F LL_TIM_IC_Config\n
<>	149:156823d33999	1801	* CCER CC1P LL_TIM_IC_Config\n
<>	149:156823d33999	1802	* CCER CC1NP LL_TIM_IC_Config\n
<>	149:156823d33999	1803	* CCER CC2P LL_TIM_IC_Config\n
<>	149:156823d33999	1804	* CCER CC2NP LL_TIM_IC_Config\n
<>	149:156823d33999	1805	* CCER CC3P LL_TIM_IC_Config\n
<>	149:156823d33999	1806	* CCER CC3NP LL_TIM_IC_Config\n
<>	149:156823d33999	1807	* CCER CC4P LL_TIM_IC_Config\n
<>	149:156823d33999	1808	* CCER CC4NP LL_TIM_IC_Config
<>	149:156823d33999	1809	* @param TIMx Timer instance
<>	149:156823d33999	1810	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1811	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1812	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1813	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1814	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1815	* @param Configuration This parameter must be a combination of all the following values:
<>	149:156823d33999	1816	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
<>	149:156823d33999	1817	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
<>	149:156823d33999	1818	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	149:156823d33999	1819	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	149:156823d33999	1820	* @retval None
<>	149:156823d33999	1821	*/
<>	149:156823d33999	1822	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	149:156823d33999	1823	{
<>	149:156823d33999	1824	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1825	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1826	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
<>	149:156823d33999	1827	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
<>	149:156823d33999	1828	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	149:156823d33999	1829	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
<>	149:156823d33999	1830	}
<>	149:156823d33999	1831
<>	149:156823d33999	1832	/**
<>	149:156823d33999	1833	* @brief Set the active input.
<>	149:156823d33999	1834	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
<>	149:156823d33999	1835	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
<>	149:156823d33999	1836	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
<>	149:156823d33999	1837	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
<>	149:156823d33999	1838	* @param TIMx Timer instance
<>	149:156823d33999	1839	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1840	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1841	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1842	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1843	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1844	* @param ICActiveInput This parameter can be one of the following values:
<>	149:156823d33999	1845	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	149:156823d33999	1846	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	149:156823d33999	1847	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	149:156823d33999	1848	* @retval None
<>	149:156823d33999	1849	*/
<>	149:156823d33999	1850	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
<>	149:156823d33999	1851	{
<>	149:156823d33999	1852	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1853	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1854	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	149:156823d33999	1855	}
<>	149:156823d33999	1856
<>	149:156823d33999	1857	/**
<>	149:156823d33999	1858	* @brief Get the current active input.
<>	149:156823d33999	1859	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
<>	149:156823d33999	1860	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
<>	149:156823d33999	1861	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
<>	149:156823d33999	1862	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
<>	149:156823d33999	1863	* @param TIMx Timer instance
<>	149:156823d33999	1864	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1865	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1866	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1867	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1868	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1869	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1870	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	149:156823d33999	1871	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	149:156823d33999	1872	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	149:156823d33999	1873	*/
<>	149:156823d33999	1874	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1875	{
<>	149:156823d33999	1876	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1877	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1878	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	149:156823d33999	1879	}
<>	149:156823d33999	1880
<>	149:156823d33999	1881	/**
<>	149:156823d33999	1882	* @brief Set the prescaler of input channel.
<>	149:156823d33999	1883	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
<>	149:156823d33999	1884	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
<>	149:156823d33999	1885	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
<>	149:156823d33999	1886	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
<>	149:156823d33999	1887	* @param TIMx Timer instance
<>	149:156823d33999	1888	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1889	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1890	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1891	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1892	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1893	* @param ICPrescaler This parameter can be one of the following values:
<>	149:156823d33999	1894	* @arg @ref LL_TIM_ICPSC_DIV1
<>	149:156823d33999	1895	* @arg @ref LL_TIM_ICPSC_DIV2
<>	149:156823d33999	1896	* @arg @ref LL_TIM_ICPSC_DIV4
<>	149:156823d33999	1897	* @arg @ref LL_TIM_ICPSC_DIV8
<>	149:156823d33999	1898	* @retval None
<>	149:156823d33999	1899	*/
<>	149:156823d33999	1900	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
<>	149:156823d33999	1901	{
<>	149:156823d33999	1902	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1903	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1904	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	149:156823d33999	1905	}
<>	149:156823d33999	1906
<>	149:156823d33999	1907	/**
<>	149:156823d33999	1908	* @brief Get the current prescaler value acting on an input channel.
<>	149:156823d33999	1909	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
<>	149:156823d33999	1910	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
<>	149:156823d33999	1911	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
<>	149:156823d33999	1912	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
<>	149:156823d33999	1913	* @param TIMx Timer instance
<>	149:156823d33999	1914	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1915	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1916	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1917	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1918	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1919	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1920	* @arg @ref LL_TIM_ICPSC_DIV1
<>	149:156823d33999	1921	* @arg @ref LL_TIM_ICPSC_DIV2
<>	149:156823d33999	1922	* @arg @ref LL_TIM_ICPSC_DIV4
<>	149:156823d33999	1923	* @arg @ref LL_TIM_ICPSC_DIV8
<>	149:156823d33999	1924	*/
<>	149:156823d33999	1925	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	1926	{
<>	149:156823d33999	1927	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1928	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1929	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	149:156823d33999	1930	}
<>	149:156823d33999	1931
<>	149:156823d33999	1932	/**
<>	149:156823d33999	1933	* @brief Set the input filter duration.
<>	149:156823d33999	1934	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
<>	149:156823d33999	1935	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
<>	149:156823d33999	1936	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
<>	149:156823d33999	1937	* CCMR2 IC4F LL_TIM_IC_SetFilter
<>	149:156823d33999	1938	* @param TIMx Timer instance
<>	149:156823d33999	1939	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1940	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1941	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1942	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1943	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1944	* @param ICFilter This parameter can be one of the following values:
<>	149:156823d33999	1945	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	149:156823d33999	1946	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	149:156823d33999	1947	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	149:156823d33999	1948	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	149:156823d33999	1949	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	149:156823d33999	1950	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	149:156823d33999	1951	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	149:156823d33999	1952	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	149:156823d33999	1953	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	149:156823d33999	1954	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	149:156823d33999	1955	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	149:156823d33999	1956	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	149:156823d33999	1957	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	149:156823d33999	1958	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	149:156823d33999	1959	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	149:156823d33999	1960	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	149:156823d33999	1961	* @retval None
<>	149:156823d33999	1962	*/
<>	149:156823d33999	1963	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
<>	149:156823d33999	1964	{
<>	149:156823d33999	1965	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	1966	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	1967	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	149:156823d33999	1968	}
<>	149:156823d33999	1969
<>	149:156823d33999	1970	/**
<>	149:156823d33999	1971	* @brief Get the input filter duration.
<>	149:156823d33999	1972	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
<>	149:156823d33999	1973	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
<>	149:156823d33999	1974	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
<>	149:156823d33999	1975	* CCMR2 IC4F LL_TIM_IC_GetFilter
<>	149:156823d33999	1976	* @param TIMx Timer instance
<>	149:156823d33999	1977	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	1978	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	1979	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	1980	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	1981	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	1982	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1983	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	149:156823d33999	1984	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	149:156823d33999	1985	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	149:156823d33999	1986	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	149:156823d33999	1987	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	149:156823d33999	1988	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	149:156823d33999	1989	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	149:156823d33999	1990	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	149:156823d33999	1991	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	149:156823d33999	1992	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	149:156823d33999	1993	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	149:156823d33999	1994	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	149:156823d33999	1995	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	149:156823d33999	1996	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	149:156823d33999	1997	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	149:156823d33999	1998	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	149:156823d33999	1999	*/
<>	149:156823d33999	2000	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	2001	{
<>	149:156823d33999	2002	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	2003	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	149:156823d33999	2004	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	149:156823d33999	2005	}
<>	149:156823d33999	2006
<>	149:156823d33999	2007	/**
<>	149:156823d33999	2008	* @brief Set the input channel polarity.
<>	149:156823d33999	2009	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
<>	149:156823d33999	2010	* CCER CC1NP LL_TIM_IC_SetPolarity\n
<>	149:156823d33999	2011	* CCER CC2P LL_TIM_IC_SetPolarity\n
<>	149:156823d33999	2012	* CCER CC2NP LL_TIM_IC_SetPolarity\n
<>	149:156823d33999	2013	* CCER CC3P LL_TIM_IC_SetPolarity\n
<>	149:156823d33999	2014	* CCER CC3NP LL_TIM_IC_SetPolarity\n
<>	149:156823d33999	2015	* CCER CC4P LL_TIM_IC_SetPolarity\n
<>	149:156823d33999	2016	* CCER CC4NP LL_TIM_IC_SetPolarity
<>	149:156823d33999	2017	* @param TIMx Timer instance
<>	149:156823d33999	2018	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	2019	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	2020	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	2021	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	2022	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	2023	* @param ICPolarity This parameter can be one of the following values:
<>	149:156823d33999	2024	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	149:156823d33999	2025	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	149:156823d33999	2026	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	149:156823d33999	2027	* @retval None
<>	149:156823d33999	2028	*/
<>	149:156823d33999	2029	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
<>	149:156823d33999	2030	{
<>	149:156823d33999	2031	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	2032	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	149:156823d33999	2033	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
<>	149:156823d33999	2034	}
<>	149:156823d33999	2035
<>	149:156823d33999	2036	/**
<>	149:156823d33999	2037	* @brief Get the current input channel polarity.
<>	149:156823d33999	2038	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
<>	149:156823d33999	2039	* CCER CC1NP LL_TIM_IC_GetPolarity\n
<>	149:156823d33999	2040	* CCER CC2P LL_TIM_IC_GetPolarity\n
<>	149:156823d33999	2041	* CCER CC2NP LL_TIM_IC_GetPolarity\n
<>	149:156823d33999	2042	* CCER CC3P LL_TIM_IC_GetPolarity\n
<>	149:156823d33999	2043	* CCER CC3NP LL_TIM_IC_GetPolarity\n
<>	149:156823d33999	2044	* CCER CC4P LL_TIM_IC_GetPolarity\n
<>	149:156823d33999	2045	* CCER CC4NP LL_TIM_IC_GetPolarity
<>	149:156823d33999	2046	* @param TIMx Timer instance
<>	149:156823d33999	2047	* @param Channel This parameter can be one of the following values:
<>	149:156823d33999	2048	* @arg @ref LL_TIM_CHANNEL_CH1
<>	149:156823d33999	2049	* @arg @ref LL_TIM_CHANNEL_CH2
<>	149:156823d33999	2050	* @arg @ref LL_TIM_CHANNEL_CH3
<>	149:156823d33999	2051	* @arg @ref LL_TIM_CHANNEL_CH4
<>	149:156823d33999	2052	* @retval Returned value can be one of the following values:
<>	149:156823d33999	2053	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	149:156823d33999	2054	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	149:156823d33999	2055	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	149:156823d33999	2056	*/
<>	149:156823d33999	2057	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	149:156823d33999	2058	{
<>	149:156823d33999	2059	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	149:156823d33999	2060	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
<>	149:156823d33999	2061	SHIFT_TAB_CCxP[iChannel]);
<>	149:156823d33999	2062	}
<>	149:156823d33999	2063
<>	149:156823d33999	2064	/**
<>	149:156823d33999	2065	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
<>	149:156823d33999	2066	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2067	* a timer instance provides an XOR input.
<>	149:156823d33999	2068	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
<>	149:156823d33999	2069	* @param TIMx Timer instance
<>	149:156823d33999	2070	* @retval None
<>	149:156823d33999	2071	*/
<>	149:156823d33999	2072	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
<>	149:156823d33999	2073	{
<>	149:156823d33999	2074	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	149:156823d33999	2075	}
<>	149:156823d33999	2076
<>	149:156823d33999	2077	/**
<>	149:156823d33999	2078	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
<>	149:156823d33999	2079	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2080	* a timer instance provides an XOR input.
<>	149:156823d33999	2081	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
<>	149:156823d33999	2082	* @param TIMx Timer instance
<>	149:156823d33999	2083	* @retval None
<>	149:156823d33999	2084	*/
<>	149:156823d33999	2085	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
<>	149:156823d33999	2086	{
<>	149:156823d33999	2087	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	149:156823d33999	2088	}
<>	149:156823d33999	2089
<>	149:156823d33999	2090	/**
<>	149:156823d33999	2091	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
<>	149:156823d33999	2092	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2093	* a timer instance provides an XOR input.
<>	149:156823d33999	2094	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
<>	149:156823d33999	2095	* @param TIMx Timer instance
<>	149:156823d33999	2096	* @retval State of bit (1 or 0).
<>	149:156823d33999	2097	*/
<>	149:156823d33999	2098	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
<>	149:156823d33999	2099	{
<>	149:156823d33999	2100	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
<>	149:156823d33999	2101	}
<>	149:156823d33999	2102
<>	149:156823d33999	2103	/**
<>	149:156823d33999	2104	* @brief Get captured value for input channel 1.
<>	149:156823d33999	2105	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	2106	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2107	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	2108	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2109	* input channel 1 is supported by a timer instance.
<>	149:156823d33999	2110	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
<>	149:156823d33999	2111	* @param TIMx Timer instance
<>	149:156823d33999	2112	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	2113	*/
<>	149:156823d33999	2114	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
<>	149:156823d33999	2115	{
<>	149:156823d33999	2116	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	149:156823d33999	2117	}
<>	149:156823d33999	2118
<>	149:156823d33999	2119	/**
<>	149:156823d33999	2120	* @brief Get captured value for input channel 2.
<>	149:156823d33999	2121	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	2122	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2123	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	2124	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2125	* input channel 2 is supported by a timer instance.
<>	149:156823d33999	2126	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
<>	149:156823d33999	2127	* @param TIMx Timer instance
<>	149:156823d33999	2128	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	2129	*/
<>	149:156823d33999	2130	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
<>	149:156823d33999	2131	{
<>	149:156823d33999	2132	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	149:156823d33999	2133	}
<>	149:156823d33999	2134
<>	149:156823d33999	2135	/**
<>	149:156823d33999	2136	* @brief Get captured value for input channel 3.
<>	149:156823d33999	2137	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	2138	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2139	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	2140	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2141	* input channel 3 is supported by a timer instance.
<>	149:156823d33999	2142	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
<>	149:156823d33999	2143	* @param TIMx Timer instance
<>	149:156823d33999	2144	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	2145	*/
<>	149:156823d33999	2146	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
<>	149:156823d33999	2147	{
<>	149:156823d33999	2148	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	149:156823d33999	2149	}
<>	149:156823d33999	2150
<>	149:156823d33999	2151	/**
<>	149:156823d33999	2152	* @brief Get captured value for input channel 4.
<>	149:156823d33999	2153	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	149:156823d33999	2154	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2155	* whether or not a timer instance supports a 32 bits counter.
<>	149:156823d33999	2156	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2157	* input channel 4 is supported by a timer instance.
<>	149:156823d33999	2158	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
<>	149:156823d33999	2159	* @param TIMx Timer instance
<>	149:156823d33999	2160	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	149:156823d33999	2161	*/
<>	149:156823d33999	2162	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
<>	149:156823d33999	2163	{
<>	149:156823d33999	2164	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	149:156823d33999	2165	}
<>	149:156823d33999	2166
<>	149:156823d33999	2167	/**
<>	149:156823d33999	2168	* @}
<>	149:156823d33999	2169	*/
<>	149:156823d33999	2170
<>	149:156823d33999	2171	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
<>	149:156823d33999	2172	* @{
<>	149:156823d33999	2173	*/
<>	149:156823d33999	2174	/**
<>	149:156823d33999	2175	* @brief Enable external clock mode 2.
<>	149:156823d33999	2176	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
<>	149:156823d33999	2177	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2178	* whether or not a timer instance supports external clock mode2.
<>	149:156823d33999	2179	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
<>	149:156823d33999	2180	* @param TIMx Timer instance
<>	149:156823d33999	2181	* @retval None
<>	149:156823d33999	2182	*/
<>	149:156823d33999	2183	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
<>	149:156823d33999	2184	{
<>	149:156823d33999	2185	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	149:156823d33999	2186	}
<>	149:156823d33999	2187
<>	149:156823d33999	2188	/**
<>	149:156823d33999	2189	* @brief Disable external clock mode 2.
<>	149:156823d33999	2190	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2191	* whether or not a timer instance supports external clock mode2.
<>	149:156823d33999	2192	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
<>	149:156823d33999	2193	* @param TIMx Timer instance
<>	149:156823d33999	2194	* @retval None
<>	149:156823d33999	2195	*/
<>	149:156823d33999	2196	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
<>	149:156823d33999	2197	{
<>	149:156823d33999	2198	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	149:156823d33999	2199	}
<>	149:156823d33999	2200
<>	149:156823d33999	2201	/**
<>	149:156823d33999	2202	* @brief Indicate whether external clock mode 2 is enabled.
<>	149:156823d33999	2203	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2204	* whether or not a timer instance supports external clock mode2.
<>	149:156823d33999	2205	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
<>	149:156823d33999	2206	* @param TIMx Timer instance
<>	149:156823d33999	2207	* @retval State of bit (1 or 0).
<>	149:156823d33999	2208	*/
<>	149:156823d33999	2209	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
<>	149:156823d33999	2210	{
<>	149:156823d33999	2211	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
<>	149:156823d33999	2212	}
<>	149:156823d33999	2213
<>	149:156823d33999	2214	/**
<>	149:156823d33999	2215	* @brief Set the clock source of the counter clock.
<>	149:156823d33999	2216	* @note when selected clock source is external clock mode 1, the timer input
<>	149:156823d33999	2217	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
<>	149:156823d33999	2218	* function. This timer input must be configured by calling
<>	149:156823d33999	2219	* the @ref LL_TIM_IC_Config() function.
<>	149:156823d33999	2220	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2221	* whether or not a timer instance supports external clock mode1.
<>	149:156823d33999	2222	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2223	* whether or not a timer instance supports external clock mode2.
<>	149:156823d33999	2224	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
<>	149:156823d33999	2225	* SMCR ECE LL_TIM_SetClockSource
<>	149:156823d33999	2226	* @param TIMx Timer instance
<>	149:156823d33999	2227	* @param ClockSource This parameter can be one of the following values:
<>	149:156823d33999	2228	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
<>	149:156823d33999	2229	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
<>	149:156823d33999	2230	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
<>	149:156823d33999	2231	* @retval None
<>	149:156823d33999	2232	*/
<>	149:156823d33999	2233	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
<>	149:156823d33999	2234	{
<>	149:156823d33999	2235	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
<>	149:156823d33999	2236	}
<>	149:156823d33999	2237
<>	149:156823d33999	2238	/**
<>	149:156823d33999	2239	* @brief Set the encoder interface mode.
<>	149:156823d33999	2240	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2241	* whether or not a timer instance supports the encoder mode.
<>	149:156823d33999	2242	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
<>	149:156823d33999	2243	* @param TIMx Timer instance
<>	149:156823d33999	2244	* @param EncoderMode This parameter can be one of the following values:
<>	149:156823d33999	2245	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
<>	149:156823d33999	2246	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
<>	149:156823d33999	2247	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
<>	149:156823d33999	2248	* @retval None
<>	149:156823d33999	2249	*/
<>	149:156823d33999	2250	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
<>	149:156823d33999	2251	{
<>	149:156823d33999	2252	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
<>	149:156823d33999	2253	}
<>	149:156823d33999	2254
<>	149:156823d33999	2255	/**
<>	149:156823d33999	2256	* @}
<>	149:156823d33999	2257	*/
<>	149:156823d33999	2258
<>	149:156823d33999	2259	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
<>	149:156823d33999	2260	* @{
<>	149:156823d33999	2261	*/
<>	149:156823d33999	2262	/**
<>	149:156823d33999	2263	* @brief Set the trigger output (TRGO) used for timer synchronization .
<>	149:156823d33999	2264	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
<>	149:156823d33999	2265	* whether or not a timer instance can operate as a master timer.
<>	149:156823d33999	2266	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
<>	149:156823d33999	2267	* @param TIMx Timer instance
<>	149:156823d33999	2268	* @param TimerSynchronization This parameter can be one of the following values:
<>	149:156823d33999	2269	* @arg @ref LL_TIM_TRGO_RESET
<>	149:156823d33999	2270	* @arg @ref LL_TIM_TRGO_ENABLE
<>	149:156823d33999	2271	* @arg @ref LL_TIM_TRGO_UPDATE
<>	149:156823d33999	2272	* @arg @ref LL_TIM_TRGO_CC1IF
<>	149:156823d33999	2273	* @arg @ref LL_TIM_TRGO_OC1REF
<>	149:156823d33999	2274	* @arg @ref LL_TIM_TRGO_OC2REF
<>	149:156823d33999	2275	* @arg @ref LL_TIM_TRGO_OC3REF
<>	149:156823d33999	2276	* @arg @ref LL_TIM_TRGO_OC4REF
<>	149:156823d33999	2277	* @retval None
<>	149:156823d33999	2278	*/
<>	149:156823d33999	2279	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
<>	149:156823d33999	2280	{
<>	149:156823d33999	2281	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
<>	149:156823d33999	2282	}
<>	149:156823d33999	2283
<>	149:156823d33999	2284	/**
<>	149:156823d33999	2285	* @brief Set the synchronization mode of a slave timer.
<>	149:156823d33999	2286	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2287	* a timer instance can operate as a slave timer.
<>	149:156823d33999	2288	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
<>	149:156823d33999	2289	* @param TIMx Timer instance
<>	149:156823d33999	2290	* @param SlaveMode This parameter can be one of the following values:
<>	149:156823d33999	2291	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
<>	149:156823d33999	2292	* @arg @ref LL_TIM_SLAVEMODE_RESET
<>	149:156823d33999	2293	* @arg @ref LL_TIM_SLAVEMODE_GATED
<>	149:156823d33999	2294	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
<>	149:156823d33999	2295	* @retval None
<>	149:156823d33999	2296	*/
<>	149:156823d33999	2297	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
<>	149:156823d33999	2298	{
<>	149:156823d33999	2299	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
<>	149:156823d33999	2300	}
<>	149:156823d33999	2301
<>	149:156823d33999	2302	/**
<>	149:156823d33999	2303	* @brief Set the selects the trigger input to be used to synchronize the counter.
<>	149:156823d33999	2304	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2305	* a timer instance can operate as a slave timer.
<>	149:156823d33999	2306	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
<>	149:156823d33999	2307	* @param TIMx Timer instance
<>	149:156823d33999	2308	* @param TriggerInput This parameter can be one of the following values:
<>	149:156823d33999	2309	* @arg @ref LL_TIM_TS_ITR0
<>	149:156823d33999	2310	* @arg @ref LL_TIM_TS_ITR1
<>	149:156823d33999	2311	* @arg @ref LL_TIM_TS_ITR2
<>	149:156823d33999	2312	* @arg @ref LL_TIM_TS_ITR3
<>	149:156823d33999	2313	* @arg @ref LL_TIM_TS_TI1F_ED
<>	149:156823d33999	2314	* @arg @ref LL_TIM_TS_TI1FP1
<>	149:156823d33999	2315	* @arg @ref LL_TIM_TS_TI2FP2
<>	149:156823d33999	2316	* @arg @ref LL_TIM_TS_ETRF
<>	149:156823d33999	2317	* @retval None
<>	149:156823d33999	2318	*/
<>	149:156823d33999	2319	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
<>	149:156823d33999	2320	{
<>	149:156823d33999	2321	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
<>	149:156823d33999	2322	}
<>	149:156823d33999	2323
<>	149:156823d33999	2324	/**
<>	149:156823d33999	2325	* @brief Enable the Master/Slave mode.
<>	149:156823d33999	2326	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2327	* a timer instance can operate as a slave timer.
<>	149:156823d33999	2328	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
<>	149:156823d33999	2329	* @param TIMx Timer instance
<>	149:156823d33999	2330	* @retval None
<>	149:156823d33999	2331	*/
<>	149:156823d33999	2332	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	149:156823d33999	2333	{
<>	149:156823d33999	2334	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	149:156823d33999	2335	}
<>	149:156823d33999	2336
<>	149:156823d33999	2337	/**
<>	149:156823d33999	2338	* @brief Disable the Master/Slave mode.
<>	149:156823d33999	2339	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2340	* a timer instance can operate as a slave timer.
<>	149:156823d33999	2341	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
<>	149:156823d33999	2342	* @param TIMx Timer instance
<>	149:156823d33999	2343	* @retval None
<>	149:156823d33999	2344	*/
<>	149:156823d33999	2345	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	149:156823d33999	2346	{
<>	149:156823d33999	2347	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	149:156823d33999	2348	}
<>	149:156823d33999	2349
<>	149:156823d33999	2350	/**
<>	149:156823d33999	2351	* @brief Indicates whether the Master/Slave mode is enabled.
<>	149:156823d33999	2352	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2353	* a timer instance can operate as a slave timer.
<>	149:156823d33999	2354	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
<>	149:156823d33999	2355	* @param TIMx Timer instance
<>	149:156823d33999	2356	* @retval State of bit (1 or 0).
<>	149:156823d33999	2357	*/
<>	149:156823d33999	2358	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
<>	149:156823d33999	2359	{
<>	149:156823d33999	2360	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
<>	149:156823d33999	2361	}
<>	149:156823d33999	2362
<>	149:156823d33999	2363	/**
<>	149:156823d33999	2364	* @brief Configure the external trigger (ETR) input.
<>	149:156823d33999	2365	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2366	* a timer instance provides an external trigger input.
<>	149:156823d33999	2367	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
<>	149:156823d33999	2368	* SMCR ETPS LL_TIM_ConfigETR\n
<>	149:156823d33999	2369	* SMCR ETF LL_TIM_ConfigETR
<>	149:156823d33999	2370	* @param TIMx Timer instance
<>	149:156823d33999	2371	* @param ETRPolarity This parameter can be one of the following values:
<>	149:156823d33999	2372	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
<>	149:156823d33999	2373	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
<>	149:156823d33999	2374	* @param ETRPrescaler This parameter can be one of the following values:
<>	149:156823d33999	2375	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
<>	149:156823d33999	2376	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
<>	149:156823d33999	2377	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
<>	149:156823d33999	2378	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
<>	149:156823d33999	2379	* @param ETRFilter This parameter can be one of the following values:
<>	149:156823d33999	2380	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
<>	149:156823d33999	2381	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
<>	149:156823d33999	2382	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
<>	149:156823d33999	2383	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
<>	149:156823d33999	2384	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
<>	149:156823d33999	2385	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
<>	149:156823d33999	2386	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
<>	149:156823d33999	2387	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
<>	149:156823d33999	2388	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
<>	149:156823d33999	2389	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
<>	149:156823d33999	2390	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
<>	149:156823d33999	2391	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
<>	149:156823d33999	2392	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
<>	149:156823d33999	2393	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
<>	149:156823d33999	2394	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
<>	149:156823d33999	2395	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
<>	149:156823d33999	2396	* @retval None
<>	149:156823d33999	2397	*/
<>	149:156823d33999	2398	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
<>	149:156823d33999	2399	uint32_t ETRFilter)
<>	149:156823d33999	2400	{
<>	149:156823d33999	2401	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
<>	149:156823d33999	2402	}
<>	149:156823d33999	2403
<>	149:156823d33999	2404	/**
<>	149:156823d33999	2405	* @}
<>	149:156823d33999	2406	*/
<>	149:156823d33999	2407
<>	149:156823d33999	2408	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
<>	149:156823d33999	2409	* @{
<>	149:156823d33999	2410	*/
<>	149:156823d33999	2411	/**
<>	149:156823d33999	2412	* @brief Configures the timer DMA burst feature.
<>	149:156823d33999	2413	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
<>	149:156823d33999	2414	* not a timer instance supports the DMA burst mode.
<>	149:156823d33999	2415	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
<>	149:156823d33999	2416	* DCR DBA LL_TIM_ConfigDMABurst
<>	149:156823d33999	2417	* @param TIMx Timer instance
<>	149:156823d33999	2418	* @param DMABurstBaseAddress This parameter can be one of the following values:
<>	149:156823d33999	2419	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
<>	149:156823d33999	2420	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
<>	149:156823d33999	2421	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
<>	149:156823d33999	2422	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
<>	149:156823d33999	2423	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
<>	149:156823d33999	2424	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
<>	149:156823d33999	2425	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
<>	149:156823d33999	2426	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
<>	149:156823d33999	2427	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
<>	149:156823d33999	2428	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
<>	149:156823d33999	2429	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
<>	149:156823d33999	2430	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
<>	149:156823d33999	2431	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
<>	149:156823d33999	2432	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
<>	149:156823d33999	2433	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
<>	149:156823d33999	2434	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
<>	149:156823d33999	2435	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
<>	149:156823d33999	2436	* @param DMABurstLength This parameter can be one of the following values:
<>	149:156823d33999	2437	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
<>	149:156823d33999	2438	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
<>	149:156823d33999	2439	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
<>	149:156823d33999	2440	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
<>	149:156823d33999	2441	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
<>	149:156823d33999	2442	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
<>	149:156823d33999	2443	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
<>	149:156823d33999	2444	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
<>	149:156823d33999	2445	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
<>	149:156823d33999	2446	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
<>	149:156823d33999	2447	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
<>	149:156823d33999	2448	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
<>	149:156823d33999	2449	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
<>	149:156823d33999	2450	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
<>	149:156823d33999	2451	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
<>	149:156823d33999	2452	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
<>	149:156823d33999	2453	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
<>	149:156823d33999	2454	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
<>	149:156823d33999	2455	* @retval None
<>	149:156823d33999	2456	*/
<>	149:156823d33999	2457	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
<>	149:156823d33999	2458	{
<>	149:156823d33999	2459	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
<>	149:156823d33999	2460	}
<>	149:156823d33999	2461
<>	149:156823d33999	2462	/**
<>	149:156823d33999	2463	* @}
<>	149:156823d33999	2464	*/
<>	149:156823d33999	2465
<>	149:156823d33999	2466	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
<>	149:156823d33999	2467	* @{
<>	149:156823d33999	2468	*/
<>	149:156823d33999	2469	/**
<>	149:156823d33999	2470	* @brief Remap TIM inputs (input channel, internal/external triggers).
<>	149:156823d33999	2471	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
<>	149:156823d33999	2472	* a some timer inputs can be remapped.
<>	149:156823d33999	2473	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2474	* TIM3_OR ITR2_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2475	* TIM9_OR TI1_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2476	* TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2477	* TIM10_OR TI1_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2478	* TIM10_OR ETR_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2479	* TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n
<>	149:156823d33999	2480	* TIM11_OR TI1_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2481	* TIM11_OR ETR_RMP LL_TIM_SetRemap\n
<>	149:156823d33999	2482	* TIM11_OR TI1_RMP_RI LL_TIM_SetRemap
<>	149:156823d33999	2483	* @param TIMx Timer instance
<>	149:156823d33999	2484	* @param Remap Remap params depends on the TIMx. Description available only
<>	149:156823d33999	2485	* in CHM version of the User Manual (not in .pdf).
<>	149:156823d33999	2486	* Otherwise see Reference Manual description of OR registers.
<>	149:156823d33999	2487	*
<>	149:156823d33999	2488	* Below description summarizes "Timer Instance" and "Remap" param combinations:
<>	149:156823d33999	2489	*
<>	149:156823d33999	2490	* TIM2: any combination of ITR1_RMP where
<>	149:156823d33999	2491	*
<>	149:156823d33999	2492	* . . ITR1_RMP can be one of the following values
<>	149:156823d33999	2493	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**)
<>	149:156823d33999	2494	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**)
<>	149:156823d33999	2495	*
<>	149:156823d33999	2496	* TIM3: any combination of ITR2_RMP where
<>	149:156823d33999	2497	*
<>	149:156823d33999	2498	* . . ITR2_RMP can be one of the following values
<>	149:156823d33999	2499	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**)
<>	149:156823d33999	2500	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**)
<>	149:156823d33999	2501	*
<>	149:156823d33999	2502	* TIM9: any combination of TI1_RMP, ITR1_RMP where
<>	149:156823d33999	2503	*
<>	149:156823d33999	2504	* . . TI1_RMP can be one of the following values
<>	149:156823d33999	2505	* @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
<>	149:156823d33999	2506	* @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
<>	149:156823d33999	2507	*
<>	149:156823d33999	2508	* . . ITR1_RMP can be one of the following values
<>	149:156823d33999	2509	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*)
<>	149:156823d33999	2510	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*)
<>	149:156823d33999	2511	*
<>	149:156823d33999	2512	*
<>	149:156823d33999	2513	* TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
<>	149:156823d33999	2514	*
<>	149:156823d33999	2515	* . . TI1_RMP can be one of the following values
<>	149:156823d33999	2516	* @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
<>	149:156823d33999	2517	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
<>	149:156823d33999	2518	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
<>	149:156823d33999	2519	* @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
<>	149:156823d33999	2520	*
<>	149:156823d33999	2521	* . . ETR_RMP can be one of the following values
<>	149:156823d33999	2522	* @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*)
<>	149:156823d33999	2523	*
<>	149:156823d33999	2524	* . . TI1_RMP_RI can be one of the following values
<>	149:156823d33999	2525	* @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*)
<>	149:156823d33999	2526	*
<>	149:156823d33999	2527	*
<>	149:156823d33999	2528	* TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
<>	149:156823d33999	2529	*
<>	149:156823d33999	2530	* . . TI1_RMP can be one of the following values
<>	149:156823d33999	2531	* @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
<>	149:156823d33999	2532	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
<>	149:156823d33999	2533	* @arg @ref LL_TIM_TIM11_TI1_RMP
<>	149:156823d33999	2534	*
<>	149:156823d33999	2535	* . . ETR_RMP can be one of the following values
<>	149:156823d33999	2536	* @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*)
<>	149:156823d33999	2537	*
<>	149:156823d33999	2538	* . . TI1_RMP_RI can be one of the following values
<>	149:156823d33999	2539	* @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*)
<>	149:156823d33999	2540	*
<>	149:156823d33999	2541	* (*) value not available in all devices categories
<>	149:156823d33999	2542	* (**) register not available in all devices categories
<>	149:156823d33999	2543	*
<>	149:156823d33999	2544	* @note Option registers are available only for cat.3, cat.4 and cat.5 devices
<>	149:156823d33999	2545	* @retval None
<>	149:156823d33999	2546	*/
<>	149:156823d33999	2547	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
<>	149:156823d33999	2548	{
<>	149:156823d33999	2549	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
<>	149:156823d33999	2550	}
<>	149:156823d33999	2551
<>	149:156823d33999	2552	/**
<>	149:156823d33999	2553	* @}
<>	149:156823d33999	2554	*/
<>	149:156823d33999	2555
<>	149:156823d33999	2556	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
<>	149:156823d33999	2557	* @{
<>	149:156823d33999	2558	*/
<>	149:156823d33999	2559	/**
AnnaBridge	184:08ed48f1de7f	2560	* @brief Set the OCREF clear input source
<>	149:156823d33999	2561	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
<>	149:156823d33999	2562	* @note This function can only be used in Output compare and PWM modes.
<>	149:156823d33999	2563	* @note the ETR signal can be connected to the output of a comparator to be used for current handling
AnnaBridge	184:08ed48f1de7f	2564	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
<>	149:156823d33999	2565	* @param TIMx Timer instance
<>	149:156823d33999	2566	* @param OCRefClearInputSource This parameter can be one of the following values:
<>	149:156823d33999	2567	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
<>	149:156823d33999	2568	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
<>	149:156823d33999	2569	* @retval None
<>	149:156823d33999	2570	*/
<>	149:156823d33999	2571	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
<>	149:156823d33999	2572	{
<>	149:156823d33999	2573	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
<>	149:156823d33999	2574	}
<>	149:156823d33999	2575	/**
<>	149:156823d33999	2576	* @}
<>	149:156823d33999	2577	*/
<>	149:156823d33999	2578
<>	149:156823d33999	2579	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
<>	149:156823d33999	2580	* @{
<>	149:156823d33999	2581	*/
<>	149:156823d33999	2582	/**
<>	149:156823d33999	2583	* @brief Clear the update interrupt flag (UIF).
<>	149:156823d33999	2584	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
<>	149:156823d33999	2585	* @param TIMx Timer instance
<>	149:156823d33999	2586	* @retval None
<>	149:156823d33999	2587	*/
<>	149:156823d33999	2588	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	2589	{
<>	149:156823d33999	2590	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
<>	149:156823d33999	2591	}
<>	149:156823d33999	2592
<>	149:156823d33999	2593	/**
<>	149:156823d33999	2594	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
<>	149:156823d33999	2595	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
<>	149:156823d33999	2596	* @param TIMx Timer instance
<>	149:156823d33999	2597	* @retval State of bit (1 or 0).
<>	149:156823d33999	2598	*/
<>	149:156823d33999	2599	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	2600	{
<>	149:156823d33999	2601	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
<>	149:156823d33999	2602	}
<>	149:156823d33999	2603
<>	149:156823d33999	2604	/**
<>	149:156823d33999	2605	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
<>	149:156823d33999	2606	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
<>	149:156823d33999	2607	* @param TIMx Timer instance
<>	149:156823d33999	2608	* @retval None
<>	149:156823d33999	2609	*/
<>	149:156823d33999	2610	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	2611	{
<>	149:156823d33999	2612	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
<>	149:156823d33999	2613	}
<>	149:156823d33999	2614
<>	149:156823d33999	2615	/**
<>	149:156823d33999	2616	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
<>	149:156823d33999	2617	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
<>	149:156823d33999	2618	* @param TIMx Timer instance
<>	149:156823d33999	2619	* @retval State of bit (1 or 0).
<>	149:156823d33999	2620	*/
<>	149:156823d33999	2621	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	2622	{
<>	149:156823d33999	2623	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
<>	149:156823d33999	2624	}
<>	149:156823d33999	2625
<>	149:156823d33999	2626	/**
<>	149:156823d33999	2627	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
<>	149:156823d33999	2628	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
<>	149:156823d33999	2629	* @param TIMx Timer instance
<>	149:156823d33999	2630	* @retval None
<>	149:156823d33999	2631	*/
<>	149:156823d33999	2632	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	2633	{
<>	149:156823d33999	2634	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
<>	149:156823d33999	2635	}
<>	149:156823d33999	2636
<>	149:156823d33999	2637	/**
<>	149:156823d33999	2638	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
<>	149:156823d33999	2639	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
<>	149:156823d33999	2640	* @param TIMx Timer instance
<>	149:156823d33999	2641	* @retval State of bit (1 or 0).
<>	149:156823d33999	2642	*/
<>	149:156823d33999	2643	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	2644	{
<>	149:156823d33999	2645	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
<>	149:156823d33999	2646	}
<>	149:156823d33999	2647
<>	149:156823d33999	2648	/**
<>	149:156823d33999	2649	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
<>	149:156823d33999	2650	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
<>	149:156823d33999	2651	* @param TIMx Timer instance
<>	149:156823d33999	2652	* @retval None
<>	149:156823d33999	2653	*/
<>	149:156823d33999	2654	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	2655	{
<>	149:156823d33999	2656	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
<>	149:156823d33999	2657	}
<>	149:156823d33999	2658
<>	149:156823d33999	2659	/**
<>	149:156823d33999	2660	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
<>	149:156823d33999	2661	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
<>	149:156823d33999	2662	* @param TIMx Timer instance
<>	149:156823d33999	2663	* @retval State of bit (1 or 0).
<>	149:156823d33999	2664	*/
<>	149:156823d33999	2665	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	2666	{
<>	149:156823d33999	2667	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
<>	149:156823d33999	2668	}
<>	149:156823d33999	2669
<>	149:156823d33999	2670	/**
<>	149:156823d33999	2671	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
<>	149:156823d33999	2672	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
<>	149:156823d33999	2673	* @param TIMx Timer instance
<>	149:156823d33999	2674	* @retval None
<>	149:156823d33999	2675	*/
<>	149:156823d33999	2676	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	2677	{
<>	149:156823d33999	2678	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
<>	149:156823d33999	2679	}
<>	149:156823d33999	2680
<>	149:156823d33999	2681	/**
<>	149:156823d33999	2682	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
<>	149:156823d33999	2683	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
<>	149:156823d33999	2684	* @param TIMx Timer instance
<>	149:156823d33999	2685	* @retval State of bit (1 or 0).
<>	149:156823d33999	2686	*/
<>	149:156823d33999	2687	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	2688	{
<>	149:156823d33999	2689	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
<>	149:156823d33999	2690	}
<>	149:156823d33999	2691
<>	149:156823d33999	2692	/**
<>	149:156823d33999	2693	* @brief Clear the trigger interrupt flag (TIF).
<>	149:156823d33999	2694	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
<>	149:156823d33999	2695	* @param TIMx Timer instance
<>	149:156823d33999	2696	* @retval None
<>	149:156823d33999	2697	*/
<>	149:156823d33999	2698	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	2699	{
<>	149:156823d33999	2700	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
<>	149:156823d33999	2701	}
<>	149:156823d33999	2702
<>	149:156823d33999	2703	/**
<>	149:156823d33999	2704	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
<>	149:156823d33999	2705	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
<>	149:156823d33999	2706	* @param TIMx Timer instance
<>	149:156823d33999	2707	* @retval State of bit (1 or 0).
<>	149:156823d33999	2708	*/
<>	149:156823d33999	2709	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	2710	{
<>	149:156823d33999	2711	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
<>	149:156823d33999	2712	}
<>	149:156823d33999	2713
<>	149:156823d33999	2714	/**
<>	149:156823d33999	2715	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
<>	149:156823d33999	2716	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
<>	149:156823d33999	2717	* @param TIMx Timer instance
<>	149:156823d33999	2718	* @retval None
<>	149:156823d33999	2719	*/
<>	149:156823d33999	2720	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2721	{
<>	149:156823d33999	2722	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
<>	149:156823d33999	2723	}
<>	149:156823d33999	2724
<>	149:156823d33999	2725	/**
<>	149:156823d33999	2726	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
<>	149:156823d33999	2727	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
<>	149:156823d33999	2728	* @param TIMx Timer instance
<>	149:156823d33999	2729	* @retval State of bit (1 or 0).
<>	149:156823d33999	2730	*/
<>	149:156823d33999	2731	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2732	{
<>	149:156823d33999	2733	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
<>	149:156823d33999	2734	}
<>	149:156823d33999	2735
<>	149:156823d33999	2736	/**
<>	149:156823d33999	2737	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
<>	149:156823d33999	2738	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
<>	149:156823d33999	2739	* @param TIMx Timer instance
<>	149:156823d33999	2740	* @retval None
<>	149:156823d33999	2741	*/
<>	149:156823d33999	2742	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2743	{
<>	149:156823d33999	2744	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
<>	149:156823d33999	2745	}
<>	149:156823d33999	2746
<>	149:156823d33999	2747	/**
<>	149:156823d33999	2748	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
<>	149:156823d33999	2749	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
<>	149:156823d33999	2750	* @param TIMx Timer instance
<>	149:156823d33999	2751	* @retval State of bit (1 or 0).
<>	149:156823d33999	2752	*/
<>	149:156823d33999	2753	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2754	{
<>	149:156823d33999	2755	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
<>	149:156823d33999	2756	}
<>	149:156823d33999	2757
<>	149:156823d33999	2758	/**
<>	149:156823d33999	2759	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
<>	149:156823d33999	2760	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
<>	149:156823d33999	2761	* @param TIMx Timer instance
<>	149:156823d33999	2762	* @retval None
<>	149:156823d33999	2763	*/
<>	149:156823d33999	2764	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2765	{
<>	149:156823d33999	2766	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
<>	149:156823d33999	2767	}
<>	149:156823d33999	2768
<>	149:156823d33999	2769	/**
<>	149:156823d33999	2770	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
<>	149:156823d33999	2771	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
<>	149:156823d33999	2772	* @param TIMx Timer instance
<>	149:156823d33999	2773	* @retval State of bit (1 or 0).
<>	149:156823d33999	2774	*/
<>	149:156823d33999	2775	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2776	{
<>	149:156823d33999	2777	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
<>	149:156823d33999	2778	}
<>	149:156823d33999	2779
<>	149:156823d33999	2780	/**
<>	149:156823d33999	2781	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
<>	149:156823d33999	2782	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
<>	149:156823d33999	2783	* @param TIMx Timer instance
<>	149:156823d33999	2784	* @retval None
<>	149:156823d33999	2785	*/
<>	149:156823d33999	2786	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2787	{
<>	149:156823d33999	2788	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
<>	149:156823d33999	2789	}
<>	149:156823d33999	2790
<>	149:156823d33999	2791	/**
<>	149:156823d33999	2792	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
<>	149:156823d33999	2793	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
<>	149:156823d33999	2794	* @param TIMx Timer instance
<>	149:156823d33999	2795	* @retval State of bit (1 or 0).
<>	149:156823d33999	2796	*/
<>	149:156823d33999	2797	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	149:156823d33999	2798	{
<>	149:156823d33999	2799	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
<>	149:156823d33999	2800	}
<>	149:156823d33999	2801
<>	149:156823d33999	2802	/**
<>	149:156823d33999	2803	* @}
<>	149:156823d33999	2804	*/
<>	149:156823d33999	2805
<>	149:156823d33999	2806	/** @defgroup TIM_LL_EF_IT_Management IT-Management
<>	149:156823d33999	2807	* @{
<>	149:156823d33999	2808	*/
<>	149:156823d33999	2809	/**
<>	149:156823d33999	2810	* @brief Enable update interrupt (UIE).
<>	149:156823d33999	2811	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
<>	149:156823d33999	2812	* @param TIMx Timer instance
<>	149:156823d33999	2813	* @retval None
<>	149:156823d33999	2814	*/
<>	149:156823d33999	2815	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	2816	{
<>	149:156823d33999	2817	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	149:156823d33999	2818	}
<>	149:156823d33999	2819
<>	149:156823d33999	2820	/**
<>	149:156823d33999	2821	* @brief Disable update interrupt (UIE).
<>	149:156823d33999	2822	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
<>	149:156823d33999	2823	* @param TIMx Timer instance
<>	149:156823d33999	2824	* @retval None
<>	149:156823d33999	2825	*/
<>	149:156823d33999	2826	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	2827	{
<>	149:156823d33999	2828	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	149:156823d33999	2829	}
<>	149:156823d33999	2830
<>	149:156823d33999	2831	/**
<>	149:156823d33999	2832	* @brief Indicates whether the update interrupt (UIE) is enabled.
<>	149:156823d33999	2833	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
<>	149:156823d33999	2834	* @param TIMx Timer instance
<>	149:156823d33999	2835	* @retval State of bit (1 or 0).
<>	149:156823d33999	2836	*/
<>	149:156823d33999	2837	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	2838	{
<>	149:156823d33999	2839	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
<>	149:156823d33999	2840	}
<>	149:156823d33999	2841
<>	149:156823d33999	2842	/**
<>	149:156823d33999	2843	* @brief Enable capture/compare 1 interrupt (CC1IE).
<>	149:156823d33999	2844	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
<>	149:156823d33999	2845	* @param TIMx Timer instance
<>	149:156823d33999	2846	* @retval None
<>	149:156823d33999	2847	*/
<>	149:156823d33999	2848	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	2849	{
<>	149:156823d33999	2850	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	149:156823d33999	2851	}
<>	149:156823d33999	2852
<>	149:156823d33999	2853	/**
<>	149:156823d33999	2854	* @brief Disable capture/compare 1 interrupt (CC1IE).
<>	149:156823d33999	2855	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
<>	149:156823d33999	2856	* @param TIMx Timer instance
<>	149:156823d33999	2857	* @retval None
<>	149:156823d33999	2858	*/
<>	149:156823d33999	2859	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	2860	{
<>	149:156823d33999	2861	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	149:156823d33999	2862	}
<>	149:156823d33999	2863
<>	149:156823d33999	2864	/**
<>	149:156823d33999	2865	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
<>	149:156823d33999	2866	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
<>	149:156823d33999	2867	* @param TIMx Timer instance
<>	149:156823d33999	2868	* @retval State of bit (1 or 0).
<>	149:156823d33999	2869	*/
<>	149:156823d33999	2870	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	2871	{
<>	149:156823d33999	2872	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
<>	149:156823d33999	2873	}
<>	149:156823d33999	2874
<>	149:156823d33999	2875	/**
<>	149:156823d33999	2876	* @brief Enable capture/compare 2 interrupt (CC2IE).
<>	149:156823d33999	2877	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
<>	149:156823d33999	2878	* @param TIMx Timer instance
<>	149:156823d33999	2879	* @retval None
<>	149:156823d33999	2880	*/
<>	149:156823d33999	2881	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	2882	{
<>	149:156823d33999	2883	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	149:156823d33999	2884	}
<>	149:156823d33999	2885
<>	149:156823d33999	2886	/**
<>	149:156823d33999	2887	* @brief Disable capture/compare 2 interrupt (CC2IE).
<>	149:156823d33999	2888	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
<>	149:156823d33999	2889	* @param TIMx Timer instance
<>	149:156823d33999	2890	* @retval None
<>	149:156823d33999	2891	*/
<>	149:156823d33999	2892	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	2893	{
<>	149:156823d33999	2894	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	149:156823d33999	2895	}
<>	149:156823d33999	2896
<>	149:156823d33999	2897	/**
<>	149:156823d33999	2898	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
<>	149:156823d33999	2899	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
<>	149:156823d33999	2900	* @param TIMx Timer instance
<>	149:156823d33999	2901	* @retval State of bit (1 or 0).
<>	149:156823d33999	2902	*/
<>	149:156823d33999	2903	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	2904	{
<>	149:156823d33999	2905	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
<>	149:156823d33999	2906	}
<>	149:156823d33999	2907
<>	149:156823d33999	2908	/**
<>	149:156823d33999	2909	* @brief Enable capture/compare 3 interrupt (CC3IE).
<>	149:156823d33999	2910	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
<>	149:156823d33999	2911	* @param TIMx Timer instance
<>	149:156823d33999	2912	* @retval None
<>	149:156823d33999	2913	*/
<>	149:156823d33999	2914	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	2915	{
<>	149:156823d33999	2916	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	149:156823d33999	2917	}
<>	149:156823d33999	2918
<>	149:156823d33999	2919	/**
<>	149:156823d33999	2920	* @brief Disable capture/compare 3 interrupt (CC3IE).
<>	149:156823d33999	2921	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
<>	149:156823d33999	2922	* @param TIMx Timer instance
<>	149:156823d33999	2923	* @retval None
<>	149:156823d33999	2924	*/
<>	149:156823d33999	2925	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	2926	{
<>	149:156823d33999	2927	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	149:156823d33999	2928	}
<>	149:156823d33999	2929
<>	149:156823d33999	2930	/**
<>	149:156823d33999	2931	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
<>	149:156823d33999	2932	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
<>	149:156823d33999	2933	* @param TIMx Timer instance
<>	149:156823d33999	2934	* @retval State of bit (1 or 0).
<>	149:156823d33999	2935	*/
<>	149:156823d33999	2936	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	2937	{
<>	149:156823d33999	2938	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
<>	149:156823d33999	2939	}
<>	149:156823d33999	2940
<>	149:156823d33999	2941	/**
<>	149:156823d33999	2942	* @brief Enable capture/compare 4 interrupt (CC4IE).
<>	149:156823d33999	2943	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
<>	149:156823d33999	2944	* @param TIMx Timer instance
<>	149:156823d33999	2945	* @retval None
<>	149:156823d33999	2946	*/
<>	149:156823d33999	2947	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	2948	{
<>	149:156823d33999	2949	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	149:156823d33999	2950	}
<>	149:156823d33999	2951
<>	149:156823d33999	2952	/**
<>	149:156823d33999	2953	* @brief Disable capture/compare 4 interrupt (CC4IE).
<>	149:156823d33999	2954	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
<>	149:156823d33999	2955	* @param TIMx Timer instance
<>	149:156823d33999	2956	* @retval None
<>	149:156823d33999	2957	*/
<>	149:156823d33999	2958	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	2959	{
<>	149:156823d33999	2960	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	149:156823d33999	2961	}
<>	149:156823d33999	2962
<>	149:156823d33999	2963	/**
<>	149:156823d33999	2964	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
<>	149:156823d33999	2965	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
<>	149:156823d33999	2966	* @param TIMx Timer instance
<>	149:156823d33999	2967	* @retval State of bit (1 or 0).
<>	149:156823d33999	2968	*/
<>	149:156823d33999	2969	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	2970	{
<>	149:156823d33999	2971	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
<>	149:156823d33999	2972	}
<>	149:156823d33999	2973
<>	149:156823d33999	2974	/**
<>	149:156823d33999	2975	* @brief Enable trigger interrupt (TIE).
<>	149:156823d33999	2976	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
<>	149:156823d33999	2977	* @param TIMx Timer instance
<>	149:156823d33999	2978	* @retval None
<>	149:156823d33999	2979	*/
<>	149:156823d33999	2980	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	2981	{
<>	149:156823d33999	2982	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	149:156823d33999	2983	}
<>	149:156823d33999	2984
<>	149:156823d33999	2985	/**
<>	149:156823d33999	2986	* @brief Disable trigger interrupt (TIE).
<>	149:156823d33999	2987	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
<>	149:156823d33999	2988	* @param TIMx Timer instance
<>	149:156823d33999	2989	* @retval None
<>	149:156823d33999	2990	*/
<>	149:156823d33999	2991	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	2992	{
<>	149:156823d33999	2993	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	149:156823d33999	2994	}
<>	149:156823d33999	2995
<>	149:156823d33999	2996	/**
<>	149:156823d33999	2997	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
<>	149:156823d33999	2998	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
<>	149:156823d33999	2999	* @param TIMx Timer instance
<>	149:156823d33999	3000	* @retval State of bit (1 or 0).
<>	149:156823d33999	3001	*/
<>	149:156823d33999	3002	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	3003	{
<>	149:156823d33999	3004	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
<>	149:156823d33999	3005	}
<>	149:156823d33999	3006
<>	149:156823d33999	3007	/**
<>	149:156823d33999	3008	* @}
<>	149:156823d33999	3009	*/
<>	149:156823d33999	3010
<>	149:156823d33999	3011	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
<>	149:156823d33999	3012	* @{
<>	149:156823d33999	3013	*/
<>	149:156823d33999	3014	/**
<>	149:156823d33999	3015	* @brief Enable update DMA request (UDE).
<>	149:156823d33999	3016	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
<>	149:156823d33999	3017	* @param TIMx Timer instance
<>	149:156823d33999	3018	* @retval None
<>	149:156823d33999	3019	*/
<>	149:156823d33999	3020	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	3021	{
<>	149:156823d33999	3022	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	149:156823d33999	3023	}
<>	149:156823d33999	3024
<>	149:156823d33999	3025	/**
<>	149:156823d33999	3026	* @brief Disable update DMA request (UDE).
<>	149:156823d33999	3027	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
<>	149:156823d33999	3028	* @param TIMx Timer instance
<>	149:156823d33999	3029	* @retval None
<>	149:156823d33999	3030	*/
<>	149:156823d33999	3031	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	3032	{
<>	149:156823d33999	3033	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	149:156823d33999	3034	}
<>	149:156823d33999	3035
<>	149:156823d33999	3036	/**
<>	149:156823d33999	3037	* @brief Indicates whether the update DMA request (UDE) is enabled.
<>	149:156823d33999	3038	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
<>	149:156823d33999	3039	* @param TIMx Timer instance
<>	149:156823d33999	3040	* @retval State of bit (1 or 0).
<>	149:156823d33999	3041	*/
<>	149:156823d33999	3042	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	3043	{
<>	149:156823d33999	3044	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
<>	149:156823d33999	3045	}
<>	149:156823d33999	3046
<>	149:156823d33999	3047	/**
<>	149:156823d33999	3048	* @brief Enable capture/compare 1 DMA request (CC1DE).
<>	149:156823d33999	3049	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
<>	149:156823d33999	3050	* @param TIMx Timer instance
<>	149:156823d33999	3051	* @retval None
<>	149:156823d33999	3052	*/
<>	149:156823d33999	3053	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	3054	{
<>	149:156823d33999	3055	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	149:156823d33999	3056	}
<>	149:156823d33999	3057
<>	149:156823d33999	3058	/**
<>	149:156823d33999	3059	* @brief Disable capture/compare 1 DMA request (CC1DE).
<>	149:156823d33999	3060	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
<>	149:156823d33999	3061	* @param TIMx Timer instance
<>	149:156823d33999	3062	* @retval None
<>	149:156823d33999	3063	*/
<>	149:156823d33999	3064	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	3065	{
<>	149:156823d33999	3066	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	149:156823d33999	3067	}
<>	149:156823d33999	3068
<>	149:156823d33999	3069	/**
<>	149:156823d33999	3070	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
<>	149:156823d33999	3071	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
<>	149:156823d33999	3072	* @param TIMx Timer instance
<>	149:156823d33999	3073	* @retval State of bit (1 or 0).
<>	149:156823d33999	3074	*/
<>	149:156823d33999	3075	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	3076	{
<>	149:156823d33999	3077	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
<>	149:156823d33999	3078	}
<>	149:156823d33999	3079
<>	149:156823d33999	3080	/**
<>	149:156823d33999	3081	* @brief Enable capture/compare 2 DMA request (CC2DE).
<>	149:156823d33999	3082	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
<>	149:156823d33999	3083	* @param TIMx Timer instance
<>	149:156823d33999	3084	* @retval None
<>	149:156823d33999	3085	*/
<>	149:156823d33999	3086	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	3087	{
<>	149:156823d33999	3088	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	149:156823d33999	3089	}
<>	149:156823d33999	3090
<>	149:156823d33999	3091	/**
<>	149:156823d33999	3092	* @brief Disable capture/compare 2 DMA request (CC2DE).
<>	149:156823d33999	3093	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
<>	149:156823d33999	3094	* @param TIMx Timer instance
<>	149:156823d33999	3095	* @retval None
<>	149:156823d33999	3096	*/
<>	149:156823d33999	3097	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	3098	{
<>	149:156823d33999	3099	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	149:156823d33999	3100	}
<>	149:156823d33999	3101
<>	149:156823d33999	3102	/**
<>	149:156823d33999	3103	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
<>	149:156823d33999	3104	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
<>	149:156823d33999	3105	* @param TIMx Timer instance
<>	149:156823d33999	3106	* @retval State of bit (1 or 0).
<>	149:156823d33999	3107	*/
<>	149:156823d33999	3108	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	3109	{
<>	149:156823d33999	3110	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
<>	149:156823d33999	3111	}
<>	149:156823d33999	3112
<>	149:156823d33999	3113	/**
<>	149:156823d33999	3114	* @brief Enable capture/compare 3 DMA request (CC3DE).
<>	149:156823d33999	3115	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
<>	149:156823d33999	3116	* @param TIMx Timer instance
<>	149:156823d33999	3117	* @retval None
<>	149:156823d33999	3118	*/
<>	149:156823d33999	3119	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	3120	{
<>	149:156823d33999	3121	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	149:156823d33999	3122	}
<>	149:156823d33999	3123
<>	149:156823d33999	3124	/**
<>	149:156823d33999	3125	* @brief Disable capture/compare 3 DMA request (CC3DE).
<>	149:156823d33999	3126	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
<>	149:156823d33999	3127	* @param TIMx Timer instance
<>	149:156823d33999	3128	* @retval None
<>	149:156823d33999	3129	*/
<>	149:156823d33999	3130	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	3131	{
<>	149:156823d33999	3132	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	149:156823d33999	3133	}
<>	149:156823d33999	3134
<>	149:156823d33999	3135	/**
<>	149:156823d33999	3136	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
<>	149:156823d33999	3137	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
<>	149:156823d33999	3138	* @param TIMx Timer instance
<>	149:156823d33999	3139	* @retval State of bit (1 or 0).
<>	149:156823d33999	3140	*/
<>	149:156823d33999	3141	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	3142	{
<>	149:156823d33999	3143	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
<>	149:156823d33999	3144	}
<>	149:156823d33999	3145
<>	149:156823d33999	3146	/**
<>	149:156823d33999	3147	* @brief Enable capture/compare 4 DMA request (CC4DE).
<>	149:156823d33999	3148	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
<>	149:156823d33999	3149	* @param TIMx Timer instance
<>	149:156823d33999	3150	* @retval None
<>	149:156823d33999	3151	*/
<>	149:156823d33999	3152	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	3153	{
<>	149:156823d33999	3154	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	149:156823d33999	3155	}
<>	149:156823d33999	3156
<>	149:156823d33999	3157	/**
<>	149:156823d33999	3158	* @brief Disable capture/compare 4 DMA request (CC4DE).
<>	149:156823d33999	3159	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
<>	149:156823d33999	3160	* @param TIMx Timer instance
<>	149:156823d33999	3161	* @retval None
<>	149:156823d33999	3162	*/
<>	149:156823d33999	3163	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	3164	{
<>	149:156823d33999	3165	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	149:156823d33999	3166	}
<>	149:156823d33999	3167
<>	149:156823d33999	3168	/**
<>	149:156823d33999	3169	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
<>	149:156823d33999	3170	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
<>	149:156823d33999	3171	* @param TIMx Timer instance
<>	149:156823d33999	3172	* @retval State of bit (1 or 0).
<>	149:156823d33999	3173	*/
<>	149:156823d33999	3174	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	3175	{
<>	149:156823d33999	3176	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
<>	149:156823d33999	3177	}
<>	149:156823d33999	3178
<>	149:156823d33999	3179	/**
<>	149:156823d33999	3180	* @brief Enable trigger interrupt (TDE).
<>	149:156823d33999	3181	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
<>	149:156823d33999	3182	* @param TIMx Timer instance
<>	149:156823d33999	3183	* @retval None
<>	149:156823d33999	3184	*/
<>	149:156823d33999	3185	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	3186	{
<>	149:156823d33999	3187	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	149:156823d33999	3188	}
<>	149:156823d33999	3189
<>	149:156823d33999	3190	/**
<>	149:156823d33999	3191	* @brief Disable trigger interrupt (TDE).
<>	149:156823d33999	3192	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
<>	149:156823d33999	3193	* @param TIMx Timer instance
<>	149:156823d33999	3194	* @retval None
<>	149:156823d33999	3195	*/
<>	149:156823d33999	3196	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	3197	{
<>	149:156823d33999	3198	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	149:156823d33999	3199	}
<>	149:156823d33999	3200
<>	149:156823d33999	3201	/**
<>	149:156823d33999	3202	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
<>	149:156823d33999	3203	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
<>	149:156823d33999	3204	* @param TIMx Timer instance
<>	149:156823d33999	3205	* @retval State of bit (1 or 0).
<>	149:156823d33999	3206	*/
<>	149:156823d33999	3207	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	3208	{
<>	149:156823d33999	3209	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
<>	149:156823d33999	3210	}
<>	149:156823d33999	3211
<>	149:156823d33999	3212	/**
<>	149:156823d33999	3213	* @}
<>	149:156823d33999	3214	*/
<>	149:156823d33999	3215
<>	149:156823d33999	3216	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
<>	149:156823d33999	3217	* @{
<>	149:156823d33999	3218	*/
<>	149:156823d33999	3219	/**
<>	149:156823d33999	3220	* @brief Generate an update event.
<>	149:156823d33999	3221	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
<>	149:156823d33999	3222	* @param TIMx Timer instance
<>	149:156823d33999	3223	* @retval None
<>	149:156823d33999	3224	*/
<>	149:156823d33999	3225	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
<>	149:156823d33999	3226	{
<>	149:156823d33999	3227	SET_BIT(TIMx->EGR, TIM_EGR_UG);
<>	149:156823d33999	3228	}
<>	149:156823d33999	3229
<>	149:156823d33999	3230	/**
<>	149:156823d33999	3231	* @brief Generate Capture/Compare 1 event.
<>	149:156823d33999	3232	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
<>	149:156823d33999	3233	* @param TIMx Timer instance
<>	149:156823d33999	3234	* @retval None
<>	149:156823d33999	3235	*/
<>	149:156823d33999	3236	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
<>	149:156823d33999	3237	{
<>	149:156823d33999	3238	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
<>	149:156823d33999	3239	}
<>	149:156823d33999	3240
<>	149:156823d33999	3241	/**
<>	149:156823d33999	3242	* @brief Generate Capture/Compare 2 event.
<>	149:156823d33999	3243	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
<>	149:156823d33999	3244	* @param TIMx Timer instance
<>	149:156823d33999	3245	* @retval None
<>	149:156823d33999	3246	*/
<>	149:156823d33999	3247	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
<>	149:156823d33999	3248	{
<>	149:156823d33999	3249	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
<>	149:156823d33999	3250	}
<>	149:156823d33999	3251
<>	149:156823d33999	3252	/**
<>	149:156823d33999	3253	* @brief Generate Capture/Compare 3 event.
<>	149:156823d33999	3254	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
<>	149:156823d33999	3255	* @param TIMx Timer instance
<>	149:156823d33999	3256	* @retval None
<>	149:156823d33999	3257	*/
<>	149:156823d33999	3258	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
<>	149:156823d33999	3259	{
<>	149:156823d33999	3260	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
<>	149:156823d33999	3261	}
<>	149:156823d33999	3262
<>	149:156823d33999	3263	/**
<>	149:156823d33999	3264	* @brief Generate Capture/Compare 4 event.
<>	149:156823d33999	3265	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
<>	149:156823d33999	3266	* @param TIMx Timer instance
<>	149:156823d33999	3267	* @retval None
<>	149:156823d33999	3268	*/
<>	149:156823d33999	3269	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
<>	149:156823d33999	3270	{
<>	149:156823d33999	3271	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
<>	149:156823d33999	3272	}
<>	149:156823d33999	3273
<>	149:156823d33999	3274	/**
<>	149:156823d33999	3275	* @brief Generate trigger event.
<>	149:156823d33999	3276	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
<>	149:156823d33999	3277	* @param TIMx Timer instance
<>	149:156823d33999	3278	* @retval None
<>	149:156823d33999	3279	*/
<>	149:156823d33999	3280	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
<>	149:156823d33999	3281	{
<>	149:156823d33999	3282	SET_BIT(TIMx->EGR, TIM_EGR_TG);
<>	149:156823d33999	3283	}
<>	149:156823d33999	3284
<>	149:156823d33999	3285	/**
<>	149:156823d33999	3286	* @}
<>	149:156823d33999	3287	*/
<>	149:156823d33999	3288
<>	149:156823d33999	3289	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	3290	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
<>	149:156823d33999	3291	* @{
<>	149:156823d33999	3292	*/
<>	149:156823d33999	3293
<>	149:156823d33999	3294	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
<>	149:156823d33999	3295	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
<>	149:156823d33999	3296	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
<>	149:156823d33999	3297	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
<>	149:156823d33999	3298	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
<>	149:156823d33999	3299	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<>	149:156823d33999	3300	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
<>	149:156823d33999	3301	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
<>	149:156823d33999	3302	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
<>	149:156823d33999	3303	/**
<>	149:156823d33999	3304	* @}
<>	149:156823d33999	3305	*/
<>	149:156823d33999	3306	#endif /* USE_FULL_LL_DRIVER */
<>	149:156823d33999	3307
<>	149:156823d33999	3308	/**
<>	149:156823d33999	3309	* @}
<>	149:156823d33999	3310	*/
<>	149:156823d33999	3311
<>	149:156823d33999	3312	/**
<>	149:156823d33999	3313	* @}
<>	149:156823d33999	3314	*/
<>	149:156823d33999	3315
<>	149:156823d33999	3316	#endif /* TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM9 \|\| TIM10 \|\| TIM11 TIM6 \|\| TIM7 */
<>	149:156823d33999	3317
<>	149:156823d33999	3318	/**
<>	149:156823d33999	3319	* @}
<>	149:156823d33999	3320	*/
<>	149:156823d33999	3321
<>	149:156823d33999	3322	#ifdef __cplusplus
<>	149:156823d33999	3323	}
<>	149:156823d33999	3324	#endif
<>	149:156823d33999	3325
<>	149:156823d33999	3326	#endif /* __STM32L1xx_LL_TIM_H */
<>	149:156823d33999	3327	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/