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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_spi.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief SPI LL module driver.
<> 149:156823d33999 6 ******************************************************************************
<> 149:156823d33999 7 * @attention
<> 149:156823d33999 8 *
AnnaBridge 184:08ed48f1de7f 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 12 * are permitted provided that the following conditions are met:
<> 149:156823d33999 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 14 * this list of conditions and the following disclaimer.
<> 149:156823d33999 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 17 * and/or other materials provided with the distribution.
<> 149:156823d33999 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 19 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 20 * without specific prior written permission.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 32 *
<> 149:156823d33999 33 ******************************************************************************
<> 149:156823d33999 34 */
<> 149:156823d33999 35 #if defined(USE_FULL_LL_DRIVER)
<> 149:156823d33999 36
<> 149:156823d33999 37 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 38 #include "stm32l1xx_ll_spi.h"
<> 149:156823d33999 39 #include "stm32l1xx_ll_bus.h"
<> 149:156823d33999 40 #include "stm32l1xx_ll_rcc.h"
<> 149:156823d33999 41
<> 149:156823d33999 42 #ifdef USE_FULL_ASSERT
<> 149:156823d33999 43 #include "stm32_assert.h"
<> 149:156823d33999 44 #else
<> 149:156823d33999 45 #define assert_param(expr) ((void)0U)
<> 149:156823d33999 46 #endif
<> 149:156823d33999 47
<> 149:156823d33999 48 /** @addtogroup STM32L1xx_LL_Driver
<> 149:156823d33999 49 * @{
<> 149:156823d33999 50 */
<> 149:156823d33999 51
<> 149:156823d33999 52 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
<> 149:156823d33999 53
<> 149:156823d33999 54 /** @addtogroup SPI_LL
<> 149:156823d33999 55 * @{
<> 149:156823d33999 56 */
<> 149:156823d33999 57
<> 149:156823d33999 58 /* Private types -------------------------------------------------------------*/
<> 149:156823d33999 59 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 60
<> 149:156823d33999 61 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 62 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
<> 149:156823d33999 63 * @{
<> 149:156823d33999 64 */
<> 149:156823d33999 65 /* SPI registers Masks */
<> 149:156823d33999 66 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
<> 149:156823d33999 67 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
<> 149:156823d33999 68 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
<> 149:156823d33999 69 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
<> 149:156823d33999 70 SPI_CR1_BIDIMODE)
<> 149:156823d33999 71 /**
<> 149:156823d33999 72 * @}
<> 149:156823d33999 73 */
<> 149:156823d33999 74
<> 149:156823d33999 75 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 76 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
<> 149:156823d33999 77 * @{
<> 149:156823d33999 78 */
<> 149:156823d33999 79 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
<> 149:156823d33999 80 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
<> 149:156823d33999 81 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
<> 149:156823d33999 82 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
<> 149:156823d33999 83
<> 149:156823d33999 84 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
<> 149:156823d33999 85 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
<> 149:156823d33999 86
<> 149:156823d33999 87 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
<> 149:156823d33999 88 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
<> 149:156823d33999 89
<> 149:156823d33999 90 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
<> 149:156823d33999 91 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
<> 149:156823d33999 92
<> 149:156823d33999 93 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
<> 149:156823d33999 94 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
<> 149:156823d33999 95
<> 149:156823d33999 96 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
<> 149:156823d33999 97 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
<> 149:156823d33999 98 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
<> 149:156823d33999 99
<> 149:156823d33999 100 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
<> 149:156823d33999 101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
<> 149:156823d33999 102 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
<> 149:156823d33999 103 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
<> 149:156823d33999 104 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
<> 149:156823d33999 105 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
<> 149:156823d33999 106 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
<> 149:156823d33999 107 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
<> 149:156823d33999 108
<> 149:156823d33999 109 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
<> 149:156823d33999 110 || ((__VALUE__) == LL_SPI_MSB_FIRST))
<> 149:156823d33999 111
<> 149:156823d33999 112 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
<> 149:156823d33999 113 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
<> 149:156823d33999 114
<> 149:156823d33999 115 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
<> 149:156823d33999 116
<> 149:156823d33999 117 /**
<> 149:156823d33999 118 * @}
<> 149:156823d33999 119 */
<> 149:156823d33999 120
<> 149:156823d33999 121 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 122
<> 149:156823d33999 123 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 124 /** @addtogroup SPI_LL_Exported_Functions
<> 149:156823d33999 125 * @{
<> 149:156823d33999 126 */
<> 149:156823d33999 127
<> 149:156823d33999 128 /** @addtogroup SPI_LL_EF_Init
<> 149:156823d33999 129 * @{
<> 149:156823d33999 130 */
<> 149:156823d33999 131
<> 149:156823d33999 132 /**
<> 149:156823d33999 133 * @brief De-initialize the SPI registers to their default reset values.
<> 149:156823d33999 134 * @param SPIx SPI Instance
<> 149:156823d33999 135 * @retval An ErrorStatus enumeration value:
<> 149:156823d33999 136 * - SUCCESS: SPI registers are de-initialized
<> 149:156823d33999 137 * - ERROR: SPI registers are not de-initialized
<> 149:156823d33999 138 */
<> 149:156823d33999 139 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
<> 149:156823d33999 140 {
<> 149:156823d33999 141 ErrorStatus status = ERROR;
<> 149:156823d33999 142
<> 149:156823d33999 143 /* Check the parameters */
<> 149:156823d33999 144 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 149:156823d33999 145
<> 149:156823d33999 146 #if defined(SPI1)
<> 149:156823d33999 147 if (SPIx == SPI1)
<> 149:156823d33999 148 {
<> 149:156823d33999 149 /* Force reset of SPI clock */
<> 149:156823d33999 150 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
<> 149:156823d33999 151
<> 149:156823d33999 152 /* Release reset of SPI clock */
<> 149:156823d33999 153 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
<> 149:156823d33999 154
<> 149:156823d33999 155 status = SUCCESS;
<> 149:156823d33999 156 }
<> 149:156823d33999 157 #endif /* SPI1 */
<> 149:156823d33999 158 #if defined(SPI2)
<> 149:156823d33999 159 if (SPIx == SPI2)
<> 149:156823d33999 160 {
<> 149:156823d33999 161 /* Force reset of SPI clock */
<> 149:156823d33999 162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 149:156823d33999 163
<> 149:156823d33999 164 /* Release reset of SPI clock */
<> 149:156823d33999 165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 149:156823d33999 166
<> 149:156823d33999 167 status = SUCCESS;
<> 149:156823d33999 168 }
<> 149:156823d33999 169 #endif /* SPI2 */
<> 149:156823d33999 170 #if defined(SPI3)
<> 149:156823d33999 171 if (SPIx == SPI3)
<> 149:156823d33999 172 {
<> 149:156823d33999 173 /* Force reset of SPI clock */
<> 149:156823d33999 174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
<> 149:156823d33999 175
<> 149:156823d33999 176 /* Release reset of SPI clock */
<> 149:156823d33999 177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
<> 149:156823d33999 178
<> 149:156823d33999 179 status = SUCCESS;
<> 149:156823d33999 180 }
<> 149:156823d33999 181 #endif /* SPI3 */
<> 149:156823d33999 182
<> 149:156823d33999 183 return status;
<> 149:156823d33999 184 }
<> 149:156823d33999 185
<> 149:156823d33999 186 /**
<> 149:156823d33999 187 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
<> 149:156823d33999 188 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
<> 149:156823d33999 189 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 149:156823d33999 190 * @param SPIx SPI Instance
<> 149:156823d33999 191 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 149:156823d33999 192 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
<> 149:156823d33999 193 */
<> 149:156823d33999 194 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
<> 149:156823d33999 195 {
<> 149:156823d33999 196 ErrorStatus status = ERROR;
<> 149:156823d33999 197
<> 149:156823d33999 198 /* Check the SPI Instance SPIx*/
<> 149:156823d33999 199 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 149:156823d33999 200
<> 149:156823d33999 201 /* Check the SPI parameters from SPI_InitStruct*/
<> 149:156823d33999 202 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
<> 149:156823d33999 203 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
<> 149:156823d33999 204 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
<> 149:156823d33999 205 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
<> 149:156823d33999 206 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
<> 149:156823d33999 207 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
<> 149:156823d33999 208 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
<> 149:156823d33999 209 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
<> 149:156823d33999 210 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
<> 149:156823d33999 211
<> 149:156823d33999 212 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
<> 149:156823d33999 213 {
<> 149:156823d33999 214 /*---------------------------- SPIx CR1 Configuration ------------------------
<> 149:156823d33999 215 * Configure SPIx CR1 with parameters:
<> 149:156823d33999 216 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
<> 149:156823d33999 217 * - Master/Slave Mode: SPI_CR1_MSTR bit
<> 149:156823d33999 218 * - DataWidth: SPI_CR1_DFF bit
<> 149:156823d33999 219 * - ClockPolarity: SPI_CR1_CPOL bit
<> 149:156823d33999 220 * - ClockPhase: SPI_CR1_CPHA bit
<> 149:156823d33999 221 * - NSS management: SPI_CR1_SSM bit
<> 149:156823d33999 222 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
<> 149:156823d33999 223 * - BitOrder: SPI_CR1_LSBFIRST bit
<> 149:156823d33999 224 * - CRCCalculation: SPI_CR1_CRCEN bit
<> 149:156823d33999 225 */
<> 149:156823d33999 226 MODIFY_REG(SPIx->CR1,
<> 149:156823d33999 227 SPI_CR1_CLEAR_MASK,
<> 149:156823d33999 228 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
<> 149:156823d33999 229 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
<> 149:156823d33999 230 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
<> 149:156823d33999 231 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
<> 149:156823d33999 232
<> 149:156823d33999 233 /*---------------------------- SPIx CR2 Configuration ------------------------
<> 149:156823d33999 234 * Configure SPIx CR2 with parameters:
<> 149:156823d33999 235 * - NSS management: SSOE bit
<> 149:156823d33999 236 */
<> 149:156823d33999 237 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
<> 149:156823d33999 238
<> 149:156823d33999 239 /*---------------------------- SPIx CRCPR Configuration ----------------------
<> 149:156823d33999 240 * Configure SPIx CRCPR with parameters:
<> 149:156823d33999 241 * - CRCPoly: CRCPOLY[15:0] bits
<> 149:156823d33999 242 */
<> 149:156823d33999 243 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
<> 149:156823d33999 244 {
<> 149:156823d33999 245 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
<> 149:156823d33999 246 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
<> 149:156823d33999 247 }
<> 149:156823d33999 248 status = SUCCESS;
<> 149:156823d33999 249 }
<> 149:156823d33999 250
<> 149:156823d33999 251 #if defined (SPI_I2S_SUPPORT)
<> 149:156823d33999 252 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
<> 149:156823d33999 253 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 149:156823d33999 254 #endif /* SPI_I2S_SUPPORT */
<> 149:156823d33999 255 return status;
<> 149:156823d33999 256 }
<> 149:156823d33999 257
<> 149:156823d33999 258 /**
<> 149:156823d33999 259 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
<> 149:156823d33999 260 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 149:156823d33999 261 * whose fields will be set to default values.
<> 149:156823d33999 262 * @retval None
<> 149:156823d33999 263 */
<> 149:156823d33999 264 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
<> 149:156823d33999 265 {
<> 149:156823d33999 266 /* Set SPI_InitStruct fields to default values */
<> 149:156823d33999 267 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
<> 149:156823d33999 268 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
<> 149:156823d33999 269 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
<> 149:156823d33999 270 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
<> 149:156823d33999 271 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
<> 149:156823d33999 272 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
<> 149:156823d33999 273 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
<> 149:156823d33999 274 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
<> 149:156823d33999 275 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
<> 149:156823d33999 276 SPI_InitStruct->CRCPoly = 7U;
<> 149:156823d33999 277 }
<> 149:156823d33999 278
<> 149:156823d33999 279 /**
<> 149:156823d33999 280 * @}
<> 149:156823d33999 281 */
<> 149:156823d33999 282
<> 149:156823d33999 283 /**
<> 149:156823d33999 284 * @}
<> 149:156823d33999 285 */
<> 149:156823d33999 286
<> 149:156823d33999 287 /**
<> 149:156823d33999 288 * @}
<> 149:156823d33999 289 */
<> 149:156823d33999 290
<> 149:156823d33999 291 #if defined(SPI_I2S_SUPPORT)
<> 149:156823d33999 292 /** @addtogroup I2S_LL
<> 149:156823d33999 293 * @{
<> 149:156823d33999 294 */
<> 149:156823d33999 295
<> 149:156823d33999 296 /* Private types -------------------------------------------------------------*/
<> 149:156823d33999 297 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 298 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 299 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
<> 149:156823d33999 300 * @{
<> 149:156823d33999 301 */
<> 149:156823d33999 302 /* I2S registers Masks */
<> 149:156823d33999 303 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
<> 149:156823d33999 304 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
<> 149:156823d33999 305 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
<> 149:156823d33999 306
<> 149:156823d33999 307 #define I2S_I2SPR_CLEAR_MASK 0x0002U
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @}
<> 149:156823d33999 310 */
<> 149:156823d33999 311 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 312 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
<> 149:156823d33999 313 * @{
<> 149:156823d33999 314 */
<> 149:156823d33999 315
<> 149:156823d33999 316 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
<> 149:156823d33999 317 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
<> 149:156823d33999 318 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
<> 149:156823d33999 319 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
<> 149:156823d33999 320
<> 149:156823d33999 321 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
<> 149:156823d33999 322 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
<> 149:156823d33999 323
<> 149:156823d33999 324 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
<> 149:156823d33999 325 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
<> 149:156823d33999 326 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
<> 149:156823d33999 327 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
<> 149:156823d33999 328 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
<> 149:156823d33999 329
<> 149:156823d33999 330 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
<> 149:156823d33999 331 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
<> 149:156823d33999 332 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
<> 149:156823d33999 333 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
<> 149:156823d33999 334
<> 149:156823d33999 335 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
<> 149:156823d33999 336 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
<> 149:156823d33999 337
<> 149:156823d33999 338 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
<> 149:156823d33999 339 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
<> 149:156823d33999 340 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
<> 149:156823d33999 341
<> 149:156823d33999 342 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
<> 149:156823d33999 343
<> 149:156823d33999 344 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
<> 149:156823d33999 345 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
<> 149:156823d33999 346 /**
<> 149:156823d33999 347 * @}
<> 149:156823d33999 348 */
<> 149:156823d33999 349
<> 149:156823d33999 350 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 351
<> 149:156823d33999 352 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 353 /** @addtogroup I2S_LL_Exported_Functions
<> 149:156823d33999 354 * @{
<> 149:156823d33999 355 */
<> 149:156823d33999 356
<> 149:156823d33999 357 /** @addtogroup I2S_LL_EF_Init
<> 149:156823d33999 358 * @{
<> 149:156823d33999 359 */
<> 149:156823d33999 360
<> 149:156823d33999 361 /**
<> 149:156823d33999 362 * @brief De-initialize the SPI/I2S registers to their default reset values.
<> 149:156823d33999 363 * @param SPIx SPI Instance
<> 149:156823d33999 364 * @retval An ErrorStatus enumeration value:
<> 149:156823d33999 365 * - SUCCESS: SPI registers are de-initialized
<> 149:156823d33999 366 * - ERROR: SPI registers are not de-initialized
<> 149:156823d33999 367 */
<> 149:156823d33999 368 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
<> 149:156823d33999 369 {
<> 149:156823d33999 370 return LL_SPI_DeInit(SPIx);
<> 149:156823d33999 371 }
<> 149:156823d33999 372
<> 149:156823d33999 373 /**
<> 149:156823d33999 374 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
<> 149:156823d33999 375 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
<> 149:156823d33999 376 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 149:156823d33999 377 * @param SPIx SPI Instance
<> 149:156823d33999 378 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
<> 149:156823d33999 379 * @retval An ErrorStatus enumeration value:
<> 149:156823d33999 380 * - SUCCESS: SPI registers are Initialized
<> 149:156823d33999 381 * - ERROR: SPI registers are not Initialized
<> 149:156823d33999 382 */
<> 149:156823d33999 383 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
<> 149:156823d33999 384 {
<> 149:156823d33999 385 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
<> 149:156823d33999 386 uint32_t tmp = 0U;
<> 149:156823d33999 387 LL_RCC_ClocksTypeDef rcc_clocks;
<> 149:156823d33999 388 uint32_t sourceclock = 0U;
<> 149:156823d33999 389 ErrorStatus status = ERROR;
<> 149:156823d33999 390
<> 149:156823d33999 391 /* Check the I2S parameters */
<> 149:156823d33999 392 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
<> 149:156823d33999 393 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
<> 149:156823d33999 394 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
<> 149:156823d33999 395 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
<> 149:156823d33999 396 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
<> 149:156823d33999 397 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
<> 149:156823d33999 398 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
<> 149:156823d33999 399
<> 149:156823d33999 400 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
<> 149:156823d33999 401 {
<> 149:156823d33999 402 /*---------------------------- SPIx I2SCFGR Configuration --------------------
<> 149:156823d33999 403 * Configure SPIx I2SCFGR with parameters:
<> 149:156823d33999 404 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
<> 149:156823d33999 405 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
<> 149:156823d33999 406 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
<> 149:156823d33999 407 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
<> 149:156823d33999 408 */
<> 149:156823d33999 409
<> 149:156823d33999 410 /* Write to SPIx I2SCFGR */
<> 149:156823d33999 411 MODIFY_REG(SPIx->I2SCFGR,
<> 149:156823d33999 412 I2S_I2SCFGR_CLEAR_MASK,
<> 149:156823d33999 413 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
<> 149:156823d33999 414 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
<> 149:156823d33999 415 SPI_I2SCFGR_I2SMOD);
<> 149:156823d33999 416
<> 149:156823d33999 417 /*---------------------------- SPIx I2SPR Configuration ----------------------
<> 149:156823d33999 418 * Configure SPIx I2SPR with parameters:
<> 149:156823d33999 419 * - MCLKOutput: SPI_I2SPR_MCKOE bit
<> 149:156823d33999 420 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
<> 149:156823d33999 421 */
<> 149:156823d33999 422
AnnaBridge 184:08ed48f1de7f 423 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
AnnaBridge 184:08ed48f1de7f 424 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
AnnaBridge 184:08ed48f1de7f 425 */
AnnaBridge 184:08ed48f1de7f 426 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
<> 149:156823d33999 427 {
AnnaBridge 184:08ed48f1de7f 428 /* Check the frame length (For the Prescaler computing)
AnnaBridge 184:08ed48f1de7f 429 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
AnnaBridge 184:08ed48f1de7f 430 */
AnnaBridge 184:08ed48f1de7f 431 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
<> 149:156823d33999 432 {
<> 149:156823d33999 433 /* Packet length is 32 bits */
<> 149:156823d33999 434 packetlength = 2U;
<> 149:156823d33999 435 }
<> 149:156823d33999 436
<> 149:156823d33999 437 /* I2S Clock source is System clock: Get System Clock frequency */
<> 149:156823d33999 438 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
<> 149:156823d33999 439
<> 149:156823d33999 440 /* Get the source clock value: based on System Clock value */
<> 149:156823d33999 441 sourceclock = rcc_clocks.SYSCLK_Frequency;
<> 149:156823d33999 442
<> 149:156823d33999 443 /* Compute the Real divider depending on the MCLK output state with a floating point */
<> 149:156823d33999 444 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
<> 149:156823d33999 445 {
<> 149:156823d33999 446 /* MCLK output is enabled */
<> 149:156823d33999 447 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
<> 149:156823d33999 448 }
<> 149:156823d33999 449 else
<> 149:156823d33999 450 {
<> 149:156823d33999 451 /* MCLK output is disabled */
<> 149:156823d33999 452 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
<> 149:156823d33999 453 }
<> 149:156823d33999 454
<> 149:156823d33999 455 /* Remove the floating point */
<> 149:156823d33999 456 tmp = tmp / 10U;
<> 149:156823d33999 457
<> 149:156823d33999 458 /* Check the parity of the divider */
<> 149:156823d33999 459 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
<> 149:156823d33999 460
<> 149:156823d33999 461 /* Compute the i2sdiv prescaler */
<> 149:156823d33999 462 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
<> 149:156823d33999 463
<> 149:156823d33999 464 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 149:156823d33999 465 i2sodd = (uint16_t)(i2sodd << 8U);
<> 149:156823d33999 466 }
<> 149:156823d33999 467
<> 149:156823d33999 468 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 149:156823d33999 469 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
<> 149:156823d33999 470 {
<> 149:156823d33999 471 /* Set the default values */
<> 149:156823d33999 472 i2sdiv = 2U;
<> 149:156823d33999 473 i2sodd = 0U;
<> 149:156823d33999 474 }
<> 149:156823d33999 475
<> 149:156823d33999 476 /* Write to SPIx I2SPR register the computed value */
<> 149:156823d33999 477 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
<> 149:156823d33999 478
<> 149:156823d33999 479 status = SUCCESS;
<> 149:156823d33999 480 }
<> 149:156823d33999 481 return status;
<> 149:156823d33999 482 }
<> 149:156823d33999 483
<> 149:156823d33999 484 /**
<> 149:156823d33999 485 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
<> 149:156823d33999 486 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
<> 149:156823d33999 487 * whose fields will be set to default values.
<> 149:156823d33999 488 * @retval None
<> 149:156823d33999 489 */
<> 149:156823d33999 490 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
<> 149:156823d33999 491 {
<> 149:156823d33999 492 /*--------------- Reset I2S init structure parameters values -----------------*/
<> 149:156823d33999 493 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
<> 149:156823d33999 494 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
<> 149:156823d33999 495 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
<> 149:156823d33999 496 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
<> 149:156823d33999 497 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
<> 149:156823d33999 498 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
<> 149:156823d33999 499 }
<> 149:156823d33999 500
<> 149:156823d33999 501 /**
<> 149:156823d33999 502 * @brief Set linear and parity prescaler.
<> 149:156823d33999 503 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
<> 149:156823d33999 504 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
<> 149:156823d33999 505 * @param SPIx SPI Instance
<> 149:156823d33999 506 * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
<> 149:156823d33999 507 * @param PrescalerParity This parameter can be one of the following values:
<> 149:156823d33999 508 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<> 149:156823d33999 509 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<> 149:156823d33999 510 * @retval None
<> 149:156823d33999 511 */
<> 149:156823d33999 512 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
<> 149:156823d33999 513 {
<> 149:156823d33999 514 /* Check the I2S parameters */
<> 149:156823d33999 515 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
<> 149:156823d33999 516 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
<> 149:156823d33999 517 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
<> 149:156823d33999 518
<> 149:156823d33999 519 /* Write to SPIx I2SPR */
<> 149:156823d33999 520 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
<> 149:156823d33999 521 }
<> 149:156823d33999 522
<> 149:156823d33999 523 /**
<> 149:156823d33999 524 * @}
<> 149:156823d33999 525 */
<> 149:156823d33999 526
<> 149:156823d33999 527 /**
<> 149:156823d33999 528 * @}
<> 149:156823d33999 529 */
<> 149:156823d33999 530
<> 149:156823d33999 531 /**
<> 149:156823d33999 532 * @}
<> 149:156823d33999 533 */
<> 149:156823d33999 534 #endif /* SPI_I2S_SUPPORT */
<> 149:156823d33999 535
<> 149:156823d33999 536 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
<> 149:156823d33999 537
<> 149:156823d33999 538 /**
<> 149:156823d33999 539 * @}
<> 149:156823d33999 540 */
<> 149:156823d33999 541
<> 149:156823d33999 542 #endif /* USE_FULL_LL_DRIVER */
<> 149:156823d33999 543
<> 149:156823d33999 544 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/