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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 184:08ed48f1de7f

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_ll_i2c.h
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @brief Header file of I2C LL module.
<>	149:156823d33999	6	******************************************************************************
<>	149:156823d33999	7	* @attention
<>	149:156823d33999	8	*
AnnaBridge	184:08ed48f1de7f	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	149:156823d33999	10	*
<>	149:156823d33999	11	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	12	* are permitted provided that the following conditions are met:
<>	149:156823d33999	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	14	* this list of conditions and the following disclaimer.
<>	149:156823d33999	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	16	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	17	* and/or other materials provided with the distribution.
<>	149:156823d33999	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	19	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	20	* without specific prior written permission.
<>	149:156823d33999	21	*
<>	149:156823d33999	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	32	*
<>	149:156823d33999	33	******************************************************************************
<>	149:156823d33999	34	*/
<>	149:156823d33999	35
<>	149:156823d33999	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	149:156823d33999	37	#ifndef __STM32L1xx_LL_I2C_H
<>	149:156823d33999	38	#define __STM32L1xx_LL_I2C_H
<>	149:156823d33999	39
<>	149:156823d33999	40	#ifdef __cplusplus
<>	149:156823d33999	41	extern "C" {
<>	149:156823d33999	42	#endif
<>	149:156823d33999	43
<>	149:156823d33999	44	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	45	#include "stm32l1xx.h"
<>	149:156823d33999	46
<>	149:156823d33999	47	/** @addtogroup STM32L1xx_LL_Driver
<>	149:156823d33999	48	* @{
<>	149:156823d33999	49	*/
<>	149:156823d33999	50
<>	149:156823d33999	51	#if defined (I2C1) \|\| defined (I2C2)
<>	149:156823d33999	52
<>	149:156823d33999	53	/** @defgroup I2C_LL I2C
<>	149:156823d33999	54	* @{
<>	149:156823d33999	55	*/
<>	149:156823d33999	56
<>	149:156823d33999	57	/* Private types -------------------------------------------------------------*/
<>	149:156823d33999	58	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	59
<>	149:156823d33999	60	/* Private constants ---------------------------------------------------------*/
<>	149:156823d33999	61	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
<>	149:156823d33999	62	* @{
<>	149:156823d33999	63	*/
<>	149:156823d33999	64
<>	149:156823d33999	65	/* Defines used to perform compute and check in the macros */
<>	149:156823d33999	66	#define LL_I2C_MAX_SPEED_STANDARD 100000U
<>	149:156823d33999	67	#define LL_I2C_MAX_SPEED_FAST 400000U
<>	149:156823d33999	68	/**
<>	149:156823d33999	69	* @}
<>	149:156823d33999	70	*/
<>	149:156823d33999	71
<>	149:156823d33999	72	/* Private macros ------------------------------------------------------------*/
<>	149:156823d33999	73	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	74	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
<>	149:156823d33999	75	* @{
<>	149:156823d33999	76	*/
<>	149:156823d33999	77	/**
<>	149:156823d33999	78	* @}
<>	149:156823d33999	79	*/
<>	149:156823d33999	80	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	81
<>	149:156823d33999	82	/* Exported types ------------------------------------------------------------*/
<>	149:156823d33999	83	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	84	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
<>	149:156823d33999	85	* @{
<>	149:156823d33999	86	*/
<>	149:156823d33999	87	typedef struct
<>	149:156823d33999	88	{
<>	149:156823d33999	89	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
<>	149:156823d33999	90	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
<>	149:156823d33999	91
<>	149:156823d33999	92	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
<>	149:156823d33999	93
<>	149:156823d33999	94	uint32_t ClockSpeed; /*!< Specifies the clock frequency.
<>	149:156823d33999	95	This parameter must be set to a value lower than 400kHz (in Hz)
<>	149:156823d33999	96
<>	149:156823d33999	97	This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
<>	149:156823d33999	98	or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
<>	149:156823d33999	99
<>	149:156823d33999	100	uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
<>	149:156823d33999	101	This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
<>	149:156823d33999	102
<>	149:156823d33999	103	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
<>	149:156823d33999	104
<>	149:156823d33999	105	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
<>	149:156823d33999	106	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
<>	149:156823d33999	107
<>	149:156823d33999	108	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	149:156823d33999	109
<>	149:156823d33999	110	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	149:156823d33999	111	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
<>	149:156823d33999	112
<>	149:156823d33999	113	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
<>	149:156823d33999	114
<>	149:156823d33999	115	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
<>	149:156823d33999	116	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
<>	149:156823d33999	117
<>	149:156823d33999	118	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	149:156823d33999	119	} LL_I2C_InitTypeDef;
<>	149:156823d33999	120	/**
<>	149:156823d33999	121	* @}
<>	149:156823d33999	122	*/
<>	149:156823d33999	123	#endif /USE_FULL_LL_DRIVER/
<>	149:156823d33999	124
<>	149:156823d33999	125	/* Exported constants --------------------------------------------------------*/
<>	149:156823d33999	126	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
<>	149:156823d33999	127	* @{
<>	149:156823d33999	128	*/
<>	149:156823d33999	129
<>	149:156823d33999	130	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
<>	149:156823d33999	131	* @brief Flags defines which can be used with LL_I2C_ReadReg function
<>	149:156823d33999	132	* @{
<>	149:156823d33999	133	*/
<>	149:156823d33999	134	#define LL_I2C_SR1_SB I2C_SR1_SB /!< Start Bit (master mode) /
<>	149:156823d33999	135	#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
<>	149:156823d33999	136	Address matched flag (slave mode) */
<>	149:156823d33999	137	#define LL_I2C_SR1_BTF I2C_SR1_BTF /!< Byte Transfer Finished flag /
<>	149:156823d33999	138	#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /!< 10-bit header sent (master mode) /
<>	149:156823d33999	139	#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /!< Stop detection flag (slave mode) /
<>	149:156823d33999	140	#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /!< Data register not empty (receivers) /
<>	149:156823d33999	141	#define LL_I2C_SR1_TXE I2C_SR1_TXE /!< Data register empty (transmitters) /
<>	149:156823d33999	142	#define LL_I2C_SR1_BERR I2C_SR1_BERR /!< Bus error /
<>	149:156823d33999	143	#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /!< Arbitration lost /
<>	149:156823d33999	144	#define LL_I2C_SR1_AF I2C_SR1_AF /!< Acknowledge failure flag /
<>	149:156823d33999	145	#define LL_I2C_SR1_OVR I2C_SR1_OVR /!< Overrun/Underrun /
<>	149:156823d33999	146	#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
<>	149:156823d33999	147	#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
<>	149:156823d33999	148	#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /!< SMBus alert (SMBus mode) /
<>	149:156823d33999	149	#define LL_I2C_SR2_MSL I2C_SR2_MSL /!< Master/Slave flag /
<>	149:156823d33999	150	#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /!< Bus busy flag /
<>	149:156823d33999	151	#define LL_I2C_SR2_TRA I2C_SR2_TRA /!< Transmitter/receiver direction /
<>	149:156823d33999	152	#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /!< General call address (Slave mode) /
<>	149:156823d33999	153	#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /!< SMBus Device default address (Slave mode) /
<>	149:156823d33999	154	#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /!< SMBus Host address (Slave mode) /
<>	149:156823d33999	155	#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /!< Dual flag (Slave mode) /
<>	149:156823d33999	156	/**
<>	149:156823d33999	157	* @}
<>	149:156823d33999	158	*/
<>	149:156823d33999	159
<>	149:156823d33999	160	/** @defgroup I2C_LL_EC_IT IT Defines
<>	149:156823d33999	161	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
<>	149:156823d33999	162	* @{
<>	149:156823d33999	163	*/
<>	149:156823d33999	164	#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /!< Events interrupts enable /
<>	149:156823d33999	165	#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /!< Buffer interrupts enable /
<>	149:156823d33999	166	#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /!< Error interrupts enable /
<>	149:156823d33999	167	/**
<>	149:156823d33999	168	* @}
<>	149:156823d33999	169	*/
<>	149:156823d33999	170
<>	149:156823d33999	171	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
<>	149:156823d33999	172	* @{
<>	149:156823d33999	173	*/
<>	149:156823d33999	174	#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /!< Own address 1 is a 7-bit address. /
<>	149:156823d33999	175	#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE \| 0x00004000U) /!< Own address 1 is a 10-bit address. /
<>	149:156823d33999	176	/**
<>	149:156823d33999	177	* @}
<>	149:156823d33999	178	*/
<>	149:156823d33999	179
<>	149:156823d33999	180	/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
<>	149:156823d33999	181	* @{
<>	149:156823d33999	182	*/
<>	149:156823d33999	183	#define LL_I2C_DUTYCYCLE_2 0x00000000U /!< I2C fast mode Tlow/Thigh = 2 /
<>	149:156823d33999	184	#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /!< I2C fast mode Tlow/Thigh = 16/9 /
<>	149:156823d33999	185	/**
<>	149:156823d33999	186	* @}
<>	149:156823d33999	187	*/
<>	149:156823d33999	188
<>	149:156823d33999	189	/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
<>	149:156823d33999	190	* @{
<>	149:156823d33999	191	*/
<>	149:156823d33999	192	#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /!< Master clock speed range is standard mode /
<>	149:156823d33999	193	#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /!< Master clock speed range is fast mode /
<>	149:156823d33999	194	/**
<>	149:156823d33999	195	* @}
<>	149:156823d33999	196	*/
<>	149:156823d33999	197
<>	149:156823d33999	198	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
<>	149:156823d33999	199	* @{
<>	149:156823d33999	200	*/
<>	149:156823d33999	201	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
<>	149:156823d33999	202	#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP) /!< SMBus Host address acknowledge /
<>	149:156823d33999	203	#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /!< SMBus Device default mode (Default address not acknowledge) /
<>	149:156823d33999	204	#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_ENARP) /!< SMBus Device Default address acknowledge /
<>	149:156823d33999	205	/**
<>	149:156823d33999	206	* @}
<>	149:156823d33999	207	*/
<>	149:156823d33999	208
<>	149:156823d33999	209	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
<>	149:156823d33999	210	* @{
<>	149:156823d33999	211	*/
<>	149:156823d33999	212	#define LL_I2C_ACK I2C_CR1_ACK /!< ACK is sent after current received byte. /
<>	149:156823d33999	213	#define LL_I2C_NACK 0x00000000U /!< NACK is sent after current received byte./
<>	149:156823d33999	214	/**
<>	149:156823d33999	215	* @}
<>	149:156823d33999	216	*/
<>	149:156823d33999	217
<>	149:156823d33999	218	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
<>	149:156823d33999	219	* @{
<>	149:156823d33999	220	*/
<>	149:156823d33999	221	#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /!< Bus is in write transfer /
<>	149:156823d33999	222	#define LL_I2C_DIRECTION_READ 0x00000000U /!< Bus is in read transfer /
<>	149:156823d33999	223	/**
<>	149:156823d33999	224	* @}
<>	149:156823d33999	225	*/
<>	149:156823d33999	226
<>	149:156823d33999	227	/**
<>	149:156823d33999	228	* @}
<>	149:156823d33999	229	*/
<>	149:156823d33999	230
<>	149:156823d33999	231	/* Exported macro ------------------------------------------------------------*/
<>	149:156823d33999	232	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
<>	149:156823d33999	233	* @{
<>	149:156823d33999	234	*/
<>	149:156823d33999	235
<>	149:156823d33999	236	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
<>	149:156823d33999	237	* @{
<>	149:156823d33999	238	*/
<>	149:156823d33999	239
<>	149:156823d33999	240	/**
<>	149:156823d33999	241	* @brief Write a value in I2C register
<>	149:156823d33999	242	* @param __INSTANCE__ I2C Instance
<>	149:156823d33999	243	* @param __REG__ Register to be written
<>	149:156823d33999	244	* @param __VALUE__ Value to be written in the register
<>	149:156823d33999	245	* @retval None
<>	149:156823d33999	246	*/
<>	149:156823d33999	247	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	149:156823d33999	248
<>	149:156823d33999	249	/**
<>	149:156823d33999	250	* @brief Read a value in I2C register
<>	149:156823d33999	251	* @param __INSTANCE__ I2C Instance
<>	149:156823d33999	252	* @param __REG__ Register to be read
<>	149:156823d33999	253	* @retval Register value
<>	149:156823d33999	254	*/
<>	149:156823d33999	255	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	149:156823d33999	256	/**
<>	149:156823d33999	257	* @}
<>	149:156823d33999	258	*/
<>	149:156823d33999	259
<>	149:156823d33999	260	/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
<>	149:156823d33999	261	* @{
<>	149:156823d33999	262	*/
<>	149:156823d33999	263
<>	149:156823d33999	264	/**
<>	149:156823d33999	265	* @brief Convert Peripheral Clock Frequency in Mhz.
<>	149:156823d33999	266	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	149:156823d33999	267	* @retval Value of peripheral clock (in Mhz)
<>	149:156823d33999	268	*/
<>	149:156823d33999	269	#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
<>	149:156823d33999	270
<>	149:156823d33999	271	/**
<>	149:156823d33999	272	* @brief Convert Peripheral Clock Frequency in Hz.
<>	149:156823d33999	273	* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
<>	149:156823d33999	274	* @retval Value of peripheral clock (in Hz)
<>	149:156823d33999	275	*/
<>	149:156823d33999	276	#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
<>	149:156823d33999	277
<>	149:156823d33999	278	/**
<>	149:156823d33999	279	* @brief Compute I2C Clock rising time.
<>	149:156823d33999	280	* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
<>	149:156823d33999	281	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
<>	149:156823d33999	282	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
<>	149:156823d33999	283	*/
<>	149:156823d33999	284	#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
<>	149:156823d33999	285
<>	149:156823d33999	286	/**
<>	149:156823d33999	287	* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
<>	149:156823d33999	288	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	149:156823d33999	289	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
<>	149:156823d33999	290	* @param __DUTYCYCLE__ This parameter can be one of the following values:
<>	149:156823d33999	291	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	149:156823d33999	292	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	149:156823d33999	293	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
<>	149:156823d33999	294	*/
<>	149:156823d33999	295	#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
<>	149:156823d33999	296	(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
<>	149:156823d33999	297	(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
<>	149:156823d33999	298
<>	149:156823d33999	299	/**
<>	149:156823d33999	300	* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
<>	149:156823d33999	301	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	149:156823d33999	302	* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
<>	149:156823d33999	303	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
<>	149:156823d33999	304	*/
<>	149:156823d33999	305	#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
<>	149:156823d33999	306
<>	149:156823d33999	307	/**
<>	149:156823d33999	308	* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
<>	149:156823d33999	309	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
<>	149:156823d33999	310	* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
<>	149:156823d33999	311	* @param __DUTYCYCLE__ This parameter can be one of the following values:
<>	149:156823d33999	312	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	149:156823d33999	313	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	149:156823d33999	314	* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
<>	149:156823d33999	315	*/
<>	149:156823d33999	316	#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
<>	149:156823d33999	317	(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
<>	149:156823d33999	318	(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
<>	149:156823d33999	319
<>	149:156823d33999	320	/**
<>	149:156823d33999	321	* @brief Get the Least significant bits of a 10-Bits address.
<>	149:156823d33999	322	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
<>	149:156823d33999	323	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	149:156823d33999	324	*/
<>	149:156823d33999	325	#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
<>	149:156823d33999	326
<>	149:156823d33999	327	/**
<>	149:156823d33999	328	* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
<>	149:156823d33999	329	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
<>	149:156823d33999	330	* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
<>	149:156823d33999	331	*/
<>	149:156823d33999	332	#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF0))))
<>	149:156823d33999	333
<>	149:156823d33999	334	/**
<>	149:156823d33999	335	* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
<>	149:156823d33999	336	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
<>	149:156823d33999	337	* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
<>	149:156823d33999	338	*/
<>	149:156823d33999	339	#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF1))))
<>	149:156823d33999	340
<>	149:156823d33999	341	/**
<>	149:156823d33999	342	* @}
<>	149:156823d33999	343	*/
<>	149:156823d33999	344
<>	149:156823d33999	345	/**
<>	149:156823d33999	346	* @}
<>	149:156823d33999	347	*/
<>	149:156823d33999	348
<>	149:156823d33999	349	/* Exported functions --------------------------------------------------------*/
<>	149:156823d33999	350
<>	149:156823d33999	351	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
<>	149:156823d33999	352	* @{
<>	149:156823d33999	353	*/
<>	149:156823d33999	354
<>	149:156823d33999	355	/** @defgroup I2C_LL_EF_Configuration Configuration
<>	149:156823d33999	356	* @{
<>	149:156823d33999	357	*/
<>	149:156823d33999	358
<>	149:156823d33999	359	/**
<>	149:156823d33999	360	* @brief Enable I2C peripheral (PE = 1).
<>	149:156823d33999	361	* @rmtoll CR1 PE LL_I2C_Enable
<>	149:156823d33999	362	* @param I2Cx I2C Instance.
<>	149:156823d33999	363	* @retval None
<>	149:156823d33999	364	*/
<>	149:156823d33999	365	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
<>	149:156823d33999	366	{
<>	149:156823d33999	367	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	149:156823d33999	368	}
<>	149:156823d33999	369
<>	149:156823d33999	370	/**
<>	149:156823d33999	371	* @brief Disable I2C peripheral (PE = 0).
<>	149:156823d33999	372	* @rmtoll CR1 PE LL_I2C_Disable
<>	149:156823d33999	373	* @param I2Cx I2C Instance.
<>	149:156823d33999	374	* @retval None
<>	149:156823d33999	375	*/
<>	149:156823d33999	376	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
<>	149:156823d33999	377	{
<>	149:156823d33999	378	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	149:156823d33999	379	}
<>	149:156823d33999	380
<>	149:156823d33999	381	/**
<>	149:156823d33999	382	* @brief Check if the I2C peripheral is enabled or disabled.
<>	149:156823d33999	383	* @rmtoll CR1 PE LL_I2C_IsEnabled
<>	149:156823d33999	384	* @param I2Cx I2C Instance.
<>	149:156823d33999	385	* @retval State of bit (1 or 0).
<>	149:156823d33999	386	*/
<>	149:156823d33999	387	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
<>	149:156823d33999	388	{
<>	149:156823d33999	389	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
<>	149:156823d33999	390	}
<>	149:156823d33999	391
<>	149:156823d33999	392
<>	149:156823d33999	393	/**
<>	149:156823d33999	394	* @brief Enable DMA transmission requests.
<>	149:156823d33999	395	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
<>	149:156823d33999	396	* @param I2Cx I2C Instance.
<>	149:156823d33999	397	* @retval None
<>	149:156823d33999	398	*/
<>	149:156823d33999	399	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	400	{
<>	149:156823d33999	401	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	149:156823d33999	402	}
<>	149:156823d33999	403
<>	149:156823d33999	404	/**
<>	149:156823d33999	405	* @brief Disable DMA transmission requests.
<>	149:156823d33999	406	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
<>	149:156823d33999	407	* @param I2Cx I2C Instance.
<>	149:156823d33999	408	* @retval None
<>	149:156823d33999	409	*/
<>	149:156823d33999	410	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	411	{
<>	149:156823d33999	412	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	149:156823d33999	413	}
<>	149:156823d33999	414
<>	149:156823d33999	415	/**
<>	149:156823d33999	416	* @brief Check if DMA transmission requests are enabled or disabled.
<>	149:156823d33999	417	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
<>	149:156823d33999	418	* @param I2Cx I2C Instance.
<>	149:156823d33999	419	* @retval State of bit (1 or 0).
<>	149:156823d33999	420	*/
<>	149:156823d33999	421	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	422	{
<>	149:156823d33999	423	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
<>	149:156823d33999	424	}
<>	149:156823d33999	425
<>	149:156823d33999	426	/**
<>	149:156823d33999	427	* @brief Enable DMA reception requests.
<>	149:156823d33999	428	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
<>	149:156823d33999	429	* @param I2Cx I2C Instance.
<>	149:156823d33999	430	* @retval None
<>	149:156823d33999	431	*/
<>	149:156823d33999	432	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	433	{
<>	149:156823d33999	434	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	149:156823d33999	435	}
<>	149:156823d33999	436
<>	149:156823d33999	437	/**
<>	149:156823d33999	438	* @brief Disable DMA reception requests.
<>	149:156823d33999	439	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
<>	149:156823d33999	440	* @param I2Cx I2C Instance.
<>	149:156823d33999	441	* @retval None
<>	149:156823d33999	442	*/
<>	149:156823d33999	443	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	444	{
<>	149:156823d33999	445	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
<>	149:156823d33999	446	}
<>	149:156823d33999	447
<>	149:156823d33999	448	/**
<>	149:156823d33999	449	* @brief Check if DMA reception requests are enabled or disabled.
<>	149:156823d33999	450	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
<>	149:156823d33999	451	* @param I2Cx I2C Instance.
<>	149:156823d33999	452	* @retval State of bit (1 or 0).
<>	149:156823d33999	453	*/
<>	149:156823d33999	454	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	455	{
<>	149:156823d33999	456	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
<>	149:156823d33999	457	}
<>	149:156823d33999	458
<>	149:156823d33999	459	/**
<>	149:156823d33999	460	* @brief Get the data register address used for DMA transfer.
<>	149:156823d33999	461	* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
<>	149:156823d33999	462	* @param I2Cx I2C Instance.
<>	149:156823d33999	463	* @retval Address of data register
<>	149:156823d33999	464	*/
<>	149:156823d33999	465	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
<>	149:156823d33999	466	{
<>	149:156823d33999	467	return (uint32_t) & (I2Cx->DR);
<>	149:156823d33999	468	}
<>	149:156823d33999	469
<>	149:156823d33999	470	/**
<>	149:156823d33999	471	* @brief Enable Clock stretching.
<>	149:156823d33999	472	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	149:156823d33999	473	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
<>	149:156823d33999	474	* @param I2Cx I2C Instance.
<>	149:156823d33999	475	* @retval None
<>	149:156823d33999	476	*/
<>	149:156823d33999	477	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
<>	149:156823d33999	478	{
<>	149:156823d33999	479	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	149:156823d33999	480	}
<>	149:156823d33999	481
<>	149:156823d33999	482	/**
<>	149:156823d33999	483	* @brief Disable Clock stretching.
<>	149:156823d33999	484	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	149:156823d33999	485	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
<>	149:156823d33999	486	* @param I2Cx I2C Instance.
<>	149:156823d33999	487	* @retval None
<>	149:156823d33999	488	*/
<>	149:156823d33999	489	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
<>	149:156823d33999	490	{
<>	149:156823d33999	491	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	149:156823d33999	492	}
<>	149:156823d33999	493
<>	149:156823d33999	494	/**
<>	149:156823d33999	495	* @brief Check if Clock stretching is enabled or disabled.
<>	149:156823d33999	496	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
<>	149:156823d33999	497	* @param I2Cx I2C Instance.
<>	149:156823d33999	498	* @retval State of bit (1 or 0).
<>	149:156823d33999	499	*/
<>	149:156823d33999	500	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
<>	149:156823d33999	501	{
<>	149:156823d33999	502	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
<>	149:156823d33999	503	}
<>	149:156823d33999	504
<>	149:156823d33999	505	/**
<>	149:156823d33999	506	* @brief Enable General Call.
<>	149:156823d33999	507	* @note When enabled the Address 0x00 is ACKed.
<>	149:156823d33999	508	* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
<>	149:156823d33999	509	* @param I2Cx I2C Instance.
<>	149:156823d33999	510	* @retval None
<>	149:156823d33999	511	*/
<>	149:156823d33999	512	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
<>	149:156823d33999	513	{
<>	149:156823d33999	514	SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
<>	149:156823d33999	515	}
<>	149:156823d33999	516
<>	149:156823d33999	517	/**
<>	149:156823d33999	518	* @brief Disable General Call.
<>	149:156823d33999	519	* @note When disabled the Address 0x00 is NACKed.
<>	149:156823d33999	520	* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
<>	149:156823d33999	521	* @param I2Cx I2C Instance.
<>	149:156823d33999	522	* @retval None
<>	149:156823d33999	523	*/
<>	149:156823d33999	524	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
<>	149:156823d33999	525	{
<>	149:156823d33999	526	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
<>	149:156823d33999	527	}
<>	149:156823d33999	528
<>	149:156823d33999	529	/**
<>	149:156823d33999	530	* @brief Check if General Call is enabled or disabled.
<>	149:156823d33999	531	* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
<>	149:156823d33999	532	* @param I2Cx I2C Instance.
<>	149:156823d33999	533	* @retval State of bit (1 or 0).
<>	149:156823d33999	534	*/
<>	149:156823d33999	535	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
<>	149:156823d33999	536	{
<>	149:156823d33999	537	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
<>	149:156823d33999	538	}
<>	149:156823d33999	539
<>	149:156823d33999	540	/**
<>	149:156823d33999	541	* @brief Set the Own Address1.
<>	149:156823d33999	542	* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
<>	149:156823d33999	543	* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
<>	149:156823d33999	544	* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
<>	149:156823d33999	545	* OAR1 ADDMODE LL_I2C_SetOwnAddress1
<>	149:156823d33999	546	* @param I2Cx I2C Instance.
<>	149:156823d33999	547	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
<>	149:156823d33999	548	* @param OwnAddrSize This parameter can be one of the following values:
<>	149:156823d33999	549	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
<>	149:156823d33999	550	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
<>	149:156823d33999	551	* @retval None
<>	149:156823d33999	552	*/
<>	149:156823d33999	553	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
<>	149:156823d33999	554	{
<>	149:156823d33999	555	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 \| I2C_OAR1_ADD1_7 \| I2C_OAR1_ADD8_9 \| I2C_OAR1_ADDMODE, OwnAddress1 \| OwnAddrSize);
<>	149:156823d33999	556	}
<>	149:156823d33999	557
<>	149:156823d33999	558	/**
<>	149:156823d33999	559	* @brief Set the 7bits Own Address2.
<>	149:156823d33999	560	* @note This action has no effect if own address2 is enabled.
<>	149:156823d33999	561	* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
<>	149:156823d33999	562	* @param I2Cx I2C Instance.
<>	149:156823d33999	563	* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
<>	149:156823d33999	564	* @retval None
<>	149:156823d33999	565	*/
<>	149:156823d33999	566	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
<>	149:156823d33999	567	{
<>	149:156823d33999	568	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
<>	149:156823d33999	569	}
<>	149:156823d33999	570
<>	149:156823d33999	571	/**
<>	149:156823d33999	572	* @brief Enable acknowledge on Own Address2 match address.
<>	149:156823d33999	573	* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
<>	149:156823d33999	574	* @param I2Cx I2C Instance.
<>	149:156823d33999	575	* @retval None
<>	149:156823d33999	576	*/
<>	149:156823d33999	577	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
<>	149:156823d33999	578	{
<>	149:156823d33999	579	SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
<>	149:156823d33999	580	}
<>	149:156823d33999	581
<>	149:156823d33999	582	/**
<>	149:156823d33999	583	* @brief Disable acknowledge on Own Address2 match address.
<>	149:156823d33999	584	* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
<>	149:156823d33999	585	* @param I2Cx I2C Instance.
<>	149:156823d33999	586	* @retval None
<>	149:156823d33999	587	*/
<>	149:156823d33999	588	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
<>	149:156823d33999	589	{
<>	149:156823d33999	590	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
<>	149:156823d33999	591	}
<>	149:156823d33999	592
<>	149:156823d33999	593	/**
<>	149:156823d33999	594	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	149:156823d33999	595	* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
<>	149:156823d33999	596	* @param I2Cx I2C Instance.
<>	149:156823d33999	597	* @retval State of bit (1 or 0).
<>	149:156823d33999	598	*/
<>	149:156823d33999	599	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
<>	149:156823d33999	600	{
<>	149:156823d33999	601	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
<>	149:156823d33999	602	}
<>	149:156823d33999	603
<>	149:156823d33999	604	/**
<>	149:156823d33999	605	* @brief Configure the Peripheral clock frequency.
<>	149:156823d33999	606	* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
<>	149:156823d33999	607	* @param I2Cx I2C Instance.
<>	149:156823d33999	608	* @param PeriphClock Peripheral Clock (in Hz)
<>	149:156823d33999	609	* @retval None
<>	149:156823d33999	610	*/
<>	149:156823d33999	611	__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
<>	149:156823d33999	612	{
<>	149:156823d33999	613	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
<>	149:156823d33999	614	}
<>	149:156823d33999	615
<>	149:156823d33999	616	/**
<>	149:156823d33999	617	* @brief Get the Peripheral clock frequency.
<>	149:156823d33999	618	* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
<>	149:156823d33999	619	* @param I2Cx I2C Instance.
<>	149:156823d33999	620	* @retval Value of Peripheral Clock (in Hz)
<>	149:156823d33999	621	*/
<>	149:156823d33999	622	__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
<>	149:156823d33999	623	{
<>	149:156823d33999	624	return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
<>	149:156823d33999	625	}
<>	149:156823d33999	626
<>	149:156823d33999	627	/**
<>	149:156823d33999	628	* @brief Configure the Duty cycle (Fast mode only).
<>	149:156823d33999	629	* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
<>	149:156823d33999	630	* @param I2Cx I2C Instance.
<>	149:156823d33999	631	* @param DutyCycle This parameter can be one of the following values:
<>	149:156823d33999	632	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	149:156823d33999	633	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	149:156823d33999	634	* @retval None
<>	149:156823d33999	635	*/
<>	149:156823d33999	636	__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
<>	149:156823d33999	637	{
<>	149:156823d33999	638	MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
<>	149:156823d33999	639	}
<>	149:156823d33999	640
<>	149:156823d33999	641	/**
<>	149:156823d33999	642	* @brief Get the Duty cycle (Fast mode only).
<>	149:156823d33999	643	* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
<>	149:156823d33999	644	* @param I2Cx I2C Instance.
<>	149:156823d33999	645	* @retval Returned value can be one of the following values:
<>	149:156823d33999	646	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	149:156823d33999	647	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	149:156823d33999	648	*/
<>	149:156823d33999	649	__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
<>	149:156823d33999	650	{
<>	149:156823d33999	651	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
<>	149:156823d33999	652	}
<>	149:156823d33999	653
<>	149:156823d33999	654	/**
<>	149:156823d33999	655	* @brief Configure the I2C master clock speed mode.
<>	149:156823d33999	656	* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
<>	149:156823d33999	657	* @param I2Cx I2C Instance.
<>	149:156823d33999	658	* @param ClockSpeedMode This parameter can be one of the following values:
<>	149:156823d33999	659	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
<>	149:156823d33999	660	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
<>	149:156823d33999	661	* @retval None
<>	149:156823d33999	662	*/
<>	149:156823d33999	663	__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
<>	149:156823d33999	664	{
<>	149:156823d33999	665	MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
<>	149:156823d33999	666	}
<>	149:156823d33999	667
<>	149:156823d33999	668	/**
<>	149:156823d33999	669	* @brief Get the the I2C master speed mode.
<>	149:156823d33999	670	* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
<>	149:156823d33999	671	* @param I2Cx I2C Instance.
<>	149:156823d33999	672	* @retval Returned value can be one of the following values:
<>	149:156823d33999	673	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
<>	149:156823d33999	674	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
<>	149:156823d33999	675	*/
<>	149:156823d33999	676	__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
<>	149:156823d33999	677	{
<>	149:156823d33999	678	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
<>	149:156823d33999	679	}
<>	149:156823d33999	680
<>	149:156823d33999	681	/**
<>	149:156823d33999	682	* @brief Configure the SCL, SDA rising time.
<>	149:156823d33999	683	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	149:156823d33999	684	* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
<>	149:156823d33999	685	* @param I2Cx I2C Instance.
<>	149:156823d33999	686	* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
<>	149:156823d33999	687	* @retval None
<>	149:156823d33999	688	*/
<>	149:156823d33999	689	__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
<>	149:156823d33999	690	{
<>	149:156823d33999	691	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
<>	149:156823d33999	692	}
<>	149:156823d33999	693
<>	149:156823d33999	694	/**
<>	149:156823d33999	695	* @brief Get the SCL, SDA rising time.
<>	149:156823d33999	696	* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
<>	149:156823d33999	697	* @param I2Cx I2C Instance.
<>	149:156823d33999	698	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
<>	149:156823d33999	699	*/
<>	149:156823d33999	700	__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
<>	149:156823d33999	701	{
<>	149:156823d33999	702	return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
<>	149:156823d33999	703	}
<>	149:156823d33999	704
<>	149:156823d33999	705	/**
<>	149:156823d33999	706	* @brief Configure the SCL high and low period.
<>	149:156823d33999	707	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	149:156823d33999	708	* @rmtoll CCR CCR LL_I2C_SetClockPeriod
<>	149:156823d33999	709	* @param I2Cx I2C Instance.
<>	149:156823d33999	710	* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
<>	149:156823d33999	711	* @retval None
<>	149:156823d33999	712	*/
<>	149:156823d33999	713	__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
<>	149:156823d33999	714	{
<>	149:156823d33999	715	MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
<>	149:156823d33999	716	}
<>	149:156823d33999	717
<>	149:156823d33999	718	/**
<>	149:156823d33999	719	* @brief Get the SCL high and low period.
<>	149:156823d33999	720	* @rmtoll CCR CCR LL_I2C_GetClockPeriod
<>	149:156823d33999	721	* @param I2Cx I2C Instance.
<>	149:156823d33999	722	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
<>	149:156823d33999	723	*/
<>	149:156823d33999	724	__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
<>	149:156823d33999	725	{
<>	149:156823d33999	726	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
<>	149:156823d33999	727	}
<>	149:156823d33999	728
<>	149:156823d33999	729	/**
<>	149:156823d33999	730	* @brief Configure the SCL speed.
<>	149:156823d33999	731	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	149:156823d33999	732	* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
<>	149:156823d33999	733	* TRISE TRISE LL_I2C_ConfigSpeed\n
<>	149:156823d33999	734	* CCR FS LL_I2C_ConfigSpeed\n
<>	149:156823d33999	735	* CCR DUTY LL_I2C_ConfigSpeed\n
<>	149:156823d33999	736	* CCR CCR LL_I2C_ConfigSpeed
<>	149:156823d33999	737	* @param I2Cx I2C Instance.
<>	149:156823d33999	738	* @param PeriphClock Peripheral Clock (in Hz)
<>	149:156823d33999	739	* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
<>	149:156823d33999	740	* @param DutyCycle This parameter can be one of the following values:
<>	149:156823d33999	741	* @arg @ref LL_I2C_DUTYCYCLE_2
<>	149:156823d33999	742	* @arg @ref LL_I2C_DUTYCYCLE_16_9
<>	149:156823d33999	743	* @retval None
<>	149:156823d33999	744	*/
<>	149:156823d33999	745	__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
<>	149:156823d33999	746	uint32_t DutyCycle)
<>	149:156823d33999	747	{
<>	149:156823d33999	748	register uint32_t freqrange = 0x0U;
<>	149:156823d33999	749	register uint32_t clockconfig = 0x0U;
<>	149:156823d33999	750
<>	149:156823d33999	751	/* Compute frequency range */
<>	149:156823d33999	752	freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
<>	149:156823d33999	753
<>	149:156823d33999	754	/* Configure I2Cx: Frequency range register */
<>	149:156823d33999	755	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
<>	149:156823d33999	756
<>	149:156823d33999	757	/* Configure I2Cx: Rise Time register */
<>	149:156823d33999	758	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
<>	149:156823d33999	759
<>	149:156823d33999	760	/* Configure Speed mode, Duty Cycle and Clock control register value */
<>	149:156823d33999	761	if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
<>	149:156823d33999	762	{
<>	149:156823d33999	763	/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
<>	149:156823d33999	764	clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE \| \
<>	149:156823d33999	765	__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) \| \
<>	149:156823d33999	766	DutyCycle;
<>	149:156823d33999	767	}
<>	149:156823d33999	768	else
<>	149:156823d33999	769	{
<>	149:156823d33999	770	/* Set Speed mode at standard for Clock Speed request in standard clock range */
<>	149:156823d33999	771	clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE \| \
<>	149:156823d33999	772	__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
<>	149:156823d33999	773	}
<>	149:156823d33999	774
<>	149:156823d33999	775	/* Configure I2Cx: Clock control register */
<>	149:156823d33999	776	MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS \| I2C_CCR_DUTY \| I2C_CCR_CCR), clockconfig);
<>	149:156823d33999	777	}
<>	149:156823d33999	778
<>	149:156823d33999	779	/**
<>	149:156823d33999	780	* @brief Configure peripheral mode.
<>	149:156823d33999	781	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	782	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	783	* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
<>	149:156823d33999	784	* CR1 SMBTYPE LL_I2C_SetMode\n
<>	149:156823d33999	785	* CR1 ENARP LL_I2C_SetMode
<>	149:156823d33999	786	* @param I2Cx I2C Instance.
<>	149:156823d33999	787	* @param PeripheralMode This parameter can be one of the following values:
<>	149:156823d33999	788	* @arg @ref LL_I2C_MODE_I2C
<>	149:156823d33999	789	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	149:156823d33999	790	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	149:156823d33999	791	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	149:156823d33999	792	* @retval None
<>	149:156823d33999	793	*/
<>	149:156823d33999	794	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
<>	149:156823d33999	795	{
<>	149:156823d33999	796	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP, PeripheralMode);
<>	149:156823d33999	797	}
<>	149:156823d33999	798
<>	149:156823d33999	799	/**
<>	149:156823d33999	800	* @brief Get peripheral mode.
<>	149:156823d33999	801	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	802	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	803	* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
<>	149:156823d33999	804	* CR1 SMBTYPE LL_I2C_GetMode\n
<>	149:156823d33999	805	* CR1 ENARP LL_I2C_GetMode
<>	149:156823d33999	806	* @param I2Cx I2C Instance.
<>	149:156823d33999	807	* @retval Returned value can be one of the following values:
<>	149:156823d33999	808	* @arg @ref LL_I2C_MODE_I2C
<>	149:156823d33999	809	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	149:156823d33999	810	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	149:156823d33999	811	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	149:156823d33999	812	*/
<>	149:156823d33999	813	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
<>	149:156823d33999	814	{
<>	149:156823d33999	815	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP));
<>	149:156823d33999	816	}
<>	149:156823d33999	817
<>	149:156823d33999	818	/**
<>	149:156823d33999	819	* @brief Enable SMBus alert (Host or Device mode)
<>	149:156823d33999	820	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	821	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	822	* @note SMBus Device mode:
<>	149:156823d33999	823	* - SMBus Alert pin is drived low and
<>	149:156823d33999	824	* Alert Response Address Header acknowledge is enabled.
<>	149:156823d33999	825	* SMBus Host mode:
<>	149:156823d33999	826	* - SMBus Alert pin management is supported.
<>	149:156823d33999	827	* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
<>	149:156823d33999	828	* @param I2Cx I2C Instance.
<>	149:156823d33999	829	* @retval None
<>	149:156823d33999	830	*/
<>	149:156823d33999	831	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
<>	149:156823d33999	832	{
<>	149:156823d33999	833	SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
<>	149:156823d33999	834	}
<>	149:156823d33999	835
<>	149:156823d33999	836	/**
<>	149:156823d33999	837	* @brief Disable SMBus alert (Host or Device mode)
<>	149:156823d33999	838	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	839	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	840	* @note SMBus Device mode:
<>	149:156823d33999	841	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
<>	149:156823d33999	842	* Alert Response Address Header acknowledge is disabled.
<>	149:156823d33999	843	* SMBus Host mode:
<>	149:156823d33999	844	* - SMBus Alert pin management is not supported.
<>	149:156823d33999	845	* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
<>	149:156823d33999	846	* @param I2Cx I2C Instance.
<>	149:156823d33999	847	* @retval None
<>	149:156823d33999	848	*/
<>	149:156823d33999	849	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
<>	149:156823d33999	850	{
<>	149:156823d33999	851	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
<>	149:156823d33999	852	}
<>	149:156823d33999	853
<>	149:156823d33999	854	/**
<>	149:156823d33999	855	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
<>	149:156823d33999	856	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	857	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	858	* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
<>	149:156823d33999	859	* @param I2Cx I2C Instance.
<>	149:156823d33999	860	* @retval State of bit (1 or 0).
<>	149:156823d33999	861	*/
<>	149:156823d33999	862	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
<>	149:156823d33999	863	{
<>	149:156823d33999	864	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
<>	149:156823d33999	865	}
<>	149:156823d33999	866
<>	149:156823d33999	867	/**
<>	149:156823d33999	868	* @brief Enable SMBus Packet Error Calculation (PEC).
<>	149:156823d33999	869	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	870	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	871	* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
<>	149:156823d33999	872	* @param I2Cx I2C Instance.
<>	149:156823d33999	873	* @retval None
<>	149:156823d33999	874	*/
<>	149:156823d33999	875	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
<>	149:156823d33999	876	{
<>	149:156823d33999	877	SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
<>	149:156823d33999	878	}
<>	149:156823d33999	879
<>	149:156823d33999	880	/**
<>	149:156823d33999	881	* @brief Disable SMBus Packet Error Calculation (PEC).
<>	149:156823d33999	882	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	883	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	884	* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
<>	149:156823d33999	885	* @param I2Cx I2C Instance.
<>	149:156823d33999	886	* @retval None
<>	149:156823d33999	887	*/
<>	149:156823d33999	888	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
<>	149:156823d33999	889	{
<>	149:156823d33999	890	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
<>	149:156823d33999	891	}
<>	149:156823d33999	892
<>	149:156823d33999	893	/**
<>	149:156823d33999	894	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
<>	149:156823d33999	895	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	896	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	897	* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
<>	149:156823d33999	898	* @param I2Cx I2C Instance.
<>	149:156823d33999	899	* @retval State of bit (1 or 0).
<>	149:156823d33999	900	*/
<>	149:156823d33999	901	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
<>	149:156823d33999	902	{
<>	149:156823d33999	903	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
<>	149:156823d33999	904	}
<>	149:156823d33999	905
<>	149:156823d33999	906	/**
<>	149:156823d33999	907	* @}
<>	149:156823d33999	908	*/
<>	149:156823d33999	909
<>	149:156823d33999	910	/** @defgroup I2C_LL_EF_IT_Management IT_Management
<>	149:156823d33999	911	* @{
<>	149:156823d33999	912	*/
<>	149:156823d33999	913
<>	149:156823d33999	914	/**
<>	149:156823d33999	915	* @brief Enable TXE interrupt.
<>	149:156823d33999	916	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
<>	149:156823d33999	917	* CR2 ITBUFEN LL_I2C_EnableIT_TX
<>	149:156823d33999	918	* @param I2Cx I2C Instance.
<>	149:156823d33999	919	* @retval None
<>	149:156823d33999	920	*/
<>	149:156823d33999	921	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	922	{
<>	149:156823d33999	923	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	149:156823d33999	924	}
<>	149:156823d33999	925
<>	149:156823d33999	926	/**
<>	149:156823d33999	927	* @brief Disable TXE interrupt.
<>	149:156823d33999	928	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
<>	149:156823d33999	929	* CR2 ITBUFEN LL_I2C_DisableIT_TX
<>	149:156823d33999	930	* @param I2Cx I2C Instance.
<>	149:156823d33999	931	* @retval None
<>	149:156823d33999	932	*/
<>	149:156823d33999	933	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	934	{
<>	149:156823d33999	935	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	149:156823d33999	936	}
<>	149:156823d33999	937
<>	149:156823d33999	938	/**
<>	149:156823d33999	939	* @brief Check if the TXE Interrupt is enabled or disabled.
<>	149:156823d33999	940	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
<>	149:156823d33999	941	* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
<>	149:156823d33999	942	* @param I2Cx I2C Instance.
<>	149:156823d33999	943	* @retval State of bit (1 or 0).
<>	149:156823d33999	944	*/
<>	149:156823d33999	945	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	946	{
<>	149:156823d33999	947	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
<>	149:156823d33999	948	}
<>	149:156823d33999	949
<>	149:156823d33999	950	/**
<>	149:156823d33999	951	* @brief Enable RXNE interrupt.
<>	149:156823d33999	952	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
<>	149:156823d33999	953	* CR2 ITBUFEN LL_I2C_EnableIT_RX
<>	149:156823d33999	954	* @param I2Cx I2C Instance.
<>	149:156823d33999	955	* @retval None
<>	149:156823d33999	956	*/
<>	149:156823d33999	957	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	958	{
<>	149:156823d33999	959	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	149:156823d33999	960	}
<>	149:156823d33999	961
<>	149:156823d33999	962	/**
<>	149:156823d33999	963	* @brief Disable RXNE interrupt.
<>	149:156823d33999	964	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
<>	149:156823d33999	965	* CR2 ITBUFEN LL_I2C_DisableIT_RX
<>	149:156823d33999	966	* @param I2Cx I2C Instance.
<>	149:156823d33999	967	* @retval None
<>	149:156823d33999	968	*/
<>	149:156823d33999	969	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	970	{
<>	149:156823d33999	971	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
<>	149:156823d33999	972	}
<>	149:156823d33999	973
<>	149:156823d33999	974	/**
<>	149:156823d33999	975	* @brief Check if the RXNE Interrupt is enabled or disabled.
<>	149:156823d33999	976	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
<>	149:156823d33999	977	* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
<>	149:156823d33999	978	* @param I2Cx I2C Instance.
<>	149:156823d33999	979	* @retval State of bit (1 or 0).
<>	149:156823d33999	980	*/
<>	149:156823d33999	981	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
<>	149:156823d33999	982	{
<>	149:156823d33999	983	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
<>	149:156823d33999	984	}
<>	149:156823d33999	985
<>	149:156823d33999	986	/**
<>	149:156823d33999	987	* @brief Enable Events interrupts.
<>	149:156823d33999	988	* @note Any of these events will generate interrupt :
<>	149:156823d33999	989	* Start Bit (SB)
<>	149:156823d33999	990	* Address sent, Address matched (ADDR)
<>	149:156823d33999	991	* 10-bit header sent (ADD10)
<>	149:156823d33999	992	* Stop detection (STOPF)
<>	149:156823d33999	993	* Byte transfer finished (BTF)
<>	149:156823d33999	994	*
<>	149:156823d33999	995	* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
<>	149:156823d33999	996	* Receive buffer not empty (RXNE)
<>	149:156823d33999	997	* Transmit buffer empty (TXE)
<>	149:156823d33999	998	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
<>	149:156823d33999	999	* @param I2Cx I2C Instance.
<>	149:156823d33999	1000	* @retval None
<>	149:156823d33999	1001	*/
<>	149:156823d33999	1002	__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1003	{
<>	149:156823d33999	1004	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
<>	149:156823d33999	1005	}
<>	149:156823d33999	1006
<>	149:156823d33999	1007	/**
<>	149:156823d33999	1008	* @brief Disable Events interrupts.
<>	149:156823d33999	1009	* @note Any of these events will generate interrupt :
<>	149:156823d33999	1010	* Start Bit (SB)
<>	149:156823d33999	1011	* Address sent, Address matched (ADDR)
<>	149:156823d33999	1012	* 10-bit header sent (ADD10)
<>	149:156823d33999	1013	* Stop detection (STOPF)
<>	149:156823d33999	1014	* Byte transfer finished (BTF)
<>	149:156823d33999	1015	* Receive buffer not empty (RXNE)
<>	149:156823d33999	1016	* Transmit buffer empty (TXE)
<>	149:156823d33999	1017	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
<>	149:156823d33999	1018	* @param I2Cx I2C Instance.
<>	149:156823d33999	1019	* @retval None
<>	149:156823d33999	1020	*/
<>	149:156823d33999	1021	__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1022	{
<>	149:156823d33999	1023	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
<>	149:156823d33999	1024	}
<>	149:156823d33999	1025
<>	149:156823d33999	1026	/**
<>	149:156823d33999	1027	* @brief Check if Events interrupts are enabled or disabled.
<>	149:156823d33999	1028	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
<>	149:156823d33999	1029	* @param I2Cx I2C Instance.
<>	149:156823d33999	1030	* @retval State of bit (1 or 0).
<>	149:156823d33999	1031	*/
<>	149:156823d33999	1032	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1033	{
<>	149:156823d33999	1034	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
<>	149:156823d33999	1035	}
<>	149:156823d33999	1036
<>	149:156823d33999	1037	/**
<>	149:156823d33999	1038	* @brief Enable Buffer interrupts.
<>	149:156823d33999	1039	* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
<>	149:156823d33999	1040	* Receive buffer not empty (RXNE)
<>	149:156823d33999	1041	* Transmit buffer empty (TXE)
<>	149:156823d33999	1042	* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
<>	149:156823d33999	1043	* @param I2Cx I2C Instance.
<>	149:156823d33999	1044	* @retval None
<>	149:156823d33999	1045	*/
<>	149:156823d33999	1046	__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1047	{
<>	149:156823d33999	1048	SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
<>	149:156823d33999	1049	}
<>	149:156823d33999	1050
<>	149:156823d33999	1051	/**
<>	149:156823d33999	1052	* @brief Disable Buffer interrupts.
<>	149:156823d33999	1053	* @note Any of these Buffer events will generate interrupt :
<>	149:156823d33999	1054	* Receive buffer not empty (RXNE)
<>	149:156823d33999	1055	* Transmit buffer empty (TXE)
<>	149:156823d33999	1056	* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
<>	149:156823d33999	1057	* @param I2Cx I2C Instance.
<>	149:156823d33999	1058	* @retval None
<>	149:156823d33999	1059	*/
<>	149:156823d33999	1060	__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1061	{
<>	149:156823d33999	1062	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
<>	149:156823d33999	1063	}
<>	149:156823d33999	1064
<>	149:156823d33999	1065	/**
<>	149:156823d33999	1066	* @brief Check if Buffer interrupts are enabled or disabled.
<>	149:156823d33999	1067	* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
<>	149:156823d33999	1068	* @param I2Cx I2C Instance.
<>	149:156823d33999	1069	* @retval State of bit (1 or 0).
<>	149:156823d33999	1070	*/
<>	149:156823d33999	1071	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1072	{
<>	149:156823d33999	1073	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
<>	149:156823d33999	1074	}
<>	149:156823d33999	1075
<>	149:156823d33999	1076	/**
<>	149:156823d33999	1077	* @brief Enable Error interrupts.
<>	149:156823d33999	1078	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1079	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1080	* @note Any of these errors will generate interrupt :
<>	149:156823d33999	1081	* Bus Error detection (BERR)
<>	149:156823d33999	1082	* Arbitration Loss (ARLO)
<>	149:156823d33999	1083	* Acknowledge Failure(AF)
<>	149:156823d33999	1084	* Overrun/Underrun (OVR)
<>	149:156823d33999	1085	* SMBus Timeout detection (TIMEOUT)
<>	149:156823d33999	1086	* SMBus PEC error detection (PECERR)
<>	149:156823d33999	1087	* SMBus Alert pin event detection (SMBALERT)
<>	149:156823d33999	1088	* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
<>	149:156823d33999	1089	* @param I2Cx I2C Instance.
<>	149:156823d33999	1090	* @retval None
<>	149:156823d33999	1091	*/
<>	149:156823d33999	1092	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1093	{
<>	149:156823d33999	1094	SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
<>	149:156823d33999	1095	}
<>	149:156823d33999	1096
<>	149:156823d33999	1097	/**
<>	149:156823d33999	1098	* @brief Disable Error interrupts.
<>	149:156823d33999	1099	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1100	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1101	* @note Any of these errors will generate interrupt :
<>	149:156823d33999	1102	* Bus Error detection (BERR)
<>	149:156823d33999	1103	* Arbitration Loss (ARLO)
<>	149:156823d33999	1104	* Acknowledge Failure(AF)
<>	149:156823d33999	1105	* Overrun/Underrun (OVR)
<>	149:156823d33999	1106	* SMBus Timeout detection (TIMEOUT)
<>	149:156823d33999	1107	* SMBus PEC error detection (PECERR)
<>	149:156823d33999	1108	* SMBus Alert pin event detection (SMBALERT)
<>	149:156823d33999	1109	* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
<>	149:156823d33999	1110	* @param I2Cx I2C Instance.
<>	149:156823d33999	1111	* @retval None
<>	149:156823d33999	1112	*/
<>	149:156823d33999	1113	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1114	{
<>	149:156823d33999	1115	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
<>	149:156823d33999	1116	}
<>	149:156823d33999	1117
<>	149:156823d33999	1118	/**
<>	149:156823d33999	1119	* @brief Check if Error interrupts are enabled or disabled.
<>	149:156823d33999	1120	* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
<>	149:156823d33999	1121	* @param I2Cx I2C Instance.
<>	149:156823d33999	1122	* @retval State of bit (1 or 0).
<>	149:156823d33999	1123	*/
<>	149:156823d33999	1124	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1125	{
<>	149:156823d33999	1126	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
<>	149:156823d33999	1127	}
<>	149:156823d33999	1128
<>	149:156823d33999	1129	/**
<>	149:156823d33999	1130	* @}
<>	149:156823d33999	1131	*/
<>	149:156823d33999	1132
<>	149:156823d33999	1133	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
<>	149:156823d33999	1134	* @{
<>	149:156823d33999	1135	*/
<>	149:156823d33999	1136
<>	149:156823d33999	1137	/**
<>	149:156823d33999	1138	* @brief Indicate the status of Transmit data register empty flag.
<>	149:156823d33999	1139	* @note RESET: When next data is written in Transmit data register.
<>	149:156823d33999	1140	* SET: When Transmit data register is empty.
<>	149:156823d33999	1141	* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
<>	149:156823d33999	1142	* @param I2Cx I2C Instance.
<>	149:156823d33999	1143	* @retval State of bit (1 or 0).
<>	149:156823d33999	1144	*/
<>	149:156823d33999	1145	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1146	{
<>	149:156823d33999	1147	return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
<>	149:156823d33999	1148	}
<>	149:156823d33999	1149
<>	149:156823d33999	1150	/**
<>	149:156823d33999	1151	* @brief Indicate the status of Byte Transfer Finished flag.
<>	149:156823d33999	1152	* RESET: When Data byte transfer not done.
<>	149:156823d33999	1153	* SET: When Data byte transfer succeeded.
<>	149:156823d33999	1154	* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
<>	149:156823d33999	1155	* @param I2Cx I2C Instance.
<>	149:156823d33999	1156	* @retval State of bit (1 or 0).
<>	149:156823d33999	1157	*/
<>	149:156823d33999	1158	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1159	{
<>	149:156823d33999	1160	return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
<>	149:156823d33999	1161	}
<>	149:156823d33999	1162
<>	149:156823d33999	1163	/**
<>	149:156823d33999	1164	* @brief Indicate the status of Receive data register not empty flag.
<>	149:156823d33999	1165	* @note RESET: When Receive data register is read.
<>	149:156823d33999	1166	* SET: When the received data is copied in Receive data register.
<>	149:156823d33999	1167	* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
<>	149:156823d33999	1168	* @param I2Cx I2C Instance.
<>	149:156823d33999	1169	* @retval State of bit (1 or 0).
<>	149:156823d33999	1170	*/
<>	149:156823d33999	1171	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1172	{
<>	149:156823d33999	1173	return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
<>	149:156823d33999	1174	}
<>	149:156823d33999	1175
<>	149:156823d33999	1176	/**
<>	149:156823d33999	1177	* @brief Indicate the status of Start Bit (master mode).
<>	149:156823d33999	1178	* @note RESET: When No Start condition.
<>	149:156823d33999	1179	* SET: When Start condition is generated.
<>	149:156823d33999	1180	* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
<>	149:156823d33999	1181	* @param I2Cx I2C Instance.
<>	149:156823d33999	1182	* @retval State of bit (1 or 0).
<>	149:156823d33999	1183	*/
<>	149:156823d33999	1184	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1185	{
<>	149:156823d33999	1186	return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
<>	149:156823d33999	1187	}
<>	149:156823d33999	1188
<>	149:156823d33999	1189	/**
<>	149:156823d33999	1190	* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
<>	149:156823d33999	1191	* @note RESET: Clear default value.
<>	149:156823d33999	1192	* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
<>	149:156823d33999	1193	* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
<>	149:156823d33999	1194	* @param I2Cx I2C Instance.
<>	149:156823d33999	1195	* @retval State of bit (1 or 0).
<>	149:156823d33999	1196	*/
<>	149:156823d33999	1197	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1198	{
<>	149:156823d33999	1199	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
<>	149:156823d33999	1200	}
<>	149:156823d33999	1201
<>	149:156823d33999	1202	/**
<>	149:156823d33999	1203	* @brief Indicate the status of 10-bit header sent (master mode).
<>	149:156823d33999	1204	* @note RESET: When no ADD10 event occured.
<>	149:156823d33999	1205	* SET: When the master has sent the first address byte (header).
<>	149:156823d33999	1206	* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
<>	149:156823d33999	1207	* @param I2Cx I2C Instance.
<>	149:156823d33999	1208	* @retval State of bit (1 or 0).
<>	149:156823d33999	1209	*/
<>	149:156823d33999	1210	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1211	{
<>	149:156823d33999	1212	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
<>	149:156823d33999	1213	}
<>	149:156823d33999	1214
<>	149:156823d33999	1215	/**
<>	149:156823d33999	1216	* @brief Indicate the status of Acknowledge failure flag.
<>	149:156823d33999	1217	* @note RESET: No acknowledge failure.
<>	149:156823d33999	1218	* SET: When an acknowledge failure is received after a byte transmission.
<>	149:156823d33999	1219	* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
<>	149:156823d33999	1220	* @param I2Cx I2C Instance.
<>	149:156823d33999	1221	* @retval State of bit (1 or 0).
<>	149:156823d33999	1222	*/
<>	149:156823d33999	1223	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1224	{
<>	149:156823d33999	1225	return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
<>	149:156823d33999	1226	}
<>	149:156823d33999	1227
<>	149:156823d33999	1228	/**
<>	149:156823d33999	1229	* @brief Indicate the status of Stop detection flag (slave mode).
<>	149:156823d33999	1230	* @note RESET: Clear default value.
<>	149:156823d33999	1231	* SET: When a Stop condition is detected.
<>	149:156823d33999	1232	* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
<>	149:156823d33999	1233	* @param I2Cx I2C Instance.
<>	149:156823d33999	1234	* @retval State of bit (1 or 0).
<>	149:156823d33999	1235	*/
<>	149:156823d33999	1236	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1237	{
<>	149:156823d33999	1238	return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
<>	149:156823d33999	1239	}
<>	149:156823d33999	1240
<>	149:156823d33999	1241	/**
<>	149:156823d33999	1242	* @brief Indicate the status of Bus error flag.
<>	149:156823d33999	1243	* @note RESET: Clear default value.
<>	149:156823d33999	1244	* SET: When a misplaced Start or Stop condition is detected.
<>	149:156823d33999	1245	* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
<>	149:156823d33999	1246	* @param I2Cx I2C Instance.
<>	149:156823d33999	1247	* @retval State of bit (1 or 0).
<>	149:156823d33999	1248	*/
<>	149:156823d33999	1249	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1250	{
<>	149:156823d33999	1251	return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
<>	149:156823d33999	1252	}
<>	149:156823d33999	1253
<>	149:156823d33999	1254	/**
<>	149:156823d33999	1255	* @brief Indicate the status of Arbitration lost flag.
<>	149:156823d33999	1256	* @note RESET: Clear default value.
<>	149:156823d33999	1257	* SET: When arbitration lost.
<>	149:156823d33999	1258	* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
<>	149:156823d33999	1259	* @param I2Cx I2C Instance.
<>	149:156823d33999	1260	* @retval State of bit (1 or 0).
<>	149:156823d33999	1261	*/
<>	149:156823d33999	1262	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1263	{
<>	149:156823d33999	1264	return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
<>	149:156823d33999	1265	}
<>	149:156823d33999	1266
<>	149:156823d33999	1267	/**
<>	149:156823d33999	1268	* @brief Indicate the status of Overrun/Underrun flag.
<>	149:156823d33999	1269	* @note RESET: Clear default value.
<>	149:156823d33999	1270	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
<>	149:156823d33999	1271	* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
<>	149:156823d33999	1272	* @param I2Cx I2C Instance.
<>	149:156823d33999	1273	* @retval State of bit (1 or 0).
<>	149:156823d33999	1274	*/
<>	149:156823d33999	1275	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1276	{
<>	149:156823d33999	1277	return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
<>	149:156823d33999	1278	}
<>	149:156823d33999	1279
<>	149:156823d33999	1280	/**
<>	149:156823d33999	1281	* @brief Indicate the status of SMBus PEC error flag in reception.
<>	149:156823d33999	1282	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1283	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1284	* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
<>	149:156823d33999	1285	* @param I2Cx I2C Instance.
<>	149:156823d33999	1286	* @retval State of bit (1 or 0).
<>	149:156823d33999	1287	*/
<>	149:156823d33999	1288	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1289	{
<>	149:156823d33999	1290	return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
<>	149:156823d33999	1291	}
<>	149:156823d33999	1292
<>	149:156823d33999	1293	/**
<>	149:156823d33999	1294	* @brief Indicate the status of SMBus Timeout detection flag.
<>	149:156823d33999	1295	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1296	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1297	* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
<>	149:156823d33999	1298	* @param I2Cx I2C Instance.
<>	149:156823d33999	1299	* @retval State of bit (1 or 0).
<>	149:156823d33999	1300	*/
<>	149:156823d33999	1301	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1302	{
<>	149:156823d33999	1303	return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
<>	149:156823d33999	1304	}
<>	149:156823d33999	1305
<>	149:156823d33999	1306	/**
<>	149:156823d33999	1307	* @brief Indicate the status of SMBus alert flag.
<>	149:156823d33999	1308	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1309	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1310	* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
<>	149:156823d33999	1311	* @param I2Cx I2C Instance.
<>	149:156823d33999	1312	* @retval State of bit (1 or 0).
<>	149:156823d33999	1313	*/
<>	149:156823d33999	1314	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1315	{
<>	149:156823d33999	1316	return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
<>	149:156823d33999	1317	}
<>	149:156823d33999	1318
<>	149:156823d33999	1319	/**
<>	149:156823d33999	1320	* @brief Indicate the status of Bus Busy flag.
<>	149:156823d33999	1321	* @note RESET: Clear default value.
<>	149:156823d33999	1322	* SET: When a Start condition is detected.
<>	149:156823d33999	1323	* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
<>	149:156823d33999	1324	* @param I2Cx I2C Instance.
<>	149:156823d33999	1325	* @retval State of bit (1 or 0).
<>	149:156823d33999	1326	*/
<>	149:156823d33999	1327	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1328	{
<>	149:156823d33999	1329	return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
<>	149:156823d33999	1330	}
<>	149:156823d33999	1331
<>	149:156823d33999	1332	/**
<>	149:156823d33999	1333	* @brief Indicate the status of Dual flag.
<>	149:156823d33999	1334	* @note RESET: Received address matched with OAR1.
<>	149:156823d33999	1335	* SET: Received address matched with OAR2.
<>	149:156823d33999	1336	* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
<>	149:156823d33999	1337	* @param I2Cx I2C Instance.
<>	149:156823d33999	1338	* @retval State of bit (1 or 0).
<>	149:156823d33999	1339	*/
<>	149:156823d33999	1340	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1341	{
<>	149:156823d33999	1342	return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
<>	149:156823d33999	1343	}
<>	149:156823d33999	1344
<>	149:156823d33999	1345	/**
<>	149:156823d33999	1346	* @brief Indicate the status of SMBus Host address reception (Slave mode).
<>	149:156823d33999	1347	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1348	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1349	* @note RESET: No SMBus Host address
<>	149:156823d33999	1350	* SET: SMBus Host address received.
<>	149:156823d33999	1351	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
<>	149:156823d33999	1352	* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
<>	149:156823d33999	1353	* @param I2Cx I2C Instance.
<>	149:156823d33999	1354	* @retval State of bit (1 or 0).
<>	149:156823d33999	1355	*/
<>	149:156823d33999	1356	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1357	{
<>	149:156823d33999	1358	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
<>	149:156823d33999	1359	}
<>	149:156823d33999	1360
<>	149:156823d33999	1361	/**
<>	149:156823d33999	1362	* @brief Indicate the status of SMBus Device default address reception (Slave mode).
<>	149:156823d33999	1363	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1364	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1365	* @note RESET: No SMBus Device default address
<>	149:156823d33999	1366	* SET: SMBus Device default address received.
<>	149:156823d33999	1367	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
<>	149:156823d33999	1368	* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
<>	149:156823d33999	1369	* @param I2Cx I2C Instance.
<>	149:156823d33999	1370	* @retval State of bit (1 or 0).
<>	149:156823d33999	1371	*/
<>	149:156823d33999	1372	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1373	{
<>	149:156823d33999	1374	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
<>	149:156823d33999	1375	}
<>	149:156823d33999	1376
<>	149:156823d33999	1377	/**
<>	149:156823d33999	1378	* @brief Indicate the status of General call address reception (Slave mode).
<>	149:156823d33999	1379	* @note RESET: No Generall call address
<>	149:156823d33999	1380	* SET: General call address received.
<>	149:156823d33999	1381	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
<>	149:156823d33999	1382	* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
<>	149:156823d33999	1383	* @param I2Cx I2C Instance.
<>	149:156823d33999	1384	* @retval State of bit (1 or 0).
<>	149:156823d33999	1385	*/
<>	149:156823d33999	1386	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1387	{
<>	149:156823d33999	1388	return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
<>	149:156823d33999	1389	}
<>	149:156823d33999	1390
<>	149:156823d33999	1391	/**
<>	149:156823d33999	1392	* @brief Indicate the status of Master/Slave flag.
<>	149:156823d33999	1393	* @note RESET: Slave Mode.
<>	149:156823d33999	1394	* SET: Master Mode.
<>	149:156823d33999	1395	* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
<>	149:156823d33999	1396	* @param I2Cx I2C Instance.
<>	149:156823d33999	1397	* @retval State of bit (1 or 0).
<>	149:156823d33999	1398	*/
<>	149:156823d33999	1399	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1400	{
<>	149:156823d33999	1401	return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
<>	149:156823d33999	1402	}
<>	149:156823d33999	1403
<>	149:156823d33999	1404	/**
<>	149:156823d33999	1405	* @brief Clear Address Matched flag.
<>	149:156823d33999	1406	* @note Clearing this flag is done by a read access to the I2Cx_SR1
<>	149:156823d33999	1407	* register followed by a read access to the I2Cx_SR2 register.
<>	149:156823d33999	1408	* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
<>	149:156823d33999	1409	* @param I2Cx I2C Instance.
<>	149:156823d33999	1410	* @retval None
<>	149:156823d33999	1411	*/
<>	149:156823d33999	1412	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1413	{
<>	149:156823d33999	1414	__IO uint32_t tmpreg;
<>	149:156823d33999	1415	tmpreg = I2Cx->SR1;
<>	149:156823d33999	1416	(void) tmpreg;
<>	149:156823d33999	1417	tmpreg = I2Cx->SR2;
<>	149:156823d33999	1418	(void) tmpreg;
<>	149:156823d33999	1419	}
<>	149:156823d33999	1420
<>	149:156823d33999	1421	/**
<>	149:156823d33999	1422	* @brief Clear Acknowledge failure flag.
<>	149:156823d33999	1423	* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
<>	149:156823d33999	1424	* @param I2Cx I2C Instance.
<>	149:156823d33999	1425	* @retval None
<>	149:156823d33999	1426	*/
<>	149:156823d33999	1427	__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1428	{
<>	149:156823d33999	1429	CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
<>	149:156823d33999	1430	}
<>	149:156823d33999	1431
<>	149:156823d33999	1432	/**
<>	149:156823d33999	1433	* @brief Clear Stop detection flag.
<>	149:156823d33999	1434	* @note Clearing this flag is done by a read access to the I2Cx_SR1
<>	149:156823d33999	1435	* register followed by a write access to I2Cx_CR1 register.
<>	149:156823d33999	1436	* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
<>	149:156823d33999	1437	* CR1 PE LL_I2C_ClearFlag_STOP
<>	149:156823d33999	1438	* @param I2Cx I2C Instance.
<>	149:156823d33999	1439	* @retval None
<>	149:156823d33999	1440	*/
<>	149:156823d33999	1441	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1442	{
<>	149:156823d33999	1443	__IO uint32_t tmpreg;
<>	149:156823d33999	1444	tmpreg = I2Cx->SR1;
<>	149:156823d33999	1445	(void) tmpreg;
<>	149:156823d33999	1446	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	149:156823d33999	1447	}
<>	149:156823d33999	1448
<>	149:156823d33999	1449	/**
<>	149:156823d33999	1450	* @brief Clear Bus error flag.
<>	149:156823d33999	1451	* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
<>	149:156823d33999	1452	* @param I2Cx I2C Instance.
<>	149:156823d33999	1453	* @retval None
<>	149:156823d33999	1454	*/
<>	149:156823d33999	1455	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1456	{
<>	149:156823d33999	1457	CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
<>	149:156823d33999	1458	}
<>	149:156823d33999	1459
<>	149:156823d33999	1460	/**
<>	149:156823d33999	1461	* @brief Clear Arbitration lost flag.
<>	149:156823d33999	1462	* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
<>	149:156823d33999	1463	* @param I2Cx I2C Instance.
<>	149:156823d33999	1464	* @retval None
<>	149:156823d33999	1465	*/
<>	149:156823d33999	1466	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1467	{
<>	149:156823d33999	1468	CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
<>	149:156823d33999	1469	}
<>	149:156823d33999	1470
<>	149:156823d33999	1471	/**
<>	149:156823d33999	1472	* @brief Clear Overrun/Underrun flag.
<>	149:156823d33999	1473	* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
<>	149:156823d33999	1474	* @param I2Cx I2C Instance.
<>	149:156823d33999	1475	* @retval None
<>	149:156823d33999	1476	*/
<>	149:156823d33999	1477	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1478	{
<>	149:156823d33999	1479	CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
<>	149:156823d33999	1480	}
<>	149:156823d33999	1481
<>	149:156823d33999	1482	/**
<>	149:156823d33999	1483	* @brief Clear SMBus PEC error flag.
<>	149:156823d33999	1484	* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
<>	149:156823d33999	1485	* @param I2Cx I2C Instance.
<>	149:156823d33999	1486	* @retval None
<>	149:156823d33999	1487	*/
<>	149:156823d33999	1488	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1489	{
<>	149:156823d33999	1490	CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
<>	149:156823d33999	1491	}
<>	149:156823d33999	1492
<>	149:156823d33999	1493	/**
<>	149:156823d33999	1494	* @brief Clear SMBus Timeout detection flag.
<>	149:156823d33999	1495	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1496	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1497	* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
<>	149:156823d33999	1498	* @param I2Cx I2C Instance.
<>	149:156823d33999	1499	* @retval None
<>	149:156823d33999	1500	*/
<>	149:156823d33999	1501	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1502	{
<>	149:156823d33999	1503	CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
<>	149:156823d33999	1504	}
<>	149:156823d33999	1505
<>	149:156823d33999	1506	/**
<>	149:156823d33999	1507	* @brief Clear SMBus Alert flag.
<>	149:156823d33999	1508	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1509	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1510	* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
<>	149:156823d33999	1511	* @param I2Cx I2C Instance.
<>	149:156823d33999	1512	* @retval None
<>	149:156823d33999	1513	*/
<>	149:156823d33999	1514	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1515	{
<>	149:156823d33999	1516	CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
<>	149:156823d33999	1517	}
<>	149:156823d33999	1518
<>	149:156823d33999	1519	/**
<>	149:156823d33999	1520	* @}
<>	149:156823d33999	1521	*/
<>	149:156823d33999	1522
<>	149:156823d33999	1523	/** @defgroup I2C_LL_EF_Data_Management Data_Management
<>	149:156823d33999	1524	* @{
<>	149:156823d33999	1525	*/
<>	149:156823d33999	1526
<>	149:156823d33999	1527	/**
<>	149:156823d33999	1528	* @brief Enable Reset of I2C peripheral.
<>	149:156823d33999	1529	* @rmtoll CR1 SWRST LL_I2C_EnableReset
<>	149:156823d33999	1530	* @param I2Cx I2C Instance.
<>	149:156823d33999	1531	* @retval None
<>	149:156823d33999	1532	*/
<>	149:156823d33999	1533	__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1534	{
<>	149:156823d33999	1535	SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
<>	149:156823d33999	1536	}
<>	149:156823d33999	1537
<>	149:156823d33999	1538	/**
AnnaBridge	184:08ed48f1de7f	1539	* @brief Disable Reset of I2C peripheral.
AnnaBridge	184:08ed48f1de7f	1540	* @rmtoll CR1 SWRST LL_I2C_DisableReset
AnnaBridge	184:08ed48f1de7f	1541	* @param I2Cx I2C Instance.
AnnaBridge	184:08ed48f1de7f	1542	* @retval None
AnnaBridge	184:08ed48f1de7f	1543	*/
AnnaBridge	184:08ed48f1de7f	1544	__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
AnnaBridge	184:08ed48f1de7f	1545	{
AnnaBridge	184:08ed48f1de7f	1546	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge	184:08ed48f1de7f	1547	}
AnnaBridge	184:08ed48f1de7f	1548
AnnaBridge	184:08ed48f1de7f	1549	/**
<>	149:156823d33999	1550	* @brief Check if the I2C peripheral is under reset state or not.
<>	149:156823d33999	1551	* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
<>	149:156823d33999	1552	* @param I2Cx I2C Instance.
<>	149:156823d33999	1553	* @retval State of bit (1 or 0).
<>	149:156823d33999	1554	*/
<>	149:156823d33999	1555	__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1556	{
<>	149:156823d33999	1557	return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
<>	149:156823d33999	1558	}
<>	149:156823d33999	1559
<>	149:156823d33999	1560	/**
<>	149:156823d33999	1561	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	149:156823d33999	1562	* @note Usage in Slave or Master mode.
<>	149:156823d33999	1563	* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
<>	149:156823d33999	1564	* @param I2Cx I2C Instance.
<>	149:156823d33999	1565	* @param TypeAcknowledge This parameter can be one of the following values:
<>	149:156823d33999	1566	* @arg @ref LL_I2C_ACK
<>	149:156823d33999	1567	* @arg @ref LL_I2C_NACK
<>	149:156823d33999	1568	* @retval None
<>	149:156823d33999	1569	*/
<>	149:156823d33999	1570	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
<>	149:156823d33999	1571	{
<>	149:156823d33999	1572	MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
<>	149:156823d33999	1573	}
<>	149:156823d33999	1574
<>	149:156823d33999	1575	/**
<>	149:156823d33999	1576	* @brief Generate a START or RESTART condition
<>	149:156823d33999	1577	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
<>	149:156823d33999	1578	* This action has no effect when RELOAD is set.
<>	149:156823d33999	1579	* @rmtoll CR1 START LL_I2C_GenerateStartCondition
<>	149:156823d33999	1580	* @param I2Cx I2C Instance.
<>	149:156823d33999	1581	* @retval None
<>	149:156823d33999	1582	*/
<>	149:156823d33999	1583	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1584	{
<>	149:156823d33999	1585	SET_BIT(I2Cx->CR1, I2C_CR1_START);
<>	149:156823d33999	1586	}
<>	149:156823d33999	1587
<>	149:156823d33999	1588	/**
<>	149:156823d33999	1589	* @brief Generate a STOP condition after the current byte transfer (master mode).
<>	149:156823d33999	1590	* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
<>	149:156823d33999	1591	* @param I2Cx I2C Instance.
<>	149:156823d33999	1592	* @retval None
<>	149:156823d33999	1593	*/
<>	149:156823d33999	1594	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1595	{
<>	149:156823d33999	1596	SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
<>	149:156823d33999	1597	}
<>	149:156823d33999	1598
<>	149:156823d33999	1599	/**
<>	149:156823d33999	1600	* @brief Enable bit POS (master/host mode).
<>	149:156823d33999	1601	* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
<>	149:156823d33999	1602	* @rmtoll CR1 POS LL_I2C_EnableBitPOS
<>	149:156823d33999	1603	* @param I2Cx I2C Instance.
<>	149:156823d33999	1604	* @retval None
<>	149:156823d33999	1605	*/
<>	149:156823d33999	1606	__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1607	{
<>	149:156823d33999	1608	SET_BIT(I2Cx->CR1, I2C_CR1_POS);
<>	149:156823d33999	1609	}
<>	149:156823d33999	1610
<>	149:156823d33999	1611	/**
<>	149:156823d33999	1612	* @brief Disable bit POS (master/host mode).
<>	149:156823d33999	1613	* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
<>	149:156823d33999	1614	* @rmtoll CR1 POS LL_I2C_DisableBitPOS
<>	149:156823d33999	1615	* @param I2Cx I2C Instance.
<>	149:156823d33999	1616	* @retval None
<>	149:156823d33999	1617	*/
<>	149:156823d33999	1618	__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1619	{
<>	149:156823d33999	1620	CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
<>	149:156823d33999	1621	}
<>	149:156823d33999	1622
<>	149:156823d33999	1623	/**
<>	149:156823d33999	1624	* @brief Check if bit POS is enabled or disabled.
<>	149:156823d33999	1625	* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
<>	149:156823d33999	1626	* @param I2Cx I2C Instance.
<>	149:156823d33999	1627	* @retval State of bit (1 or 0).
<>	149:156823d33999	1628	*/
<>	149:156823d33999	1629	__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1630	{
<>	149:156823d33999	1631	return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
<>	149:156823d33999	1632	}
<>	149:156823d33999	1633
<>	149:156823d33999	1634	/**
<>	149:156823d33999	1635	* @brief Indicate the value of transfer direction.
<>	149:156823d33999	1636	* @note RESET: Bus is in read transfer (peripheral point of view).
<>	149:156823d33999	1637	* SET: Bus is in write transfer (peripheral point of view).
<>	149:156823d33999	1638	* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
<>	149:156823d33999	1639	* @param I2Cx I2C Instance.
<>	149:156823d33999	1640	* @retval Returned value can be one of the following values:
<>	149:156823d33999	1641	* @arg @ref LL_I2C_DIRECTION_WRITE
<>	149:156823d33999	1642	* @arg @ref LL_I2C_DIRECTION_READ
<>	149:156823d33999	1643	*/
<>	149:156823d33999	1644	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1645	{
<>	149:156823d33999	1646	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
<>	149:156823d33999	1647	}
<>	149:156823d33999	1648
<>	149:156823d33999	1649	/**
<>	149:156823d33999	1650	* @brief Enable DMA last transfer.
<>	149:156823d33999	1651	* @note This action mean that next DMA EOT is the last transfer.
<>	149:156823d33999	1652	* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
<>	149:156823d33999	1653	* @param I2Cx I2C Instance.
<>	149:156823d33999	1654	* @retval None
<>	149:156823d33999	1655	*/
<>	149:156823d33999	1656	__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1657	{
<>	149:156823d33999	1658	SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
<>	149:156823d33999	1659	}
<>	149:156823d33999	1660
<>	149:156823d33999	1661	/**
<>	149:156823d33999	1662	* @brief Disable DMA last transfer.
<>	149:156823d33999	1663	* @note This action mean that next DMA EOT is not the last transfer.
<>	149:156823d33999	1664	* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
<>	149:156823d33999	1665	* @param I2Cx I2C Instance.
<>	149:156823d33999	1666	* @retval None
<>	149:156823d33999	1667	*/
<>	149:156823d33999	1668	__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1669	{
<>	149:156823d33999	1670	CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
<>	149:156823d33999	1671	}
<>	149:156823d33999	1672
<>	149:156823d33999	1673	/**
<>	149:156823d33999	1674	* @brief Check if DMA last transfer is enabled or disabled.
<>	149:156823d33999	1675	* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
<>	149:156823d33999	1676	* @param I2Cx I2C Instance.
<>	149:156823d33999	1677	* @retval State of bit (1 or 0).
<>	149:156823d33999	1678	*/
<>	149:156823d33999	1679	__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1680	{
<>	149:156823d33999	1681	return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
<>	149:156823d33999	1682	}
<>	149:156823d33999	1683
<>	149:156823d33999	1684	/**
<>	149:156823d33999	1685	* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	149:156823d33999	1686	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1687	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1688	* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
<>	149:156823d33999	1689	* or by a START or STOP condition, it is also cleared by software.
<>	149:156823d33999	1690	* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
<>	149:156823d33999	1691	* @param I2Cx I2C Instance.
<>	149:156823d33999	1692	* @retval None
<>	149:156823d33999	1693	*/
<>	149:156823d33999	1694	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1695	{
<>	149:156823d33999	1696	SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
<>	149:156823d33999	1697	}
<>	149:156823d33999	1698
<>	149:156823d33999	1699	/**
<>	149:156823d33999	1700	* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	149:156823d33999	1701	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1702	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1703	* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
<>	149:156823d33999	1704	* @param I2Cx I2C Instance.
<>	149:156823d33999	1705	* @retval None
<>	149:156823d33999	1706	*/
<>	149:156823d33999	1707	__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1708	{
<>	149:156823d33999	1709	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
<>	149:156823d33999	1710	}
<>	149:156823d33999	1711
<>	149:156823d33999	1712	/**
<>	149:156823d33999	1713	* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
<>	149:156823d33999	1714	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1715	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1716	* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
<>	149:156823d33999	1717	* @param I2Cx I2C Instance.
<>	149:156823d33999	1718	* @retval State of bit (1 or 0).
<>	149:156823d33999	1719	*/
<>	149:156823d33999	1720	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1721	{
<>	149:156823d33999	1722	return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
<>	149:156823d33999	1723	}
<>	149:156823d33999	1724
<>	149:156823d33999	1725	/**
<>	149:156823d33999	1726	* @brief Get the SMBus Packet Error byte calculated.
<>	149:156823d33999	1727	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	149:156823d33999	1728	* SMBus feature is supported by the I2Cx Instance.
<>	149:156823d33999	1729	* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
<>	149:156823d33999	1730	* @param I2Cx I2C Instance.
<>	149:156823d33999	1731	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	149:156823d33999	1732	*/
<>	149:156823d33999	1733	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1734	{
AnnaBridge	184:08ed48f1de7f	1735	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
<>	149:156823d33999	1736	}
<>	149:156823d33999	1737
<>	149:156823d33999	1738	/**
<>	149:156823d33999	1739	* @brief Read Receive Data register.
<>	149:156823d33999	1740	* @rmtoll DR DR LL_I2C_ReceiveData8
<>	149:156823d33999	1741	* @param I2Cx I2C Instance.
<>	149:156823d33999	1742	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
<>	149:156823d33999	1743	*/
<>	149:156823d33999	1744	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
<>	149:156823d33999	1745	{
<>	149:156823d33999	1746	return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
<>	149:156823d33999	1747	}
<>	149:156823d33999	1748
<>	149:156823d33999	1749	/**
<>	149:156823d33999	1750	* @brief Write in Transmit Data Register .
<>	149:156823d33999	1751	* @rmtoll DR DR LL_I2C_TransmitData8
<>	149:156823d33999	1752	* @param I2Cx I2C Instance.
<>	149:156823d33999	1753	* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
<>	149:156823d33999	1754	* @retval None
<>	149:156823d33999	1755	*/
<>	149:156823d33999	1756	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
<>	149:156823d33999	1757	{
<>	149:156823d33999	1758	MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
<>	149:156823d33999	1759	}
<>	149:156823d33999	1760
<>	149:156823d33999	1761	/**
<>	149:156823d33999	1762	* @}
<>	149:156823d33999	1763	*/
<>	149:156823d33999	1764
<>	149:156823d33999	1765	#if defined(USE_FULL_LL_DRIVER)
<>	149:156823d33999	1766	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
<>	149:156823d33999	1767	* @{
<>	149:156823d33999	1768	*/
<>	149:156823d33999	1769
<>	149:156823d33999	1770	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
<>	149:156823d33999	1771	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
<>	149:156823d33999	1772	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
<>	149:156823d33999	1773
<>	149:156823d33999	1774
<>	149:156823d33999	1775	/**
<>	149:156823d33999	1776	* @}
<>	149:156823d33999	1777	*/
<>	149:156823d33999	1778	#endif /* USE_FULL_LL_DRIVER */
<>	149:156823d33999	1779
<>	149:156823d33999	1780	/**
<>	149:156823d33999	1781	* @}
<>	149:156823d33999	1782	*/
<>	149:156823d33999	1783
<>	149:156823d33999	1784	/**
<>	149:156823d33999	1785	* @}
<>	149:156823d33999	1786	*/
<>	149:156823d33999	1787
<>	149:156823d33999	1788	#endif /* I2C1 \|\| I2C2 */
<>	149:156823d33999	1789
<>	149:156823d33999	1790	/**
<>	149:156823d33999	1791	* @}
<>	149:156823d33999	1792	*/
<>	149:156823d33999	1793
<>	149:156823d33999	1794	#ifdef __cplusplus
<>	149:156823d33999	1795	}
<>	149:156823d33999	1796	#endif
<>	149:156823d33999	1797
<>	149:156823d33999	1798	#endif /* __STM32L1xx_LL_I2C_H */
<>	149:156823d33999	1799
<>	149:156823d33999	1800	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/