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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_fsmc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_fsmc.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Header file of FSMC HAL module.
<> 149:156823d33999 6 ******************************************************************************
<> 149:156823d33999 7 * @attention
<> 149:156823d33999 8 *
AnnaBridge 184:08ed48f1de7f 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 12 * are permitted provided that the following conditions are met:
<> 149:156823d33999 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 14 * this list of conditions and the following disclaimer.
<> 149:156823d33999 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 17 * and/or other materials provided with the distribution.
<> 149:156823d33999 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 19 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 20 * without specific prior written permission.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 32 *
<> 149:156823d33999 33 ******************************************************************************
<> 149:156823d33999 34 */
<> 149:156823d33999 35
<> 149:156823d33999 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 37 #ifndef __STM32L1xx_LL_FSMC_H
<> 149:156823d33999 38 #define __STM32L1xx_LL_FSMC_H
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifdef __cplusplus
<> 149:156823d33999 41 extern "C" {
<> 149:156823d33999 42 #endif
<> 149:156823d33999 43
<> 149:156823d33999 44 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 45 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 46
<> 149:156823d33999 47 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 48 * @{
<> 149:156823d33999 49 */
<> 149:156823d33999 50
<> 149:156823d33999 51 #if defined(FSMC_BANK1)
<> 149:156823d33999 52
<> 149:156823d33999 53 /** @addtogroup FSMC_LL
<> 149:156823d33999 54 * @{
<> 149:156823d33999 55 */
<> 149:156823d33999 56
<> 149:156823d33999 57 /** @addtogroup FSMC_LL_Private_Macros
<> 149:156823d33999 58 * @{
<> 149:156823d33999 59 */
<> 149:156823d33999 60
<> 149:156823d33999 61 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
<> 149:156823d33999 62 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
<> 149:156823d33999 63 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
<> 149:156823d33999 64 ((__BANK__) == FSMC_NORSRAM_BANK4))
<> 149:156823d33999 65
<> 149:156823d33999 66 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
<> 149:156823d33999 67 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
<> 149:156823d33999 68
<> 149:156823d33999 69 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
<> 149:156823d33999 70 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
<> 149:156823d33999 71 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
<> 149:156823d33999 72
<> 149:156823d33999 73 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
<> 149:156823d33999 74 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
<> 149:156823d33999 75 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
<> 149:156823d33999 76
<> 149:156823d33999 77 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
<> 149:156823d33999 78 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
<> 149:156823d33999 79
<> 149:156823d33999 80 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
<> 149:156823d33999 81 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
<> 149:156823d33999 82 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
<> 149:156823d33999 83 ((__MODE__) == FSMC_ACCESS_MODE_D))
<> 149:156823d33999 84
<> 149:156823d33999 85
<> 149:156823d33999 86 /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
<> 149:156823d33999 87 * @{
<> 149:156823d33999 88 */
<> 149:156823d33999 89
<> 149:156823d33999 90 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
<> 149:156823d33999 91
<> 149:156823d33999 92 /**
<> 149:156823d33999 93 * @}
<> 149:156823d33999 94 */
<> 149:156823d33999 95
<> 149:156823d33999 96 /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
<> 149:156823d33999 97 * @{
<> 149:156823d33999 98 */
<> 149:156823d33999 99
<> 149:156823d33999 100 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
<> 149:156823d33999 101
<> 149:156823d33999 102 /**
<> 149:156823d33999 103 * @}
<> 149:156823d33999 104 */
<> 149:156823d33999 105
<> 149:156823d33999 106 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
<> 149:156823d33999 107 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
<> 149:156823d33999 108
<> 149:156823d33999 109 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
<> 149:156823d33999 110 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
<> 149:156823d33999 111
<> 149:156823d33999 112 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
<> 149:156823d33999 113 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
<> 149:156823d33999 114
<> 149:156823d33999 115 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
<> 149:156823d33999 116 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
<> 149:156823d33999 117
<> 149:156823d33999 118 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
<> 149:156823d33999 119 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
<> 149:156823d33999 120
<> 149:156823d33999 121 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
<> 149:156823d33999 122 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
<> 149:156823d33999 123
<> 149:156823d33999 124 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
<> 149:156823d33999 125 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
<> 149:156823d33999 126
<> 149:156823d33999 127 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
<> 149:156823d33999 128 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
<> 149:156823d33999 129
<> 149:156823d33999 130 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
<> 149:156823d33999 131
<> 149:156823d33999 132 /** @defgroup FSMC_Data_Latency FSMC Data Latency
<> 149:156823d33999 133 * @{
<> 149:156823d33999 134 */
<> 149:156823d33999 135 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
<> 149:156823d33999 136 /**
<> 149:156823d33999 137 * @}
<> 149:156823d33999 138 */
<> 149:156823d33999 139
<> 149:156823d33999 140 /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
<> 149:156823d33999 141 * @{
<> 149:156823d33999 142 */
<> 149:156823d33999 143 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
<> 149:156823d33999 144 /**
<> 149:156823d33999 145 * @}
<> 149:156823d33999 146 */
<> 149:156823d33999 147
<> 149:156823d33999 148 /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
<> 149:156823d33999 149 * @{
<> 149:156823d33999 150 */
<> 149:156823d33999 151 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
<> 149:156823d33999 152 /**
<> 149:156823d33999 153 * @}
<> 149:156823d33999 154 */
<> 149:156823d33999 155
<> 149:156823d33999 156 /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
<> 149:156823d33999 157 * @{
<> 149:156823d33999 158 */
<> 149:156823d33999 159 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
<> 149:156823d33999 160 /**
<> 149:156823d33999 161 * @}
<> 149:156823d33999 162 */
<> 149:156823d33999 163
<> 149:156823d33999 164 /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
<> 149:156823d33999 165 * @{
<> 149:156823d33999 166 */
<> 149:156823d33999 167 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
<> 149:156823d33999 168 /**
<> 149:156823d33999 169 * @}
<> 149:156823d33999 170 */
<> 149:156823d33999 171
<> 149:156823d33999 172 /**
<> 149:156823d33999 173 * @}
<> 149:156823d33999 174 */
<> 149:156823d33999 175
<> 149:156823d33999 176 /* Exported typedef ----------------------------------------------------------*/
<> 149:156823d33999 177
<> 149:156823d33999 178 /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
<> 149:156823d33999 179 * @{
<> 149:156823d33999 180 */
<> 149:156823d33999 181
<> 149:156823d33999 182 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
<> 149:156823d33999 183 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
<> 149:156823d33999 184
<> 149:156823d33999 185 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
<> 149:156823d33999 186 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
<> 149:156823d33999 187
<> 149:156823d33999 188 /**
<> 149:156823d33999 189 * @brief FSMC_NORSRAM Configuration Structure definition
<> 149:156823d33999 190 */
<> 149:156823d33999 191 typedef struct
<> 149:156823d33999 192 {
<> 149:156823d33999 193 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
<> 149:156823d33999 194 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
<> 149:156823d33999 195
<> 149:156823d33999 196 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
<> 149:156823d33999 197 multiplexed on the data bus or not.
<> 149:156823d33999 198 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
<> 149:156823d33999 199
<> 149:156823d33999 200 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
<> 149:156823d33999 201 the corresponding memory device.
<> 149:156823d33999 202 This parameter can be a value of @ref FSMC_Memory_Type */
<> 149:156823d33999 203
<> 149:156823d33999 204 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
<> 149:156823d33999 205 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
<> 149:156823d33999 206
<> 149:156823d33999 207 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
<> 149:156823d33999 208 valid only with synchronous burst Flash memories.
<> 149:156823d33999 209 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
<> 149:156823d33999 210
<> 149:156823d33999 211 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
<> 149:156823d33999 212 the Flash memory in burst mode.
<> 149:156823d33999 213 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
<> 149:156823d33999 214
<> 149:156823d33999 215 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
<> 149:156823d33999 216 memory, valid only when accessing Flash memories in burst mode.
<> 149:156823d33999 217 This parameter can be a value of @ref FSMC_Wrap_Mode */
<> 149:156823d33999 218
<> 149:156823d33999 219 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
<> 149:156823d33999 220 clock cycle before the wait state or during the wait state,
<> 149:156823d33999 221 valid only when accessing memories in burst mode.
<> 149:156823d33999 222 This parameter can be a value of @ref FSMC_Wait_Timing */
<> 149:156823d33999 223
<> 149:156823d33999 224 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
<> 149:156823d33999 225 This parameter can be a value of @ref FSMC_Write_Operation */
<> 149:156823d33999 226
<> 149:156823d33999 227 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
<> 149:156823d33999 228 signal, valid for Flash memory access in burst mode.
<> 149:156823d33999 229 This parameter can be a value of @ref FSMC_Wait_Signal */
<> 149:156823d33999 230
<> 149:156823d33999 231 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
<> 149:156823d33999 232 This parameter can be a value of @ref FSMC_Extended_Mode */
<> 149:156823d33999 233
<> 149:156823d33999 234 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
<> 149:156823d33999 235 valid only with asynchronous Flash memories.
<> 149:156823d33999 236 This parameter can be a value of @ref FSMC_AsynchronousWait */
<> 149:156823d33999 237
<> 149:156823d33999 238 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
<> 149:156823d33999 239 This parameter can be a value of @ref FSMC_Write_Burst */
<> 149:156823d33999 240
<> 149:156823d33999 241 }FSMC_NORSRAM_InitTypeDef;
<> 149:156823d33999 242
<> 149:156823d33999 243 /**
<> 149:156823d33999 244 * @brief FSMC_NORSRAM Timing parameters structure definition
<> 149:156823d33999 245 */
<> 149:156823d33999 246 typedef struct
<> 149:156823d33999 247 {
<> 149:156823d33999 248 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 149:156823d33999 249 the duration of the address setup time.
<> 149:156823d33999 250 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 149:156823d33999 251 @note This parameter is not used with synchronous NOR Flash memories. */
<> 149:156823d33999 252
<> 149:156823d33999 253 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
<> 149:156823d33999 254 the duration of the address hold time.
<> 149:156823d33999 255 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
<> 149:156823d33999 256 @note This parameter is not used with synchronous NOR Flash memories. */
<> 149:156823d33999 257
<> 149:156823d33999 258 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 149:156823d33999 259 the duration of the data setup time.
<> 149:156823d33999 260 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
<> 149:156823d33999 261 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
<> 149:156823d33999 262 NOR Flash memories. */
<> 149:156823d33999 263
<> 149:156823d33999 264 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
<> 149:156823d33999 265 the duration of the bus turnaround.
<> 149:156823d33999 266 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 149:156823d33999 267 @note This parameter is only used for multiplexed NOR Flash memories. */
<> 149:156823d33999 268
<> 149:156823d33999 269 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
<> 149:156823d33999 270 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
<> 149:156823d33999 271 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
<> 149:156823d33999 272 accesses. */
<> 149:156823d33999 273
<> 149:156823d33999 274 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
<> 149:156823d33999 275 to the memory before getting the first data.
<> 149:156823d33999 276 The parameter value depends on the memory type as shown below:
<> 149:156823d33999 277 - It must be set to 0 in case of a CRAM
<> 149:156823d33999 278 - It is don't care in asynchronous NOR, SRAM or ROM accesses
<> 149:156823d33999 279 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
<> 149:156823d33999 280 with synchronous burst mode enable */
<> 149:156823d33999 281
<> 149:156823d33999 282 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
<> 149:156823d33999 283 This parameter can be a value of @ref FSMC_Access_Mode */
<> 149:156823d33999 284
<> 149:156823d33999 285 }FSMC_NORSRAM_TimingTypeDef;
<> 149:156823d33999 286
<> 149:156823d33999 287 /**
<> 149:156823d33999 288 * @}
<> 149:156823d33999 289 */
<> 149:156823d33999 290
<> 149:156823d33999 291 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 292
<> 149:156823d33999 293 /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
<> 149:156823d33999 294 * @{
<> 149:156823d33999 295 */
<> 149:156823d33999 296
<> 149:156823d33999 297 /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
<> 149:156823d33999 298 * @{
<> 149:156823d33999 299 */
<> 149:156823d33999 300
<> 149:156823d33999 301 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
<> 149:156823d33999 302 * @{
<> 149:156823d33999 303 */
AnnaBridge 184:08ed48f1de7f 304 #define FSMC_NORSRAM_BANK1 (0x00000000U)
AnnaBridge 184:08ed48f1de7f 305 #define FSMC_NORSRAM_BANK2 (0x00000002U)
AnnaBridge 184:08ed48f1de7f 306 #define FSMC_NORSRAM_BANK3 (0x00000004U)
AnnaBridge 184:08ed48f1de7f 307 #define FSMC_NORSRAM_BANK4 (0x00000006U)
<> 149:156823d33999 308
<> 149:156823d33999 309 /**
<> 149:156823d33999 310 * @}
<> 149:156823d33999 311 */
<> 149:156823d33999 312
<> 149:156823d33999 313 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
<> 149:156823d33999 314 * @{
<> 149:156823d33999 315 */
<> 149:156823d33999 316
AnnaBridge 184:08ed48f1de7f 317 #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
<> 149:156823d33999 318 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN)
<> 149:156823d33999 319
<> 149:156823d33999 320 /**
<> 149:156823d33999 321 * @}
<> 149:156823d33999 322 */
<> 149:156823d33999 323
<> 149:156823d33999 324 /** @defgroup FSMC_Memory_Type FSMC Memory Type
<> 149:156823d33999 325 * @{
<> 149:156823d33999 326 */
<> 149:156823d33999 327
AnnaBridge 184:08ed48f1de7f 328 #define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
<> 149:156823d33999 329 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
<> 149:156823d33999 330 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
<> 149:156823d33999 331
<> 149:156823d33999 332 /**
<> 149:156823d33999 333 * @}
<> 149:156823d33999 334 */
<> 149:156823d33999 335
<> 149:156823d33999 336 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
<> 149:156823d33999 337 * @{
<> 149:156823d33999 338 */
<> 149:156823d33999 339
AnnaBridge 184:08ed48f1de7f 340 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
<> 149:156823d33999 341 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0)
<> 149:156823d33999 342 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1)
<> 149:156823d33999 343
<> 149:156823d33999 344 /**
<> 149:156823d33999 345 * @}
<> 149:156823d33999 346 */
<> 149:156823d33999 347
<> 149:156823d33999 348 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
<> 149:156823d33999 349 * @{
<> 149:156823d33999 350 */
<> 149:156823d33999 351
<> 149:156823d33999 352 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
AnnaBridge 184:08ed48f1de7f 353 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
<> 149:156823d33999 354 /**
<> 149:156823d33999 355 * @}
<> 149:156823d33999 356 */
<> 149:156823d33999 357
<> 149:156823d33999 358 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
<> 149:156823d33999 359 * @{
<> 149:156823d33999 360 */
<> 149:156823d33999 361
AnnaBridge 184:08ed48f1de7f 362 #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
<> 149:156823d33999 363 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
<> 149:156823d33999 364
<> 149:156823d33999 365 /**
<> 149:156823d33999 366 * @}
<> 149:156823d33999 367 */
<> 149:156823d33999 368
<> 149:156823d33999 369
<> 149:156823d33999 370 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
<> 149:156823d33999 371 * @{
<> 149:156823d33999 372 */
<> 149:156823d33999 373
AnnaBridge 184:08ed48f1de7f 374 #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
<> 149:156823d33999 375 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
<> 149:156823d33999 376
<> 149:156823d33999 377 /**
<> 149:156823d33999 378 * @}
<> 149:156823d33999 379 */
<> 149:156823d33999 380
<> 149:156823d33999 381 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
<> 149:156823d33999 382 * @{
<> 149:156823d33999 383 */
<> 149:156823d33999 384
AnnaBridge 184:08ed48f1de7f 385 #define FSMC_WRAP_MODE_DISABLE (0x00000000U)
<> 149:156823d33999 386 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
<> 149:156823d33999 387
<> 149:156823d33999 388 /**
<> 149:156823d33999 389 * @}
<> 149:156823d33999 390 */
<> 149:156823d33999 391
<> 149:156823d33999 392 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
<> 149:156823d33999 393 * @{
<> 149:156823d33999 394 */
<> 149:156823d33999 395
AnnaBridge 184:08ed48f1de7f 396 #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
<> 149:156823d33999 397 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
<> 149:156823d33999 398
<> 149:156823d33999 399 /**
<> 149:156823d33999 400 * @}
<> 149:156823d33999 401 */
<> 149:156823d33999 402
<> 149:156823d33999 403 /** @defgroup FSMC_Write_Operation FSMC Write Operation
<> 149:156823d33999 404 * @{
<> 149:156823d33999 405 */
<> 149:156823d33999 406
AnnaBridge 184:08ed48f1de7f 407 #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
<> 149:156823d33999 408 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
<> 149:156823d33999 409
<> 149:156823d33999 410 /**
<> 149:156823d33999 411 * @}
<> 149:156823d33999 412 */
<> 149:156823d33999 413
<> 149:156823d33999 414 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
<> 149:156823d33999 415 * @{
<> 149:156823d33999 416 */
<> 149:156823d33999 417
AnnaBridge 184:08ed48f1de7f 418 #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
<> 149:156823d33999 419 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
<> 149:156823d33999 420
<> 149:156823d33999 421 /**
<> 149:156823d33999 422 * @}
<> 149:156823d33999 423 */
<> 149:156823d33999 424
<> 149:156823d33999 425 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
<> 149:156823d33999 426 * @{
<> 149:156823d33999 427 */
<> 149:156823d33999 428
AnnaBridge 184:08ed48f1de7f 429 #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
<> 149:156823d33999 430 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
<> 149:156823d33999 431
<> 149:156823d33999 432 /**
<> 149:156823d33999 433 * @}
<> 149:156823d33999 434 */
<> 149:156823d33999 435
<> 149:156823d33999 436 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
<> 149:156823d33999 437 * @{
<> 149:156823d33999 438 */
<> 149:156823d33999 439
AnnaBridge 184:08ed48f1de7f 440 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
<> 149:156823d33999 441 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
<> 149:156823d33999 442
<> 149:156823d33999 443 /**
<> 149:156823d33999 444 * @}
<> 149:156823d33999 445 */
<> 149:156823d33999 446
<> 149:156823d33999 447 /** @defgroup FSMC_Write_Burst FSMC Write Burst
<> 149:156823d33999 448 * @{
<> 149:156823d33999 449 */
<> 149:156823d33999 450
AnnaBridge 184:08ed48f1de7f 451 #define FSMC_WRITE_BURST_DISABLE (0x00000000U)
<> 149:156823d33999 452 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW)
<> 149:156823d33999 453
<> 149:156823d33999 454 /**
<> 149:156823d33999 455 * @}
<> 149:156823d33999 456 */
<> 149:156823d33999 457
<> 149:156823d33999 458 /** @defgroup FSMC_Access_Mode FSMC Access Mode
<> 149:156823d33999 459 * @{
<> 149:156823d33999 460 */
<> 149:156823d33999 461
AnnaBridge 184:08ed48f1de7f 462 #define FSMC_ACCESS_MODE_A (0x00000000U)
<> 149:156823d33999 463 #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
<> 149:156823d33999 464 #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
<> 149:156823d33999 465 #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
<> 149:156823d33999 466
<> 149:156823d33999 467 /**
<> 149:156823d33999 468 * @}
<> 149:156823d33999 469 */
<> 149:156823d33999 470
<> 149:156823d33999 471 /**
<> 149:156823d33999 472 * @}
<> 149:156823d33999 473 */
<> 149:156823d33999 474
<> 149:156823d33999 475
<> 149:156823d33999 476 /**
<> 149:156823d33999 477 * @}
<> 149:156823d33999 478 */
<> 149:156823d33999 479
<> 149:156823d33999 480 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 481
<> 149:156823d33999 482 /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
<> 149:156823d33999 483 * @{
<> 149:156823d33999 484 */
<> 149:156823d33999 485
<> 149:156823d33999 486 /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
<> 149:156823d33999 487 * @brief macros to handle NOR device enable/disable and read/write operations
<> 149:156823d33999 488 * @{
<> 149:156823d33999 489 */
<> 149:156823d33999 490
<> 149:156823d33999 491 /**
<> 149:156823d33999 492 * @brief Enable the NORSRAM device access.
<> 149:156823d33999 493 * @param __INSTANCE__ FSMC_NORSRAM Instance
<> 149:156823d33999 494 * @param __BANK__ FSMC_NORSRAM Bank
<> 149:156823d33999 495 * @retval none
<> 149:156823d33999 496 */
<> 149:156823d33999 497 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
<> 149:156823d33999 498
<> 149:156823d33999 499 /**
<> 149:156823d33999 500 * @brief Disable the NORSRAM device access.
<> 149:156823d33999 501 * @param __INSTANCE__ FSMC_NORSRAM Instance
<> 149:156823d33999 502 * @param __BANK__ FSMC_NORSRAM Bank
<> 149:156823d33999 503 * @retval none
<> 149:156823d33999 504 */
<> 149:156823d33999 505 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
<> 149:156823d33999 506
<> 149:156823d33999 507 /**
<> 149:156823d33999 508 * @}
<> 149:156823d33999 509 */
<> 149:156823d33999 510
<> 149:156823d33999 511
<> 149:156823d33999 512 /**
<> 149:156823d33999 513 * @}
<> 149:156823d33999 514 */
<> 149:156823d33999 515
<> 149:156823d33999 516 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 517
<> 149:156823d33999 518 /** @addtogroup FSMC_LL_Exported_Functions
<> 149:156823d33999 519 * @{
<> 149:156823d33999 520 */
<> 149:156823d33999 521
<> 149:156823d33999 522 /** @addtogroup FSMC_NORSRAM
<> 149:156823d33999 523 * @{
<> 149:156823d33999 524 */
<> 149:156823d33999 525
<> 149:156823d33999 526 /** @addtogroup FSMC_NORSRAM_Group1
<> 149:156823d33999 527 * @{
<> 149:156823d33999 528 */
<> 149:156823d33999 529
<> 149:156823d33999 530 /* FSMC_NORSRAM Controller functions ******************************************/
<> 149:156823d33999 531 /* Initialization/de-initialization functions */
<> 149:156823d33999 532 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
<> 149:156823d33999 533 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
<> 149:156823d33999 534 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
<> 149:156823d33999 535 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
<> 149:156823d33999 536
<> 149:156823d33999 537 /**
<> 149:156823d33999 538 * @}
<> 149:156823d33999 539 */
<> 149:156823d33999 540
<> 149:156823d33999 541 /** @addtogroup FSMC_NORSRAM_Group2
<> 149:156823d33999 542 * @{
<> 149:156823d33999 543 */
<> 149:156823d33999 544
<> 149:156823d33999 545 /* FSMC_NORSRAM Control functions */
<> 149:156823d33999 546 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 149:156823d33999 547 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 149:156823d33999 548
<> 149:156823d33999 549 /**
<> 149:156823d33999 550 * @}
<> 149:156823d33999 551 */
<> 149:156823d33999 552
<> 149:156823d33999 553 /**
<> 149:156823d33999 554 * @}
<> 149:156823d33999 555 */
<> 149:156823d33999 556
<> 149:156823d33999 557 /**
<> 149:156823d33999 558 * @}
<> 149:156823d33999 559 */
<> 149:156823d33999 560
<> 149:156823d33999 561 /**
<> 149:156823d33999 562 * @}
<> 149:156823d33999 563 */
<> 149:156823d33999 564
<> 149:156823d33999 565 #endif /* FSMC_BANK1 */
<> 149:156823d33999 566
<> 149:156823d33999 567 /**
<> 149:156823d33999 568 * @}
<> 149:156823d33999 569 */
<> 149:156823d33999 570
<> 149:156823d33999 571 #ifdef __cplusplus
<> 149:156823d33999 572 }
<> 149:156823d33999 573 #endif
<> 149:156823d33999 574
<> 149:156823d33999 575 #endif /* __STM32L1xx_LL_FSMC_H */
<> 149:156823d33999 576
<> 149:156823d33999 577 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 149:156823d33999 578