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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_fsmc.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_fsmc.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief FSMC Low Layer HAL module driver.
<> 149:156823d33999 6 *
<> 149:156823d33999 7 * This file provides firmware functions to manage the following
<> 149:156823d33999 8 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
<> 149:156823d33999 9 * + Initialization/de-initialization functions
<> 149:156823d33999 10 * + Peripheral Control functions
<> 149:156823d33999 11 * + Peripheral State functions
<> 149:156823d33999 12 *
<> 149:156823d33999 13 @verbatim
<> 149:156823d33999 14 =============================================================================
<> 149:156823d33999 15 ##### FSMC peripheral features #####
<> 149:156823d33999 16 =============================================================================
<> 149:156823d33999 17 [..] The Flexible static memory controller (FSMC) includes following memory controllers:
<> 149:156823d33999 18 (+) The NOR/PSRAM memory controller
<> 149:156823d33999 19
<> 149:156823d33999 20 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
<> 149:156823d33999 21 memories. Its main purposes are:
<> 149:156823d33999 22 (+) to translate AHB transactions into the appropriate external device protocol.
<> 149:156823d33999 23 (+) to meet the access time requirements of the external memory devices.
<> 149:156823d33999 24
<> 149:156823d33999 25 [..] All external memories share the addresses, data and control signals with the controller.
<> 149:156823d33999 26 Each external device is accessed by means of a unique Chip Select. The FSMC performs
<> 149:156823d33999 27 only one access at a time to an external device.
<> 149:156823d33999 28 The main features of the FSMC controller are the following:
<> 149:156823d33999 29 (+) Interface with static-memory mapped devices including:
<> 149:156823d33999 30 (++) Static random access memory (SRAM).
<> 149:156823d33999 31 (++) NOR Flash memory.
<> 149:156823d33999 32 (++) PSRAM (4 memory banks).
<> 149:156823d33999 33 (+) Independent Chip Select control for each memory bank
<> 149:156823d33999 34 (+) Independent configuration for each memory bank
<> 149:156823d33999 35
<> 149:156823d33999 36 @endverbatim
<> 149:156823d33999 37 ******************************************************************************
<> 149:156823d33999 38 * @attention
<> 149:156823d33999 39 *
AnnaBridge 184:08ed48f1de7f 40 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 41 *
<> 149:156823d33999 42 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 43 * are permitted provided that the following conditions are met:
<> 149:156823d33999 44 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 45 * this list of conditions and the following disclaimer.
<> 149:156823d33999 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 47 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 48 * and/or other materials provided with the distribution.
<> 149:156823d33999 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 50 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 51 * without specific prior written permission.
<> 149:156823d33999 52 *
<> 149:156823d33999 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 63 *
<> 149:156823d33999 64 ******************************************************************************
<> 149:156823d33999 65 */
<> 149:156823d33999 66
<> 149:156823d33999 67 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 68 #include "stm32l1xx_hal.h"
<> 149:156823d33999 69
<> 149:156823d33999 70 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 71 * @{
<> 149:156823d33999 72 */
<> 149:156823d33999 73
<> 149:156823d33999 74 #if defined(FSMC_BANK1)
<> 149:156823d33999 75
<> 149:156823d33999 76 #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED)
<> 149:156823d33999 77
<> 149:156823d33999 78 /** @defgroup FSMC_LL FSMC Low Layer
<> 149:156823d33999 79 * @brief FSMC driver modules
<> 149:156823d33999 80 * @{
<> 149:156823d33999 81 */
<> 149:156823d33999 82
<> 149:156823d33999 83 /* Private typedef -----------------------------------------------------------*/
<> 149:156823d33999 84 /* Private define ------------------------------------------------------------*/
<> 149:156823d33999 85 /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
<> 149:156823d33999 86 * @{
<> 149:156823d33999 87 */
<> 149:156823d33999 88
<> 149:156823d33999 89 /* ----------------------- FSMC registers bit mask --------------------------- */
<> 149:156823d33999 90 /* --- BCR Register ---*/
<> 149:156823d33999 91 /* BCR register clear mask */
<> 149:156823d33999 92 #define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \
<> 149:156823d33999 93 FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \
<> 149:156823d33999 94 FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \
<> 149:156823d33999 95 FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
<> 149:156823d33999 96 FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \
<> 149:156823d33999 97 FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \
<> 149:156823d33999 98 FSMC_BCRx_CBURSTRW))
<> 149:156823d33999 99 /* --- BTR Register ---*/
<> 149:156823d33999 100 /* BTR register clear mask */
<> 149:156823d33999 101 #define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\
<> 149:156823d33999 102 FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
<> 149:156823d33999 103 FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\
<> 149:156823d33999 104 FSMC_BTRx_ACCMOD))
<> 149:156823d33999 105
<> 149:156823d33999 106 /* --- BWTR Register ---*/
<> 149:156823d33999 107 /* BWTR register clear mask */
<> 149:156823d33999 108 #define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
<> 149:156823d33999 109 FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
<> 149:156823d33999 110 FSMC_BWTRx_BUSTURN))
<> 149:156823d33999 111
<> 149:156823d33999 112 /**
<> 149:156823d33999 113 * @}
<> 149:156823d33999 114 */
<> 149:156823d33999 115
<> 149:156823d33999 116 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 117 /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
<> 149:156823d33999 118 * @{
<> 149:156823d33999 119 */
<> 149:156823d33999 120
<> 149:156823d33999 121 /**
<> 149:156823d33999 122 * @}
<> 149:156823d33999 123 */
<> 149:156823d33999 124
<> 149:156823d33999 125 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 126 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 127 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 128
<> 149:156823d33999 129 /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
<> 149:156823d33999 130 * @{
<> 149:156823d33999 131 */
<> 149:156823d33999 132
<> 149:156823d33999 133 /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
<> 149:156823d33999 134 * @brief NORSRAM Controller functions
<> 149:156823d33999 135 *
<> 149:156823d33999 136 @verbatim
<> 149:156823d33999 137 ==============================================================================
<> 149:156823d33999 138 ##### How to use NORSRAM device driver #####
<> 149:156823d33999 139 ==============================================================================
<> 149:156823d33999 140
<> 149:156823d33999 141 [..]
<> 149:156823d33999 142 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
<> 149:156823d33999 143 to run the NORSRAM external devices.
<> 149:156823d33999 144
<> 149:156823d33999 145 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
<> 149:156823d33999 146 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
<> 149:156823d33999 147 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
<> 149:156823d33999 148 (+) FSMC NORSRAM bank extended timing configuration using the function
<> 149:156823d33999 149 FSMC_NORSRAM_Extended_Timing_Init()
<> 149:156823d33999 150 (+) FSMC NORSRAM bank enable/disable write operation using the functions
<> 149:156823d33999 151 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
<> 149:156823d33999 152
<> 149:156823d33999 153
<> 149:156823d33999 154 @endverbatim
<> 149:156823d33999 155 * @{
<> 149:156823d33999 156 */
<> 149:156823d33999 157
<> 149:156823d33999 158 /** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions
<> 149:156823d33999 159 * @brief Initialization and Configuration functions
<> 149:156823d33999 160 *
<> 149:156823d33999 161 @verbatim
<> 149:156823d33999 162 ==============================================================================
<> 149:156823d33999 163 ##### Initialization and de_initialization functions #####
<> 149:156823d33999 164 ==============================================================================
<> 149:156823d33999 165 [..]
<> 149:156823d33999 166 This section provides functions allowing to:
<> 149:156823d33999 167 (+) Initialize and configure the FSMC NORSRAM interface
<> 149:156823d33999 168 (+) De-initialize the FSMC NORSRAM interface
<> 149:156823d33999 169 (+) Configure the FSMC clock and associated GPIOs
<> 149:156823d33999 170
<> 149:156823d33999 171 @endverbatim
<> 149:156823d33999 172 * @{
<> 149:156823d33999 173 */
<> 149:156823d33999 174
<> 149:156823d33999 175 /**
<> 149:156823d33999 176 * @brief Initialize the FSMC_NORSRAM device according to the specified
<> 149:156823d33999 177 * control parameters in the FSMC_NORSRAM_InitTypeDef
<> 149:156823d33999 178 * @param Device Pointer to NORSRAM device instance
<> 149:156823d33999 179 * @param Init Pointer to NORSRAM Initialization structure
<> 149:156823d33999 180 * @retval HAL status
<> 149:156823d33999 181 */
<> 149:156823d33999 182 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
<> 149:156823d33999 183 {
<> 149:156823d33999 184 /* Check the parameters */
<> 149:156823d33999 185 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 149:156823d33999 186 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
<> 149:156823d33999 187 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
<> 149:156823d33999 188 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
<> 149:156823d33999 189 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 149:156823d33999 190 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
<> 149:156823d33999 191 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
<> 149:156823d33999 192 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
<> 149:156823d33999 193 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
<> 149:156823d33999 194 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
<> 149:156823d33999 195 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
<> 149:156823d33999 196 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
<> 149:156823d33999 197 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
<> 149:156823d33999 198 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
<> 149:156823d33999 199
<> 149:156823d33999 200 /* Disable NORSRAM Device */
<> 149:156823d33999 201 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
<> 149:156823d33999 202
<> 149:156823d33999 203 /* Set NORSRAM device control parameters */
<> 149:156823d33999 204 if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
<> 149:156823d33999 205 {
<> 149:156823d33999 206 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
<> 149:156823d33999 207 | Init->DataAddressMux
<> 149:156823d33999 208 | Init->MemoryType
<> 149:156823d33999 209 | Init->MemoryDataWidth
<> 149:156823d33999 210 | Init->BurstAccessMode
<> 149:156823d33999 211 | Init->WaitSignalPolarity
<> 149:156823d33999 212 | Init->WrapMode
<> 149:156823d33999 213 | Init->WaitSignalActive
<> 149:156823d33999 214 | Init->WriteOperation
<> 149:156823d33999 215 | Init->WaitSignal
<> 149:156823d33999 216 | Init->ExtendedMode
<> 149:156823d33999 217 | Init->AsynchronousWait
<> 149:156823d33999 218 | Init->WriteBurst
<> 149:156823d33999 219 )
<> 149:156823d33999 220 );
<> 149:156823d33999 221 }
<> 149:156823d33999 222 else
<> 149:156823d33999 223 {
<> 149:156823d33999 224 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
<> 149:156823d33999 225 | Init->DataAddressMux
<> 149:156823d33999 226 | Init->MemoryType
<> 149:156823d33999 227 | Init->MemoryDataWidth
<> 149:156823d33999 228 | Init->BurstAccessMode
<> 149:156823d33999 229 | Init->WaitSignalPolarity
<> 149:156823d33999 230 | Init->WrapMode
<> 149:156823d33999 231 | Init->WaitSignalActive
<> 149:156823d33999 232 | Init->WriteOperation
<> 149:156823d33999 233 | Init->WaitSignal
<> 149:156823d33999 234 | Init->ExtendedMode
<> 149:156823d33999 235 | Init->AsynchronousWait
<> 149:156823d33999 236 | Init->WriteBurst
<> 149:156823d33999 237 )
<> 149:156823d33999 238 );
<> 149:156823d33999 239 }
<> 149:156823d33999 240
<> 149:156823d33999 241 return HAL_OK;
<> 149:156823d33999 242 }
<> 149:156823d33999 243
<> 149:156823d33999 244
<> 149:156823d33999 245 /**
<> 149:156823d33999 246 * @brief DeInitialize the FSMC_NORSRAM peripheral
<> 149:156823d33999 247 * @param Device Pointer to NORSRAM device instance
<> 149:156823d33999 248 * @param ExDevice Pointer to NORSRAM extended mode device instance
<> 149:156823d33999 249 * @param Bank NORSRAM bank number
<> 149:156823d33999 250 * @retval HAL status
<> 149:156823d33999 251 */
<> 149:156823d33999 252 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
<> 149:156823d33999 253 {
<> 149:156823d33999 254 /* Check the parameters */
<> 149:156823d33999 255 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 149:156823d33999 256 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
<> 149:156823d33999 257 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 149:156823d33999 258
<> 149:156823d33999 259 /* Disable the FSMC_NORSRAM device */
<> 149:156823d33999 260 __FSMC_NORSRAM_DISABLE(Device, Bank);
<> 149:156823d33999 261
<> 149:156823d33999 262 /* De-initialize the FSMC_NORSRAM device */
<> 149:156823d33999 263 /* FSMC_NORSRAM_BANK1 */
<> 149:156823d33999 264 if (Bank == FSMC_NORSRAM_BANK1)
<> 149:156823d33999 265 {
<> 149:156823d33999 266 Device->BTCR[Bank] = 0x000030DB;
<> 149:156823d33999 267 }
<> 149:156823d33999 268 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
<> 149:156823d33999 269 else
<> 149:156823d33999 270 {
<> 149:156823d33999 271 Device->BTCR[Bank] = 0x000030D2;
<> 149:156823d33999 272 }
<> 149:156823d33999 273
<> 149:156823d33999 274 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
<> 149:156823d33999 275 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
<> 149:156823d33999 276
<> 149:156823d33999 277 return HAL_OK;
<> 149:156823d33999 278 }
<> 149:156823d33999 279
<> 149:156823d33999 280
<> 149:156823d33999 281 /**
<> 149:156823d33999 282 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
<> 149:156823d33999 283 * parameters in the FSMC_NORSRAM_TimingTypeDef
<> 149:156823d33999 284 * @param Device Pointer to NORSRAM device instance
<> 149:156823d33999 285 * @param Timing Pointer to NORSRAM Timing structure
<> 149:156823d33999 286 * @param Bank NORSRAM bank number
<> 149:156823d33999 287 * @retval HAL status
<> 149:156823d33999 288 */
<> 149:156823d33999 289 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 149:156823d33999 290 {
<> 149:156823d33999 291 /* Check the parameters */
<> 149:156823d33999 292 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 149:156823d33999 293 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 149:156823d33999 294 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 149:156823d33999 295 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 149:156823d33999 296 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 149:156823d33999 297 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
<> 149:156823d33999 298 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
<> 149:156823d33999 299 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
<> 149:156823d33999 300 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 149:156823d33999 301
<> 149:156823d33999 302 /* Set FSMC_NORSRAM device timing parameters */
<> 149:156823d33999 303 MODIFY_REG(Device->BTCR[Bank + 1], \
<> 149:156823d33999 304 BTR_CLEAR_MASK, \
<> 149:156823d33999 305 (uint32_t)(Timing->AddressSetupTime | \
<> 149:156823d33999 306 ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \
<> 149:156823d33999 307 ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) | \
<> 149:156823d33999 308 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) | \
<> 149:156823d33999 309 (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \
<> 149:156823d33999 310 (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BTRx_DATLAT)) | \
<> 149:156823d33999 311 (Timing->AccessMode)));
<> 149:156823d33999 312
<> 149:156823d33999 313 return HAL_OK;
<> 149:156823d33999 314 }
<> 149:156823d33999 315
<> 149:156823d33999 316 /**
<> 149:156823d33999 317 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
<> 149:156823d33999 318 * parameters in the FSMC_NORSRAM_TimingTypeDef
<> 149:156823d33999 319 * @param Device Pointer to NORSRAM device instance
<> 149:156823d33999 320 * @param Timing Pointer to NORSRAM Timing structure
<> 149:156823d33999 321 * @param Bank NORSRAM bank number
<> 149:156823d33999 322 * @param ExtendedMode FSMC Extended Mode
<> 149:156823d33999 323 * This parameter can be one of the following values:
<> 149:156823d33999 324 * @arg FSMC_EXTENDED_MODE_DISABLE
<> 149:156823d33999 325 * @arg FSMC_EXTENDED_MODE_ENABLE
<> 149:156823d33999 326 * @retval HAL status
<> 149:156823d33999 327 */
<> 149:156823d33999 328 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
<> 149:156823d33999 329 {
<> 149:156823d33999 330 /* Check the parameters */
<> 149:156823d33999 331 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
<> 149:156823d33999 332
<> 149:156823d33999 333 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 149:156823d33999 334 if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
<> 149:156823d33999 335 {
<> 149:156823d33999 336 /* Check the parameters */
<> 149:156823d33999 337 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
<> 149:156823d33999 338 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 149:156823d33999 339 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 149:156823d33999 340 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 149:156823d33999 341 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 149:156823d33999 342 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
<> 149:156823d33999 343 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 149:156823d33999 344
<> 149:156823d33999 345 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 149:156823d33999 346 MODIFY_REG(Device->BWTR[Bank], \
<> 149:156823d33999 347 BWTR_CLEAR_MASK, \
<> 149:156823d33999 348 (uint32_t)(Timing->AddressSetupTime | \
<> 149:156823d33999 349 ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \
<> 149:156823d33999 350 ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \
<> 149:156823d33999 351 Timing->AccessMode | \
<> 149:156823d33999 352 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN))));
<> 149:156823d33999 353 }
<> 149:156823d33999 354 else
<> 149:156823d33999 355 {
<> 149:156823d33999 356 Device->BWTR[Bank] = 0x0FFFFFFF;
<> 149:156823d33999 357 }
<> 149:156823d33999 358
<> 149:156823d33999 359 return HAL_OK;
<> 149:156823d33999 360 }
<> 149:156823d33999 361
<> 149:156823d33999 362
<> 149:156823d33999 363 /**
<> 149:156823d33999 364 * @}
<> 149:156823d33999 365 */
<> 149:156823d33999 366
<> 149:156823d33999 367
<> 149:156823d33999 368 /** @defgroup FSMC_NORSRAM_Group2 Control functions
<> 149:156823d33999 369 * @brief management functions
<> 149:156823d33999 370 *
<> 149:156823d33999 371 @verbatim
<> 149:156823d33999 372 ==============================================================================
<> 149:156823d33999 373 ##### FSMC_NORSRAM Control functions #####
<> 149:156823d33999 374 ==============================================================================
<> 149:156823d33999 375 [..]
<> 149:156823d33999 376 This subsection provides a set of functions allowing to control dynamically
<> 149:156823d33999 377 the FSMC NORSRAM interface.
<> 149:156823d33999 378
<> 149:156823d33999 379 @endverbatim
<> 149:156823d33999 380 * @{
<> 149:156823d33999 381 */
<> 149:156823d33999 382
<> 149:156823d33999 383 /**
<> 149:156823d33999 384 * @brief Enables dynamically FSMC_NORSRAM write operation.
<> 149:156823d33999 385 * @param Device Pointer to NORSRAM device instance
<> 149:156823d33999 386 * @param Bank NORSRAM bank number
<> 149:156823d33999 387 * @retval HAL status
<> 149:156823d33999 388 */
<> 149:156823d33999 389 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 149:156823d33999 390 {
<> 149:156823d33999 391 /* Check the parameters */
<> 149:156823d33999 392 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 149:156823d33999 393 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 149:156823d33999 394
<> 149:156823d33999 395 /* Enable write operation */
<> 149:156823d33999 396 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
<> 149:156823d33999 397
<> 149:156823d33999 398 return HAL_OK;
<> 149:156823d33999 399 }
<> 149:156823d33999 400
<> 149:156823d33999 401 /**
<> 149:156823d33999 402 * @brief Disables dynamically FSMC_NORSRAM write operation.
<> 149:156823d33999 403 * @param Device Pointer to NORSRAM device instance
<> 149:156823d33999 404 * @param Bank NORSRAM bank number
<> 149:156823d33999 405 * @retval HAL status
<> 149:156823d33999 406 */
<> 149:156823d33999 407 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 149:156823d33999 408 {
<> 149:156823d33999 409 /* Check the parameters */
<> 149:156823d33999 410 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 149:156823d33999 411 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 149:156823d33999 412
<> 149:156823d33999 413 /* Disable write operation */
<> 149:156823d33999 414 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
<> 149:156823d33999 415
<> 149:156823d33999 416 return HAL_OK;
<> 149:156823d33999 417 }
<> 149:156823d33999 418
<> 149:156823d33999 419 /**
<> 149:156823d33999 420 * @}
<> 149:156823d33999 421 */
<> 149:156823d33999 422
<> 149:156823d33999 423 /**
<> 149:156823d33999 424 * @}
<> 149:156823d33999 425 */
<> 149:156823d33999 426 /**
<> 149:156823d33999 427 * @}
<> 149:156823d33999 428 */
<> 149:156823d33999 429
<> 149:156823d33999 430 /**
<> 149:156823d33999 431 * @}
<> 149:156823d33999 432 */
<> 149:156823d33999 433
<> 149:156823d33999 434 #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) */
<> 149:156823d33999 435
<> 149:156823d33999 436 #endif /* FSMC_BANK1 */
<> 149:156823d33999 437
<> 149:156823d33999 438 /**
<> 149:156823d33999 439 * @}
<> 149:156823d33999 440 */
<> 149:156823d33999 441
<> 149:156823d33999 442 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/