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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_cortex.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Header file of CORTEX LL module.
<> 149:156823d33999 6 @verbatim
<> 149:156823d33999 7 ==============================================================================
<> 149:156823d33999 8 ##### How to use this driver #####
<> 149:156823d33999 9 ==============================================================================
<> 149:156823d33999 10 [..]
<> 149:156823d33999 11 The LL CORTEX driver contains a set of generic APIs that can be
<> 149:156823d33999 12 used by user:
<> 149:156823d33999 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
<> 149:156823d33999 14 functions
<> 149:156823d33999 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
<> 149:156823d33999 16 (+) MPU API to configure and enable regions
<> 149:156823d33999 17 (+) API to access to MCU info (CPUID register)
<> 149:156823d33999 18 (+) API to enable fault handler (SHCSR accesses)
<> 149:156823d33999 19
<> 149:156823d33999 20 @endverbatim
<> 149:156823d33999 21 ******************************************************************************
<> 149:156823d33999 22 * @attention
<> 149:156823d33999 23 *
AnnaBridge 184:08ed48f1de7f 24 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 27 * are permitted provided that the following conditions are met:
<> 149:156823d33999 28 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 29 * this list of conditions and the following disclaimer.
<> 149:156823d33999 30 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 31 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 32 * and/or other materials provided with the distribution.
<> 149:156823d33999 33 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 34 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 35 * without specific prior written permission.
<> 149:156823d33999 36 *
<> 149:156823d33999 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 40 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 41 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 42 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 43 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 44 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 47 *
<> 149:156823d33999 48 ******************************************************************************
<> 149:156823d33999 49 */
<> 149:156823d33999 50
<> 149:156823d33999 51 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 52 #ifndef __STM32L1xx_LL_CORTEX_H
<> 149:156823d33999 53 #define __STM32L1xx_LL_CORTEX_H
<> 149:156823d33999 54
<> 149:156823d33999 55 #ifdef __cplusplus
<> 149:156823d33999 56 extern "C" {
<> 149:156823d33999 57 #endif
<> 149:156823d33999 58
<> 149:156823d33999 59 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 60 #include "stm32l1xx.h"
<> 149:156823d33999 61
<> 149:156823d33999 62 /** @addtogroup STM32L1xx_LL_Driver
<> 149:156823d33999 63 * @{
<> 149:156823d33999 64 */
<> 149:156823d33999 65
<> 149:156823d33999 66 /** @defgroup CORTEX_LL CORTEX
<> 149:156823d33999 67 * @{
<> 149:156823d33999 68 */
<> 149:156823d33999 69
<> 149:156823d33999 70 /* Private types -------------------------------------------------------------*/
<> 149:156823d33999 71 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 72
<> 149:156823d33999 73 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 74
<> 149:156823d33999 75 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 76
<> 149:156823d33999 77 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 78 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 79 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
<> 149:156823d33999 80 * @{
<> 149:156823d33999 81 */
<> 149:156823d33999 82
<> 149:156823d33999 83 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
<> 149:156823d33999 84 * @{
<> 149:156823d33999 85 */
AnnaBridge 184:08ed48f1de7f 86 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 184:08ed48f1de7f 87 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
<> 149:156823d33999 88 /**
<> 149:156823d33999 89 * @}
<> 149:156823d33999 90 */
<> 149:156823d33999 91
<> 149:156823d33999 92 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
<> 149:156823d33999 93 * @{
<> 149:156823d33999 94 */
<> 149:156823d33999 95 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
<> 149:156823d33999 96 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
<> 149:156823d33999 97 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
<> 149:156823d33999 98 /**
<> 149:156823d33999 99 * @}
<> 149:156823d33999 100 */
<> 149:156823d33999 101
<> 149:156823d33999 102 #if __MPU_PRESENT
<> 149:156823d33999 103
<> 149:156823d33999 104 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
<> 149:156823d33999 105 * @{
<> 149:156823d33999 106 */
AnnaBridge 184:08ed48f1de7f 107 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
<> 149:156823d33999 108 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
<> 149:156823d33999 109 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
<> 149:156823d33999 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
<> 149:156823d33999 111 /**
<> 149:156823d33999 112 * @}
<> 149:156823d33999 113 */
<> 149:156823d33999 114
<> 149:156823d33999 115 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
<> 149:156823d33999 116 * @{
<> 149:156823d33999 117 */
AnnaBridge 184:08ed48f1de7f 118 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 184:08ed48f1de7f 119 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 184:08ed48f1de7f 120 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 184:08ed48f1de7f 121 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 184:08ed48f1de7f 122 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 184:08ed48f1de7f 123 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 184:08ed48f1de7f 124 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 184:08ed48f1de7f 125 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
<> 149:156823d33999 126 /**
<> 149:156823d33999 127 * @}
<> 149:156823d33999 128 */
<> 149:156823d33999 129
<> 149:156823d33999 130 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
<> 149:156823d33999 131 * @{
<> 149:156823d33999 132 */
AnnaBridge 184:08ed48f1de7f 133 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 134 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 135 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 136 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 137 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 138 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 139 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 140 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 141 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 142 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 143 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 144 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 145 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 146 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 147 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 148 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 149 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 150 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 151 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 152 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 153 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 154 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 155 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 156 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 157 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 158 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 159 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 184:08ed48f1de7f 160 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
<> 149:156823d33999 161 /**
<> 149:156823d33999 162 * @}
<> 149:156823d33999 163 */
<> 149:156823d33999 164
<> 149:156823d33999 165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
<> 149:156823d33999 166 * @{
<> 149:156823d33999 167 */
AnnaBridge 184:08ed48f1de7f 168 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 184:08ed48f1de7f 169 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 184:08ed48f1de7f 170 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 184:08ed48f1de7f 171 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 184:08ed48f1de7f 172 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 184:08ed48f1de7f 173 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
<> 149:156823d33999 174 /**
<> 149:156823d33999 175 * @}
<> 149:156823d33999 176 */
<> 149:156823d33999 177
<> 149:156823d33999 178 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
<> 149:156823d33999 179 * @{
<> 149:156823d33999 180 */
AnnaBridge 184:08ed48f1de7f 181 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 184:08ed48f1de7f 182 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 184:08ed48f1de7f 183 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 184:08ed48f1de7f 184 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
<> 149:156823d33999 185 /**
<> 149:156823d33999 186 * @}
<> 149:156823d33999 187 */
<> 149:156823d33999 188
<> 149:156823d33999 189 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
<> 149:156823d33999 190 * @{
<> 149:156823d33999 191 */
AnnaBridge 184:08ed48f1de7f 192 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
<> 149:156823d33999 193 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
<> 149:156823d33999 194 /**
<> 149:156823d33999 195 * @}
<> 149:156823d33999 196 */
<> 149:156823d33999 197
<> 149:156823d33999 198 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
<> 149:156823d33999 199 * @{
<> 149:156823d33999 200 */
<> 149:156823d33999 201 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 184:08ed48f1de7f 202 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
<> 149:156823d33999 203 /**
<> 149:156823d33999 204 * @}
<> 149:156823d33999 205 */
<> 149:156823d33999 206
<> 149:156823d33999 207 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
<> 149:156823d33999 208 * @{
<> 149:156823d33999 209 */
<> 149:156823d33999 210 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 184:08ed48f1de7f 211 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
<> 149:156823d33999 212 /**
<> 149:156823d33999 213 * @}
<> 149:156823d33999 214 */
<> 149:156823d33999 215
<> 149:156823d33999 216 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
<> 149:156823d33999 217 * @{
<> 149:156823d33999 218 */
<> 149:156823d33999 219 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 184:08ed48f1de7f 220 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
<> 149:156823d33999 221 /**
<> 149:156823d33999 222 * @}
<> 149:156823d33999 223 */
<> 149:156823d33999 224 #endif /* __MPU_PRESENT */
<> 149:156823d33999 225 /**
<> 149:156823d33999 226 * @}
<> 149:156823d33999 227 */
<> 149:156823d33999 228
<> 149:156823d33999 229 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 230
<> 149:156823d33999 231 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 232 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
<> 149:156823d33999 233 * @{
<> 149:156823d33999 234 */
<> 149:156823d33999 235
<> 149:156823d33999 236 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
<> 149:156823d33999 237 * @{
<> 149:156823d33999 238 */
<> 149:156823d33999 239
<> 149:156823d33999 240 /**
<> 149:156823d33999 241 * @brief This function checks if the Systick counter flag is active or not.
<> 149:156823d33999 242 * @note It can be used in timeout function on application side.
<> 149:156823d33999 243 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
<> 149:156823d33999 244 * @retval State of bit (1 or 0).
<> 149:156823d33999 245 */
<> 149:156823d33999 246 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
<> 149:156823d33999 247 {
<> 149:156823d33999 248 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
<> 149:156823d33999 249 }
<> 149:156823d33999 250
<> 149:156823d33999 251 /**
<> 149:156823d33999 252 * @brief Configures the SysTick clock source
<> 149:156823d33999 253 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
<> 149:156823d33999 254 * @param Source This parameter can be one of the following values:
<> 149:156823d33999 255 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 149:156823d33999 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 149:156823d33999 257 * @retval None
<> 149:156823d33999 258 */
<> 149:156823d33999 259 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
<> 149:156823d33999 260 {
<> 149:156823d33999 261 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
<> 149:156823d33999 262 {
<> 149:156823d33999 263 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 149:156823d33999 264 }
<> 149:156823d33999 265 else
<> 149:156823d33999 266 {
<> 149:156823d33999 267 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 149:156823d33999 268 }
<> 149:156823d33999 269 }
<> 149:156823d33999 270
<> 149:156823d33999 271 /**
<> 149:156823d33999 272 * @brief Get the SysTick clock source
<> 149:156823d33999 273 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
<> 149:156823d33999 274 * @retval Returned value can be one of the following values:
<> 149:156823d33999 275 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 149:156823d33999 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 149:156823d33999 277 */
<> 149:156823d33999 278 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
<> 149:156823d33999 279 {
<> 149:156823d33999 280 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 149:156823d33999 281 }
<> 149:156823d33999 282
<> 149:156823d33999 283 /**
<> 149:156823d33999 284 * @brief Enable SysTick exception request
<> 149:156823d33999 285 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
<> 149:156823d33999 286 * @retval None
<> 149:156823d33999 287 */
<> 149:156823d33999 288 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
<> 149:156823d33999 289 {
<> 149:156823d33999 290 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 149:156823d33999 291 }
<> 149:156823d33999 292
<> 149:156823d33999 293 /**
<> 149:156823d33999 294 * @brief Disable SysTick exception request
<> 149:156823d33999 295 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
<> 149:156823d33999 296 * @retval None
<> 149:156823d33999 297 */
<> 149:156823d33999 298 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
<> 149:156823d33999 299 {
<> 149:156823d33999 300 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 149:156823d33999 301 }
<> 149:156823d33999 302
<> 149:156823d33999 303 /**
<> 149:156823d33999 304 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
<> 149:156823d33999 305 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
<> 149:156823d33999 306 * @retval State of bit (1 or 0).
<> 149:156823d33999 307 */
<> 149:156823d33999 308 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
<> 149:156823d33999 309 {
<> 149:156823d33999 310 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
<> 149:156823d33999 311 }
<> 149:156823d33999 312
<> 149:156823d33999 313 /**
<> 149:156823d33999 314 * @}
<> 149:156823d33999 315 */
<> 149:156823d33999 316
<> 149:156823d33999 317 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
<> 149:156823d33999 318 * @{
<> 149:156823d33999 319 */
<> 149:156823d33999 320
<> 149:156823d33999 321 /**
<> 149:156823d33999 322 * @brief Processor uses sleep as its low power mode
<> 149:156823d33999 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
<> 149:156823d33999 324 * @retval None
<> 149:156823d33999 325 */
<> 149:156823d33999 326 __STATIC_INLINE void LL_LPM_EnableSleep(void)
<> 149:156823d33999 327 {
<> 149:156823d33999 328 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 149:156823d33999 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 149:156823d33999 330 }
<> 149:156823d33999 331
<> 149:156823d33999 332 /**
<> 149:156823d33999 333 * @brief Processor uses deep sleep as its low power mode
<> 149:156823d33999 334 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
<> 149:156823d33999 335 * @retval None
<> 149:156823d33999 336 */
<> 149:156823d33999 337 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
<> 149:156823d33999 338 {
<> 149:156823d33999 339 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 149:156823d33999 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 149:156823d33999 341 }
<> 149:156823d33999 342
<> 149:156823d33999 343 /**
<> 149:156823d33999 344 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
<> 149:156823d33999 345 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
<> 149:156823d33999 346 * empty main application.
<> 149:156823d33999 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
<> 149:156823d33999 348 * @retval None
<> 149:156823d33999 349 */
<> 149:156823d33999 350 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
<> 149:156823d33999 351 {
<> 149:156823d33999 352 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 149:156823d33999 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 149:156823d33999 354 }
<> 149:156823d33999 355
<> 149:156823d33999 356 /**
<> 149:156823d33999 357 * @brief Do not sleep when returning to Thread mode.
<> 149:156823d33999 358 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
<> 149:156823d33999 359 * @retval None
<> 149:156823d33999 360 */
<> 149:156823d33999 361 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
<> 149:156823d33999 362 {
<> 149:156823d33999 363 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 149:156823d33999 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 149:156823d33999 365 }
<> 149:156823d33999 366
<> 149:156823d33999 367 /**
<> 149:156823d33999 368 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
<> 149:156823d33999 369 * processor.
<> 149:156823d33999 370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
<> 149:156823d33999 371 * @retval None
<> 149:156823d33999 372 */
<> 149:156823d33999 373 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
<> 149:156823d33999 374 {
<> 149:156823d33999 375 /* Set SEVEONPEND bit of Cortex System Control Register */
<> 149:156823d33999 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 149:156823d33999 377 }
<> 149:156823d33999 378
<> 149:156823d33999 379 /**
<> 149:156823d33999 380 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
<> 149:156823d33999 381 * excluded
<> 149:156823d33999 382 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
<> 149:156823d33999 383 * @retval None
<> 149:156823d33999 384 */
<> 149:156823d33999 385 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
<> 149:156823d33999 386 {
<> 149:156823d33999 387 /* Clear SEVEONPEND bit of Cortex System Control Register */
<> 149:156823d33999 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 149:156823d33999 389 }
<> 149:156823d33999 390
<> 149:156823d33999 391 /**
<> 149:156823d33999 392 * @}
<> 149:156823d33999 393 */
<> 149:156823d33999 394
<> 149:156823d33999 395 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
<> 149:156823d33999 396 * @{
<> 149:156823d33999 397 */
<> 149:156823d33999 398
<> 149:156823d33999 399 /**
<> 149:156823d33999 400 * @brief Enable a fault in System handler control register (SHCSR)
<> 149:156823d33999 401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
<> 149:156823d33999 402 * @param Fault This parameter can be a combination of the following values:
<> 149:156823d33999 403 * @arg @ref LL_HANDLER_FAULT_USG
<> 149:156823d33999 404 * @arg @ref LL_HANDLER_FAULT_BUS
<> 149:156823d33999 405 * @arg @ref LL_HANDLER_FAULT_MEM
<> 149:156823d33999 406 * @retval None
<> 149:156823d33999 407 */
<> 149:156823d33999 408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
<> 149:156823d33999 409 {
<> 149:156823d33999 410 /* Enable the system handler fault */
<> 149:156823d33999 411 SET_BIT(SCB->SHCSR, Fault);
<> 149:156823d33999 412 }
<> 149:156823d33999 413
<> 149:156823d33999 414 /**
<> 149:156823d33999 415 * @brief Disable a fault in System handler control register (SHCSR)
<> 149:156823d33999 416 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
<> 149:156823d33999 417 * @param Fault This parameter can be a combination of the following values:
<> 149:156823d33999 418 * @arg @ref LL_HANDLER_FAULT_USG
<> 149:156823d33999 419 * @arg @ref LL_HANDLER_FAULT_BUS
<> 149:156823d33999 420 * @arg @ref LL_HANDLER_FAULT_MEM
<> 149:156823d33999 421 * @retval None
<> 149:156823d33999 422 */
<> 149:156823d33999 423 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
<> 149:156823d33999 424 {
<> 149:156823d33999 425 /* Disable the system handler fault */
<> 149:156823d33999 426 CLEAR_BIT(SCB->SHCSR, Fault);
<> 149:156823d33999 427 }
<> 149:156823d33999 428
<> 149:156823d33999 429 /**
<> 149:156823d33999 430 * @}
<> 149:156823d33999 431 */
<> 149:156823d33999 432
<> 149:156823d33999 433 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
<> 149:156823d33999 434 * @{
<> 149:156823d33999 435 */
<> 149:156823d33999 436
<> 149:156823d33999 437 /**
<> 149:156823d33999 438 * @brief Get Implementer code
<> 149:156823d33999 439 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
<> 149:156823d33999 440 * @retval Value should be equal to 0x41 for ARM
<> 149:156823d33999 441 */
<> 149:156823d33999 442 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
<> 149:156823d33999 443 {
<> 149:156823d33999 444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
<> 149:156823d33999 445 }
<> 149:156823d33999 446
<> 149:156823d33999 447 /**
<> 149:156823d33999 448 * @brief Get Variant number (The r value in the rnpn product revision identifier)
<> 149:156823d33999 449 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
<> 149:156823d33999 450 * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
<> 149:156823d33999 451 */
<> 149:156823d33999 452 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
<> 149:156823d33999 453 {
<> 149:156823d33999 454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
<> 149:156823d33999 455 }
<> 149:156823d33999 456
<> 149:156823d33999 457 /**
<> 149:156823d33999 458 * @brief Get Constant number
<> 149:156823d33999 459 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
<> 149:156823d33999 460 * @retval Value should be equal to 0xF for Cortex-M3 devices
<> 149:156823d33999 461 */
<> 149:156823d33999 462 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
<> 149:156823d33999 463 {
<> 149:156823d33999 464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
<> 149:156823d33999 465 }
<> 149:156823d33999 466
<> 149:156823d33999 467 /**
<> 149:156823d33999 468 * @brief Get Part number
<> 149:156823d33999 469 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
<> 149:156823d33999 470 * @retval Value should be equal to 0xC23 for Cortex-M3
<> 149:156823d33999 471 */
<> 149:156823d33999 472 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
<> 149:156823d33999 473 {
<> 149:156823d33999 474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
<> 149:156823d33999 475 }
<> 149:156823d33999 476
<> 149:156823d33999 477 /**
<> 149:156823d33999 478 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
<> 149:156823d33999 479 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
<> 149:156823d33999 480 * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
<> 149:156823d33999 481 */
<> 149:156823d33999 482 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
<> 149:156823d33999 483 {
<> 149:156823d33999 484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
<> 149:156823d33999 485 }
<> 149:156823d33999 486
<> 149:156823d33999 487 /**
<> 149:156823d33999 488 * @}
<> 149:156823d33999 489 */
<> 149:156823d33999 490
<> 149:156823d33999 491 #if __MPU_PRESENT
<> 149:156823d33999 492 /** @defgroup CORTEX_LL_EF_MPU MPU
<> 149:156823d33999 493 * @{
<> 149:156823d33999 494 */
<> 149:156823d33999 495
<> 149:156823d33999 496 /**
<> 149:156823d33999 497 * @brief Enable MPU with input options
<> 149:156823d33999 498 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
<> 149:156823d33999 499 * @param Options This parameter can be one of the following values:
<> 149:156823d33999 500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
<> 149:156823d33999 501 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
<> 149:156823d33999 502 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
<> 149:156823d33999 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
<> 149:156823d33999 504 * @retval None
<> 149:156823d33999 505 */
<> 149:156823d33999 506 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
<> 149:156823d33999 507 {
<> 149:156823d33999 508 /* Enable the MPU*/
<> 149:156823d33999 509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
<> 149:156823d33999 510 /* Ensure MPU settings take effects */
<> 149:156823d33999 511 __DSB();
<> 149:156823d33999 512 /* Sequence instruction fetches using update settings */
<> 149:156823d33999 513 __ISB();
<> 149:156823d33999 514 }
<> 149:156823d33999 515
<> 149:156823d33999 516 /**
<> 149:156823d33999 517 * @brief Disable MPU
<> 149:156823d33999 518 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
<> 149:156823d33999 519 * @retval None
<> 149:156823d33999 520 */
<> 149:156823d33999 521 __STATIC_INLINE void LL_MPU_Disable(void)
<> 149:156823d33999 522 {
<> 149:156823d33999 523 /* Make sure outstanding transfers are done */
<> 149:156823d33999 524 __DMB();
<> 149:156823d33999 525 /* Disable MPU*/
<> 149:156823d33999 526 WRITE_REG(MPU->CTRL, 0U);
<> 149:156823d33999 527 }
<> 149:156823d33999 528
<> 149:156823d33999 529 /**
<> 149:156823d33999 530 * @brief Check if MPU is enabled or not
<> 149:156823d33999 531 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
<> 149:156823d33999 532 * @retval State of bit (1 or 0).
<> 149:156823d33999 533 */
<> 149:156823d33999 534 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
<> 149:156823d33999 535 {
<> 149:156823d33999 536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
<> 149:156823d33999 537 }
<> 149:156823d33999 538
<> 149:156823d33999 539 /**
<> 149:156823d33999 540 * @brief Enable a MPU region
<> 149:156823d33999 541 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
<> 149:156823d33999 542 * @param Region This parameter can be one of the following values:
<> 149:156823d33999 543 * @arg @ref LL_MPU_REGION_NUMBER0
<> 149:156823d33999 544 * @arg @ref LL_MPU_REGION_NUMBER1
<> 149:156823d33999 545 * @arg @ref LL_MPU_REGION_NUMBER2
<> 149:156823d33999 546 * @arg @ref LL_MPU_REGION_NUMBER3
<> 149:156823d33999 547 * @arg @ref LL_MPU_REGION_NUMBER4
<> 149:156823d33999 548 * @arg @ref LL_MPU_REGION_NUMBER5
<> 149:156823d33999 549 * @arg @ref LL_MPU_REGION_NUMBER6
<> 149:156823d33999 550 * @arg @ref LL_MPU_REGION_NUMBER7
<> 149:156823d33999 551 * @retval None
<> 149:156823d33999 552 */
<> 149:156823d33999 553 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
<> 149:156823d33999 554 {
<> 149:156823d33999 555 /* Set Region number */
<> 149:156823d33999 556 WRITE_REG(MPU->RNR, Region);
<> 149:156823d33999 557 /* Enable the MPU region */
<> 149:156823d33999 558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 149:156823d33999 559 }
<> 149:156823d33999 560
<> 149:156823d33999 561 /**
<> 149:156823d33999 562 * @brief Configure and enable a region
<> 149:156823d33999 563 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
<> 149:156823d33999 564 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
<> 149:156823d33999 565 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
<> 149:156823d33999 566 * MPU_RASR XN LL_MPU_ConfigRegion\n
<> 149:156823d33999 567 * MPU_RASR AP LL_MPU_ConfigRegion\n
<> 149:156823d33999 568 * MPU_RASR S LL_MPU_ConfigRegion\n
<> 149:156823d33999 569 * MPU_RASR C LL_MPU_ConfigRegion\n
<> 149:156823d33999 570 * MPU_RASR B LL_MPU_ConfigRegion\n
<> 149:156823d33999 571 * MPU_RASR SIZE LL_MPU_ConfigRegion
<> 149:156823d33999 572 * @param Region This parameter can be one of the following values:
<> 149:156823d33999 573 * @arg @ref LL_MPU_REGION_NUMBER0
<> 149:156823d33999 574 * @arg @ref LL_MPU_REGION_NUMBER1
<> 149:156823d33999 575 * @arg @ref LL_MPU_REGION_NUMBER2
<> 149:156823d33999 576 * @arg @ref LL_MPU_REGION_NUMBER3
<> 149:156823d33999 577 * @arg @ref LL_MPU_REGION_NUMBER4
<> 149:156823d33999 578 * @arg @ref LL_MPU_REGION_NUMBER5
<> 149:156823d33999 579 * @arg @ref LL_MPU_REGION_NUMBER6
<> 149:156823d33999 580 * @arg @ref LL_MPU_REGION_NUMBER7
<> 149:156823d33999 581 * @param Address Value of region base address
<> 149:156823d33999 582 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
<> 149:156823d33999 583 * @param Attributes This parameter can be a combination of the following values:
<> 149:156823d33999 584 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
<> 149:156823d33999 585 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
<> 149:156823d33999 586 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
<> 149:156823d33999 587 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
<> 149:156823d33999 588 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
<> 149:156823d33999 589 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
<> 149:156823d33999 590 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
<> 149:156823d33999 591 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
<> 149:156823d33999 592 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
<> 149:156823d33999 593 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
<> 149:156823d33999 594 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
<> 149:156823d33999 595 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
<> 149:156823d33999 596 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
<> 149:156823d33999 597 * @retval None
<> 149:156823d33999 598 */
<> 149:156823d33999 599 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
<> 149:156823d33999 600 {
<> 149:156823d33999 601 /* Set Region number */
<> 149:156823d33999 602 WRITE_REG(MPU->RNR, Region);
<> 149:156823d33999 603 /* Set base address */
<> 149:156823d33999 604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
<> 149:156823d33999 605 /* Configure MPU */
<> 149:156823d33999 606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
<> 149:156823d33999 607 }
<> 149:156823d33999 608
<> 149:156823d33999 609 /**
<> 149:156823d33999 610 * @brief Disable a region
<> 149:156823d33999 611 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
<> 149:156823d33999 612 * MPU_RASR ENABLE LL_MPU_DisableRegion
<> 149:156823d33999 613 * @param Region This parameter can be one of the following values:
<> 149:156823d33999 614 * @arg @ref LL_MPU_REGION_NUMBER0
<> 149:156823d33999 615 * @arg @ref LL_MPU_REGION_NUMBER1
<> 149:156823d33999 616 * @arg @ref LL_MPU_REGION_NUMBER2
<> 149:156823d33999 617 * @arg @ref LL_MPU_REGION_NUMBER3
<> 149:156823d33999 618 * @arg @ref LL_MPU_REGION_NUMBER4
<> 149:156823d33999 619 * @arg @ref LL_MPU_REGION_NUMBER5
<> 149:156823d33999 620 * @arg @ref LL_MPU_REGION_NUMBER6
<> 149:156823d33999 621 * @arg @ref LL_MPU_REGION_NUMBER7
<> 149:156823d33999 622 * @retval None
<> 149:156823d33999 623 */
<> 149:156823d33999 624 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
<> 149:156823d33999 625 {
<> 149:156823d33999 626 /* Set Region number */
<> 149:156823d33999 627 WRITE_REG(MPU->RNR, Region);
<> 149:156823d33999 628 /* Disable the MPU region */
<> 149:156823d33999 629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 149:156823d33999 630 }
<> 149:156823d33999 631
<> 149:156823d33999 632 /**
<> 149:156823d33999 633 * @}
<> 149:156823d33999 634 */
<> 149:156823d33999 635
<> 149:156823d33999 636 #endif /* __MPU_PRESENT */
<> 149:156823d33999 637 /**
<> 149:156823d33999 638 * @}
<> 149:156823d33999 639 */
<> 149:156823d33999 640
<> 149:156823d33999 641 /**
<> 149:156823d33999 642 * @}
<> 149:156823d33999 643 */
<> 149:156823d33999 644
<> 149:156823d33999 645 /**
<> 149:156823d33999 646 * @}
<> 149:156823d33999 647 */
<> 149:156823d33999 648
<> 149:156823d33999 649 #ifdef __cplusplus
<> 149:156823d33999 650 }
<> 149:156823d33999 651 #endif
<> 149:156823d33999 652
<> 149:156823d33999 653 #endif /* __STM32L1xx_LL_CORTEX_H */
<> 149:156823d33999 654
<> 149:156823d33999 655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/