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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_spi.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Header file of SPI HAL module.
<> 149:156823d33999 6 ******************************************************************************
<> 149:156823d33999 7 * @attention
<> 149:156823d33999 8 *
AnnaBridge 184:08ed48f1de7f 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 12 * are permitted provided that the following conditions are met:
<> 149:156823d33999 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 14 * this list of conditions and the following disclaimer.
<> 149:156823d33999 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 17 * and/or other materials provided with the distribution.
<> 149:156823d33999 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 19 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 20 * without specific prior written permission.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 32 *
<> 149:156823d33999 33 ******************************************************************************
<> 149:156823d33999 34 */
<> 149:156823d33999 35
<> 149:156823d33999 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 37 #ifndef __STM32L1xx_HAL_SPI_H
<> 149:156823d33999 38 #define __STM32L1xx_HAL_SPI_H
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifdef __cplusplus
<> 149:156823d33999 41 extern "C" {
<> 149:156823d33999 42 #endif
<> 149:156823d33999 43
<> 149:156823d33999 44 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 45 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 46
<> 149:156823d33999 47 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 48 * @{
<> 149:156823d33999 49 */
<> 149:156823d33999 50
<> 149:156823d33999 51 /** @addtogroup SPI
<> 149:156823d33999 52 * @{
<> 149:156823d33999 53 */
<> 149:156823d33999 54
<> 149:156823d33999 55 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 56 /** @defgroup SPI_Exported_Types SPI Exported Types
<> 149:156823d33999 57 * @{
<> 149:156823d33999 58 */
<> 149:156823d33999 59
<> 149:156823d33999 60 /**
<> 149:156823d33999 61 * @brief SPI Configuration Structure definition
<> 149:156823d33999 62 */
<> 149:156823d33999 63 typedef struct
<> 149:156823d33999 64 {
<> 149:156823d33999 65 uint32_t Mode; /*!< Specifies the SPI operating mode.
<> 149:156823d33999 66 This parameter can be a value of @ref SPI_mode */
<> 149:156823d33999 67
<> 149:156823d33999 68 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
<> 149:156823d33999 69 This parameter can be a value of @ref SPI_Direction_mode */
<> 149:156823d33999 70
<> 149:156823d33999 71 uint32_t DataSize; /*!< Specifies the SPI data size.
<> 149:156823d33999 72 This parameter can be a value of @ref SPI_data_size */
<> 149:156823d33999 73
<> 149:156823d33999 74 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
<> 149:156823d33999 75 This parameter can be a value of @ref SPI_Clock_Polarity */
<> 149:156823d33999 76
<> 149:156823d33999 77 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
<> 149:156823d33999 78 This parameter can be a value of @ref SPI_Clock_Phase */
<> 149:156823d33999 79
<> 149:156823d33999 80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
<> 149:156823d33999 81 hardware (NSS pin) or by software using the SSI bit.
<> 149:156823d33999 82 This parameter can be a value of @ref SPI_Slave_Select_management */
<> 149:156823d33999 83
<> 149:156823d33999 84 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
<> 149:156823d33999 85 used to configure the transmit and receive SCK clock.
<> 149:156823d33999 86 This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 149:156823d33999 87 @note The communication clock is derived from the master
<> 149:156823d33999 88 clock. The slave clock does not need to be set */
<> 149:156823d33999 89
<> 149:156823d33999 90 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 149:156823d33999 91 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
<> 149:156823d33999 92
<> 149:156823d33999 93 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
<> 149:156823d33999 94 This parameter can be a value of @ref SPI_TI_mode */
<> 149:156823d33999 95
<> 149:156823d33999 96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 149:156823d33999 97 This parameter can be a value of @ref SPI_CRC_Calculation */
<> 149:156823d33999 98
<> 149:156823d33999 99 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
<> 149:156823d33999 100 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
<> 149:156823d33999 101
<> 149:156823d33999 102 }SPI_InitTypeDef;
<> 149:156823d33999 103
<> 149:156823d33999 104 /**
<> 149:156823d33999 105 * @brief HAL SPI State structure definition
<> 149:156823d33999 106 */
<> 149:156823d33999 107 typedef enum
<> 149:156823d33999 108 {
<> 149:156823d33999 109 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
<> 149:156823d33999 110 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
<> 149:156823d33999 111 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
<> 149:156823d33999 112 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 149:156823d33999 113 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 149:156823d33999 114 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
<> 149:156823d33999 115 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
<> 149:156823d33999 116
<> 149:156823d33999 117 }HAL_SPI_StateTypeDef;
<> 149:156823d33999 118
<> 149:156823d33999 119 /**
<> 149:156823d33999 120 * @brief SPI handle Structure definition
<> 149:156823d33999 121 */
<> 149:156823d33999 122 typedef struct __SPI_HandleTypeDef
<> 149:156823d33999 123 {
<> 149:156823d33999 124 SPI_TypeDef *Instance; /* SPI registers base address */
<> 149:156823d33999 125
<> 149:156823d33999 126 SPI_InitTypeDef Init; /* SPI communication parameters */
<> 149:156823d33999 127
<> 149:156823d33999 128 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
<> 149:156823d33999 129
<> 149:156823d33999 130 uint16_t TxXferSize; /* SPI Tx transfer size */
<> 149:156823d33999 131
<> 149:156823d33999 132 __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
<> 149:156823d33999 133
<> 149:156823d33999 134 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
<> 149:156823d33999 135
<> 149:156823d33999 136 uint16_t RxXferSize; /* SPI Rx transfer size */
<> 149:156823d33999 137
<> 149:156823d33999 138 __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
<> 149:156823d33999 139
<> 149:156823d33999 140 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
<> 149:156823d33999 141
<> 149:156823d33999 142 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
<> 149:156823d33999 143
<> 149:156823d33999 144 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
<> 149:156823d33999 145
<> 149:156823d33999 146 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
<> 149:156823d33999 147
<> 149:156823d33999 148 HAL_LockTypeDef Lock; /* SPI locking object */
<> 149:156823d33999 149
<> 149:156823d33999 150 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
<> 149:156823d33999 151
<> 149:156823d33999 152 __IO uint32_t ErrorCode; /* SPI Error code */
<> 149:156823d33999 153
<> 149:156823d33999 154 }SPI_HandleTypeDef;
<> 149:156823d33999 155 /**
<> 149:156823d33999 156 * @}
<> 149:156823d33999 157 */
<> 149:156823d33999 158
<> 149:156823d33999 159
<> 149:156823d33999 160 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 161
<> 149:156823d33999 162 /** @defgroup SPI_Exported_Constants SPI Exported Constants
<> 149:156823d33999 163 * @{
<> 149:156823d33999 164 */
<> 149:156823d33999 165
<> 149:156823d33999 166 /** @defgroup SPI_Error_Codes SPI Error Codes
<> 149:156823d33999 167 * @{
<> 149:156823d33999 168 */
AnnaBridge 184:08ed48f1de7f 169 #define HAL_SPI_ERROR_NONE (0x00U) /*!< No error */
AnnaBridge 184:08ed48f1de7f 170 #define HAL_SPI_ERROR_MODF (0x01U) /*!< MODF error */
AnnaBridge 184:08ed48f1de7f 171 #define HAL_SPI_ERROR_CRC (0x02U) /*!< CRC error */
AnnaBridge 184:08ed48f1de7f 172 #define HAL_SPI_ERROR_OVR (0x04U) /*!< OVR error */
AnnaBridge 184:08ed48f1de7f 173 #define HAL_SPI_ERROR_FRE (0x08U) /*!< FRE error */
AnnaBridge 184:08ed48f1de7f 174 #define HAL_SPI_ERROR_DMA (0x10U) /*!< DMA transfer error */
AnnaBridge 184:08ed48f1de7f 175 #define HAL_SPI_ERROR_FLAG (0x20U) /*!< Flag: RXNE,TXE, BSY */
<> 149:156823d33999 176
<> 149:156823d33999 177 /**
<> 149:156823d33999 178 * @}
<> 149:156823d33999 179 */
<> 149:156823d33999 180
<> 149:156823d33999 181 /** @defgroup SPI_mode SPI mode
<> 149:156823d33999 182 * @{
<> 149:156823d33999 183 */
AnnaBridge 184:08ed48f1de7f 184 #define SPI_MODE_SLAVE (0x00000000U)
<> 149:156823d33999 185 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
<> 149:156823d33999 186
<> 149:156823d33999 187 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
<> 149:156823d33999 188 ((MODE) == SPI_MODE_MASTER))
<> 149:156823d33999 189 /**
<> 149:156823d33999 190 * @}
<> 149:156823d33999 191 */
<> 149:156823d33999 192
<> 149:156823d33999 193 /** @defgroup SPI_Direction_mode SPI Direction mode
<> 149:156823d33999 194 * @{
<> 149:156823d33999 195 */
AnnaBridge 184:08ed48f1de7f 196 #define SPI_DIRECTION_2LINES (0x00000000U)
<> 149:156823d33999 197 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
<> 149:156823d33999 198 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
<> 149:156823d33999 199
<> 149:156823d33999 200 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 149:156823d33999 201 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
<> 149:156823d33999 202 ((MODE) == SPI_DIRECTION_1LINE))
<> 149:156823d33999 203
<> 149:156823d33999 204 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 149:156823d33999 205 ((MODE) == SPI_DIRECTION_1LINE))
<> 149:156823d33999 206
<> 149:156823d33999 207 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
<> 149:156823d33999 208
<> 149:156823d33999 209 /**
<> 149:156823d33999 210 * @}
<> 149:156823d33999 211 */
<> 149:156823d33999 212
<> 149:156823d33999 213 /** @defgroup SPI_data_size SPI data size
<> 149:156823d33999 214 * @{
<> 149:156823d33999 215 */
AnnaBridge 184:08ed48f1de7f 216 #define SPI_DATASIZE_8BIT (0x00000000U)
<> 149:156823d33999 217 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
<> 149:156823d33999 218
<> 149:156823d33999 219 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
<> 149:156823d33999 220 ((DATASIZE) == SPI_DATASIZE_8BIT))
<> 149:156823d33999 221 /**
<> 149:156823d33999 222 * @}
<> 149:156823d33999 223 */
<> 149:156823d33999 224
<> 149:156823d33999 225 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
<> 149:156823d33999 226 * @{
<> 149:156823d33999 227 */
AnnaBridge 184:08ed48f1de7f 228 #define SPI_POLARITY_LOW (0x00000000U)
<> 149:156823d33999 229 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
<> 149:156823d33999 230
<> 149:156823d33999 231 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
<> 149:156823d33999 232 ((CPOL) == SPI_POLARITY_HIGH))
<> 149:156823d33999 233 /**
<> 149:156823d33999 234 * @}
<> 149:156823d33999 235 */
<> 149:156823d33999 236
<> 149:156823d33999 237 /** @defgroup SPI_Clock_Phase SPI Clock Phase
<> 149:156823d33999 238 * @{
<> 149:156823d33999 239 */
AnnaBridge 184:08ed48f1de7f 240 #define SPI_PHASE_1EDGE (0x00000000U)
<> 149:156823d33999 241 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
<> 149:156823d33999 242
<> 149:156823d33999 243 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
<> 149:156823d33999 244 ((CPHA) == SPI_PHASE_2EDGE))
<> 149:156823d33999 245 /**
<> 149:156823d33999 246 * @}
<> 149:156823d33999 247 */
<> 149:156823d33999 248
<> 149:156823d33999 249 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
<> 149:156823d33999 250 * @{
<> 149:156823d33999 251 */
<> 149:156823d33999 252 #define SPI_NSS_SOFT SPI_CR1_SSM
AnnaBridge 184:08ed48f1de7f 253 #define SPI_NSS_HARD_INPUT (0x00000000U)
<> 149:156823d33999 254 #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
<> 149:156823d33999 255
<> 149:156823d33999 256 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
<> 149:156823d33999 257 ((NSS) == SPI_NSS_HARD_INPUT) || \
<> 149:156823d33999 258 ((NSS) == SPI_NSS_HARD_OUTPUT))
<> 149:156823d33999 259 /**
<> 149:156823d33999 260 * @}
<> 149:156823d33999 261 */
<> 149:156823d33999 262
<> 149:156823d33999 263 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
<> 149:156823d33999 264 * @{
<> 149:156823d33999 265 */
AnnaBridge 184:08ed48f1de7f 266 #define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
<> 149:156823d33999 267 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0)
<> 149:156823d33999 268 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1)
<> 149:156823d33999 269 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 149:156823d33999 270 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2)
<> 149:156823d33999 271 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
<> 149:156823d33999 272 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
<> 149:156823d33999 273 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 149:156823d33999 274
<> 149:156823d33999 275 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
<> 149:156823d33999 276 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
<> 149:156823d33999 277 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
<> 149:156823d33999 278 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
<> 149:156823d33999 279 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
<> 149:156823d33999 280 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
<> 149:156823d33999 281 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
<> 149:156823d33999 282 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
<> 149:156823d33999 283 /**
<> 149:156823d33999 284 * @}
<> 149:156823d33999 285 */
<> 149:156823d33999 286
<> 149:156823d33999 287 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
<> 149:156823d33999 288 * @{
<> 149:156823d33999 289 */
AnnaBridge 184:08ed48f1de7f 290 #define SPI_FIRSTBIT_MSB (0x00000000U)
<> 149:156823d33999 291 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
<> 149:156823d33999 292
<> 149:156823d33999 293 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
<> 149:156823d33999 294 ((BIT) == SPI_FIRSTBIT_LSB))
<> 149:156823d33999 295 /**
<> 149:156823d33999 296 * @}
<> 149:156823d33999 297 */
<> 149:156823d33999 298
<> 149:156823d33999 299 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
<> 149:156823d33999 300 * @{
<> 149:156823d33999 301 */
AnnaBridge 184:08ed48f1de7f 302 #define SPI_CRCCALCULATION_DISABLE (0x00000000U)
<> 149:156823d33999 303 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
<> 149:156823d33999 304
<> 149:156823d33999 305 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
<> 149:156823d33999 306 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
<> 149:156823d33999 307
<> 149:156823d33999 308 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
<> 149:156823d33999 309 /**
<> 149:156823d33999 310 * @}
<> 149:156823d33999 311 */
<> 149:156823d33999 312
<> 149:156823d33999 313 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
<> 149:156823d33999 314 * @{
<> 149:156823d33999 315 */
<> 149:156823d33999 316 #define SPI_IT_TXE SPI_CR2_TXEIE
<> 149:156823d33999 317 #define SPI_IT_RXNE SPI_CR2_RXNEIE
<> 149:156823d33999 318 #define SPI_IT_ERR SPI_CR2_ERRIE
<> 149:156823d33999 319 /**
<> 149:156823d33999 320 * @}
<> 149:156823d33999 321 */
<> 149:156823d33999 322
<> 149:156823d33999 323 /** @defgroup SPI_Flag_definition SPI Flag definition
<> 149:156823d33999 324 * @{
<> 149:156823d33999 325 */
<> 149:156823d33999 326 #define SPI_FLAG_RXNE SPI_SR_RXNE
<> 149:156823d33999 327 #define SPI_FLAG_TXE SPI_SR_TXE
<> 149:156823d33999 328 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
<> 149:156823d33999 329 #define SPI_FLAG_MODF SPI_SR_MODF
<> 149:156823d33999 330 #define SPI_FLAG_OVR SPI_SR_OVR
<> 149:156823d33999 331 #define SPI_FLAG_BSY SPI_SR_BSY
<> 149:156823d33999 332 #define SPI_FLAG_FRE SPI_SR_FRE
<> 149:156823d33999 333
<> 149:156823d33999 334 /**
<> 149:156823d33999 335 * @}
<> 149:156823d33999 336 */
<> 149:156823d33999 337
<> 149:156823d33999 338 /**
<> 149:156823d33999 339 * @}
<> 149:156823d33999 340 */
<> 149:156823d33999 341
<> 149:156823d33999 342
<> 149:156823d33999 343 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 344 /** @defgroup SPI_Exported_Macros SPI Exported Macros
<> 149:156823d33999 345 * @{
<> 149:156823d33999 346 */
<> 149:156823d33999 347
<> 149:156823d33999 348 /** @brief Reset SPI handle state
<> 149:156823d33999 349 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 350 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 351 * @retval None
<> 149:156823d33999 352 */
<> 149:156823d33999 353 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
<> 149:156823d33999 354
<> 149:156823d33999 355 /** @brief Enable or disable the specified SPI interrupts.
<> 149:156823d33999 356 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 357 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 358 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 149:156823d33999 359 * This parameter can be one of the following values:
<> 149:156823d33999 360 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 149:156823d33999 361 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 149:156823d33999 362 * @arg SPI_IT_ERR: Error interrupt enable
<> 149:156823d33999 363 * @retval None
<> 149:156823d33999 364 */
<> 149:156823d33999 365 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 149:156823d33999 366 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 149:156823d33999 367
<> 149:156823d33999 368 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
<> 149:156823d33999 369 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 370 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 371 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
<> 149:156823d33999 372 * This parameter can be one of the following values:
<> 149:156823d33999 373 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 149:156823d33999 374 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 149:156823d33999 375 * @arg SPI_IT_ERR: Error interrupt enable
<> 149:156823d33999 376 * @retval The new state of __IT__ (TRUE or FALSE).
<> 149:156823d33999 377 */
<> 149:156823d33999 378 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 149:156823d33999 379
<> 149:156823d33999 380 /** @brief Check whether the specified SPI flag is set or not.
<> 149:156823d33999 381 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 382 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 383 * @param __FLAG__: specifies the flag to check.
<> 149:156823d33999 384 * This parameter can be one of the following values:
<> 149:156823d33999 385 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
<> 149:156823d33999 386 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
<> 149:156823d33999 387 * @arg SPI_FLAG_CRCERR: CRC error flag
<> 149:156823d33999 388 * @arg SPI_FLAG_MODF: Mode fault flag
<> 149:156823d33999 389 * @arg SPI_FLAG_OVR: Overrun flag
<> 149:156823d33999 390 * @arg SPI_FLAG_BSY: Busy flag
<> 149:156823d33999 391 * @arg SPI_FLAG_FRE: Frame format error flag
<> 149:156823d33999 392 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 149:156823d33999 393 */
<> 149:156823d33999 394 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 149:156823d33999 395
<> 149:156823d33999 396 /** @brief Clear the SPI CRCERR pending flag.
<> 149:156823d33999 397 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 398 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 399 * @retval None
<> 149:156823d33999 400 */
<> 149:156823d33999 401 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
<> 149:156823d33999 402
<> 149:156823d33999 403 /** @brief Clear the SPI MODF pending flag.
<> 149:156823d33999 404 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 405 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 406 * @retval None
<> 149:156823d33999 407 */
<> 149:156823d33999 408 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
<> 149:156823d33999 409 do{ \
<> 149:156823d33999 410 __IO uint32_t tmpreg_modf; \
<> 149:156823d33999 411 tmpreg_modf = (__HANDLE__)->Instance->SR; \
<> 149:156823d33999 412 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
<> 149:156823d33999 413 UNUSED(tmpreg_modf); \
<> 149:156823d33999 414 }while(0)
<> 149:156823d33999 415
<> 149:156823d33999 416 /** @brief Clear the SPI OVR pending flag.
<> 149:156823d33999 417 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 418 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 419 * @retval None
<> 149:156823d33999 420 */
<> 149:156823d33999 421 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
<> 149:156823d33999 422 do{ \
<> 149:156823d33999 423 __IO uint32_t tmpreg_ovr; \
<> 149:156823d33999 424 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
<> 149:156823d33999 425 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
<> 149:156823d33999 426 UNUSED(tmpreg_ovr); \
<> 149:156823d33999 427 }while(0)
<> 149:156823d33999 428
<> 149:156823d33999 429 /** @brief Clear the SPI FRE pending flag.
<> 149:156823d33999 430 * @param __HANDLE__: specifies the SPI handle.
<> 149:156823d33999 431 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 432 * @retval None
<> 149:156823d33999 433 */
<> 149:156823d33999 434 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
<> 149:156823d33999 435 do{ \
<> 149:156823d33999 436 __IO uint32_t tmpreg_fre; \
<> 149:156823d33999 437 tmpreg_fre = (__HANDLE__)->Instance->SR; \
<> 149:156823d33999 438 UNUSED(tmpreg_fre); \
<> 149:156823d33999 439 }while(0)
<> 149:156823d33999 440
<> 149:156823d33999 441 /** @brief Enables the SPI.
<> 149:156823d33999 442 * @param __HANDLE__: specifies the SPI Handle.
<> 149:156823d33999 443 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 444 * @retval None
<> 149:156823d33999 445 */
<> 149:156823d33999 446 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 149:156823d33999 447
<> 149:156823d33999 448 /** @brief Disables the SPI.
<> 149:156823d33999 449 * @param __HANDLE__: specifies the SPI Handle.
<> 149:156823d33999 450 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 451 * @retval None
<> 149:156823d33999 452 */
<> 149:156823d33999 453 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 149:156823d33999 454 /**
<> 149:156823d33999 455 * @}
<> 149:156823d33999 456 */
<> 149:156823d33999 457
<> 149:156823d33999 458
<> 149:156823d33999 459 /* Private macro ------------------------------------------------------------*/
<> 149:156823d33999 460 /** @defgroup SPI_Private_Macros SPI Private Macros
<> 149:156823d33999 461 * @{
<> 149:156823d33999 462 */
<> 149:156823d33999 463
<> 149:156823d33999 464 /** @brief Sets the SPI transmit-only mode.
<> 149:156823d33999 465 * @param __HANDLE__: specifies the SPI Handle.
<> 149:156823d33999 466 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 467 * @retval None
<> 149:156823d33999 468 */
<> 149:156823d33999 469 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 149:156823d33999 470
<> 149:156823d33999 471 /** @brief Sets the SPI receive-only mode.
<> 149:156823d33999 472 * @param __HANDLE__: specifies the SPI Handle.
<> 149:156823d33999 473 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 474 * @retval None
<> 149:156823d33999 475 */
<> 149:156823d33999 476 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 149:156823d33999 477
<> 149:156823d33999 478 /** @brief Resets the CRC calculation of the SPI.
<> 149:156823d33999 479 * @param __HANDLE__: specifies the SPI Handle.
<> 149:156823d33999 480 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 149:156823d33999 481 * @retval None
<> 149:156823d33999 482 */
<> 149:156823d33999 483 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
<> 149:156823d33999 484 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
<> 149:156823d33999 485 /**
<> 149:156823d33999 486 * @}
<> 149:156823d33999 487 */
<> 149:156823d33999 488
<> 149:156823d33999 489 /* Include SPI HAL Extension module */
<> 149:156823d33999 490 #include "stm32l1xx_hal_spi_ex.h"
<> 149:156823d33999 491
<> 149:156823d33999 492 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 493 /** @addtogroup SPI_Exported_Functions
<> 149:156823d33999 494 * @{
<> 149:156823d33999 495 */
<> 149:156823d33999 496
<> 149:156823d33999 497 /* Initialization/de-initialization functions **********************************/
<> 149:156823d33999 498 /** @addtogroup SPI_Exported_Functions_Group1
<> 149:156823d33999 499 * @{
<> 149:156823d33999 500 */
<> 149:156823d33999 501 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 502 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
<> 149:156823d33999 503 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 504 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 505 /**
<> 149:156823d33999 506 * @}
<> 149:156823d33999 507 */
<> 149:156823d33999 508
<> 149:156823d33999 509 /* I/O operation functions *****************************************************/
<> 149:156823d33999 510 /** @addtogroup SPI_Exported_Functions_Group2
<> 149:156823d33999 511 * @{
<> 149:156823d33999 512 */
<> 149:156823d33999 513 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 149:156823d33999 514 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 149:156823d33999 515 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 149:156823d33999 516 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 149:156823d33999 517 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 149:156823d33999 518 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 149:156823d33999 519 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 149:156823d33999 520 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 149:156823d33999 521 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 149:156823d33999 522 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 523 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 524 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 525
<> 149:156823d33999 526 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 527 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 528 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 529 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 530 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 531 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 532 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 533 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 534 /**
<> 149:156823d33999 535 * @}
<> 149:156823d33999 536 */
<> 149:156823d33999 537
<> 149:156823d33999 538
<> 149:156823d33999 539 /* Peripheral State and Control functions **************************************/
<> 149:156823d33999 540 /** @addtogroup SPI_Exported_Functions_Group3
<> 149:156823d33999 541 * @{
<> 149:156823d33999 542 */
<> 149:156823d33999 543 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 544 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
<> 149:156823d33999 545
<> 149:156823d33999 546 /**
<> 149:156823d33999 547 * @}
<> 149:156823d33999 548 */
<> 149:156823d33999 549
<> 149:156823d33999 550 /**
<> 149:156823d33999 551 * @}
<> 149:156823d33999 552 */
<> 149:156823d33999 553
<> 149:156823d33999 554
<> 149:156823d33999 555 /**
<> 149:156823d33999 556 * @}
<> 149:156823d33999 557 */
<> 149:156823d33999 558
<> 149:156823d33999 559 /**
<> 149:156823d33999 560 * @}
<> 149:156823d33999 561 */
<> 149:156823d33999 562
<> 149:156823d33999 563 #ifdef __cplusplus
<> 149:156823d33999 564 }
<> 149:156823d33999 565 #endif
<> 149:156823d33999 566
<> 149:156823d33999 567 #endif /* __STM32L1xx_HAL_SPI_H */
<> 149:156823d33999 568
<> 149:156823d33999 569 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/