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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 184:08ed48f1de7f

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_hal_spi.c
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @brief SPI HAL module driver.
<>	149:156823d33999	6	*
<>	149:156823d33999	7	* This file provides firmware functions to manage the following
<>	149:156823d33999	8	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
<>	149:156823d33999	9	* + Initialization and de-initialization functions
<>	149:156823d33999	10	* + IO operation functions
<>	149:156823d33999	11	* + Peripheral Control functions
<>	149:156823d33999	12	* + Peripheral State functions
<>	149:156823d33999	13	@verbatim
<>	149:156823d33999	14	==============================================================================
<>	149:156823d33999	15	##### How to use this driver #####
<>	149:156823d33999	16	==============================================================================
<>	149:156823d33999	17	[..]
<>	149:156823d33999	18	The SPI HAL driver can be used as follows:
<>	149:156823d33999	19
<>	149:156823d33999	20	(#) Declare a SPI_HandleTypeDef handle structure, for example:
<>	149:156823d33999	21	SPI_HandleTypeDef hspi;
<>	149:156823d33999	22
<>	149:156823d33999	23	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
<>	149:156823d33999	24	(##) Enable the SPIx interface clock
<>	149:156823d33999	25	(##) SPI pins configuration
<>	149:156823d33999	26	(+++) Enable the clock for the SPI GPIOs
<>	149:156823d33999	27	(+++) Configure these SPI pins as alternate function push-pull
<>	149:156823d33999	28	(##) NVIC configuration if you need to use interrupt process
<>	149:156823d33999	29	(+++) Configure the SPIx interrupt priority
<>	149:156823d33999	30	(+++) Enable the NVIC SPI IRQ handle
<>	149:156823d33999	31	(##) DMA Configuration if you need to use DMA process
<>	149:156823d33999	32	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
<>	149:156823d33999	33	(+++) Enable the DMAx clock
<>	149:156823d33999	34	(+++) Configure the DMA handle parameters
<>	149:156823d33999	35	(+++) Configure the DMA Tx or Rx Channel
<>	149:156823d33999	36	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
<>	149:156823d33999	37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
<>	149:156823d33999	38
<>	149:156823d33999	39	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
<>	149:156823d33999	40	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<>	149:156823d33999	41
<>	149:156823d33999	42	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<>	149:156823d33999	43	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<>	149:156823d33999	44	by calling the customed HAL_SPI_MspInit() API.
<>	149:156823d33999	45	[..]
<>	149:156823d33999	46	Circular mode restriction:
<>	149:156823d33999	47	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<>	149:156823d33999	48	(##) Master 2Lines RxOnly
<>	149:156823d33999	49	(##) Master 1Line Rx
<>	149:156823d33999	50	(#) The CRC feature is not managed when the DMA circular mode is enabled
<>	149:156823d33999	51	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<>	149:156823d33999	52	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<>	149:156823d33999	53
<>	149:156823d33999	54
<>	149:156823d33999	55
<>	149:156823d33999	56	@endverbatim
<>	149:156823d33999	57	******************************************************************************
<>	149:156823d33999	58	* @attention
<>	149:156823d33999	59	*
AnnaBridge	184:08ed48f1de7f	60	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	149:156823d33999	61	*
<>	149:156823d33999	62	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	63	* are permitted provided that the following conditions are met:
<>	149:156823d33999	64	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	65	* this list of conditions and the following disclaimer.
<>	149:156823d33999	66	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	67	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	68	* and/or other materials provided with the distribution.
<>	149:156823d33999	69	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	70	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	71	* without specific prior written permission.
<>	149:156823d33999	72	*
<>	149:156823d33999	73	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	74	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	75	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	76	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	77	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	78	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	79	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	80	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	81	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	82	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	83	*
<>	149:156823d33999	84	******************************************************************************
<>	149:156823d33999	85	*/
<>	149:156823d33999	86
<>	149:156823d33999	87	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	88	#include "stm32l1xx_hal.h"
<>	149:156823d33999	89
<>	149:156823d33999	90	/** @addtogroup STM32L1xx_HAL_Driver
<>	149:156823d33999	91	* @{
<>	149:156823d33999	92	*/
<>	149:156823d33999	93
<>	149:156823d33999	94	/** @defgroup SPI SPI
<>	149:156823d33999	95	* @brief SPI HAL module driver
<>	149:156823d33999	96	* @{
<>	149:156823d33999	97	*/
<>	149:156823d33999	98
<>	149:156823d33999	99	#ifdef HAL_SPI_MODULE_ENABLED
<>	149:156823d33999	100
<>	149:156823d33999	101	/* Private typedef -----------------------------------------------------------*/
<>	149:156823d33999	102	/* Private define ------------------------------------------------------------*/
<>	149:156823d33999	103	/** @defgroup SPI_Private_Constants SPI Private Constants
<>	149:156823d33999	104	* @{
<>	149:156823d33999	105	*/
<>	149:156823d33999	106	#define SPI_TIMEOUT_VALUE 10
<>	153:fa9ff456f731	107	#define SPI_DEFAULT_TIMEOUT 100U
<>	153:fa9ff456f731	108
<>	149:156823d33999	109	/**
<>	149:156823d33999	110	* @}
<>	149:156823d33999	111	*/
<>	149:156823d33999	112
<>	149:156823d33999	113	/* Private macro -------------------------------------------------------------*/
<>	149:156823d33999	114	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	115	/* Private function prototypes -----------------------------------------------*/
<>	149:156823d33999	116	/** @defgroup SPI_Private_Functions SPI Private Functions
<>	149:156823d33999	117	* @{
<>	149:156823d33999	118	*/
<>	153:fa9ff456f731	119	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
<>	153:fa9ff456f731	120	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	121	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	122	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	123	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	124	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	125	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	126	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	127	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	128	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	129	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	130	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	131	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	132	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	133	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	134	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	135	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	136	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
<>	149:156823d33999	137	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	138	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	139	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	140	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	141	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	142	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	143	static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	144	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<>	149:156823d33999	145	/**
<>	149:156823d33999	146	* @}
<>	149:156823d33999	147	*/
<>	149:156823d33999	148
<>	149:156823d33999	149	/* Exported functions ---------------------------------------------------------*/
<>	149:156823d33999	150
<>	149:156823d33999	151	/** @defgroup SPI_Exported_Functions SPI Exported Functions
<>	149:156823d33999	152	* @{
<>	149:156823d33999	153	*/
<>	149:156823d33999	154
<>	149:156823d33999	155	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<>	149:156823d33999	156	* @brief Initialization and Configuration functions
<>	149:156823d33999	157	*
<>	149:156823d33999	158	@verbatim
<>	149:156823d33999	159	===============================================================================
<>	149:156823d33999	160	##### Initialization and de-initialization functions #####
<>	149:156823d33999	161	===============================================================================
<>	149:156823d33999	162	[..] This subsection provides a set of functions allowing to initialize and
<>	149:156823d33999	163	de-initialiaze the SPIx peripheral:
<>	149:156823d33999	164
<>	149:156823d33999	165	(+) User must implement HAL_SPI_MspInit() function in which he configures
<>	149:156823d33999	166	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<>	149:156823d33999	167
<>	149:156823d33999	168	(+) Call the function HAL_SPI_Init() to configure the selected device with
<>	149:156823d33999	169	the selected configuration:
<>	149:156823d33999	170	(++) Mode
<>	149:156823d33999	171	(++) Direction
<>	149:156823d33999	172	(++) Data Size
<>	149:156823d33999	173	(++) Clock Polarity and Phase
<>	149:156823d33999	174	(++) NSS Management
<>	149:156823d33999	175	(++) BaudRate Prescaler
<>	149:156823d33999	176	(++) FirstBit
<>	149:156823d33999	177	(++) TIMode
<>	149:156823d33999	178	(++) CRC Calculation
<>	149:156823d33999	179	(++) CRC Polynomial if CRC enabled
<>	149:156823d33999	180
<>	149:156823d33999	181	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
<>	149:156823d33999	182	of the selected SPIx periperal.
<>	149:156823d33999	183
<>	149:156823d33999	184	@endverbatim
<>	149:156823d33999	185	* @{
<>	149:156823d33999	186	*/
<>	149:156823d33999	187
<>	149:156823d33999	188	/**
<>	149:156823d33999	189	* @brief Initializes the SPI according to the specified parameters
<>	149:156823d33999	190	* in the SPI_InitTypeDef and create the associated handle.
<>	149:156823d33999	191	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	192	* the configuration information for SPI module.
<>	149:156823d33999	193	* @retval HAL status
<>	149:156823d33999	194	*/
<>	149:156823d33999	195	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	196	{
<>	149:156823d33999	197	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	198	UNUSED(hspi);
<>	149:156823d33999	199
<>	149:156823d33999	200	return HAL_ERROR;
<>	149:156823d33999	201	}
<>	149:156823d33999	202
<>	149:156823d33999	203	/**
<>	149:156823d33999	204	* @brief DeInitializes the SPI peripheral
<>	149:156823d33999	205	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	206	* the configuration information for SPI module.
<>	149:156823d33999	207	* @retval HAL status
<>	149:156823d33999	208	*/
<>	149:156823d33999	209	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	210	{
<>	149:156823d33999	211	/* Check the SPI handle allocation */
<>	149:156823d33999	212	if(hspi == NULL)
<>	149:156823d33999	213	{
<>	149:156823d33999	214	return HAL_ERROR;
<>	149:156823d33999	215	}
<>	149:156823d33999	216
<>	149:156823d33999	217	/* Disable the SPI Peripheral Clock */
<>	149:156823d33999	218	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	219
<>	149:156823d33999	220	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<>	149:156823d33999	221	HAL_SPI_MspDeInit(hspi);
<>	149:156823d33999	222
<>	149:156823d33999	223	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	224	hspi->State = HAL_SPI_STATE_RESET;
<>	149:156823d33999	225
<>	149:156823d33999	226	/* Release Lock */
<>	149:156823d33999	227	__HAL_UNLOCK(hspi);
<>	149:156823d33999	228
<>	149:156823d33999	229	return HAL_OK;
<>	149:156823d33999	230	}
<>	149:156823d33999	231
<>	149:156823d33999	232	/**
<>	149:156823d33999	233	* @brief SPI MSP Init
<>	149:156823d33999	234	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	235	* the configuration information for SPI module.
<>	149:156823d33999	236	* @retval None
<>	149:156823d33999	237	*/
<>	149:156823d33999	238	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	239	{
<>	149:156823d33999	240	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	241	UNUSED(hspi);
<>	149:156823d33999	242
<>	149:156823d33999	243	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	244	the HAL_SPI_MspInit could be implenetd in the user file
<>	149:156823d33999	245	*/
<>	149:156823d33999	246	}
<>	149:156823d33999	247
<>	149:156823d33999	248	/**
<>	149:156823d33999	249	* @brief SPI MSP DeInit
<>	149:156823d33999	250	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	251	* the configuration information for SPI module.
<>	149:156823d33999	252	* @retval None
<>	149:156823d33999	253	*/
<>	149:156823d33999	254	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	255	{
<>	149:156823d33999	256	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	257	UNUSED(hspi);
<>	149:156823d33999	258
<>	149:156823d33999	259	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	260	the HAL_SPI_MspDeInit could be implenetd in the user file
<>	149:156823d33999	261	*/
<>	149:156823d33999	262	}
<>	149:156823d33999	263
<>	149:156823d33999	264	/**
<>	149:156823d33999	265	* @}
<>	149:156823d33999	266	*/
<>	149:156823d33999	267
<>	149:156823d33999	268	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<>	149:156823d33999	269	* @brief Data transfers functions
<>	149:156823d33999	270	*
<>	149:156823d33999	271	@verbatim
<>	149:156823d33999	272	==============================================================================
<>	149:156823d33999	273	##### IO operation functions #####
<>	149:156823d33999	274	===============================================================================
<>	149:156823d33999	275	This subsection provides a set of functions allowing to manage the SPI
<>	149:156823d33999	276	data transfers.
<>	149:156823d33999	277
<>	149:156823d33999	278	[..] The SPI supports master and slave mode :
<>	149:156823d33999	279
<>	149:156823d33999	280	(#) There are two modes of transfer:
<>	149:156823d33999	281	(++) Blocking mode: The communication is performed in polling mode.
<>	149:156823d33999	282	The HAL status of all data processing is returned by the same function
<>	149:156823d33999	283	after finishing transfer.
<>	149:156823d33999	284	(++) No-Blocking mode: The communication is performed using Interrupts
<>	149:156823d33999	285	or DMA, These APIs return the HAL status.
<>	149:156823d33999	286	The end of the data processing will be indicated through the
<>	149:156823d33999	287	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<>	149:156823d33999	288	using DMA mode.
<>	149:156823d33999	289	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<>	149:156823d33999	290	will be executed respectivelly at the end of the transmit or Receive process
<>	149:156823d33999	291	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<>	149:156823d33999	292
<>	149:156823d33999	293	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<>	149:156823d33999	294	exist for 1Line (simplex) and 2Lines (full duplex) modes.
<>	149:156823d33999	295
<>	149:156823d33999	296	@endverbatim
<>	149:156823d33999	297	* @{
<>	149:156823d33999	298	*/
<>	149:156823d33999	299
<>	149:156823d33999	300	/**
<>	149:156823d33999	301	* @brief Transmit an amount of data in blocking mode
<>	149:156823d33999	302	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	303	* the configuration information for SPI module.
<>	149:156823d33999	304	* @param pData: pointer to data buffer
<>	149:156823d33999	305	* @param Size: amount of data to be sent
<>	149:156823d33999	306	* @param Timeout: Timeout duration
<>	149:156823d33999	307	* @retval HAL status
<>	149:156823d33999	308	*/
<>	149:156823d33999	309	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	310	{
<>	149:156823d33999	311
<>	149:156823d33999	312	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	313	{
<>	149:156823d33999	314	if((pData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	315	{
<>	149:156823d33999	316	return HAL_ERROR;
<>	149:156823d33999	317	}
<>	149:156823d33999	318
<>	149:156823d33999	319	/* Check the parameters */
<>	149:156823d33999	320	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	321
<>	149:156823d33999	322	/* Process Locked */
<>	149:156823d33999	323	__HAL_LOCK(hspi);
<>	149:156823d33999	324
<>	149:156823d33999	325	/* Configure communication */
<>	149:156823d33999	326	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	327	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	328
<>	149:156823d33999	329	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	330	hspi->TxXferSize = Size;
<>	149:156823d33999	331	hspi->TxXferCount = Size;
<>	149:156823d33999	332
<>	149:156823d33999	333	/Init field not used in handle to zero /
<>	149:156823d33999	334	hspi->TxISR = 0;
<>	149:156823d33999	335	hspi->RxISR = 0;
<>	149:156823d33999	336	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	337	hspi->RxXferSize = 0;
<>	149:156823d33999	338	hspi->RxXferCount = 0;
<>	149:156823d33999	339
<>	149:156823d33999	340	/* Reset CRC Calculation */
<>	149:156823d33999	341	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	342	{
<>	149:156823d33999	343	SPI_RESET_CRC(hspi);
<>	149:156823d33999	344	}
<>	149:156823d33999	345
<>	149:156823d33999	346	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	347	{
<>	149:156823d33999	348	/* Configure communication direction : 1Line */
<>	149:156823d33999	349	SPI_1LINE_TX(hspi);
<>	149:156823d33999	350	}
<>	149:156823d33999	351
<>	149:156823d33999	352	/* Check if the SPI is already enabled */
<>	149:156823d33999	353	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	354	{
<>	149:156823d33999	355	/* Enable SPI peripheral */
<>	149:156823d33999	356	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	357	}
<>	149:156823d33999	358
<>	149:156823d33999	359	/* Transmit data in 8 Bit mode */
<>	149:156823d33999	360	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	361	{
<>	149:156823d33999	362	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
<>	149:156823d33999	363	{
<>	149:156823d33999	364	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	365	hspi->TxXferCount--;
<>	149:156823d33999	366	}
<>	149:156823d33999	367	while(hspi->TxXferCount > 0)
<>	149:156823d33999	368	{
<>	149:156823d33999	369	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	370	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	371	{
<>	149:156823d33999	372	return HAL_TIMEOUT;
<>	149:156823d33999	373	}
<>	149:156823d33999	374	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	375	hspi->TxXferCount--;
<>	149:156823d33999	376	}
<>	149:156823d33999	377	/* Enable CRC Transmission */
<>	149:156823d33999	378	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	379	{
<>	149:156823d33999	380	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	381	}
<>	149:156823d33999	382	}
<>	149:156823d33999	383	/* Transmit data in 16 Bit mode */
<>	149:156823d33999	384	else
<>	149:156823d33999	385	{
<>	149:156823d33999	386	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
<>	149:156823d33999	387	{
<>	149:156823d33999	388	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	389	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	390	hspi->TxXferCount--;
<>	149:156823d33999	391	}
<>	149:156823d33999	392	while(hspi->TxXferCount > 0)
<>	149:156823d33999	393	{
<>	149:156823d33999	394	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	395	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	396	{
<>	149:156823d33999	397	return HAL_TIMEOUT;
<>	149:156823d33999	398	}
<>	149:156823d33999	399	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	400	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	401	hspi->TxXferCount--;
<>	149:156823d33999	402	}
<>	149:156823d33999	403	/* Enable CRC Transmission */
<>	149:156823d33999	404	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	405	{
<>	149:156823d33999	406	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	407	}
<>	149:156823d33999	408	}
<>	149:156823d33999	409
<>	149:156823d33999	410	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	411	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	412	{
<>	149:156823d33999	413	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	414	return HAL_TIMEOUT;
<>	149:156823d33999	415	}
<>	149:156823d33999	416
<>	149:156823d33999	417	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	418	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	149:156823d33999	419	{
<>	149:156823d33999	420	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	421	return HAL_TIMEOUT;
<>	149:156823d33999	422	}
<>	149:156823d33999	423
<>	149:156823d33999	424	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	149:156823d33999	425	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	426	{
<>	149:156823d33999	427	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	428	}
<>	149:156823d33999	429
<>	149:156823d33999	430	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	431
<>	149:156823d33999	432	/* Process Unlocked */
<>	149:156823d33999	433	__HAL_UNLOCK(hspi);
<>	149:156823d33999	434
<>	149:156823d33999	435	return HAL_OK;
<>	149:156823d33999	436	}
<>	149:156823d33999	437	else
<>	149:156823d33999	438	{
<>	149:156823d33999	439	return HAL_BUSY;
<>	149:156823d33999	440	}
<>	149:156823d33999	441	}
<>	149:156823d33999	442
<>	149:156823d33999	443	/**
<>	149:156823d33999	444	* @brief Receive an amount of data in blocking mode
<>	149:156823d33999	445	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	446	* the configuration information for SPI module.
<>	149:156823d33999	447	* @param pData: pointer to data buffer
<>	149:156823d33999	448	* @param Size: amount of data to be sent
<>	149:156823d33999	449	* @param Timeout: Timeout duration
<>	149:156823d33999	450	* @retval HAL status
<>	149:156823d33999	451	*/
<>	149:156823d33999	452	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	453	{
<>	149:156823d33999	454	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	455
<>	149:156823d33999	456	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	457	{
<>	149:156823d33999	458	if((pData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	459	{
<>	149:156823d33999	460	return HAL_ERROR;
<>	149:156823d33999	461	}
<>	149:156823d33999	462
<>	149:156823d33999	463	/* Process Locked */
<>	149:156823d33999	464	__HAL_LOCK(hspi);
<>	149:156823d33999	465
<>	149:156823d33999	466	/* Configure communication */
<>	149:156823d33999	467	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	468	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	469
<>	149:156823d33999	470	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	471	hspi->RxXferSize = Size;
<>	149:156823d33999	472	hspi->RxXferCount = Size;
<>	149:156823d33999	473
<>	149:156823d33999	474	/Init field not used in handle to zero /
<>	149:156823d33999	475	hspi->RxISR = 0;
<>	149:156823d33999	476	hspi->TxISR = 0;
<>	149:156823d33999	477	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	478	hspi->TxXferSize = 0;
<>	149:156823d33999	479	hspi->TxXferCount = 0;
<>	149:156823d33999	480
<>	149:156823d33999	481	/* Configure communication direction : 1Line */
<>	149:156823d33999	482	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	483	{
<>	149:156823d33999	484	SPI_1LINE_RX(hspi);
<>	149:156823d33999	485	}
<>	149:156823d33999	486
<>	149:156823d33999	487	/* Reset CRC Calculation */
<>	149:156823d33999	488	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	489	{
<>	149:156823d33999	490	SPI_RESET_CRC(hspi);
<>	149:156823d33999	491	}
<>	149:156823d33999	492
<>	149:156823d33999	493	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<>	149:156823d33999	494	{
<>	149:156823d33999	495	/* Process Unlocked */
<>	149:156823d33999	496	__HAL_UNLOCK(hspi);
<>	149:156823d33999	497
<>	149:156823d33999	498	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	499	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<>	149:156823d33999	500	}
<>	149:156823d33999	501
<>	149:156823d33999	502	/* Check if the SPI is already enabled */
<>	149:156823d33999	503	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	504	{
<>	149:156823d33999	505	/* Enable SPI peripheral */
<>	149:156823d33999	506	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	507	}
<>	149:156823d33999	508
<>	149:156823d33999	509	/* Receive data in 8 Bit mode */
<>	149:156823d33999	510	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	511	{
<>	149:156823d33999	512	while(hspi->RxXferCount > 1)
<>	149:156823d33999	513	{
<>	149:156823d33999	514	/* Wait until RXNE flag is set */
<>	149:156823d33999	515	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	516	{
<>	149:156823d33999	517	return HAL_TIMEOUT;
<>	149:156823d33999	518	}
<>	149:156823d33999	519
<>	149:156823d33999	520	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	521	hspi->RxXferCount--;
<>	149:156823d33999	522	}
<>	149:156823d33999	523	/* Enable CRC Transmission */
<>	149:156823d33999	524	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	525	{
<>	149:156823d33999	526	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	527	}
<>	149:156823d33999	528	}
<>	149:156823d33999	529	/* Receive data in 16 Bit mode */
<>	149:156823d33999	530	else
<>	149:156823d33999	531	{
<>	149:156823d33999	532	while(hspi->RxXferCount > 1)
<>	149:156823d33999	533	{
<>	149:156823d33999	534	/* Wait until RXNE flag is set to read data */
<>	149:156823d33999	535	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	536	{
<>	149:156823d33999	537	return HAL_TIMEOUT;
<>	149:156823d33999	538	}
<>	149:156823d33999	539
<>	149:156823d33999	540	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	541	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	542	hspi->RxXferCount--;
<>	149:156823d33999	543	}
<>	149:156823d33999	544	/* Enable CRC Transmission */
<>	149:156823d33999	545	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	546	{
<>	149:156823d33999	547	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	548	}
<>	149:156823d33999	549	}
<>	149:156823d33999	550
<>	149:156823d33999	551	/* Wait until RXNE flag is set */
<>	149:156823d33999	552	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	553	{
<>	149:156823d33999	554	return HAL_TIMEOUT;
<>	149:156823d33999	555	}
<>	149:156823d33999	556
<>	149:156823d33999	557	/* Receive last data in 8 Bit mode */
<>	149:156823d33999	558	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	559	{
<>	149:156823d33999	560	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	561	}
<>	149:156823d33999	562	/* Receive last data in 16 Bit mode */
<>	149:156823d33999	563	else
<>	149:156823d33999	564	{
<>	149:156823d33999	565	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	566	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	567	}
<>	149:156823d33999	568	hspi->RxXferCount--;
<>	149:156823d33999	569
<>	149:156823d33999	570	/* Wait until RXNE flag is set: CRC Received */
<>	149:156823d33999	571	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	572	{
<>	149:156823d33999	573	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	574	{
<>	149:156823d33999	575	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	576	return HAL_TIMEOUT;
<>	149:156823d33999	577	}
<>	149:156823d33999	578
<>	149:156823d33999	579	/* Read CRC to Flush RXNE flag */
<>	149:156823d33999	580	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	581	UNUSED(tmpreg);
<>	149:156823d33999	582	}
<>	149:156823d33999	583
<>	149:156823d33999	584	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	149:156823d33999	585	{
<>	149:156823d33999	586	/* Disable SPI peripheral */
<>	149:156823d33999	587	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	588	}
<>	149:156823d33999	589
<>	149:156823d33999	590	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	591
<>	149:156823d33999	592	/* Check if CRC error occurred */
<>	149:156823d33999	593	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	149:156823d33999	594	{
<>	149:156823d33999	595	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	596
<>	149:156823d33999	597	/* Reset CRC Calculation */
<>	149:156823d33999	598	SPI_RESET_CRC(hspi);
<>	149:156823d33999	599
<>	149:156823d33999	600	/* Process Unlocked */
<>	149:156823d33999	601	__HAL_UNLOCK(hspi);
<>	149:156823d33999	602
<>	149:156823d33999	603	return HAL_ERROR;
<>	149:156823d33999	604	}
<>	149:156823d33999	605
<>	149:156823d33999	606	/* Process Unlocked */
<>	149:156823d33999	607	__HAL_UNLOCK(hspi);
<>	149:156823d33999	608
<>	149:156823d33999	609	return HAL_OK;
<>	149:156823d33999	610	}
<>	149:156823d33999	611	else
<>	149:156823d33999	612	{
<>	149:156823d33999	613	return HAL_BUSY;
<>	149:156823d33999	614	}
<>	149:156823d33999	615	}
<>	149:156823d33999	616
<>	149:156823d33999	617	/**
<>	149:156823d33999	618	* @brief Transmit and Receive an amount of data in blocking mode
<>	149:156823d33999	619	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	620	* the configuration information for SPI module.
<>	149:156823d33999	621	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	622	* @param pRxData: pointer to reception data buffer to be
<>	149:156823d33999	623	* @param Size: amount of data to be sent
<>	149:156823d33999	624	* @param Timeout: Timeout duration
<>	149:156823d33999	625	* @retval HAL status
<>	149:156823d33999	626	*/
<>	149:156823d33999	627	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	628	{
<>	149:156823d33999	629	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	630
<>	149:156823d33999	631	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
<>	149:156823d33999	632	{
<>	149:156823d33999	633	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	634	{
<>	149:156823d33999	635	return HAL_ERROR;
<>	149:156823d33999	636	}
<>	149:156823d33999	637
<>	149:156823d33999	638	/* Check the parameters */
<>	149:156823d33999	639	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	640
<>	149:156823d33999	641	/* Process Locked */
<>	149:156823d33999	642	__HAL_LOCK(hspi);
<>	149:156823d33999	643
<>	149:156823d33999	644	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	645	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	646	{
<>	149:156823d33999	647	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	648	}
<>	149:156823d33999	649
<>	149:156823d33999	650	/* Configure communication */
<>	149:156823d33999	651	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	652
<>	149:156823d33999	653	hspi->pRxBuffPtr = pRxData;
<>	149:156823d33999	654	hspi->RxXferSize = Size;
<>	149:156823d33999	655	hspi->RxXferCount = Size;
<>	149:156823d33999	656
<>	149:156823d33999	657	hspi->pTxBuffPtr = pTxData;
<>	149:156823d33999	658	hspi->TxXferSize = Size;
<>	149:156823d33999	659	hspi->TxXferCount = Size;
<>	149:156823d33999	660
<>	149:156823d33999	661	/Init field not used in handle to zero /
<>	149:156823d33999	662	hspi->RxISR = 0;
<>	149:156823d33999	663	hspi->TxISR = 0;
<>	149:156823d33999	664
<>	149:156823d33999	665	/* Reset CRC Calculation */
<>	149:156823d33999	666	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	667	{
<>	149:156823d33999	668	SPI_RESET_CRC(hspi);
<>	149:156823d33999	669	}
<>	149:156823d33999	670
<>	149:156823d33999	671	/* Check if the SPI is already enabled */
<>	149:156823d33999	672	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	673	{
<>	149:156823d33999	674	/* Enable SPI peripheral */
<>	149:156823d33999	675	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	676	}
<>	149:156823d33999	677
<>	149:156823d33999	678	/* Transmit and Receive data in 16 Bit mode */
<>	149:156823d33999	679	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<>	149:156823d33999	680	{
<>	149:156823d33999	681	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	149:156823d33999	682	{
<>	149:156823d33999	683	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	684	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	685	hspi->TxXferCount--;
<>	149:156823d33999	686	}
<>	149:156823d33999	687	if(hspi->TxXferCount == 0)
<>	149:156823d33999	688	{
<>	149:156823d33999	689	/* Enable CRC Transmission */
<>	149:156823d33999	690	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	691	{
<>	149:156823d33999	692	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	693	}
<>	149:156823d33999	694
<>	149:156823d33999	695	/* Wait until RXNE flag is set */
<>	149:156823d33999	696	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	697	{
<>	149:156823d33999	698	return HAL_TIMEOUT;
<>	149:156823d33999	699	}
<>	149:156823d33999	700
<>	149:156823d33999	701	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	702	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	703	hspi->RxXferCount--;
<>	149:156823d33999	704	}
<>	149:156823d33999	705	else
<>	149:156823d33999	706	{
<>	149:156823d33999	707	while(hspi->TxXferCount > 0)
<>	149:156823d33999	708	{
<>	149:156823d33999	709	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	710	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	711	{
<>	149:156823d33999	712	return HAL_TIMEOUT;
<>	149:156823d33999	713	}
<>	149:156823d33999	714
<>	149:156823d33999	715	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	716	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	717	hspi->TxXferCount--;
<>	149:156823d33999	718
<>	149:156823d33999	719	/* Enable CRC Transmission */
<>	149:156823d33999	720	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	149:156823d33999	721	{
<>	149:156823d33999	722	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	723	}
<>	149:156823d33999	724
<>	149:156823d33999	725	/* Wait until RXNE flag is set */
<>	149:156823d33999	726	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	727	{
<>	149:156823d33999	728	return HAL_TIMEOUT;
<>	149:156823d33999	729	}
<>	149:156823d33999	730
<>	149:156823d33999	731	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	732	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	733	hspi->RxXferCount--;
<>	149:156823d33999	734	}
<>	149:156823d33999	735	/* Receive the last byte */
<>	149:156823d33999	736	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	149:156823d33999	737	{
<>	149:156823d33999	738	/* Wait until RXNE flag is set */
<>	149:156823d33999	739	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	740	{
<>	149:156823d33999	741	return HAL_TIMEOUT;
<>	149:156823d33999	742	}
<>	149:156823d33999	743
<>	149:156823d33999	744	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	745	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	746	hspi->RxXferCount--;
<>	149:156823d33999	747	}
<>	149:156823d33999	748	}
<>	149:156823d33999	749	}
<>	149:156823d33999	750	/* Transmit and Receive data in 8 Bit mode */
<>	149:156823d33999	751	else
<>	149:156823d33999	752	{
<>	149:156823d33999	753	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	149:156823d33999	754	{
<>	149:156823d33999	755	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	756	hspi->TxXferCount--;
<>	149:156823d33999	757	}
<>	149:156823d33999	758	if(hspi->TxXferCount == 0)
<>	149:156823d33999	759	{
<>	149:156823d33999	760	/* Enable CRC Transmission */
<>	149:156823d33999	761	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	762	{
<>	149:156823d33999	763	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	764	}
<>	149:156823d33999	765
<>	149:156823d33999	766	/* Wait until RXNE flag is set */
<>	149:156823d33999	767	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	768	{
<>	149:156823d33999	769	return HAL_TIMEOUT;
<>	149:156823d33999	770	}
<>	149:156823d33999	771
<>	149:156823d33999	772	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	773	hspi->RxXferCount--;
<>	149:156823d33999	774	}
<>	149:156823d33999	775	else
<>	149:156823d33999	776	{
<>	149:156823d33999	777	while(hspi->TxXferCount > 0)
<>	149:156823d33999	778	{
<>	149:156823d33999	779	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	780	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	781	{
<>	149:156823d33999	782	return HAL_TIMEOUT;
<>	149:156823d33999	783	}
<>	149:156823d33999	784
<>	149:156823d33999	785	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	786	hspi->TxXferCount--;
<>	149:156823d33999	787
<>	149:156823d33999	788	/* Enable CRC Transmission */
<>	149:156823d33999	789	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	149:156823d33999	790	{
<>	149:156823d33999	791	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	792	}
<>	149:156823d33999	793
<>	149:156823d33999	794	/* Wait until RXNE flag is set */
<>	149:156823d33999	795	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	796	{
<>	149:156823d33999	797	return HAL_TIMEOUT;
<>	149:156823d33999	798	}
<>	149:156823d33999	799
<>	149:156823d33999	800	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	801	hspi->RxXferCount--;
<>	149:156823d33999	802	}
<>	149:156823d33999	803	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	149:156823d33999	804	{
<>	149:156823d33999	805	/* Wait until RXNE flag is set */
<>	149:156823d33999	806	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	807	{
<>	149:156823d33999	808	return HAL_TIMEOUT;
<>	149:156823d33999	809	}
<>	149:156823d33999	810
<>	149:156823d33999	811	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	812	hspi->RxXferCount--;
<>	149:156823d33999	813	}
<>	149:156823d33999	814	}
<>	149:156823d33999	815	}
<>	149:156823d33999	816
<>	149:156823d33999	817	/* Read CRC from DR to close CRC calculation process */
<>	149:156823d33999	818	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	819	{
<>	149:156823d33999	820	/* Wait until RXNE flag is set */
<>	149:156823d33999	821	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	822	{
<>	149:156823d33999	823	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	824	return HAL_TIMEOUT;
<>	149:156823d33999	825	}
<>	149:156823d33999	826	/* Read CRC */
<>	149:156823d33999	827	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	828	UNUSED(tmpreg);
<>	149:156823d33999	829	}
<>	149:156823d33999	830
<>	149:156823d33999	831	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	832	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	149:156823d33999	833	{
<>	149:156823d33999	834	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	835	return HAL_TIMEOUT;
<>	149:156823d33999	836	}
<>	149:156823d33999	837
<>	149:156823d33999	838	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	839
<>	149:156823d33999	840	/* Check if CRC error occurred */
<>	149:156823d33999	841	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	149:156823d33999	842	{
<>	149:156823d33999	843	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	844
<>	149:156823d33999	845	/* Reset CRC Calculation */
<>	149:156823d33999	846	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	847	{
<>	149:156823d33999	848	SPI_RESET_CRC(hspi);
<>	149:156823d33999	849	}
<>	149:156823d33999	850
<>	149:156823d33999	851	/* Process Unlocked */
<>	149:156823d33999	852	__HAL_UNLOCK(hspi);
<>	149:156823d33999	853
<>	149:156823d33999	854	return HAL_ERROR;
<>	149:156823d33999	855	}
<>	149:156823d33999	856
<>	149:156823d33999	857	/* Process Unlocked */
<>	149:156823d33999	858	__HAL_UNLOCK(hspi);
<>	149:156823d33999	859
<>	149:156823d33999	860	return HAL_OK;
<>	149:156823d33999	861	}
<>	149:156823d33999	862	else
<>	149:156823d33999	863	{
<>	149:156823d33999	864	return HAL_BUSY;
<>	149:156823d33999	865	}
<>	149:156823d33999	866	}
<>	149:156823d33999	867
<>	149:156823d33999	868	/**
<>	149:156823d33999	869	* @brief Transmit an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	870	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	871	* the configuration information for SPI module.
<>	149:156823d33999	872	* @param pData: pointer to data buffer
<>	149:156823d33999	873	* @param Size: amount of data to be sent
<>	149:156823d33999	874	* @retval HAL status
<>	149:156823d33999	875	*/
<>	149:156823d33999	876	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	877	{
<>	149:156823d33999	878	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	879	{
<>	149:156823d33999	880	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	881	{
<>	149:156823d33999	882	return HAL_ERROR;
<>	149:156823d33999	883	}
<>	149:156823d33999	884
<>	149:156823d33999	885	/* Check the parameters */
<>	149:156823d33999	886	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	887
<>	149:156823d33999	888	/* Process Locked */
<>	149:156823d33999	889	__HAL_LOCK(hspi);
<>	149:156823d33999	890
<>	149:156823d33999	891	/* Configure communication */
<>	149:156823d33999	892	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	893	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	894
<>	153:fa9ff456f731	895	/* Set the function for IT treatment */
<>	153:fa9ff456f731	896	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<>	153:fa9ff456f731	897	{
<>	153:fa9ff456f731	898	hspi->TxISR = SPI_TxISR_16BIT;
<>	153:fa9ff456f731	899	}
<>	153:fa9ff456f731	900	else
<>	153:fa9ff456f731	901	{
<>	153:fa9ff456f731	902	hspi->TxISR = SPI_TxISR_8BIT;
<>	153:fa9ff456f731	903	}
<>	153:fa9ff456f731	904
<>	149:156823d33999	905	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	906	hspi->TxXferSize = Size;
<>	149:156823d33999	907	hspi->TxXferCount = Size;
<>	149:156823d33999	908
<>	149:156823d33999	909	/Init field not used in handle to zero /
<>	149:156823d33999	910	hspi->RxISR = 0;
<>	149:156823d33999	911	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	912	hspi->RxXferSize = 0;
<>	149:156823d33999	913	hspi->RxXferCount = 0;
<>	149:156823d33999	914
<>	149:156823d33999	915	/* Configure communication direction : 1Line */
<>	149:156823d33999	916	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	917	{
<>	149:156823d33999	918	SPI_1LINE_TX(hspi);
<>	149:156823d33999	919	}
<>	149:156823d33999	920
<>	149:156823d33999	921	/* Reset CRC Calculation */
<>	149:156823d33999	922	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	923	{
<>	149:156823d33999	924	SPI_RESET_CRC(hspi);
<>	149:156823d33999	925	}
<>	149:156823d33999	926
<>	149:156823d33999	927	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	928	{
<>	149:156823d33999	929	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
<>	149:156823d33999	930	}else
<>	149:156823d33999	931	{
<>	149:156823d33999	932	/* Enable TXE and ERR interrupt */
<>	149:156823d33999	933	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	149:156823d33999	934	}
<>	149:156823d33999	935	/* Process Unlocked */
<>	149:156823d33999	936	__HAL_UNLOCK(hspi);
<>	149:156823d33999	937
<>	149:156823d33999	938	/* Check if the SPI is already enabled */
<>	149:156823d33999	939	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	940	{
<>	149:156823d33999	941	/* Enable SPI peripheral */
<>	149:156823d33999	942	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	943	}
<>	149:156823d33999	944
<>	149:156823d33999	945	return HAL_OK;
<>	149:156823d33999	946	}
<>	149:156823d33999	947	else
<>	149:156823d33999	948	{
<>	149:156823d33999	949	return HAL_BUSY;
<>	149:156823d33999	950	}
<>	149:156823d33999	951	}
<>	149:156823d33999	952
<>	149:156823d33999	953	/**
<>	149:156823d33999	954	* @brief Receive an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	955	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	956	* the configuration information for SPI module.
<>	149:156823d33999	957	* @param pData: pointer to data buffer
<>	149:156823d33999	958	* @param Size: amount of data to be sent
<>	149:156823d33999	959	* @retval HAL status
<>	149:156823d33999	960	*/
<>	149:156823d33999	961	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	962	{
<>	149:156823d33999	963	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	964	{
<>	149:156823d33999	965	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	966	{
<>	149:156823d33999	967	return HAL_ERROR;
<>	149:156823d33999	968	}
<>	149:156823d33999	969
<>	149:156823d33999	970	/* Process Locked */
<>	149:156823d33999	971	__HAL_LOCK(hspi);
<>	149:156823d33999	972
<>	149:156823d33999	973	/* Configure communication */
<>	149:156823d33999	974	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	975	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	976
<>	153:fa9ff456f731	977	/* Set the function for IT treatment */
<>	153:fa9ff456f731	978	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<>	153:fa9ff456f731	979	{
<>	153:fa9ff456f731	980	hspi->RxISR = SPI_RxISR_16BIT;
<>	153:fa9ff456f731	981	}
<>	153:fa9ff456f731	982	else
<>	153:fa9ff456f731	983	{
<>	153:fa9ff456f731	984	hspi->RxISR = SPI_RxISR_8BIT;
<>	153:fa9ff456f731	985	}
<>	149:156823d33999	986	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	987	hspi->RxXferSize = Size;
<>	149:156823d33999	988	hspi->RxXferCount = Size ;
<>	149:156823d33999	989
<>	149:156823d33999	990	/Init field not used in handle to zero /
<>	149:156823d33999	991	hspi->TxISR = 0;
<>	149:156823d33999	992	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	993	hspi->TxXferSize = 0;
<>	149:156823d33999	994	hspi->TxXferCount = 0;
<>	149:156823d33999	995
<>	149:156823d33999	996	/* Configure communication direction : 1Line */
<>	149:156823d33999	997	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	998	{
<>	149:156823d33999	999	SPI_1LINE_RX(hspi);
<>	149:156823d33999	1000	}
<>	149:156823d33999	1001	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<>	149:156823d33999	1002	{
<>	149:156823d33999	1003	/* Process Unlocked */
<>	149:156823d33999	1004	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1005
<>	149:156823d33999	1006	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	1007	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<>	149:156823d33999	1008	}
<>	149:156823d33999	1009
<>	149:156823d33999	1010	/* Reset CRC Calculation */
<>	149:156823d33999	1011	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1012	{
<>	149:156823d33999	1013	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1014	}
<>	149:156823d33999	1015
<>	149:156823d33999	1016	/* Enable TXE and ERR interrupt */
<>	149:156823d33999	1017	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	1018
<>	149:156823d33999	1019	/* Process Unlocked */
<>	149:156823d33999	1020	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1021
<>	149:156823d33999	1022	/* Note : The SPI must be enabled after unlocking current process
<>	149:156823d33999	1023	to avoid the risk of SPI interrupt handle execution before current
<>	149:156823d33999	1024	process unlock */
<>	149:156823d33999	1025
<>	149:156823d33999	1026	/* Check if the SPI is already enabled */
<>	149:156823d33999	1027	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1028	{
<>	149:156823d33999	1029	/* Enable SPI peripheral */
<>	149:156823d33999	1030	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1031	}
<>	149:156823d33999	1032
<>	149:156823d33999	1033	return HAL_OK;
<>	149:156823d33999	1034	}
<>	149:156823d33999	1035	else
<>	149:156823d33999	1036	{
<>	149:156823d33999	1037	return HAL_BUSY;
<>	149:156823d33999	1038	}
<>	149:156823d33999	1039	}
<>	149:156823d33999	1040
<>	149:156823d33999	1041	/**
<>	149:156823d33999	1042	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	1043	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1044	* the configuration information for SPI module.
<>	149:156823d33999	1045	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	1046	* @param pRxData: pointer to reception data buffer to be
<>	149:156823d33999	1047	* @param Size: amount of data to be sent
<>	149:156823d33999	1048	* @retval HAL status
<>	149:156823d33999	1049	*/
<>	149:156823d33999	1050	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	149:156823d33999	1051	{
<>	149:156823d33999	1052
<>	149:156823d33999	1053	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	149:156823d33999	1054	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	149:156823d33999	1055	{
<>	149:156823d33999	1056	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	1057	{
<>	149:156823d33999	1058	return HAL_ERROR;
<>	149:156823d33999	1059	}
<>	149:156823d33999	1060
<>	149:156823d33999	1061	/* Check the parameters */
<>	149:156823d33999	1062	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	1063
<>	149:156823d33999	1064	/* Process locked */
<>	149:156823d33999	1065	__HAL_LOCK(hspi);
<>	149:156823d33999	1066
<>	149:156823d33999	1067	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	1068	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1069	{
<>	149:156823d33999	1070	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	1071	}
<>	149:156823d33999	1072
<>	149:156823d33999	1073	/* Configure communication */
<>	149:156823d33999	1074	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1075
<>	149:156823d33999	1076	hspi->pTxBuffPtr = pTxData;
<>	149:156823d33999	1077	hspi->TxXferSize = Size;
<>	149:156823d33999	1078	hspi->TxXferCount = Size;
<>	149:156823d33999	1079
<>	149:156823d33999	1080	hspi->pRxBuffPtr = pRxData;
<>	149:156823d33999	1081	hspi->RxXferSize = Size;
<>	149:156823d33999	1082	hspi->RxXferCount = Size;
<>	149:156823d33999	1083
<>	153:fa9ff456f731	1084	/* Set the function for IT treatment */
<>	153:fa9ff456f731	1085	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<>	153:fa9ff456f731	1086	{
<>	153:fa9ff456f731	1087	hspi->RxISR = SPI_2linesRxISR_16BIT;
<>	153:fa9ff456f731	1088	hspi->TxISR = SPI_2linesTxISR_16BIT;
<>	153:fa9ff456f731	1089	}
<>	153:fa9ff456f731	1090	else
<>	153:fa9ff456f731	1091	{
<>	153:fa9ff456f731	1092	hspi->RxISR = SPI_2linesRxISR_8BIT;
<>	153:fa9ff456f731	1093	hspi->TxISR = SPI_2linesTxISR_8BIT;
<>	153:fa9ff456f731	1094	}
<>	153:fa9ff456f731	1095
<>	149:156823d33999	1096	/* Reset CRC Calculation */
<>	149:156823d33999	1097	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1098	{
<>	149:156823d33999	1099	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1100	}
<>	149:156823d33999	1101
<>	149:156823d33999	1102	/* Enable TXE, RXNE and ERR interrupt */
<>	149:156823d33999	1103	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	1104
<>	149:156823d33999	1105	/* Process Unlocked */
<>	149:156823d33999	1106	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1107
<>	149:156823d33999	1108	/* Check if the SPI is already enabled */
<>	149:156823d33999	1109	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1110	{
<>	149:156823d33999	1111	/* Enable SPI peripheral */
<>	149:156823d33999	1112	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1113	}
<>	149:156823d33999	1114
<>	149:156823d33999	1115	return HAL_OK;
<>	149:156823d33999	1116	}
<>	149:156823d33999	1117	else
<>	149:156823d33999	1118	{
<>	149:156823d33999	1119	return HAL_BUSY;
<>	149:156823d33999	1120	}
<>	149:156823d33999	1121	}
<>	149:156823d33999	1122
<>	149:156823d33999	1123	/**
<>	149:156823d33999	1124	* @brief Transmit an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1125	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1126	* the configuration information for SPI module.
<>	149:156823d33999	1127	* @param pData: pointer to data buffer
<>	149:156823d33999	1128	* @param Size: amount of data to be sent
<>	149:156823d33999	1129	* @retval HAL status
<>	149:156823d33999	1130	*/
<>	149:156823d33999	1131	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	1132	{
<>	149:156823d33999	1133	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	1134	{
<>	149:156823d33999	1135	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	1136	{
<>	149:156823d33999	1137	return HAL_ERROR;
<>	149:156823d33999	1138	}
<>	149:156823d33999	1139
<>	149:156823d33999	1140	/* Check the parameters */
<>	149:156823d33999	1141	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	1142
<>	149:156823d33999	1143	/* Process Locked */
<>	149:156823d33999	1144	__HAL_LOCK(hspi);
<>	149:156823d33999	1145
<>	149:156823d33999	1146	/* Configure communication */
<>	149:156823d33999	1147	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	1148	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1149
<>	149:156823d33999	1150	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	1151	hspi->TxXferSize = Size;
<>	149:156823d33999	1152	hspi->TxXferCount = Size;
<>	149:156823d33999	1153
<>	149:156823d33999	1154	/Init field not used in handle to zero /
<>	149:156823d33999	1155	hspi->TxISR = 0;
<>	149:156823d33999	1156	hspi->RxISR = 0;
<>	149:156823d33999	1157	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	1158	hspi->RxXferSize = 0;
<>	149:156823d33999	1159	hspi->RxXferCount = 0;
<>	149:156823d33999	1160
<>	149:156823d33999	1161	/* Configure communication direction : 1Line */
<>	149:156823d33999	1162	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	1163	{
<>	149:156823d33999	1164	SPI_1LINE_TX(hspi);
<>	149:156823d33999	1165	}
<>	149:156823d33999	1166
<>	149:156823d33999	1167	/* Reset CRC Calculation */
<>	149:156823d33999	1168	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1169	{
<>	149:156823d33999	1170	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1171	}
<>	149:156823d33999	1172
<>	149:156823d33999	1173	/* Set the SPI TxDMA Half transfer complete callback */
<>	149:156823d33999	1174	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<>	149:156823d33999	1175
<>	149:156823d33999	1176	/* Set the SPI TxDMA transfer complete callback */
<>	149:156823d33999	1177	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<>	149:156823d33999	1178
<>	149:156823d33999	1179	/* Set the DMA error callback */
<>	149:156823d33999	1180	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1181
<>	149:156823d33999	1182	/* Enable the Tx DMA Channel */
<>	149:156823d33999	1183	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	149:156823d33999	1184
<>	149:156823d33999	1185	/* Enable Tx DMA Request */
<>	149:156823d33999	1186	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1187
<>	149:156823d33999	1188	/* Process Unlocked */
<>	149:156823d33999	1189	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1190
<>	149:156823d33999	1191	/* Check if the SPI is already enabled */
<>	149:156823d33999	1192	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1193	{
<>	149:156823d33999	1194	/* Enable SPI peripheral */
<>	149:156823d33999	1195	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1196	}
<>	149:156823d33999	1197
<>	149:156823d33999	1198	return HAL_OK;
<>	149:156823d33999	1199	}
<>	149:156823d33999	1200	else
<>	149:156823d33999	1201	{
<>	149:156823d33999	1202	return HAL_BUSY;
<>	149:156823d33999	1203	}
<>	149:156823d33999	1204	}
<>	149:156823d33999	1205
<>	149:156823d33999	1206	/**
<>	149:156823d33999	1207	* @brief Receive an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1208	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1209	* the configuration information for SPI module.
<>	149:156823d33999	1210	* @param pData: pointer to data buffer
<>	149:156823d33999	1211	* @note When the CRC feature is enabled the pData Length must be Size + 1.
<>	149:156823d33999	1212	* @param Size: amount of data to be sent
<>	149:156823d33999	1213	* @retval HAL status
<>	149:156823d33999	1214	*/
<>	149:156823d33999	1215	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	1216	{
<>	149:156823d33999	1217	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	1218	{
<>	149:156823d33999	1219	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	1220	{
<>	149:156823d33999	1221	return HAL_ERROR;
<>	149:156823d33999	1222	}
<>	149:156823d33999	1223
<>	149:156823d33999	1224	/* Process Locked */
<>	149:156823d33999	1225	__HAL_LOCK(hspi);
<>	149:156823d33999	1226
<>	149:156823d33999	1227	/* Configure communication */
<>	149:156823d33999	1228	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	1229	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1230
<>	149:156823d33999	1231	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	1232	hspi->RxXferSize = Size;
<>	149:156823d33999	1233	hspi->RxXferCount = Size;
<>	149:156823d33999	1234
<>	149:156823d33999	1235	/Init field not used in handle to zero /
<>	149:156823d33999	1236	hspi->RxISR = 0;
<>	149:156823d33999	1237	hspi->TxISR = 0;
<>	149:156823d33999	1238	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	1239	hspi->TxXferSize = 0;
<>	149:156823d33999	1240	hspi->TxXferCount = 0;
<>	149:156823d33999	1241
<>	149:156823d33999	1242	/* Configure communication direction : 1Line */
<>	149:156823d33999	1243	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	1244	{
<>	149:156823d33999	1245	SPI_1LINE_RX(hspi);
<>	149:156823d33999	1246	}
<>	149:156823d33999	1247	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
<>	149:156823d33999	1248	{
<>	149:156823d33999	1249	/* Process Unlocked */
<>	149:156823d33999	1250	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1251
<>	149:156823d33999	1252	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	1253	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<>	149:156823d33999	1254	}
<>	149:156823d33999	1255
<>	149:156823d33999	1256	/* Reset CRC Calculation */
<>	149:156823d33999	1257	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1258	{
<>	149:156823d33999	1259	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1260	}
<>	149:156823d33999	1261
<>	149:156823d33999	1262	/* Set the SPI RxDMA Half transfer complete callback */
<>	149:156823d33999	1263	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	149:156823d33999	1264
<>	149:156823d33999	1265	/* Set the SPI Rx DMA transfer complete callback */
<>	149:156823d33999	1266	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	149:156823d33999	1267
<>	149:156823d33999	1268	/* Set the DMA error callback */
<>	149:156823d33999	1269	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1270
<>	149:156823d33999	1271	/* Enable the Rx DMA Channel */
<>	149:156823d33999	1272	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	149:156823d33999	1273
<>	149:156823d33999	1274	/* Enable Rx DMA Request */
<>	149:156823d33999	1275	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1276
<>	149:156823d33999	1277	/* Process Unlocked */
<>	149:156823d33999	1278	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1279
<>	149:156823d33999	1280	/* Check if the SPI is already enabled */
<>	149:156823d33999	1281	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1282	{
<>	149:156823d33999	1283	/* Enable SPI peripheral */
<>	149:156823d33999	1284	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1285	}
<>	149:156823d33999	1286
<>	149:156823d33999	1287	return HAL_OK;
<>	149:156823d33999	1288	}
<>	149:156823d33999	1289	else
<>	149:156823d33999	1290	{
<>	149:156823d33999	1291	return HAL_BUSY;
<>	149:156823d33999	1292	}
<>	149:156823d33999	1293	}
<>	149:156823d33999	1294
<>	149:156823d33999	1295	/**
<>	149:156823d33999	1296	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1297	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1298	* the configuration information for SPI module.
<>	149:156823d33999	1299	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	1300	* @param pRxData: pointer to reception data buffer
<>	149:156823d33999	1301	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
<>	149:156823d33999	1302	* @param Size: amount of data to be sent
<>	149:156823d33999	1303	* @retval HAL status
<>	149:156823d33999	1304	*/
<>	149:156823d33999	1305	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	149:156823d33999	1306	{
<>	149:156823d33999	1307	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	149:156823d33999	1308	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	149:156823d33999	1309	{
<>	149:156823d33999	1310	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	1311	{
<>	149:156823d33999	1312	return HAL_ERROR;
<>	149:156823d33999	1313	}
<>	149:156823d33999	1314
<>	149:156823d33999	1315	/* Check the parameters */
<>	149:156823d33999	1316	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	1317
<>	149:156823d33999	1318	/* Process locked */
<>	149:156823d33999	1319	__HAL_LOCK(hspi);
<>	149:156823d33999	1320
<>	149:156823d33999	1321	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	1322	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1323	{
<>	149:156823d33999	1324	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	1325	}
<>	149:156823d33999	1326
<>	149:156823d33999	1327	/* Configure communication */
<>	149:156823d33999	1328	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1329
<>	149:156823d33999	1330	hspi->pTxBuffPtr = (uint8_t*)pTxData;
<>	149:156823d33999	1331	hspi->TxXferSize = Size;
<>	149:156823d33999	1332	hspi->TxXferCount = Size;
<>	149:156823d33999	1333
<>	149:156823d33999	1334	hspi->pRxBuffPtr = (uint8_t*)pRxData;
<>	149:156823d33999	1335	hspi->RxXferSize = Size;
<>	149:156823d33999	1336	hspi->RxXferCount = Size;
<>	149:156823d33999	1337
<>	149:156823d33999	1338	/Init field not used in handle to zero /
<>	149:156823d33999	1339	hspi->RxISR = 0;
<>	149:156823d33999	1340	hspi->TxISR = 0;
<>	149:156823d33999	1341
<>	149:156823d33999	1342	/* Reset CRC Calculation */
<>	149:156823d33999	1343	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1344	{
<>	149:156823d33999	1345	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1346	}
<>	149:156823d33999	1347
<>	149:156823d33999	1348	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<>	149:156823d33999	1349	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1350	{
<>	149:156823d33999	1351	/* Set the SPI Rx DMA Half transfer complete callback */
<>	149:156823d33999	1352	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	149:156823d33999	1353
<>	149:156823d33999	1354	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	149:156823d33999	1355	}
<>	149:156823d33999	1356	else
<>	149:156823d33999	1357	{
<>	149:156823d33999	1358	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
<>	149:156823d33999	1359	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<>	149:156823d33999	1360
<>	149:156823d33999	1361	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<>	149:156823d33999	1362	}
<>	149:156823d33999	1363
<>	149:156823d33999	1364	/* Set the DMA error callback */
<>	149:156823d33999	1365	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1366
<>	149:156823d33999	1367	/* Enable the Rx DMA Channel */
<>	149:156823d33999	1368	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	149:156823d33999	1369
<>	149:156823d33999	1370	/* Enable Rx DMA Request */
<>	149:156823d33999	1371	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1372
<>	149:156823d33999	1373	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<>	149:156823d33999	1374	is performed in DMA reception complete callback */
<>	149:156823d33999	1375	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	149:156823d33999	1376	{
<>	149:156823d33999	1377	/* Set the DMA error callback */
<>	149:156823d33999	1378	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1379	}
<>	149:156823d33999	1380	else
<>	149:156823d33999	1381	{
<>	149:156823d33999	1382	hspi->hdmatx->XferErrorCallback = NULL;
<>	149:156823d33999	1383	}
<>	149:156823d33999	1384
<>	149:156823d33999	1385	/* Enable the Tx DMA Channel */
<>	149:156823d33999	1386	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	149:156823d33999	1387
<>	149:156823d33999	1388	/* Check if the SPI is already enabled */
<>	149:156823d33999	1389	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1390	{
<>	149:156823d33999	1391	/* Enable SPI peripheral */
<>	149:156823d33999	1392	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1393	}
<>	149:156823d33999	1394
<>	149:156823d33999	1395	/* Enable Tx DMA Request */
<>	149:156823d33999	1396	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1397
<>	149:156823d33999	1398	/* Process Unlocked */
<>	149:156823d33999	1399	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1400
<>	149:156823d33999	1401	return HAL_OK;
<>	149:156823d33999	1402	}
<>	149:156823d33999	1403	else
<>	149:156823d33999	1404	{
<>	149:156823d33999	1405	return HAL_BUSY;
<>	149:156823d33999	1406	}
<>	149:156823d33999	1407	}
<>	149:156823d33999	1408
<>	149:156823d33999	1409
<>	149:156823d33999	1410	/**
<>	149:156823d33999	1411	* @brief Pauses the DMA Transfer.
<>	149:156823d33999	1412	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1413	* the configuration information for the specified SPI module.
<>	149:156823d33999	1414	* @retval HAL status
<>	149:156823d33999	1415	*/
<>	149:156823d33999	1416	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1417	{
<>	149:156823d33999	1418	/* Process Locked */
<>	149:156823d33999	1419	__HAL_LOCK(hspi);
<>	149:156823d33999	1420
<>	149:156823d33999	1421	/* Disable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1422	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1423	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1424
<>	149:156823d33999	1425	/* Process Unlocked */
<>	149:156823d33999	1426	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1427
<>	149:156823d33999	1428	return HAL_OK;
<>	149:156823d33999	1429	}
<>	149:156823d33999	1430
<>	149:156823d33999	1431	/**
<>	149:156823d33999	1432	* @brief Resumes the DMA Transfer.
<>	149:156823d33999	1433	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1434	* the configuration information for the specified SPI module.
<>	149:156823d33999	1435	* @retval HAL status
<>	149:156823d33999	1436	*/
<>	149:156823d33999	1437	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1438	{
<>	149:156823d33999	1439	/* Process Locked */
<>	149:156823d33999	1440	__HAL_LOCK(hspi);
<>	149:156823d33999	1441
<>	149:156823d33999	1442	/* Enable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1443	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1444	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1445
<>	149:156823d33999	1446	/* Process Unlocked */
<>	149:156823d33999	1447	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1448
<>	149:156823d33999	1449	return HAL_OK;
<>	149:156823d33999	1450	}
<>	149:156823d33999	1451
<>	149:156823d33999	1452	/**
<>	149:156823d33999	1453	* @brief Stops the DMA Transfer.
<>	149:156823d33999	1454	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1455	* the configuration information for the specified UART module.
<>	149:156823d33999	1456	* @retval HAL status
<>	149:156823d33999	1457	*/
<>	149:156823d33999	1458	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1459	{
<>	149:156823d33999	1460	/* The Lock is not implemented on this API to allow the user application
<>	149:156823d33999	1461	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<>	149:156823d33999	1462	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<>	149:156823d33999	1463	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<>	149:156823d33999	1464	*/
<>	149:156823d33999	1465
<>	149:156823d33999	1466	/* Abort the SPI DMA tx Channel */
<>	149:156823d33999	1467	if(hspi->hdmatx != NULL)
<>	149:156823d33999	1468	{
<>	149:156823d33999	1469	HAL_DMA_Abort(hspi->hdmatx);
<>	149:156823d33999	1470	}
<>	149:156823d33999	1471	/* Abort the SPI DMA rx Channel */
<>	149:156823d33999	1472	if(hspi->hdmarx != NULL)
<>	149:156823d33999	1473	{
<>	149:156823d33999	1474	HAL_DMA_Abort(hspi->hdmarx);
<>	149:156823d33999	1475	}
<>	149:156823d33999	1476
<>	149:156823d33999	1477	/* Disable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1478	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1479	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1480
<>	149:156823d33999	1481	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1482
<>	149:156823d33999	1483	return HAL_OK;
<>	149:156823d33999	1484	}
<>	149:156823d33999	1485
<>	149:156823d33999	1486	/**
<>	149:156823d33999	1487	* @brief This function handles SPI interrupt request.
<>	149:156823d33999	1488	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1489	* the configuration information for SPI module.
<>	149:156823d33999	1490	* @retval HAL status
<>	149:156823d33999	1491	*/
<>	149:156823d33999	1492	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1493	{
<>	149:156823d33999	1494	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
<>	149:156823d33999	1495	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
<>	149:156823d33999	1496	{
<>	149:156823d33999	1497	hspi->RxISR(hspi);
<>	149:156823d33999	1498	return;
<>	149:156823d33999	1499	}
<>	149:156823d33999	1500
<>	149:156823d33999	1501	/* SPI in mode Tramitter ---------------------------------------------------*/
<>	149:156823d33999	1502	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
<>	149:156823d33999	1503	{
<>	149:156823d33999	1504	hspi->TxISR(hspi);
<>	149:156823d33999	1505	return;
<>	149:156823d33999	1506	}
<>	149:156823d33999	1507
<>	149:156823d33999	1508	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
<>	149:156823d33999	1509	{
<>	149:156823d33999	1510	/* SPI CRC error interrupt occurred ---------------------------------------*/
<>	149:156823d33999	1511	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	1512	{
<>	149:156823d33999	1513	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	1514	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	1515	}
<>	149:156823d33999	1516	/* SPI Mode Fault error interrupt occurred --------------------------------*/
<>	149:156823d33999	1517	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
<>	149:156823d33999	1518	{
<>	149:156823d33999	1519	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<>	149:156823d33999	1520	__HAL_SPI_CLEAR_MODFFLAG(hspi);
<>	149:156823d33999	1521	}
<>	149:156823d33999	1522
<>	149:156823d33999	1523	/* SPI Overrun error interrupt occurred -----------------------------------*/
<>	149:156823d33999	1524	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
<>	149:156823d33999	1525	{
<>	149:156823d33999	1526	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
<>	149:156823d33999	1527	{
<>	149:156823d33999	1528	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<>	149:156823d33999	1529	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	1530	}
<>	149:156823d33999	1531	}
<>	149:156823d33999	1532
<>	149:156823d33999	1533	/* SPI Frame error interrupt occurred -------------------------------------*/
<>	149:156823d33999	1534	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
<>	149:156823d33999	1535	{
<>	149:156823d33999	1536	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<>	149:156823d33999	1537	__HAL_SPI_CLEAR_FREFLAG(hspi);
<>	149:156823d33999	1538	}
<>	149:156823d33999	1539
<>	149:156823d33999	1540	/* Call the Error call Back in case of Errors */
<>	149:156823d33999	1541	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
<>	149:156823d33999	1542	{
<>	149:156823d33999	1543	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
<>	149:156823d33999	1544	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1545	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	1546	}
<>	149:156823d33999	1547	}
<>	149:156823d33999	1548	}
<>	149:156823d33999	1549
<>	149:156823d33999	1550	/**
<>	149:156823d33999	1551	* @brief Tx Transfer completed callbacks
<>	149:156823d33999	1552	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1553	* the configuration information for SPI module.
<>	149:156823d33999	1554	* @retval None
<>	149:156823d33999	1555	*/
<>	149:156823d33999	1556	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1557	{
<>	149:156823d33999	1558	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1559	UNUSED(hspi);
<>	149:156823d33999	1560
<>	149:156823d33999	1561	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1562	the HAL_SPI_TxCpltCallback could be implenetd in the user file
<>	149:156823d33999	1563	*/
<>	149:156823d33999	1564	}
<>	149:156823d33999	1565
<>	149:156823d33999	1566	/**
<>	149:156823d33999	1567	* @brief Rx Transfer completed callbacks
<>	149:156823d33999	1568	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1569	* the configuration information for SPI module.
<>	149:156823d33999	1570	* @retval None
<>	149:156823d33999	1571	*/
<>	149:156823d33999	1572	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1573	{
<>	149:156823d33999	1574	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1575	UNUSED(hspi);
<>	149:156823d33999	1576
<>	149:156823d33999	1577	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1578	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1579	*/
<>	149:156823d33999	1580	}
<>	149:156823d33999	1581
<>	149:156823d33999	1582	/**
<>	149:156823d33999	1583	* @brief Tx and Rx Transfer completed callbacks
<>	149:156823d33999	1584	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1585	* the configuration information for SPI module.
<>	149:156823d33999	1586	* @retval None
<>	149:156823d33999	1587	*/
<>	149:156823d33999	1588	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1589	{
<>	149:156823d33999	1590	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1591	UNUSED(hspi);
<>	149:156823d33999	1592
<>	149:156823d33999	1593	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1594	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1595	*/
<>	149:156823d33999	1596	}
<>	149:156823d33999	1597
<>	149:156823d33999	1598	/**
<>	149:156823d33999	1599	* @brief Tx Half Transfer completed callbacks
<>	149:156823d33999	1600	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1601	* the configuration information for SPI module.
<>	149:156823d33999	1602	* @retval None
<>	149:156823d33999	1603	*/
<>	149:156823d33999	1604	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1605	{
<>	149:156823d33999	1606	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1607	UNUSED(hspi);
<>	149:156823d33999	1608
<>	149:156823d33999	1609	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1610	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
<>	149:156823d33999	1611	*/
<>	149:156823d33999	1612	}
<>	149:156823d33999	1613
<>	149:156823d33999	1614	/**
<>	149:156823d33999	1615	* @brief Rx Half Transfer completed callbacks
<>	149:156823d33999	1616	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1617	* the configuration information for SPI module.
<>	149:156823d33999	1618	* @retval None
<>	149:156823d33999	1619	*/
<>	149:156823d33999	1620	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1621	{
<>	149:156823d33999	1622	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1623	UNUSED(hspi);
<>	149:156823d33999	1624
<>	149:156823d33999	1625	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1626	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1627	*/
<>	149:156823d33999	1628	}
<>	149:156823d33999	1629
<>	149:156823d33999	1630	/**
<>	149:156823d33999	1631	* @brief Tx and Rx Transfer completed callbacks
<>	149:156823d33999	1632	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1633	* the configuration information for SPI module.
<>	149:156823d33999	1634	* @retval None
<>	149:156823d33999	1635	*/
<>	149:156823d33999	1636	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1637	{
<>	149:156823d33999	1638	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1639	UNUSED(hspi);
<>	149:156823d33999	1640
<>	149:156823d33999	1641	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1642	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1643	*/
<>	149:156823d33999	1644	}
<>	149:156823d33999	1645
<>	149:156823d33999	1646	/**
<>	149:156823d33999	1647	* @brief SPI error callbacks
<>	149:156823d33999	1648	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1649	* the configuration information for SPI module.
<>	149:156823d33999	1650	* @retval None
<>	149:156823d33999	1651	*/
<>	149:156823d33999	1652	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1653	{
<>	149:156823d33999	1654	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1655	UNUSED(hspi);
<>	149:156823d33999	1656
<>	149:156823d33999	1657	/* NOTE : - This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1658	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
<>	149:156823d33999	1659	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
<>	149:156823d33999	1660	and user can use HAL_SPI_GetError() API to check the latest error occurred.
<>	149:156823d33999	1661	*/
<>	149:156823d33999	1662	}
<>	149:156823d33999	1663
<>	149:156823d33999	1664	/**
<>	149:156823d33999	1665	* @}
<>	149:156823d33999	1666	*/
<>	149:156823d33999	1667
<>	149:156823d33999	1668	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<>	149:156823d33999	1669	* @brief SPI control functions
<>	149:156823d33999	1670	*
<>	149:156823d33999	1671	@verbatim
<>	149:156823d33999	1672	===============================================================================
<>	149:156823d33999	1673	##### Peripheral State and Errors functions #####
<>	149:156823d33999	1674	===============================================================================
<>	149:156823d33999	1675	[..]
<>	149:156823d33999	1676	This subsection provides a set of functions allowing to control the SPI.
<>	149:156823d33999	1677	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<>	149:156823d33999	1678	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<>	149:156823d33999	1679	@endverbatim
<>	149:156823d33999	1680	* @{
<>	149:156823d33999	1681	*/
<>	149:156823d33999	1682
<>	149:156823d33999	1683	/**
<>	149:156823d33999	1684	* @brief Return the SPI state
<>	149:156823d33999	1685	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1686	* the configuration information for SPI module.
<>	149:156823d33999	1687	* @retval HAL state
<>	149:156823d33999	1688	*/
<>	149:156823d33999	1689	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1690	{
<>	149:156823d33999	1691	return hspi->State;
<>	149:156823d33999	1692	}
<>	149:156823d33999	1693
<>	149:156823d33999	1694	/**
<>	149:156823d33999	1695	* @brief Return the SPI error code
<>	149:156823d33999	1696	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1697	* the configuration information for SPI module.
<>	149:156823d33999	1698	* @retval SPI Error Code
<>	149:156823d33999	1699	*/
<>	149:156823d33999	1700	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1701	{
<>	149:156823d33999	1702	return hspi->ErrorCode;
<>	149:156823d33999	1703	}
<>	149:156823d33999	1704
<>	149:156823d33999	1705	/**
<>	149:156823d33999	1706	* @}
<>	149:156823d33999	1707	*/
<>	149:156823d33999	1708
<>	149:156823d33999	1709	/**
<>	149:156823d33999	1710	* @}
<>	149:156823d33999	1711	*/
<>	149:156823d33999	1712
<>	149:156823d33999	1713
<>	149:156823d33999	1714
<>	149:156823d33999	1715	/** @addtogroup SPI_Private_Functions
<>	149:156823d33999	1716	* @{
<>	149:156823d33999	1717	*/
<>	149:156823d33999	1718
<>	153:fa9ff456f731	1719	/**
<>	153:fa9ff456f731	1720	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<>	149:156823d33999	1721	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1722	* the configuration information for SPI module.
<>	153:fa9ff456f731	1723	* @retval None
<>	149:156823d33999	1724	*/
<>	153:fa9ff456f731	1725	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1726	{
<>	153:fa9ff456f731	1727	/* Receive data in 8bit mode */
<>	153:fa9ff456f731	1728	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
<>	153:fa9ff456f731	1729	hspi->RxXferCount--;
<>	153:fa9ff456f731	1730
<>	153:fa9ff456f731	1731	/* check end of the reception */
<>	153:fa9ff456f731	1732	if(hspi->RxXferCount == 0U)
<>	149:156823d33999	1733	{
<>	153:fa9ff456f731	1734	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1735	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	1736	{
<>	153:fa9ff456f731	1737	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<>	153:fa9ff456f731	1738	return;
<>	153:fa9ff456f731	1739	}
<>	153:fa9ff456f731	1740	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1741
<>	153:fa9ff456f731	1742	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1743	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	1744
<>	153:fa9ff456f731	1745	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1746	{
<>	153:fa9ff456f731	1747	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1748	}
<>	149:156823d33999	1749	}
<>	153:fa9ff456f731	1750	}
<>	149:156823d33999	1751
<>	153:fa9ff456f731	1752	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1753	/**
<>	153:fa9ff456f731	1754	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1755	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1756	* the configuration information for SPI module.
<>	153:fa9ff456f731	1757	* @retval None
<>	153:fa9ff456f731	1758	*/
<>	153:fa9ff456f731	1759	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1760	{
<>	153:fa9ff456f731	1761	__IO uint8_t tmpreg = 0U;
<>	149:156823d33999	1762
<>	153:fa9ff456f731	1763	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1764	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
<>	153:fa9ff456f731	1765
<>	153:fa9ff456f731	1766	/* To avoid GCC warning */
<>	153:fa9ff456f731	1767
<>	153:fa9ff456f731	1768	UNUSED(tmpreg);
<>	153:fa9ff456f731	1769
<>	153:fa9ff456f731	1770	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1771	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	1772
<>	153:fa9ff456f731	1773	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1774	{
<>	153:fa9ff456f731	1775	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1776	}
<>	153:fa9ff456f731	1777	}
<>	153:fa9ff456f731	1778	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1779
<>	153:fa9ff456f731	1780	/**
<>	153:fa9ff456f731	1781	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1782	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1783	* the configuration information for SPI module.
<>	153:fa9ff456f731	1784	* @retval None
<>	153:fa9ff456f731	1785	*/
<>	153:fa9ff456f731	1786	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1787	{
<>	153:fa9ff456f731	1788	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	153:fa9ff456f731	1789	hspi->TxXferCount--;
<>	153:fa9ff456f731	1790
<>	153:fa9ff456f731	1791	/* check the end of the transmission */
<>	153:fa9ff456f731	1792	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1793	{
<>	153:fa9ff456f731	1794	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1795	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1796	{
<>	153:fa9ff456f731	1797	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	1798	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1799	return;
<>	149:156823d33999	1800	}
<>	153:fa9ff456f731	1801	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1802
<>	153:fa9ff456f731	1803	/* Disable TXE interrupt */
<>	153:fa9ff456f731	1804	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1805
<>	153:fa9ff456f731	1806	if(hspi->RxXferCount == 0U)
<>	149:156823d33999	1807	{
<>	153:fa9ff456f731	1808	SPI_CloseRxTx_ISR(hspi);
<>	149:156823d33999	1809	}
<>	149:156823d33999	1810	}
<>	149:156823d33999	1811	}
<>	149:156823d33999	1812
<>	149:156823d33999	1813	/**
<>	153:fa9ff456f731	1814	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
<>	149:156823d33999	1815	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1816	* the configuration information for SPI module.
<>	153:fa9ff456f731	1817	* @retval None
<>	149:156823d33999	1818	*/
<>	153:fa9ff456f731	1819	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1820	{
<>	153:fa9ff456f731	1821	/* Receive data in 16 Bit mode */
<>	153:fa9ff456f731	1822	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	153:fa9ff456f731	1823	hspi->pRxBuffPtr += sizeof(uint16_t);
<>	153:fa9ff456f731	1824	hspi->RxXferCount--;
<>	153:fa9ff456f731	1825
<>	153:fa9ff456f731	1826	if(hspi->RxXferCount == 0U)
<>	149:156823d33999	1827	{
<>	153:fa9ff456f731	1828	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1829	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	1830	{
<>	153:fa9ff456f731	1831	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<>	153:fa9ff456f731	1832	return;
<>	153:fa9ff456f731	1833	}
<>	153:fa9ff456f731	1834	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1835
<>	153:fa9ff456f731	1836	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1837	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<>	153:fa9ff456f731	1838
<>	153:fa9ff456f731	1839	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1840	{
<>	153:fa9ff456f731	1841	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1842	}
<>	149:156823d33999	1843	}
<>	153:fa9ff456f731	1844	}
<>	153:fa9ff456f731	1845
<>	153:fa9ff456f731	1846	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1847	/**
<>	153:fa9ff456f731	1848	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1849	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1850	* the configuration information for SPI module.
<>	153:fa9ff456f731	1851	* @retval None
<>	153:fa9ff456f731	1852	*/
<>	153:fa9ff456f731	1853	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1854	{
<>	153:fa9ff456f731	1855	/* Receive data in 16 Bit mode */
<>	153:fa9ff456f731	1856	__IO uint16_t tmpreg = 0U;
<>	153:fa9ff456f731	1857
<>	153:fa9ff456f731	1858	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1859	tmpreg = hspi->Instance->DR;
<>	153:fa9ff456f731	1860
<>	153:fa9ff456f731	1861	/* To avoid GCC warning */
<>	153:fa9ff456f731	1862	UNUSED(tmpreg);
<>	153:fa9ff456f731	1863
<>	153:fa9ff456f731	1864	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1865	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<>	153:fa9ff456f731	1866
<>	153:fa9ff456f731	1867	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1868	}
<>	153:fa9ff456f731	1869	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1870
<>	153:fa9ff456f731	1871	/**
<>	153:fa9ff456f731	1872	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1873	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1874	* the configuration information for SPI module.
<>	153:fa9ff456f731	1875	* @retval None
<>	153:fa9ff456f731	1876	*/
<>	153:fa9ff456f731	1877	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1878	{
<>	149:156823d33999	1879	/* Transmit data in 16 Bit mode */
<>	153:fa9ff456f731	1880	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
<>	153:fa9ff456f731	1881	hspi->pTxBuffPtr += sizeof(uint16_t);
<>	149:156823d33999	1882	hspi->TxXferCount--;
<>	149:156823d33999	1883
<>	153:fa9ff456f731	1884	/* Enable CRC Transmission */
<>	153:fa9ff456f731	1885	if(hspi->TxXferCount == 0U)
<>	149:156823d33999	1886	{
<>	153:fa9ff456f731	1887	#if (USE_SPI_CRC != 0U)
<>	149:156823d33999	1888	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1889	{
<>	149:156823d33999	1890	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	1891	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1892	return;
<>	149:156823d33999	1893	}
<>	153:fa9ff456f731	1894	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1895
<>	153:fa9ff456f731	1896	/* Disable TXE interrupt */
<>	153:fa9ff456f731	1897	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1898
<>	153:fa9ff456f731	1899	if(hspi->RxXferCount == 0U)
<>	153:fa9ff456f731	1900	{
<>	153:fa9ff456f731	1901	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1902	}
<>	153:fa9ff456f731	1903	}
<>	153:fa9ff456f731	1904	}
<>	153:fa9ff456f731	1905
<>	153:fa9ff456f731	1906	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1907	/**
<>	153:fa9ff456f731	1908	* @brief Manage the CRC 8-bit receive in Interrupt context.
<>	153:fa9ff456f731	1909	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1910	* the configuration information for SPI module.
<>	153:fa9ff456f731	1911	* @retval None
<>	153:fa9ff456f731	1912	*/
<>	153:fa9ff456f731	1913	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1914	{
<>	153:fa9ff456f731	1915	__IO uint8_t tmpreg = 0U;
<>	153:fa9ff456f731	1916
<>	153:fa9ff456f731	1917	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1918	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
<>	153:fa9ff456f731	1919
<>	153:fa9ff456f731	1920	/* To avoid GCC warning */
<>	153:fa9ff456f731	1921	UNUSED(tmpreg);
<>	153:fa9ff456f731	1922
<>	153:fa9ff456f731	1923	SPI_CloseRx_ISR(hspi);
<>	153:fa9ff456f731	1924	}
<>	153:fa9ff456f731	1925	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1926
<>	153:fa9ff456f731	1927	/**
<>	153:fa9ff456f731	1928	* @brief Manage the receive 8-bit in Interrupt context.
<>	153:fa9ff456f731	1929	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1930	* the configuration information for SPI module.
<>	153:fa9ff456f731	1931	* @retval None
<>	153:fa9ff456f731	1932	*/
<>	153:fa9ff456f731	1933	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1934	{
<>	153:fa9ff456f731	1935	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
<>	153:fa9ff456f731	1936	hspi->RxXferCount--;
<>	153:fa9ff456f731	1937
<>	153:fa9ff456f731	1938	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1939	/* Enable CRC Transmission */
<>	153:fa9ff456f731	1940	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	153:fa9ff456f731	1941	{
<>	153:fa9ff456f731	1942	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	1943	}
<>	153:fa9ff456f731	1944	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1945
<>	153:fa9ff456f731	1946	if(hspi->RxXferCount == 0U)
<>	153:fa9ff456f731	1947	{
<>	153:fa9ff456f731	1948	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1949	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	1950	{
<>	153:fa9ff456f731	1951	hspi->RxISR = SPI_RxISR_8BITCRC;
<>	153:fa9ff456f731	1952	return;
<>	153:fa9ff456f731	1953	}
<>	153:fa9ff456f731	1954	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1955	SPI_CloseRx_ISR(hspi);
<>	153:fa9ff456f731	1956	}
<>	153:fa9ff456f731	1957	}
<>	153:fa9ff456f731	1958
<>	153:fa9ff456f731	1959	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1960	/**
<>	153:fa9ff456f731	1961	* @brief Manage the CRC 16-bit receive in Interrupt context.
<>	153:fa9ff456f731	1962	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1963	* the configuration information for SPI module.
<>	153:fa9ff456f731	1964	* @retval None
<>	153:fa9ff456f731	1965	*/
<>	153:fa9ff456f731	1966	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1967	{
<>	153:fa9ff456f731	1968	__IO uint16_t tmpreg = 0U;
<>	153:fa9ff456f731	1969
<>	153:fa9ff456f731	1970	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1971	tmpreg = hspi->Instance->DR;
<>	153:fa9ff456f731	1972
<>	153:fa9ff456f731	1973	/* To avoid GCC warning */
<>	153:fa9ff456f731	1974	UNUSED(tmpreg);
<>	153:fa9ff456f731	1975
<>	153:fa9ff456f731	1976	/* Disable RXNE and ERR interrupt */
<>	153:fa9ff456f731	1977	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	1978
<>	153:fa9ff456f731	1979	SPI_CloseRx_ISR(hspi);
<>	153:fa9ff456f731	1980	}
<>	153:fa9ff456f731	1981	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1982
<>	153:fa9ff456f731	1983	/**
<>	153:fa9ff456f731	1984	* @brief Manage the 16-bit receive in Interrupt context.
<>	153:fa9ff456f731	1985	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1986	* the configuration information for SPI module.
<>	153:fa9ff456f731	1987	* @retval None
<>	153:fa9ff456f731	1988	*/
<>	153:fa9ff456f731	1989	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1990	{
<>	153:fa9ff456f731	1991	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	153:fa9ff456f731	1992	hspi->pRxBuffPtr += sizeof(uint16_t);
<>	153:fa9ff456f731	1993	hspi->RxXferCount--;
<>	153:fa9ff456f731	1994
<>	153:fa9ff456f731	1995	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1996	/* Enable CRC Transmission */
<>	153:fa9ff456f731	1997	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	153:fa9ff456f731	1998	{
<>	153:fa9ff456f731	1999	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	2000	}
<>	153:fa9ff456f731	2001	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2002
<>	153:fa9ff456f731	2003	if(hspi->RxXferCount == 0U)
<>	153:fa9ff456f731	2004	{
<>	153:fa9ff456f731	2005	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2006	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	2007	{
<>	153:fa9ff456f731	2008	hspi->RxISR = SPI_RxISR_16BITCRC;
<>	153:fa9ff456f731	2009	return;
<>	153:fa9ff456f731	2010	}
<>	153:fa9ff456f731	2011	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2012	SPI_CloseRx_ISR(hspi);
<>	149:156823d33999	2013	}
<>	149:156823d33999	2014	}
<>	149:156823d33999	2015
<>	149:156823d33999	2016	/**
<>	153:fa9ff456f731	2017	* @brief Handle the data 8-bit transmit in Interrupt mode.
<>	149:156823d33999	2018	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2019	* the configuration information for SPI module.
<>	153:fa9ff456f731	2020	* @retval None
<>	149:156823d33999	2021	*/
<>	153:fa9ff456f731	2022	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	2023	{
<>	153:fa9ff456f731	2024	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	153:fa9ff456f731	2025	hspi->TxXferCount--;
<>	149:156823d33999	2026
<>	153:fa9ff456f731	2027	if(hspi->TxXferCount == 0U)
<>	149:156823d33999	2028	{
<>	153:fa9ff456f731	2029	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2030	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2031	{
<>	153:fa9ff456f731	2032	/* Enable CRC Transmission */
<>	153:fa9ff456f731	2033	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	2034	}
<>	153:fa9ff456f731	2035	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2036	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<>	153:fa9ff456f731	2037	SPI_CloseTx_ISR(hspi);
<>	149:156823d33999	2038	}
<>	149:156823d33999	2039	}
<>	149:156823d33999	2040
<>	149:156823d33999	2041	/**
<>	153:fa9ff456f731	2042	* @brief Handle the data 16-bit transmit in Interrupt mode.
<>	149:156823d33999	2043	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2044	* the configuration information for SPI module.
<>	153:fa9ff456f731	2045	* @retval None
<>	149:156823d33999	2046	*/
<>	153:fa9ff456f731	2047	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	2048	{
<>	153:fa9ff456f731	2049	/* Transmit data in 16 Bit mode */
<>	153:fa9ff456f731	2050	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
<>	153:fa9ff456f731	2051	hspi->pTxBuffPtr += sizeof(uint16_t);
<>	153:fa9ff456f731	2052	hspi->TxXferCount--;
<>	153:fa9ff456f731	2053
<>	153:fa9ff456f731	2054	if(hspi->TxXferCount == 0U)
<>	149:156823d33999	2055	{
<>	153:fa9ff456f731	2056	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2057	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	2058	{
<>	153:fa9ff456f731	2059	/* Enable CRC Transmission */
<>	153:fa9ff456f731	2060	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	2061	}
<>	153:fa9ff456f731	2062	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2063	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<>	153:fa9ff456f731	2064	SPI_CloseTx_ISR(hspi);
<>	149:156823d33999	2065	}
<>	149:156823d33999	2066	}
<>	149:156823d33999	2067
<>	149:156823d33999	2068	/**
<>	153:fa9ff456f731	2069	* @brief Handle SPI Communication Timeout.
<>	153:fa9ff456f731	2070	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2071	* the configuration information for SPI module.
<>	153:fa9ff456f731	2072	* @param Flag: SPI flag to check
<>	153:fa9ff456f731	2073	* @param State: flag state to check
<>	153:fa9ff456f731	2074	* @param Timeout: Timeout duration
<>	153:fa9ff456f731	2075	* @param Tickstart: tick start value
<>	153:fa9ff456f731	2076	* @retval HAL status
<>	149:156823d33999	2077	*/
<>	153:fa9ff456f731	2078	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
<>	149:156823d33999	2079	{
<>	153:fa9ff456f731	2080	while((hspi->Instance->SR & Flag) != State)
<>	149:156823d33999	2081	{
<>	153:fa9ff456f731	2082	if(Timeout != HAL_MAX_DELAY)
<>	153:fa9ff456f731	2083	{
<>	153:fa9ff456f731	2084	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) >= Timeout))
<>	153:fa9ff456f731	2085	{
<>	153:fa9ff456f731	2086	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	153:fa9ff456f731	2087	on both master and slave sides in order to resynchronize the master
<>	153:fa9ff456f731	2088	and slave for their respective CRC calculation */
<>	153:fa9ff456f731	2089
<>	153:fa9ff456f731	2090	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	153:fa9ff456f731	2091	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2092
<>	153:fa9ff456f731	2093	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	153:fa9ff456f731	2094	{
<>	153:fa9ff456f731	2095	/* Disable SPI peripheral */
<>	153:fa9ff456f731	2096	__HAL_SPI_DISABLE(hspi);
<>	153:fa9ff456f731	2097	}
<>	153:fa9ff456f731	2098
<>	153:fa9ff456f731	2099	/* Reset CRC Calculation */
<>	153:fa9ff456f731	2100	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	2101	{
<>	153:fa9ff456f731	2102	SPI_RESET_CRC(hspi);
<>	153:fa9ff456f731	2103	}
<>	153:fa9ff456f731	2104
<>	153:fa9ff456f731	2105	hspi->State= HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2106
<>	153:fa9ff456f731	2107	/* Process Unlocked */
<>	153:fa9ff456f731	2108	__HAL_UNLOCK(hspi);
<>	153:fa9ff456f731	2109
<>	153:fa9ff456f731	2110	return HAL_TIMEOUT;
<>	153:fa9ff456f731	2111	}
<>	153:fa9ff456f731	2112	}
<>	149:156823d33999	2113	}
<>	149:156823d33999	2114
<>	153:fa9ff456f731	2115	return HAL_OK;
<>	149:156823d33999	2116	}
<>	149:156823d33999	2117
<>	149:156823d33999	2118	/**
<>	149:156823d33999	2119	* @brief DMA SPI transmit process complete callback
<>	149:156823d33999	2120	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2121	* the configuration information for the specified DMA module.
<>	149:156823d33999	2122	* @retval None
<>	149:156823d33999	2123	*/
<>	149:156823d33999	2124	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2125	{
<>	149:156823d33999	2126	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2127
<>	149:156823d33999	2128	/* DMA Normal Mode */
<>	149:156823d33999	2129	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	2130	{
<>	149:156823d33999	2131	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	2132	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2133	{
<>	149:156823d33999	2134	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2135	}
<>	149:156823d33999	2136
<>	149:156823d33999	2137	/* Disable Tx DMA Request */
<>	149:156823d33999	2138	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	2139
<>	149:156823d33999	2140	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	2141	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2142	{
<>	149:156823d33999	2143	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2144	}
<>	149:156823d33999	2145
<>	149:156823d33999	2146	hspi->TxXferCount = 0;
<>	149:156823d33999	2147	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2148	}
<>	149:156823d33999	2149
<>	149:156823d33999	2150	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	149:156823d33999	2151	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	2152	{
<>	149:156823d33999	2153	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	2154	}
<>	149:156823d33999	2155
<>	149:156823d33999	2156	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2157	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2158	{
<>	149:156823d33999	2159	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2160	}
<>	149:156823d33999	2161	else
<>	149:156823d33999	2162	{
<>	149:156823d33999	2163	HAL_SPI_TxCpltCallback(hspi);
<>	149:156823d33999	2164	}
<>	149:156823d33999	2165	}
<>	149:156823d33999	2166
<>	149:156823d33999	2167	/**
<>	149:156823d33999	2168	* @brief DMA SPI receive process complete callback
<>	149:156823d33999	2169	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2170	* the configuration information for the specified DMA module.
<>	149:156823d33999	2171	* @retval None
<>	149:156823d33999	2172	*/
<>	149:156823d33999	2173	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2174	{
<>	149:156823d33999	2175	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	2176
<>	149:156823d33999	2177	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2178
<>	149:156823d33999	2179	/* DMA Normal mode */
<>	149:156823d33999	2180	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	2181	{
<>	149:156823d33999	2182	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	149:156823d33999	2183	{
<>	149:156823d33999	2184	/* Disable SPI peripheral */
<>	149:156823d33999	2185	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2186	}
<>	149:156823d33999	2187
<>	149:156823d33999	2188	/* Disable Rx DMA Request */
<>	149:156823d33999	2189	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	2190
<>	149:156823d33999	2191	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
<>	149:156823d33999	2192	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	2193
<>	149:156823d33999	2194	/* Reset CRC Calculation */
<>	149:156823d33999	2195	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2196	{
<>	149:156823d33999	2197	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	2198	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2199	{
<>	149:156823d33999	2200	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2201	}
<>	149:156823d33999	2202
<>	149:156823d33999	2203	/* Read CRC */
<>	149:156823d33999	2204	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	2205	UNUSED(tmpreg);
<>	149:156823d33999	2206
<>	149:156823d33999	2207	/* Wait until RXNE flag is set */
<>	149:156823d33999	2208	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2209	{
<>	149:156823d33999	2210	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2211	}
<>	149:156823d33999	2212
<>	149:156823d33999	2213	/* Check if CRC error occurred */
<>	149:156823d33999	2214	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	2215	{
<>	149:156823d33999	2216	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	2217	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	2218	}
<>	149:156823d33999	2219	}
<>	149:156823d33999	2220
<>	149:156823d33999	2221	hspi->RxXferCount = 0;
<>	149:156823d33999	2222	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2223
<>	149:156823d33999	2224	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2225	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2226	{
<>	149:156823d33999	2227	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2228	}
<>	149:156823d33999	2229	else
<>	149:156823d33999	2230	{
<>	149:156823d33999	2231	HAL_SPI_RxCpltCallback(hspi);
<>	149:156823d33999	2232	}
<>	149:156823d33999	2233	}
<>	149:156823d33999	2234	else
<>	149:156823d33999	2235	{
<>	149:156823d33999	2236	HAL_SPI_RxCpltCallback(hspi);
<>	149:156823d33999	2237	}
<>	149:156823d33999	2238	}
<>	149:156823d33999	2239
<>	149:156823d33999	2240	/**
<>	149:156823d33999	2241	* @brief DMA SPI transmit receive process complete callback
<>	149:156823d33999	2242	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2243	* the configuration information for the specified DMA module.
<>	149:156823d33999	2244	* @retval None
<>	149:156823d33999	2245	*/
<>	149:156823d33999	2246	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2247	{
<>	149:156823d33999	2248	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	2249
<>	149:156823d33999	2250	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2251
<>	149:156823d33999	2252	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	2253	{
<>	149:156823d33999	2254	/* Reset CRC Calculation */
<>	149:156823d33999	2255	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2256	{
<>	149:156823d33999	2257	/* Check if CRC is done on going (RXNE flag set) */
<>	149:156823d33999	2258	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
<>	149:156823d33999	2259	{
<>	149:156823d33999	2260	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	2261	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2262	{
<>	149:156823d33999	2263	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2264	}
<>	149:156823d33999	2265	}
<>	149:156823d33999	2266	/* Read CRC */
<>	149:156823d33999	2267	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	2268	UNUSED(tmpreg);
<>	149:156823d33999	2269
<>	149:156823d33999	2270	/* Check if CRC error occurred */
<>	149:156823d33999	2271	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	2272	{
<>	149:156823d33999	2273	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	2274	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	2275	}
<>	149:156823d33999	2276	}
<>	149:156823d33999	2277
<>	149:156823d33999	2278	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	2279	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2280	{
<>	149:156823d33999	2281	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2282	}
<>	149:156823d33999	2283
<>	149:156823d33999	2284	/* Disable Tx DMA Request */
<>	149:156823d33999	2285	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	2286
<>	149:156823d33999	2287	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	2288	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2289	{
<>	149:156823d33999	2290	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2291	}
<>	149:156823d33999	2292
<>	149:156823d33999	2293	/* Disable Rx DMA Request */
<>	149:156823d33999	2294	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	2295
<>	149:156823d33999	2296	hspi->TxXferCount = 0;
<>	149:156823d33999	2297	hspi->RxXferCount = 0;
<>	149:156823d33999	2298
<>	149:156823d33999	2299	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2300
<>	149:156823d33999	2301	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2302	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2303	{
<>	149:156823d33999	2304	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2305	}
<>	149:156823d33999	2306	else
<>	149:156823d33999	2307	{
<>	149:156823d33999	2308	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	2309	}
<>	149:156823d33999	2310	}
<>	149:156823d33999	2311	else
<>	149:156823d33999	2312	{
<>	149:156823d33999	2313	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	2314	}
<>	149:156823d33999	2315	}
<>	149:156823d33999	2316
<>	149:156823d33999	2317	/**
<>	149:156823d33999	2318	* @brief DMA SPI half transmit process complete callback
<>	149:156823d33999	2319	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2320	* the configuration information for the specified DMA module.
<>	149:156823d33999	2321	* @retval None
<>	149:156823d33999	2322	*/
<>	149:156823d33999	2323	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2324	{
<>	149:156823d33999	2325	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2326
<>	149:156823d33999	2327	HAL_SPI_TxHalfCpltCallback(hspi);
<>	149:156823d33999	2328	}
<>	149:156823d33999	2329
<>	149:156823d33999	2330	/**
<>	149:156823d33999	2331	* @brief DMA SPI half receive process complete callback
<>	149:156823d33999	2332	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2333	* the configuration information for the specified DMA module.
<>	149:156823d33999	2334	* @retval None
<>	149:156823d33999	2335	*/
<>	149:156823d33999	2336	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2337	{
<>	149:156823d33999	2338	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2339
<>	149:156823d33999	2340	HAL_SPI_RxHalfCpltCallback(hspi);
<>	149:156823d33999	2341	}
<>	149:156823d33999	2342
<>	149:156823d33999	2343	/**
<>	149:156823d33999	2344	* @brief DMA SPI Half transmit receive process complete callback
<>	149:156823d33999	2345	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2346	* the configuration information for the specified DMA module.
<>	149:156823d33999	2347	* @retval None
<>	149:156823d33999	2348	*/
<>	149:156823d33999	2349	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2350	{
<>	149:156823d33999	2351	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2352
<>	149:156823d33999	2353	HAL_SPI_TxRxHalfCpltCallback(hspi);
<>	149:156823d33999	2354	}
<>	149:156823d33999	2355
<>	149:156823d33999	2356	/**
<>	149:156823d33999	2357	* @brief DMA SPI communication error callback
<>	149:156823d33999	2358	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2359	* the configuration information for the specified DMA module.
<>	149:156823d33999	2360	* @retval None
<>	149:156823d33999	2361	*/
<>	149:156823d33999	2362	static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2363	{
<>	149:156823d33999	2364	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2365	hspi->TxXferCount = 0;
<>	149:156823d33999	2366	hspi->RxXferCount = 0;
<>	149:156823d33999	2367	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2368	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<>	149:156823d33999	2369	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2370	}
<>	149:156823d33999	2371
<>	149:156823d33999	2372	/**
<>	149:156823d33999	2373	* @brief This function handles SPI Communication Timeout.
<>	149:156823d33999	2374	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	2375	* the configuration information for SPI module.
<>	149:156823d33999	2376	* @param Flag: SPI flag to check
<>	149:156823d33999	2377	* @param Status: Flag status to check: RESET or set
<>	149:156823d33999	2378	* @param Timeout: Timeout duration
<>	149:156823d33999	2379	* @retval HAL status
<>	149:156823d33999	2380	*/
<>	149:156823d33999	2381	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<>	149:156823d33999	2382	{
<>	149:156823d33999	2383	uint32_t tickstart = 0;
<>	149:156823d33999	2384
<>	149:156823d33999	2385	/* Get tick */
<>	149:156823d33999	2386	tickstart = HAL_GetTick();
<>	149:156823d33999	2387
<>	149:156823d33999	2388	/* Wait until flag is set */
<>	149:156823d33999	2389	if(Status == RESET)
<>	149:156823d33999	2390	{
<>	149:156823d33999	2391	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
<>	149:156823d33999	2392	{
<>	149:156823d33999	2393	if(Timeout != HAL_MAX_DELAY)
<>	149:156823d33999	2394	{
<>	149:156823d33999	2395	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	149:156823d33999	2396	{
<>	149:156823d33999	2397	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	149:156823d33999	2398	on both master and slave sides in order to resynchronize the master
<>	149:156823d33999	2399	and slave for their respective CRC calculation */
<>	149:156823d33999	2400
<>	149:156823d33999	2401	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	149:156823d33999	2402	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2403
<>	149:156823d33999	2404	/* Disable SPI peripheral */
<>	149:156823d33999	2405	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2406
<>	149:156823d33999	2407	/* Reset CRC Calculation */
<>	149:156823d33999	2408	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2409	{
<>	149:156823d33999	2410	SPI_RESET_CRC(hspi);
<>	149:156823d33999	2411	}
<>	149:156823d33999	2412
<>	149:156823d33999	2413	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2414
<>	149:156823d33999	2415	/* Process Unlocked */
<>	149:156823d33999	2416	__HAL_UNLOCK(hspi);
<>	149:156823d33999	2417
<>	149:156823d33999	2418	return HAL_TIMEOUT;
<>	149:156823d33999	2419	}
<>	149:156823d33999	2420	}
<>	149:156823d33999	2421	}
<>	149:156823d33999	2422	}
<>	149:156823d33999	2423	else
<>	149:156823d33999	2424	{
<>	149:156823d33999	2425	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
<>	149:156823d33999	2426	{
<>	149:156823d33999	2427	if(Timeout != HAL_MAX_DELAY)
<>	149:156823d33999	2428	{
<>	149:156823d33999	2429	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	149:156823d33999	2430	{
<>	149:156823d33999	2431	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	149:156823d33999	2432	on both master and slave sides in order to resynchronize the master
<>	149:156823d33999	2433	and slave for their respective CRC calculation */
<>	149:156823d33999	2434
<>	149:156823d33999	2435	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	149:156823d33999	2436	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2437
<>	149:156823d33999	2438	/* Disable SPI peripheral */
<>	149:156823d33999	2439	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2440
<>	149:156823d33999	2441	/* Reset CRC Calculation */
<>	149:156823d33999	2442	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2443	{
<>	149:156823d33999	2444	SPI_RESET_CRC(hspi);
<>	149:156823d33999	2445	}
<>	149:156823d33999	2446
<>	149:156823d33999	2447	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2448
<>	149:156823d33999	2449	/* Process Unlocked */
<>	149:156823d33999	2450	__HAL_UNLOCK(hspi);
<>	149:156823d33999	2451
<>	149:156823d33999	2452	return HAL_TIMEOUT;
<>	149:156823d33999	2453	}
<>	149:156823d33999	2454	}
<>	149:156823d33999	2455	}
<>	149:156823d33999	2456	}
<>	149:156823d33999	2457	return HAL_OK;
<>	149:156823d33999	2458	}
<>	149:156823d33999	2459	/**
<>	149:156823d33999	2460	* @}
<>	149:156823d33999	2461	*/
<>	149:156823d33999	2462
<>	153:fa9ff456f731	2463	/**
<>	153:fa9ff456f731	2464	* @brief Handle to check BSY flag before start a new transaction.
<>	153:fa9ff456f731	2465	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2466	* the configuration information for SPI module.
<>	153:fa9ff456f731	2467	* @param Timeout: Timeout duration
<>	153:fa9ff456f731	2468	* @param Tickstart: tick start value
<>	153:fa9ff456f731	2469	* @retval HAL status
<>	153:fa9ff456f731	2470	*/
<>	153:fa9ff456f731	2471	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<>	153:fa9ff456f731	2472	{
<>	153:fa9ff456f731	2473	/* Control the BSY flag */
<>	153:fa9ff456f731	2474	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<>	153:fa9ff456f731	2475	{
<>	153:fa9ff456f731	2476	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2477	return HAL_TIMEOUT;
<>	153:fa9ff456f731	2478	}
<>	153:fa9ff456f731	2479	return HAL_OK;
<>	153:fa9ff456f731	2480	}
<>	153:fa9ff456f731	2481
<>	153:fa9ff456f731	2482	/**
<>	153:fa9ff456f731	2483	* @brief Handle the end of the RXTX transaction.
<>	153:fa9ff456f731	2484	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2485	* the configuration information for SPI module.
<>	153:fa9ff456f731	2486	* @retval None
<>	153:fa9ff456f731	2487	*/
<>	153:fa9ff456f731	2488	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	2489	{
<>	153:fa9ff456f731	2490	uint32_t tickstart = 0U;
<>	153:fa9ff456f731	2491	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
<>	153:fa9ff456f731	2492	/* Init tickstart for timeout managment*/
<>	153:fa9ff456f731	2493	tickstart = HAL_GetTick();
<>	153:fa9ff456f731	2494
<>	153:fa9ff456f731	2495	/* Disable ERR interrupt */
<>	153:fa9ff456f731	2496	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<>	153:fa9ff456f731	2497
<>	153:fa9ff456f731	2498	/* Wait until TXE flag is set */
<>	153:fa9ff456f731	2499	do
<>	153:fa9ff456f731	2500	{
<>	153:fa9ff456f731	2501	if(count-- == 0)
<>	153:fa9ff456f731	2502	{
<>	153:fa9ff456f731	2503	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2504	break;
<>	153:fa9ff456f731	2505	}
<>	153:fa9ff456f731	2506	}
<>	153:fa9ff456f731	2507	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
<>	153:fa9ff456f731	2508
<>	153:fa9ff456f731	2509	/* Check the end of the transaction */
<>	153:fa9ff456f731	2510	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
<>	153:fa9ff456f731	2511	{
<>	153:fa9ff456f731	2512	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2513	}
<>	153:fa9ff456f731	2514
<>	153:fa9ff456f731	2515	/* Clear overrun flag in 2 Lines communication mode because received is not read */
<>	153:fa9ff456f731	2516	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	153:fa9ff456f731	2517	{
<>	153:fa9ff456f731	2518	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	153:fa9ff456f731	2519	}
<>	153:fa9ff456f731	2520
<>	153:fa9ff456f731	2521	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2522	/* Check if CRC error occurred */
<>	153:fa9ff456f731	2523	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	153:fa9ff456f731	2524	{
<>	153:fa9ff456f731	2525	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2526	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	153:fa9ff456f731	2527	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	153:fa9ff456f731	2528	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2529	}
<>	153:fa9ff456f731	2530	else
<>	153:fa9ff456f731	2531	{
<>	153:fa9ff456f731	2532	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2533	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	153:fa9ff456f731	2534	{
<>	153:fa9ff456f731	2535	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	153:fa9ff456f731	2536	{
<>	153:fa9ff456f731	2537	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2538	HAL_SPI_RxCpltCallback(hspi);
<>	153:fa9ff456f731	2539	}
<>	153:fa9ff456f731	2540	else
<>	153:fa9ff456f731	2541	{
<>	153:fa9ff456f731	2542	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2543	HAL_SPI_TxRxCpltCallback(hspi);
<>	153:fa9ff456f731	2544	}
<>	153:fa9ff456f731	2545	}
<>	153:fa9ff456f731	2546	else
<>	153:fa9ff456f731	2547	{
<>	153:fa9ff456f731	2548	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2549	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2550	}
<>	153:fa9ff456f731	2551	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2552	}
<>	153:fa9ff456f731	2553	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2554	}
<>	153:fa9ff456f731	2555
<>	153:fa9ff456f731	2556	/**
<>	153:fa9ff456f731	2557	* @brief Handle the end of the RX transaction.
<>	153:fa9ff456f731	2558	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2559	* the configuration information for SPI module.
<>	153:fa9ff456f731	2560	* @retval None
<>	153:fa9ff456f731	2561	*/
<>	153:fa9ff456f731	2562	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	2563	{
<>	153:fa9ff456f731	2564	/* Disable RXNE and ERR interrupt */
<>	153:fa9ff456f731	2565	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	2566
<>	153:fa9ff456f731	2567	/* Check the end of the transaction */
<>	153:fa9ff456f731	2568	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	153:fa9ff456f731	2569	{
<>	153:fa9ff456f731	2570	/* Disable SPI peripheral */
<>	153:fa9ff456f731	2571	__HAL_SPI_DISABLE(hspi);
<>	153:fa9ff456f731	2572	}
<>	153:fa9ff456f731	2573
<>	153:fa9ff456f731	2574	/* Clear overrun flag in 2 Lines communication mode because received is not read */
<>	153:fa9ff456f731	2575	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	153:fa9ff456f731	2576	{
<>	153:fa9ff456f731	2577	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	153:fa9ff456f731	2578	}
<>	153:fa9ff456f731	2579	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2580
<>	153:fa9ff456f731	2581	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2582	/* Check if CRC error occurred */
<>	153:fa9ff456f731	2583	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	153:fa9ff456f731	2584	{
<>	153:fa9ff456f731	2585	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	153:fa9ff456f731	2586	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	153:fa9ff456f731	2587	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2588	}
<>	153:fa9ff456f731	2589	else
<>	153:fa9ff456f731	2590	{
<>	153:fa9ff456f731	2591	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2592	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	153:fa9ff456f731	2593	{
<>	153:fa9ff456f731	2594	HAL_SPI_RxCpltCallback(hspi);
<>	153:fa9ff456f731	2595	}
<>	153:fa9ff456f731	2596	else
<>	153:fa9ff456f731	2597	{
<>	153:fa9ff456f731	2598	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2599	}
<>	153:fa9ff456f731	2600	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2601	}
<>	153:fa9ff456f731	2602	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2603	}
<>	153:fa9ff456f731	2604
<>	153:fa9ff456f731	2605	/**
<>	153:fa9ff456f731	2606	* @brief Handle the end of the TX transaction.
<>	153:fa9ff456f731	2607	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2608	* the configuration information for SPI module.
<>	153:fa9ff456f731	2609	* @retval None
<>	153:fa9ff456f731	2610	*/
<>	153:fa9ff456f731	2611	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	2612	{
<>	153:fa9ff456f731	2613	uint32_t tickstart = 0U;
<>	153:fa9ff456f731	2614	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
<>	153:fa9ff456f731	2615
<>	153:fa9ff456f731	2616	/* Init tickstart for timeout management*/
<>	153:fa9ff456f731	2617	tickstart = HAL_GetTick();
<>	153:fa9ff456f731	2618
<>	153:fa9ff456f731	2619	/* Wait until TXE flag is set */
<>	153:fa9ff456f731	2620	do
<>	153:fa9ff456f731	2621	{
<>	153:fa9ff456f731	2622	if(count-- == 0)
<>	153:fa9ff456f731	2623	{
<>	153:fa9ff456f731	2624	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2625	break;
<>	153:fa9ff456f731	2626	}
<>	153:fa9ff456f731	2627	}
<>	153:fa9ff456f731	2628	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
<>	153:fa9ff456f731	2629
<>	153:fa9ff456f731	2630	/* Disable TXE and ERR interrupt */
<>	153:fa9ff456f731	2631	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	153:fa9ff456f731	2632
<>	153:fa9ff456f731	2633	/* Check Busy flag */
<>	153:fa9ff456f731	2634	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	153:fa9ff456f731	2635	{
<>	153:fa9ff456f731	2636	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2637	}
<>	153:fa9ff456f731	2638
<>	153:fa9ff456f731	2639	/* Clear overrun flag in 2 Lines communication mode because received is not read */
<>	153:fa9ff456f731	2640	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	153:fa9ff456f731	2641	{
<>	153:fa9ff456f731	2642	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	153:fa9ff456f731	2643	}
<>	153:fa9ff456f731	2644
<>	153:fa9ff456f731	2645	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2646	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	153:fa9ff456f731	2647	{
<>	153:fa9ff456f731	2648	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2649	}
<>	153:fa9ff456f731	2650	else
<>	153:fa9ff456f731	2651	{
<>	153:fa9ff456f731	2652	HAL_SPI_TxCpltCallback(hspi);
<>	153:fa9ff456f731	2653	}
<>	153:fa9ff456f731	2654	}
<>	153:fa9ff456f731	2655
<>	153:fa9ff456f731	2656	/**
<>	153:fa9ff456f731	2657	* @}
<>	153:fa9ff456f731	2658	*/
<>	153:fa9ff456f731	2659
<>	153:fa9ff456f731	2660
<>	149:156823d33999	2661	#endif /* HAL_SPI_MODULE_ENABLED */
<>	149:156823d33999	2662	/**
<>	149:156823d33999	2663	* @}
<>	149:156823d33999	2664	*/
<>	149:156823d33999	2665
<>	149:156823d33999	2666	/**
<>	149:156823d33999	2667	* @}
<>	149:156823d33999	2668	*/
<>	149:156823d33999	2669
<>	149:156823d33999	2670	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/