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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_dma.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Header file of DMA HAL module.
<> 149:156823d33999 6 ******************************************************************************
<> 149:156823d33999 7 * @attention
<> 149:156823d33999 8 *
AnnaBridge 184:08ed48f1de7f 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 12 * are permitted provided that the following conditions are met:
<> 149:156823d33999 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 14 * this list of conditions and the following disclaimer.
<> 149:156823d33999 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 17 * and/or other materials provided with the distribution.
<> 149:156823d33999 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 19 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 20 * without specific prior written permission.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 32 *
<> 149:156823d33999 33 ******************************************************************************
<> 149:156823d33999 34 */
<> 149:156823d33999 35
<> 149:156823d33999 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 37 #ifndef __STM32L1xx_HAL_DMA_H
<> 149:156823d33999 38 #define __STM32L1xx_HAL_DMA_H
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifdef __cplusplus
<> 149:156823d33999 41 extern "C" {
<> 149:156823d33999 42 #endif
<> 149:156823d33999 43
<> 149:156823d33999 44 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 45 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 46
<> 149:156823d33999 47 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 48 * @{
<> 149:156823d33999 49 */
<> 149:156823d33999 50
<> 149:156823d33999 51 /** @addtogroup DMA
<> 149:156823d33999 52 * @{
<> 149:156823d33999 53 */
<> 149:156823d33999 54
<> 149:156823d33999 55 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 56
<> 149:156823d33999 57 /** @defgroup DMA_Exported_Types DMA Exported Types
<> 149:156823d33999 58 * @{
<> 149:156823d33999 59 */
<> 149:156823d33999 60
<> 149:156823d33999 61 /**
<> 149:156823d33999 62 * @brief DMA Configuration Structure definition
<> 149:156823d33999 63 */
<> 149:156823d33999 64 typedef struct
<> 149:156823d33999 65 {
<> 149:156823d33999 66 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 149:156823d33999 67 from memory to memory or from peripheral to memory.
<> 149:156823d33999 68 This parameter can be a value of @ref DMA_Data_transfer_direction */
<> 149:156823d33999 69
<> 149:156823d33999 70 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<> 149:156823d33999 71 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
<> 149:156823d33999 72
<> 149:156823d33999 73 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<> 149:156823d33999 74 This parameter can be a value of @ref DMA_Memory_incremented_mode */
<> 149:156823d33999 75
<> 149:156823d33999 76 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<> 149:156823d33999 77 This parameter can be a value of @ref DMA_Peripheral_data_size */
<> 149:156823d33999 78
<> 149:156823d33999 79 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<> 149:156823d33999 80 This parameter can be a value of @ref DMA_Memory_data_size */
<> 149:156823d33999 81
<> 149:156823d33999 82 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
<> 149:156823d33999 83 This parameter can be a value of @ref DMA_mode
<> 149:156823d33999 84 @note The circular buffer mode cannot be used if the memory-to-memory
<> 149:156823d33999 85 data transfer is configured on the selected Channel */
<> 149:156823d33999 86
<> 149:156823d33999 87 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
<> 149:156823d33999 88 This parameter can be a value of @ref DMA_Priority_level */
<> 149:156823d33999 89 } DMA_InitTypeDef;
<> 149:156823d33999 90
<> 149:156823d33999 91 /**
<> 149:156823d33999 92 * @brief HAL DMA State structures definition
<> 149:156823d33999 93 */
<> 149:156823d33999 94 typedef enum
<> 149:156823d33999 95 {
<> 149:156823d33999 96 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
<> 149:156823d33999 97 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
<> 149:156823d33999 98 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
<> 149:156823d33999 99 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
<> 149:156823d33999 100 }HAL_DMA_StateTypeDef;
<> 149:156823d33999 101
<> 149:156823d33999 102 /**
<> 149:156823d33999 103 * @brief HAL DMA Error Code structure definition
<> 149:156823d33999 104 */
<> 149:156823d33999 105 typedef enum
<> 149:156823d33999 106 {
<> 149:156823d33999 107 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
<> 149:156823d33999 108 HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
<> 149:156823d33999 109 }HAL_DMA_LevelCompleteTypeDef;
<> 149:156823d33999 110
<> 149:156823d33999 111
<> 149:156823d33999 112 /**
<> 149:156823d33999 113 * @brief HAL DMA Callback ID structure definition
<> 149:156823d33999 114 */
<> 149:156823d33999 115 typedef enum
<> 149:156823d33999 116 {
<> 149:156823d33999 117 HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
<> 149:156823d33999 118 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
<> 149:156823d33999 119 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
<> 149:156823d33999 120 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
<> 149:156823d33999 121 HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
<> 149:156823d33999 122
<> 149:156823d33999 123 }HAL_DMA_CallbackIDTypeDef;
<> 149:156823d33999 124
<> 149:156823d33999 125 /**
<> 149:156823d33999 126 * @brief DMA handle Structure definition
<> 149:156823d33999 127 */
<> 149:156823d33999 128 typedef struct __DMA_HandleTypeDef
<> 149:156823d33999 129 {
<> 149:156823d33999 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
<> 149:156823d33999 131
<> 149:156823d33999 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
<> 149:156823d33999 133
<> 149:156823d33999 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
<> 149:156823d33999 135
<> 149:156823d33999 136 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
<> 149:156823d33999 137
<> 149:156823d33999 138 void *Parent; /*!< Parent object state */
<> 149:156823d33999 139
<> 149:156823d33999 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
<> 149:156823d33999 141
<> 149:156823d33999 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
<> 149:156823d33999 143
<> 149:156823d33999 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
<> 149:156823d33999 145
<> 149:156823d33999 146 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
<> 149:156823d33999 147
<> 149:156823d33999 148 __IO uint32_t ErrorCode; /*!< DMA Error code */
<> 149:156823d33999 149
<> 149:156823d33999 150 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
<> 149:156823d33999 151
<> 149:156823d33999 152 uint32_t ChannelIndex; /*!< DMA Channel Index */
<> 149:156823d33999 153
<> 149:156823d33999 154 } DMA_HandleTypeDef;
<> 149:156823d33999 155 /**
<> 149:156823d33999 156 * @}
<> 149:156823d33999 157 */
<> 149:156823d33999 158
<> 149:156823d33999 159 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 160
<> 149:156823d33999 161 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 149:156823d33999 162 * @{
<> 149:156823d33999 163 */
<> 149:156823d33999 164
<> 149:156823d33999 165 /** @defgroup DMA_Error_Code DMA Error Code
<> 149:156823d33999 166 * @{
<> 149:156823d33999 167 */
AnnaBridge 184:08ed48f1de7f 168 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
AnnaBridge 184:08ed48f1de7f 169 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
AnnaBridge 184:08ed48f1de7f 170 #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoing transfer */
AnnaBridge 184:08ed48f1de7f 171 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
AnnaBridge 184:08ed48f1de7f 172 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
<> 149:156823d33999 173 /**
<> 149:156823d33999 174 * @}
<> 149:156823d33999 175 */
<> 149:156823d33999 176
<> 149:156823d33999 177 /** @defgroup DMA_request DMA request
<> 149:156823d33999 178 * @{
<> 149:156823d33999 179 */
AnnaBridge 184:08ed48f1de7f 180 #define DMA_REQUEST_0 (0x00000000U)
AnnaBridge 184:08ed48f1de7f 181 #define DMA_REQUEST_1 (0x00000001U)
AnnaBridge 184:08ed48f1de7f 182 #define DMA_REQUEST_2 (0x00000002U)
AnnaBridge 184:08ed48f1de7f 183 #define DMA_REQUEST_3 (0x00000003U)
AnnaBridge 184:08ed48f1de7f 184 #define DMA_REQUEST_4 (0x00000004U)
AnnaBridge 184:08ed48f1de7f 185 #define DMA_REQUEST_5 (0x00000005U)
AnnaBridge 184:08ed48f1de7f 186 #define DMA_REQUEST_6 (0x00000006U)
AnnaBridge 184:08ed48f1de7f 187 #define DMA_REQUEST_7 (0x00000007U)
<> 149:156823d33999 188
<> 149:156823d33999 189 /**
<> 149:156823d33999 190 * @}
<> 149:156823d33999 191 */
<> 149:156823d33999 192
<> 149:156823d33999 193 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
<> 149:156823d33999 194 * @{
<> 149:156823d33999 195 */
AnnaBridge 184:08ed48f1de7f 196 #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
<> 149:156823d33999 197 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
<> 149:156823d33999 198 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
<> 149:156823d33999 199
<> 149:156823d33999 200 /**
<> 149:156823d33999 201 * @}
<> 149:156823d33999 202 */
<> 149:156823d33999 203
<> 149:156823d33999 204 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
<> 149:156823d33999 205 * @{
<> 149:156823d33999 206 */
<> 149:156823d33999 207 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
AnnaBridge 184:08ed48f1de7f 208 #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
<> 149:156823d33999 209 /**
<> 149:156823d33999 210 * @}
<> 149:156823d33999 211 */
<> 149:156823d33999 212
<> 149:156823d33999 213 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
<> 149:156823d33999 214 * @{
<> 149:156823d33999 215 */
<> 149:156823d33999 216 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
AnnaBridge 184:08ed48f1de7f 217 #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
<> 149:156823d33999 218 /**
<> 149:156823d33999 219 * @}
<> 149:156823d33999 220 */
<> 149:156823d33999 221
<> 149:156823d33999 222 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
<> 149:156823d33999 223 * @{
<> 149:156823d33999 224 */
AnnaBridge 184:08ed48f1de7f 225 #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment: Byte */
<> 149:156823d33999 226 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
<> 149:156823d33999 227 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
<> 149:156823d33999 228 /**
<> 149:156823d33999 229 * @}
<> 149:156823d33999 230 */
<> 149:156823d33999 231
<> 149:156823d33999 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
<> 149:156823d33999 233 * @{
<> 149:156823d33999 234 */
AnnaBridge 184:08ed48f1de7f 235 #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment: Byte */
<> 149:156823d33999 236 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
<> 149:156823d33999 237 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
<> 149:156823d33999 238 /**
<> 149:156823d33999 239 * @}
<> 149:156823d33999 240 */
<> 149:156823d33999 241
<> 149:156823d33999 242 /** @defgroup DMA_mode DMA mode
<> 149:156823d33999 243 * @{
<> 149:156823d33999 244 */
AnnaBridge 184:08ed48f1de7f 245 #define DMA_NORMAL (0x00000000U) /*!< Normal mode */
<> 149:156823d33999 246 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
<> 149:156823d33999 247 /**
<> 149:156823d33999 248 * @}
<> 149:156823d33999 249 */
<> 149:156823d33999 250
<> 149:156823d33999 251 /** @defgroup DMA_Priority_level DMA Priority level
<> 149:156823d33999 252 * @{
<> 149:156823d33999 253 */
AnnaBridge 184:08ed48f1de7f 254 #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
<> 149:156823d33999 255 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
<> 149:156823d33999 256 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
<> 149:156823d33999 257 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
<> 149:156823d33999 258 /**
<> 149:156823d33999 259 * @}
<> 149:156823d33999 260 */
<> 149:156823d33999 261
<> 149:156823d33999 262
<> 149:156823d33999 263 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
<> 149:156823d33999 264 * @{
<> 149:156823d33999 265 */
<> 149:156823d33999 266 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
<> 149:156823d33999 267 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
<> 149:156823d33999 268 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
<> 149:156823d33999 269 /**
<> 149:156823d33999 270 * @}
<> 149:156823d33999 271 */
<> 149:156823d33999 272
<> 149:156823d33999 273 /** @defgroup DMA_flag_definitions DMA flag definitions
<> 149:156823d33999 274 * @{
<> 149:156823d33999 275 */
AnnaBridge 184:08ed48f1de7f 276 #define DMA_FLAG_GL1 (0x00000001U)
AnnaBridge 184:08ed48f1de7f 277 #define DMA_FLAG_TC1 (0x00000002U)
AnnaBridge 184:08ed48f1de7f 278 #define DMA_FLAG_HT1 (0x00000004U)
AnnaBridge 184:08ed48f1de7f 279 #define DMA_FLAG_TE1 (0x00000008U)
AnnaBridge 184:08ed48f1de7f 280 #define DMA_FLAG_GL2 (0x00000010U)
AnnaBridge 184:08ed48f1de7f 281 #define DMA_FLAG_TC2 (0x00000020U)
AnnaBridge 184:08ed48f1de7f 282 #define DMA_FLAG_HT2 (0x00000040U)
AnnaBridge 184:08ed48f1de7f 283 #define DMA_FLAG_TE2 (0x00000080U)
AnnaBridge 184:08ed48f1de7f 284 #define DMA_FLAG_GL3 (0x00000100U)
AnnaBridge 184:08ed48f1de7f 285 #define DMA_FLAG_TC3 (0x00000200U)
AnnaBridge 184:08ed48f1de7f 286 #define DMA_FLAG_HT3 (0x00000400U)
AnnaBridge 184:08ed48f1de7f 287 #define DMA_FLAG_TE3 (0x00000800U)
AnnaBridge 184:08ed48f1de7f 288 #define DMA_FLAG_GL4 (0x00001000U)
AnnaBridge 184:08ed48f1de7f 289 #define DMA_FLAG_TC4 (0x00002000U)
AnnaBridge 184:08ed48f1de7f 290 #define DMA_FLAG_HT4 (0x00004000U)
AnnaBridge 184:08ed48f1de7f 291 #define DMA_FLAG_TE4 (0x00008000U)
AnnaBridge 184:08ed48f1de7f 292 #define DMA_FLAG_GL5 (0x00010000U)
AnnaBridge 184:08ed48f1de7f 293 #define DMA_FLAG_TC5 (0x00020000U)
AnnaBridge 184:08ed48f1de7f 294 #define DMA_FLAG_HT5 (0x00040000U)
AnnaBridge 184:08ed48f1de7f 295 #define DMA_FLAG_TE5 (0x00080000U)
AnnaBridge 184:08ed48f1de7f 296 #define DMA_FLAG_GL6 (0x00100000U)
AnnaBridge 184:08ed48f1de7f 297 #define DMA_FLAG_TC6 (0x00200000U)
AnnaBridge 184:08ed48f1de7f 298 #define DMA_FLAG_HT6 (0x00400000U)
AnnaBridge 184:08ed48f1de7f 299 #define DMA_FLAG_TE6 (0x00800000U)
AnnaBridge 184:08ed48f1de7f 300 #define DMA_FLAG_GL7 (0x01000000U)
AnnaBridge 184:08ed48f1de7f 301 #define DMA_FLAG_TC7 (0x02000000U)
AnnaBridge 184:08ed48f1de7f 302 #define DMA_FLAG_HT7 (0x04000000U)
AnnaBridge 184:08ed48f1de7f 303 #define DMA_FLAG_TE7 (0x08000000U)
<> 149:156823d33999 304 /**
<> 149:156823d33999 305 * @}
<> 149:156823d33999 306 */
<> 149:156823d33999 307
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @}
<> 149:156823d33999 310 */
<> 149:156823d33999 311
<> 149:156823d33999 312 /* Exported macros -----------------------------------------------------------*/
<> 149:156823d33999 313 /** @defgroup DMA_Exported_Macros DMA Exported Macros
<> 149:156823d33999 314 * @{
<> 149:156823d33999 315 */
<> 149:156823d33999 316
<> 149:156823d33999 317 /** @brief Reset DMA handle state
<> 149:156823d33999 318 * @param __HANDLE__: DMA handle
<> 149:156823d33999 319 * @retval None
<> 149:156823d33999 320 */
<> 149:156823d33999 321 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<> 149:156823d33999 322
<> 149:156823d33999 323 /**
<> 149:156823d33999 324 * @brief Enable the specified DMA Channel.
<> 149:156823d33999 325 * @param __HANDLE__: DMA handle
<> 149:156823d33999 326 * @retval None
<> 149:156823d33999 327 */
<> 149:156823d33999 328 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
<> 149:156823d33999 329
<> 149:156823d33999 330 /**
<> 149:156823d33999 331 * @brief Disable the specified DMA Channel.
<> 149:156823d33999 332 * @param __HANDLE__: DMA handle
<> 149:156823d33999 333 * @retval None
<> 149:156823d33999 334 */
<> 149:156823d33999 335 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
<> 149:156823d33999 336
<> 149:156823d33999 337
<> 149:156823d33999 338 /* Interrupt & Flag management */
<> 149:156823d33999 339 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
<> 149:156823d33999 340 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
<> 149:156823d33999 341 defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 342
<> 149:156823d33999 343 /**
<> 149:156823d33999 344 * @brief Return the current DMA Channel transfer complete flag.
<> 149:156823d33999 345 * @param __HANDLE__: DMA handle
<> 149:156823d33999 346 * @retval The specified transfer complete flag index.
<> 149:156823d33999 347 */
<> 149:156823d33999 348
<> 149:156823d33999 349 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 149:156823d33999 350 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 149:156823d33999 351 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
<> 149:156823d33999 352 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 149:156823d33999 353 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
<> 149:156823d33999 354 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 149:156823d33999 355 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
<> 149:156823d33999 356 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 149:156823d33999 357 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
<> 149:156823d33999 358 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<> 149:156823d33999 359 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
<> 149:156823d33999 360 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<> 149:156823d33999 361 DMA_FLAG_TC7)
<> 149:156823d33999 362
<> 149:156823d33999 363 /**
<> 149:156823d33999 364 * @brief Return the current DMA Channel half transfer complete flag.
<> 149:156823d33999 365 * @param __HANDLE__: DMA handle
<> 149:156823d33999 366 * @retval The specified half transfer complete flag index.
<> 149:156823d33999 367 */
<> 149:156823d33999 368 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 149:156823d33999 369 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 149:156823d33999 370 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
<> 149:156823d33999 371 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 149:156823d33999 372 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
<> 149:156823d33999 373 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 149:156823d33999 374 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
<> 149:156823d33999 375 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 149:156823d33999 376 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
<> 149:156823d33999 377 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<> 149:156823d33999 378 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
<> 149:156823d33999 379 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<> 149:156823d33999 380 DMA_FLAG_HT7)
<> 149:156823d33999 381
<> 149:156823d33999 382 /**
<> 149:156823d33999 383 * @brief Return the current DMA Channel transfer error flag.
<> 149:156823d33999 384 * @param __HANDLE__: DMA handle
<> 149:156823d33999 385 * @retval The specified transfer error flag index.
<> 149:156823d33999 386 */
<> 149:156823d33999 387 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 149:156823d33999 388 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 149:156823d33999 389 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
<> 149:156823d33999 390 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 149:156823d33999 391 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
<> 149:156823d33999 392 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 149:156823d33999 393 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
<> 149:156823d33999 394 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 149:156823d33999 395 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
<> 149:156823d33999 396 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<> 149:156823d33999 397 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
<> 149:156823d33999 398 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<> 149:156823d33999 399 DMA_FLAG_TE7)
<> 149:156823d33999 400
<> 149:156823d33999 401 /**
<> 149:156823d33999 402 * @brief Return the current DMA Channel Global interrupt flag.
<> 149:156823d33999 403 * @param __HANDLE__: DMA handle
<> 149:156823d33999 404 * @retval The specified transfer error flag index.
<> 149:156823d33999 405 */
<> 149:156823d33999 406 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 149:156823d33999 407 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
<> 149:156823d33999 408 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
<> 149:156823d33999 409 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
<> 149:156823d33999 410 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
<> 149:156823d33999 411 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
<> 149:156823d33999 412 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
<> 149:156823d33999 413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
<> 149:156823d33999 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
<> 149:156823d33999 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
<> 149:156823d33999 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
<> 149:156823d33999 417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
<> 149:156823d33999 418 DMA_ISR_GIF7)
<> 149:156823d33999 419
<> 149:156823d33999 420 /**
<> 149:156823d33999 421 * @brief Get the DMA Channel pending flags.
<> 149:156823d33999 422 * @param __HANDLE__: DMA handle
<> 149:156823d33999 423 * @param __FLAG__: Get the specified flag.
<> 149:156823d33999 424 * This parameter can be any combination of the following values:
<> 149:156823d33999 425 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 149:156823d33999 426 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 149:156823d33999 427 * @arg DMA_FLAG_TEx: Transfer error flag
<> 149:156823d33999 428 * @arg DMA_FLAG_GLx: Global interrupt flag
<> 149:156823d33999 429 * Where x can be from 1 to 7 to select the DMA Channel x flag.
<> 149:156823d33999 430 * @retval The state of FLAG (SET or RESET).
<> 149:156823d33999 431 */
<> 149:156823d33999 432 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
<> 149:156823d33999 433 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
<> 149:156823d33999 434
<> 149:156823d33999 435 /**
<> 149:156823d33999 436 * @brief Clear the DMA Channel pending flags.
<> 149:156823d33999 437 * @param __HANDLE__: DMA handle
<> 149:156823d33999 438 * @param __FLAG__: specifies the flag to clear.
<> 149:156823d33999 439 * This parameter can be any combination of the following values:
<> 149:156823d33999 440 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 149:156823d33999 441 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 149:156823d33999 442 * @arg DMA_FLAG_TEx: Transfer error flag
<> 149:156823d33999 443 * @arg DMA_FLAG_GLx: Global interrupt flag
<> 149:156823d33999 444 * Where x can be from 1 to 7 to select the DMA Channel x flag.
<> 149:156823d33999 445 * @retval None
<> 149:156823d33999 446 */
<> 149:156823d33999 447 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
<> 149:156823d33999 448 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
<> 149:156823d33999 449
<> 149:156823d33999 450 #else
<> 149:156823d33999 451 /**
<> 149:156823d33999 452 * @brief Return the current DMA Channel transfer complete flag.
<> 149:156823d33999 453 * @param __HANDLE__: DMA handle
<> 149:156823d33999 454 * @retval The specified transfer complete flag index.
<> 149:156823d33999 455 */
<> 149:156823d33999 456
<> 149:156823d33999 457 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 149:156823d33999 458 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 149:156823d33999 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 149:156823d33999 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 149:156823d33999 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 149:156823d33999 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<> 149:156823d33999 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<> 149:156823d33999 464 DMA_FLAG_TC7)
<> 149:156823d33999 465
<> 149:156823d33999 466 /**
<> 149:156823d33999 467 * @brief Return the current DMA Channel half transfer complete flag.
<> 149:156823d33999 468 * @param __HANDLE__: DMA handle
<> 149:156823d33999 469 * @retval The specified half transfer complete flag index.
<> 149:156823d33999 470 */
<> 149:156823d33999 471 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 149:156823d33999 472 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 149:156823d33999 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 149:156823d33999 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 149:156823d33999 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 149:156823d33999 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<> 149:156823d33999 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<> 149:156823d33999 478 DMA_FLAG_HT7)
<> 149:156823d33999 479
<> 149:156823d33999 480 /**
<> 149:156823d33999 481 * @brief Return the current DMA Channel transfer error flag.
<> 149:156823d33999 482 * @param __HANDLE__: DMA handle
<> 149:156823d33999 483 * @retval The specified transfer error flag index.
<> 149:156823d33999 484 */
<> 149:156823d33999 485 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 149:156823d33999 486 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 149:156823d33999 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 149:156823d33999 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 149:156823d33999 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 149:156823d33999 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<> 149:156823d33999 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<> 149:156823d33999 492 DMA_FLAG_TE7)
<> 149:156823d33999 493
<> 149:156823d33999 494 /**
<> 149:156823d33999 495 * @brief Return the current DMA Channel Global interrupt flag.
<> 149:156823d33999 496 * @param __HANDLE__: DMA handle
<> 149:156823d33999 497 * @retval The specified transfer error flag index.
<> 149:156823d33999 498 */
<> 149:156823d33999 499 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 149:156823d33999 500 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
<> 149:156823d33999 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
<> 149:156823d33999 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
<> 149:156823d33999 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
<> 149:156823d33999 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
<> 149:156823d33999 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
<> 149:156823d33999 506 DMA_ISR_GIF7)
<> 149:156823d33999 507
<> 149:156823d33999 508 /**
<> 149:156823d33999 509 * @brief Get the DMA Channel pending flags.
<> 149:156823d33999 510 * @param __HANDLE__: DMA handle
<> 149:156823d33999 511 * @param __FLAG__: Get the specified flag.
<> 149:156823d33999 512 * This parameter can be any combination of the following values:
<> 149:156823d33999 513 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 149:156823d33999 514 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 149:156823d33999 515 * @arg DMA_FLAG_TEx: Transfer error flag
<> 149:156823d33999 516 * @arg DMA_FLAG_GLx: Global interrupt flag
<> 149:156823d33999 517 * Where x can be from 1 to 7 to select the DMA Channel x flag.
<> 149:156823d33999 518 * @retval The state of FLAG (SET or RESET).
<> 149:156823d33999 519 */
<> 149:156823d33999 520 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
<> 149:156823d33999 521
<> 149:156823d33999 522 /**
<> 149:156823d33999 523 * @brief Clear the DMA Channel pending flags.
<> 149:156823d33999 524 * @param __HANDLE__: DMA handle
<> 149:156823d33999 525 * @param __FLAG__: specifies the flag to clear.
<> 149:156823d33999 526 * This parameter can be any combination of the following values:
<> 149:156823d33999 527 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 149:156823d33999 528 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 149:156823d33999 529 * @arg DMA_FLAG_TEx: Transfer error flag
<> 149:156823d33999 530 * @arg DMA_FLAG_GLx: Global interrupt flag
<> 149:156823d33999 531 * Where x can be from 1 to 7 to select the DMA Channel x flag.
<> 149:156823d33999 532 * @retval None
<> 149:156823d33999 533 */
<> 149:156823d33999 534 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
<> 149:156823d33999 535
<> 149:156823d33999 536 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 537
<> 149:156823d33999 538 /**
<> 149:156823d33999 539 * @brief Enable the specified DMA Channel interrupts.
<> 149:156823d33999 540 * @param __HANDLE__: DMA handle
<> 149:156823d33999 541 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 149:156823d33999 542 * This parameter can be any combination of the following values:
<> 149:156823d33999 543 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 149:156823d33999 544 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 149:156823d33999 545 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 149:156823d33999 546 * @retval None
<> 149:156823d33999 547 */
<> 149:156823d33999 548 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
<> 149:156823d33999 549
<> 149:156823d33999 550 /**
<> 149:156823d33999 551 * @brief Disable the specified DMA Channel interrupts.
<> 149:156823d33999 552 * @param __HANDLE__: DMA handle
<> 149:156823d33999 553 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 149:156823d33999 554 * This parameter can be any combination of the following values:
<> 149:156823d33999 555 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 149:156823d33999 556 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 149:156823d33999 557 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 149:156823d33999 558 * @retval None
<> 149:156823d33999 559 */
<> 149:156823d33999 560 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
<> 149:156823d33999 561
<> 149:156823d33999 562 /**
<> 149:156823d33999 563 * @brief Check whether the specified DMA Channel interrupt is enabled or not.
<> 149:156823d33999 564 * @param __HANDLE__: DMA handle
<> 149:156823d33999 565 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
<> 149:156823d33999 566 * This parameter can be one of the following values:
<> 149:156823d33999 567 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 149:156823d33999 568 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 149:156823d33999 569 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 149:156823d33999 570 * @retval The state of DMA_IT (SET or RESET).
<> 149:156823d33999 571 */
<> 149:156823d33999 572 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
<> 149:156823d33999 573
<> 149:156823d33999 574 /**
<> 149:156823d33999 575 * @brief Return the number of remaining data units in the current DMA Channel transfer.
<> 149:156823d33999 576 * @param __HANDLE__: DMA handle
<> 149:156823d33999 577 * @retval The number of remaining data units in the current DMA Channel transfer.
<> 149:156823d33999 578 */
<> 149:156823d33999 579 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
<> 149:156823d33999 580
<> 149:156823d33999 581 /**
<> 149:156823d33999 582 * @}
<> 149:156823d33999 583 */
<> 149:156823d33999 584
<> 149:156823d33999 585 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 586
<> 149:156823d33999 587 /** @addtogroup DMA_Exported_Functions
<> 149:156823d33999 588 * @{
<> 149:156823d33999 589 */
<> 149:156823d33999 590
<> 149:156823d33999 591 /** @addtogroup DMA_Exported_Functions_Group1
<> 149:156823d33999 592 * @{
<> 149:156823d33999 593 */
<> 149:156823d33999 594 /* Initialization and de-initialization functions *****************************/
<> 149:156823d33999 595 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 596 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
<> 149:156823d33999 597 /**
<> 149:156823d33999 598 * @}
<> 149:156823d33999 599 */
<> 149:156823d33999 600
<> 149:156823d33999 601 /** @addtogroup DMA_Exported_Functions_Group2
<> 149:156823d33999 602 * @{
<> 149:156823d33999 603 */
<> 149:156823d33999 604 /* IO operation functions *****************************************************/
<> 149:156823d33999 605 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 149:156823d33999 606 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 149:156823d33999 607 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 608 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 609 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
<> 149:156823d33999 610 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 611 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
<> 149:156823d33999 612 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
<> 149:156823d33999 613
<> 149:156823d33999 614 /**
<> 149:156823d33999 615 * @}
<> 149:156823d33999 616 */
<> 149:156823d33999 617
<> 149:156823d33999 618 /** @addtogroup DMA_Exported_Functions_Group3
<> 149:156823d33999 619 * @{
<> 149:156823d33999 620 */
<> 149:156823d33999 621 /* Peripheral State and Error functions ***************************************/
<> 149:156823d33999 622 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 623 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 624 /**
<> 149:156823d33999 625 * @}
<> 149:156823d33999 626 */
<> 149:156823d33999 627
<> 149:156823d33999 628 /**
<> 149:156823d33999 629 * @}
<> 149:156823d33999 630 */
<> 149:156823d33999 631
<> 149:156823d33999 632 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 633 /** @defgroup DMA_Private_Macros DMA Private Macros
<> 149:156823d33999 634 * @{
<> 149:156823d33999 635 */
<> 149:156823d33999 636
<> 149:156823d33999 637 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
<> 149:156823d33999 638 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
<> 149:156823d33999 639 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
<> 149:156823d33999 640
<> 149:156823d33999 641 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
<> 149:156823d33999 642
<> 149:156823d33999 643 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
<> 149:156823d33999 644 ((STATE) == DMA_PINC_DISABLE))
<> 149:156823d33999 645
<> 149:156823d33999 646 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
<> 149:156823d33999 647 ((STATE) == DMA_MINC_DISABLE))
<> 149:156823d33999 648
<> 149:156823d33999 649 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
<> 149:156823d33999 650 ((REQUEST) == DMA_REQUEST_1) || \
<> 149:156823d33999 651 ((REQUEST) == DMA_REQUEST_2) || \
<> 149:156823d33999 652 ((REQUEST) == DMA_REQUEST_3) || \
<> 149:156823d33999 653 ((REQUEST) == DMA_REQUEST_4) || \
<> 149:156823d33999 654 ((REQUEST) == DMA_REQUEST_5) || \
<> 149:156823d33999 655 ((REQUEST) == DMA_REQUEST_6) || \
<> 149:156823d33999 656 ((REQUEST) == DMA_REQUEST_7))
<> 149:156823d33999 657 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
<> 149:156823d33999 658 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
<> 149:156823d33999 659 ((SIZE) == DMA_PDATAALIGN_WORD))
<> 149:156823d33999 660
<> 149:156823d33999 661 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
<> 149:156823d33999 662 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
<> 149:156823d33999 663 ((SIZE) == DMA_MDATAALIGN_WORD ))
<> 149:156823d33999 664
<> 149:156823d33999 665 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
<> 149:156823d33999 666 ((MODE) == DMA_CIRCULAR))
<> 149:156823d33999 667
<> 149:156823d33999 668 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
<> 149:156823d33999 669 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
<> 149:156823d33999 670 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
<> 149:156823d33999 671 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<> 149:156823d33999 672
<> 149:156823d33999 673 /**
<> 149:156823d33999 674 * @}
<> 149:156823d33999 675 */
<> 149:156823d33999 676
<> 149:156823d33999 677 /* Private functions ---------------------------------------------------------*/
<> 149:156823d33999 678
<> 149:156823d33999 679 /**
<> 149:156823d33999 680 * @}
<> 149:156823d33999 681 */
<> 149:156823d33999 682
<> 149:156823d33999 683 /**
<> 149:156823d33999 684 * @}
<> 149:156823d33999 685 */
<> 149:156823d33999 686
<> 149:156823d33999 687 #ifdef __cplusplus
<> 149:156823d33999 688 }
<> 149:156823d33999 689 #endif
<> 149:156823d33999 690
<> 149:156823d33999 691 #endif /* __STM32L1xx_HAL_DMA_H */
<> 149:156823d33999 692
<> 149:156823d33999 693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/