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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_adc_ex.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Header file of ADC HAL Extension module.
<> 149:156823d33999 6 ******************************************************************************
<> 149:156823d33999 7 * @attention
<> 149:156823d33999 8 *
AnnaBridge 184:08ed48f1de7f 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 12 * are permitted provided that the following conditions are met:
<> 149:156823d33999 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 14 * this list of conditions and the following disclaimer.
<> 149:156823d33999 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 17 * and/or other materials provided with the distribution.
<> 149:156823d33999 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 19 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 20 * without specific prior written permission.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 32 *
<> 149:156823d33999 33 ******************************************************************************
<> 149:156823d33999 34 */
<> 149:156823d33999 35
<> 149:156823d33999 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 37 #ifndef __STM32L1xx_HAL_ADC_EX_H
<> 149:156823d33999 38 #define __STM32L1xx_HAL_ADC_EX_H
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifdef __cplusplus
<> 149:156823d33999 41 extern "C" {
<> 149:156823d33999 42 #endif
<> 149:156823d33999 43
<> 149:156823d33999 44 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 45 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 46
<> 149:156823d33999 47 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 48 * @{
<> 149:156823d33999 49 */
<> 149:156823d33999 50
<> 149:156823d33999 51 /** @addtogroup ADCEx
<> 149:156823d33999 52 * @{
<> 149:156823d33999 53 */
<> 149:156823d33999 54
<> 149:156823d33999 55 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 56 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types
<> 149:156823d33999 57 * @{
<> 149:156823d33999 58 */
<> 149:156823d33999 59
<> 149:156823d33999 60 /**
<> 149:156823d33999 61 * @brief ADC Configuration injected Channel structure definition
<> 149:156823d33999 62 * @note Parameters of this structure are shared within 2 scopes:
<> 149:156823d33999 63 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
<> 149:156823d33999 64 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
<> 149:156823d33999 65 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
<> 149:156823d33999 66 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
<> 149:156823d33999 67 * ADC state can be either:
<> 149:156823d33999 68 * - For all parameters: ADC disabled
<> 149:156823d33999 69 * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
<> 149:156823d33999 70 * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
<> 149:156823d33999 71 */
<> 149:156823d33999 72 typedef struct
<> 149:156823d33999 73 {
<> 149:156823d33999 74 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
<> 149:156823d33999 75 This parameter can be a value of @ref ADC_channels
<> 149:156823d33999 76 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
<> 149:156823d33999 77 uint32_t InjectedRank; /*!< Rank in the injected group sequencer
<> 149:156823d33999 78 This parameter must be a value of @ref ADCEx_injected_rank
<> 149:156823d33999 79 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<> 149:156823d33999 80 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 149:156823d33999 81 Unit: ADC clock cycles
<> 149:156823d33999 82 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
<> 149:156823d33999 83 This parameter can be a value of @ref ADC_sampling_times
<> 149:156823d33999 84 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<> 149:156823d33999 85 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<> 149:156823d33999 86 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<> 149:156823d33999 87 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 149:156823d33999 88 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
<> 149:156823d33999 89 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
<> 149:156823d33999 90 Offset value must be a positive number.
<> 149:156823d33999 91 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
<> 149:156823d33999 92 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<> 149:156823d33999 93 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
<> 149:156823d33999 94 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 149:156823d33999 95 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
<> 149:156823d33999 96 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 149:156823d33999 97 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 149:156823d33999 98 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 149:156823d33999 99 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 149:156823d33999 100 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 149:156823d33999 101 This parameter can be set to ENABLE or DISABLE.
<> 149:156823d33999 102 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
<> 149:156823d33999 103 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 149:156823d33999 104 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 149:156823d33999 105 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
<> 149:156823d33999 106 This parameter can be set to ENABLE or DISABLE.
<> 149:156823d33999 107 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
<> 149:156823d33999 108 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
<> 149:156823d33999 109 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
<> 149:156823d33999 110 To maintain JAUTO always enabled, DMA must be configured in circular mode.
<> 149:156823d33999 111 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 149:156823d33999 112 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 149:156823d33999 113 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
<> 149:156823d33999 114 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
<> 149:156823d33999 115 If set to external trigger source, triggering is on event rising edge.
<> 149:156823d33999 116 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
<> 149:156823d33999 117 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<> 149:156823d33999 118 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
<> 149:156823d33999 119 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 149:156823d33999 120 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 149:156823d33999 121 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
<> 149:156823d33999 122 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
<> 149:156823d33999 123 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
<> 149:156823d33999 124 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 149:156823d33999 125 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 149:156823d33999 126 }ADC_InjectionConfTypeDef;
<> 149:156823d33999 127 /**
<> 149:156823d33999 128 * @}
<> 149:156823d33999 129 */
<> 149:156823d33999 130
<> 149:156823d33999 131
<> 149:156823d33999 132 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 133
<> 149:156823d33999 134 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
<> 149:156823d33999 135 * @{
<> 149:156823d33999 136 */
<> 149:156823d33999 137
<> 149:156823d33999 138 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group
<> 149:156823d33999 139 * @{
<> 149:156823d33999 140 */
AnnaBridge 184:08ed48f1de7f 141 #define ADC_INJECTED_RANK_1 (0x00000001U)
AnnaBridge 184:08ed48f1de7f 142 #define ADC_INJECTED_RANK_2 (0x00000002U)
AnnaBridge 184:08ed48f1de7f 143 #define ADC_INJECTED_RANK_3 (0x00000003U)
AnnaBridge 184:08ed48f1de7f 144 #define ADC_INJECTED_RANK_4 (0x00000004U)
<> 149:156823d33999 145 /**
<> 149:156823d33999 146 * @}
<> 149:156823d33999 147 */
<> 149:156823d33999 148
<> 149:156823d33999 149 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
<> 149:156823d33999 150 * @{
<> 149:156823d33999 151 */
AnnaBridge 184:08ed48f1de7f 152 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
<> 149:156823d33999 153 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
<> 149:156823d33999 154 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
<> 149:156823d33999 155 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
<> 149:156823d33999 156 /**
<> 149:156823d33999 157 * @}
<> 149:156823d33999 158 */
<> 149:156823d33999 159
<> 149:156823d33999 160 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected
<> 149:156823d33999 161 * @{
<> 149:156823d33999 162 */
<> 149:156823d33999 163 /* External triggers for injected groups of ADC1 */
<> 149:156823d33999 164 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
<> 149:156823d33999 165 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
<> 149:156823d33999 166 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
<> 149:156823d33999 167 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
<> 149:156823d33999 168 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1
<> 149:156823d33999 169 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2
<> 149:156823d33999 170 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3
<> 149:156823d33999 171 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO
<> 149:156823d33999 172 #define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1
<> 149:156823d33999 173 #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO
<> 149:156823d33999 174 #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1
<> 149:156823d33999 175 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
AnnaBridge 184:08ed48f1de7f 176 #define ADC_INJECTED_SOFTWARE_START (0x00000010U)
<> 149:156823d33999 177 /**
<> 149:156823d33999 178 * @}
<> 149:156823d33999 179 */
<> 149:156823d33999 180
<> 149:156823d33999 181 /**
<> 149:156823d33999 182 * @}
<> 149:156823d33999 183 */
<> 149:156823d33999 184
<> 149:156823d33999 185
<> 149:156823d33999 186 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 187
<> 149:156823d33999 188 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
<> 149:156823d33999 189 * @{
<> 149:156823d33999 190 */
<> 149:156823d33999 191
<> 149:156823d33999 192 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected
<> 149:156823d33999 193 * @{
<> 149:156823d33999 194 */
<> 149:156823d33999 195
<> 149:156823d33999 196 /* List of external triggers of injected group for ADC1: */
<> 149:156823d33999 197 /* (used internally by HAL driver. To not use into HAL structure parameters) */
AnnaBridge 184:08ed48f1de7f 198 #define ADC_EXTERNALTRIGINJEC_T9_CC1 (0x00000000U)
<> 149:156823d33999 199 #define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0))
<> 149:156823d33999 200 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
<> 149:156823d33999 201 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 149:156823d33999 202 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 ))
<> 149:156823d33999 203 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
<> 149:156823d33999 204 #define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
<> 149:156823d33999 205 #define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 149:156823d33999 206 #define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 ))
<> 149:156823d33999 207 #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
<> 149:156823d33999 208 #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 ))
<> 149:156823d33999 209 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 149:156823d33999 210 /**
<> 149:156823d33999 211 * @}
<> 149:156823d33999 212 */
<> 149:156823d33999 213
<> 149:156823d33999 214 /**
<> 149:156823d33999 215 * @}
<> 149:156823d33999 216 */
<> 149:156823d33999 217
<> 149:156823d33999 218
<> 149:156823d33999 219 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 220
<> 149:156823d33999 221 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
<> 149:156823d33999 222 * @{
<> 149:156823d33999 223 */
<> 149:156823d33999 224 /* Macro for internal HAL driver usage, and possibly can be used into code of */
<> 149:156823d33999 225 /* final user. */
<> 149:156823d33999 226
<> 149:156823d33999 227 /**
<> 149:156823d33999 228 * @brief Selection of channels bank.
<> 149:156823d33999 229 * Note: Banks availability depends on devices categories.
<> 149:156823d33999 230 * This macro is intended to change bank selection quickly on the fly,
<> 149:156823d33999 231 * without going through ADC init structure update and execution of function
<> 149:156823d33999 232 * 'HAL_ADC_Init()'.
<> 149:156823d33999 233 * @param __HANDLE__: ADC handle
<> 149:156823d33999 234 * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank.
<> 149:156823d33999 235 * @retval None
<> 149:156823d33999 236 */
<> 149:156823d33999 237 #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \
<> 149:156823d33999 238 MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__))
<> 149:156823d33999 239
<> 149:156823d33999 240 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 241 /**
<> 149:156823d33999 242 * @brief Configures the ADC channels speed.
<> 149:156823d33999 243 * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5.
<> 149:156823d33999 244 * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is
<> 149:156823d33999 245 * in power down mode.
<> 149:156823d33999 246 * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is
<> 149:156823d33999 247 * in power down mode.
<> 149:156823d33999 248 * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in
<> 149:156823d33999 249 * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and
<> 149:156823d33999 250 * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix.
<> 149:156823d33999 251 * (Note: OPAMP3 is available on STM32L1 Cat.4 only).
<> 149:156823d33999 252 * @param __CHANNEL__: ADC channel
<> 149:156823d33999 253 * This parameter can be one of the following values:
<> 149:156823d33999 254 * @arg ADC_CHANNEL_3: Channel 3 is selected.
<> 149:156823d33999 255 * @arg ADC_CHANNEL_8: Channel 8 is selected.
<> 149:156823d33999 256 * @arg ADC_CHANNEL_13: Channel 13 is selected.
<> 149:156823d33999 257 * @retval None
<> 149:156823d33999 258 */
<> 149:156823d33999 259 #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \
<> 149:156823d33999 260 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \
<> 149:156823d33999 261 )? \
<> 149:156823d33999 262 (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \
<> 149:156823d33999 263 : \
<> 149:156823d33999 264 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \
<> 149:156823d33999 265 )? \
<> 149:156823d33999 266 (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \
<> 149:156823d33999 267 : \
<> 149:156823d33999 268 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \
<> 149:156823d33999 269 )? \
<> 149:156823d33999 270 (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \
<> 149:156823d33999 271 : \
<> 149:156823d33999 272 (SET_BIT(COMP->CSR, 0x00000000)) \
<> 149:156823d33999 273 ) \
<> 149:156823d33999 274 ) \
<> 149:156823d33999 275 )
<> 149:156823d33999 276
<> 149:156823d33999 277 #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \
<> 149:156823d33999 278 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \
<> 149:156823d33999 279 )? \
<> 149:156823d33999 280 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \
<> 149:156823d33999 281 : \
<> 149:156823d33999 282 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \
<> 149:156823d33999 283 )? \
<> 149:156823d33999 284 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \
<> 149:156823d33999 285 : \
<> 149:156823d33999 286 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \
<> 149:156823d33999 287 )? \
<> 149:156823d33999 288 (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \
<> 149:156823d33999 289 : \
<> 149:156823d33999 290 (SET_BIT(COMP->CSR, 0x00000000)) \
<> 149:156823d33999 291 ) \
<> 149:156823d33999 292 ) \
<> 149:156823d33999 293 )
<> 149:156823d33999 294 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 295
<> 149:156823d33999 296 /**
<> 149:156823d33999 297 * @}
<> 149:156823d33999 298 */
<> 149:156823d33999 299
<> 149:156823d33999 300 /* Private macro ------------------------------------------------------------*/
<> 149:156823d33999 301
<> 149:156823d33999 302 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro
<> 149:156823d33999 303 * @{
<> 149:156823d33999 304 */
<> 149:156823d33999 305 /* Macro reserved for internal HAL driver usage, not intended to be used in */
<> 149:156823d33999 306 /* code of final user. */
<> 149:156823d33999 307
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @brief Set ADC ranks available in register SQR1.
<> 149:156823d33999 310 * Register SQR1 bits availability depends on device category.
<> 149:156823d33999 311 * @param _NbrOfConversion_: Regular channel sequence length
<> 149:156823d33999 312 * @retval None
<> 149:156823d33999 313 */
<> 149:156823d33999 314 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 315 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25)
<> 149:156823d33999 316 #else
<> 149:156823d33999 317 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25)
<> 149:156823d33999 318 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 319
<> 149:156823d33999 320 /**
<> 149:156823d33999 321 * @brief Set the ADC's sample time for channel numbers between 30 and 31.
<> 149:156823d33999 322 * Register SMPR0 availability depends on device category. If register is not
<> 149:156823d33999 323 * available on the current device, this macro does nothing.
<> 149:156823d33999 324 * @retval None
<> 149:156823d33999 325 * @param _SAMPLETIME_: Sample time parameter.
<> 149:156823d33999 326 * @param _CHANNELNB_: Channel number.
<> 149:156823d33999 327 * @retval None
<> 149:156823d33999 328 */
<> 149:156823d33999 329 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 330 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \
<> 149:156823d33999 331 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30)))
<> 149:156823d33999 332 #else
<> 149:156823d33999 333 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \
AnnaBridge 184:08ed48f1de7f 334 (0x00000000U)
<> 149:156823d33999 335 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 336
<> 149:156823d33999 337 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 338 /**
<> 149:156823d33999 339 * @brief Set the ADC's sample time for channel numbers between 20 and 29.
<> 149:156823d33999 340 * @param _SAMPLETIME_: Sample time parameter.
<> 149:156823d33999 341 * @param _CHANNELNB_: Channel number.
<> 149:156823d33999 342 * @retval None
<> 149:156823d33999 343 */
<> 149:156823d33999 344 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
<> 149:156823d33999 345 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
<> 149:156823d33999 346 #else
<> 149:156823d33999 347 /**
<> 149:156823d33999 348 * @brief Set the ADC's sample time for channel numbers between 20 and 26.
<> 149:156823d33999 349 * @param _SAMPLETIME_: Sample time parameter.
<> 149:156823d33999 350 * @param _CHANNELNB_: Channel number.
<> 149:156823d33999 351 * @retval None
<> 149:156823d33999 352 */
<> 149:156823d33999 353 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
<> 149:156823d33999 354 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
<> 149:156823d33999 355 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 356
<> 149:156823d33999 357 /**
<> 149:156823d33999 358 * @brief Defines the highest channel available in register SMPR1. Channels
<> 149:156823d33999 359 * availability depends on device category:
<> 149:156823d33999 360 * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3
<> 149:156823d33999 361 * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5
<> 149:156823d33999 362 * @param None
<> 149:156823d33999 363 * @retval None
<> 149:156823d33999 364 */
<> 149:156823d33999 365 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 366 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29
<> 149:156823d33999 367 #else
<> 149:156823d33999 368 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26
<> 149:156823d33999 369 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 370
<> 149:156823d33999 371
<> 149:156823d33999 372 /**
<> 149:156823d33999 373 * @brief Define mask of configuration bits of ADC and regular group in
<> 149:156823d33999 374 * register CR2 (bits of ADC enable, conversion start and injected group are
<> 149:156823d33999 375 * excluded of this mask).
<> 149:156823d33999 376 * @retval None
<> 149:156823d33999 377 */
<> 149:156823d33999 378 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 379 #define ADC_CR2_MASK_ADCINIT() \
<> 149:156823d33999 380 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT)
<> 149:156823d33999 381 #else
<> 149:156823d33999 382 #define ADC_CR2_MASK_ADCINIT() \
<> 149:156823d33999 383 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT)
<> 149:156823d33999 384 #endif
<> 149:156823d33999 385
<> 149:156823d33999 386
<> 149:156823d33999 387 /**
<> 149:156823d33999 388 * @brief Get the maximum ADC conversion cycles on all channels.
<> 149:156823d33999 389 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
<> 149:156823d33999 390 * Approximation of sampling time within 2 ranges, returns the highest value:
<> 149:156823d33999 391 * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles}
<> 149:156823d33999 392 * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles}
<> 149:156823d33999 393 * Unit: ADC clock cycles
<> 149:156823d33999 394 * @param __HANDLE__: ADC handle
<> 149:156823d33999 395 * @retval ADC conversion cycles on all channels
<> 149:156823d33999 396 */
<> 149:156823d33999 397 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 398 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
<> 149:156823d33999 399 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \
<> 149:156823d33999 400 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
<> 149:156823d33999 401 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \
<> 149:156823d33999 402 (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \
<> 149:156823d33999 403 \
<> 149:156823d33999 404 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \
<> 149:156823d33999 405 )
<> 149:156823d33999 406 #else
<> 149:156823d33999 407 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
<> 149:156823d33999 408 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \
<> 149:156823d33999 409 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
<> 149:156823d33999 410 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
<> 149:156823d33999 411 \
<> 149:156823d33999 412 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \
<> 149:156823d33999 413 )
<> 149:156823d33999 414 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 415
<> 149:156823d33999 416 /**
<> 149:156823d33999 417 * @brief Get the ADC clock prescaler from ADC common control register
<> 149:156823d33999 418 * and convert it to its decimal number setting (refer to reference manual)
<> 149:156823d33999 419 * @retval None
<> 149:156823d33999 420 */
<> 149:156823d33999 421 #define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \
<> 149:156823d33999 422 ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE)))
<> 149:156823d33999 423
<> 149:156823d33999 424 /**
<> 149:156823d33999 425 * @brief Clear register SMPR0.
<> 149:156823d33999 426 * Register SMPR0 availability depends on device category. If register is not
<> 149:156823d33999 427 * available on the current device, this macro performs no action.
<> 149:156823d33999 428 * @param __HANDLE__: ADC handle
<> 149:156823d33999 429 * @retval None
<> 149:156823d33999 430 */
<> 149:156823d33999 431 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 432 #define ADC_SMPR1_CLEAR(__HANDLE__) \
<> 149:156823d33999 433 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \
<> 149:156823d33999 434 ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \
<> 149:156823d33999 435 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \
<> 149:156823d33999 436 ADC_SMPR1_SMP20 ))
<> 149:156823d33999 437
<> 149:156823d33999 438 #define ADC_SMPR0_CLEAR(__HANDLE__) \
<> 149:156823d33999 439 (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)))
<> 149:156823d33999 440 #else
<> 149:156823d33999 441 #define ADC_SMPR1_CLEAR(__HANDLE__) \
<> 149:156823d33999 442 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \
<> 149:156823d33999 443 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \
<> 149:156823d33999 444 ADC_SMPR1_SMP20 ))
<> 149:156823d33999 445
<> 149:156823d33999 446 #define ADC_SMPR0_CLEAR(__HANDLE__) __NOP()
<> 149:156823d33999 447 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 448
<> 149:156823d33999 449 /**
<> 149:156823d33999 450 * @brief Clear register CR2.
<> 149:156823d33999 451 * @param __HANDLE__: ADC handle
<> 149:156823d33999 452 * @retval None
<> 149:156823d33999 453 */
<> 149:156823d33999 454 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 455 #define ADC_CR2_CLEAR(__HANDLE__) \
<> 149:156823d33999 456 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \
<> 149:156823d33999 457 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \
<> 149:156823d33999 458 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \
<> 149:156823d33999 459 ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \
<> 149:156823d33999 460 ADC_CR2_CONT | ADC_CR2_ADON )) \
<> 149:156823d33999 461 )
<> 149:156823d33999 462 #else
<> 149:156823d33999 463 #define ADC_CR2_CLEAR(__HANDLE__) \
<> 149:156823d33999 464 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \
<> 149:156823d33999 465 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \
<> 149:156823d33999 466 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \
<> 149:156823d33999 467 ADC_CR2_DMA | ADC_CR2_DELS | \
<> 149:156823d33999 468 ADC_CR2_CONT | ADC_CR2_ADON )) \
<> 149:156823d33999 469 )
<> 149:156823d33999 470 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 471
<> 149:156823d33999 472 /**
<> 149:156823d33999 473 * @brief Set the sampling time of selected channel on register SMPR0
<> 149:156823d33999 474 * Register SMPR0 availability depends on device category. If register is not
<> 149:156823d33999 475 * available on the current device, this macro performs no action.
<> 149:156823d33999 476 * @param __HANDLE__: ADC handle
<> 149:156823d33999 477 * @param _SAMPLETIME_: Sample time parameter.
<> 149:156823d33999 478 * @param __CHANNEL__: Channel number.
<> 149:156823d33999 479 * @retval None
<> 149:156823d33999 480 */
<> 149:156823d33999 481 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 482 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \
<> 149:156823d33999 483 MODIFY_REG((__HANDLE__)->Instance->SMPR0, \
<> 149:156823d33999 484 ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \
<> 149:156823d33999 485 ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) )
<> 149:156823d33999 486 #else
<> 149:156823d33999 487 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP()
<> 149:156823d33999 488 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 489
<> 149:156823d33999 490
<> 149:156823d33999 491 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
<> 149:156823d33999 492 ((CHANNEL) == ADC_INJECTED_RANK_2) || \
<> 149:156823d33999 493 ((CHANNEL) == ADC_INJECTED_RANK_3) || \
<> 149:156823d33999 494 ((CHANNEL) == ADC_INJECTED_RANK_4) )
<> 149:156823d33999 495
<> 149:156823d33999 496 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
<> 149:156823d33999 497 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
<> 149:156823d33999 498 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
<> 149:156823d33999 499 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
<> 149:156823d33999 500
<> 149:156823d33999 501 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
<> 149:156823d33999 502 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
<> 149:156823d33999 503 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
<> 149:156823d33999 504 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
<> 149:156823d33999 505 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
<> 149:156823d33999 506 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
<> 149:156823d33999 507 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
<> 149:156823d33999 508 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
<> 149:156823d33999 509 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \
<> 149:156823d33999 510 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \
<> 149:156823d33999 511 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \
<> 149:156823d33999 512 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
<> 149:156823d33999 513 ((REGTRIG) == ADC_SOFTWARE_START) )
<> 149:156823d33999 514
<> 149:156823d33999 515 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
<> 149:156823d33999 516 * @{
<> 149:156823d33999 517 */
AnnaBridge 184:08ed48f1de7f 518 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
<> 149:156823d33999 519 /**
<> 149:156823d33999 520 * @}
<> 149:156823d33999 521 */
<> 149:156823d33999 522
<> 149:156823d33999 523 /**
<> 149:156823d33999 524 * @}
<> 149:156823d33999 525 */
<> 149:156823d33999 526
<> 149:156823d33999 527
<> 149:156823d33999 528 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 529 /** @addtogroup ADCEx_Exported_Functions
<> 149:156823d33999 530 * @{
<> 149:156823d33999 531 */
<> 149:156823d33999 532
<> 149:156823d33999 533 /* IO operation functions *****************************************************/
<> 149:156823d33999 534 /** @addtogroup ADCEx_Exported_Functions_Group1
<> 149:156823d33999 535 * @{
<> 149:156823d33999 536 */
<> 149:156823d33999 537
<> 149:156823d33999 538 /* Blocking mode: Polling */
<> 149:156823d33999 539 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
<> 149:156823d33999 540 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
<> 149:156823d33999 541 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 149:156823d33999 542
<> 149:156823d33999 543 /* Non-blocking mode: Interruption */
<> 149:156823d33999 544 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
<> 149:156823d33999 545 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
<> 149:156823d33999 546
<> 149:156823d33999 547 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 149:156823d33999 548 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
<> 149:156823d33999 549
<> 149:156823d33999 550 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
<> 149:156823d33999 551 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 149:156823d33999 552 /**
<> 149:156823d33999 553 * @}
<> 149:156823d33999 554 */
<> 149:156823d33999 555
<> 149:156823d33999 556
<> 149:156823d33999 557 /* Peripheral Control functions ***********************************************/
<> 149:156823d33999 558 /** @addtogroup ADCEx_Exported_Functions_Group2
<> 149:156823d33999 559 * @{
<> 149:156823d33999 560 */
<> 149:156823d33999 561
<> 149:156823d33999 562 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
<> 149:156823d33999 563 /**
<> 149:156823d33999 564 * @}
<> 149:156823d33999 565 */
<> 149:156823d33999 566
<> 149:156823d33999 567
<> 149:156823d33999 568 /**
<> 149:156823d33999 569 * @}
<> 149:156823d33999 570 */
<> 149:156823d33999 571
<> 149:156823d33999 572
<> 149:156823d33999 573 /**
<> 149:156823d33999 574 * @}
<> 149:156823d33999 575 */
<> 149:156823d33999 576
<> 149:156823d33999 577 /**
<> 149:156823d33999 578 * @}
<> 149:156823d33999 579 */
<> 149:156823d33999 580
<> 149:156823d33999 581 #ifdef __cplusplus
<> 149:156823d33999 582 }
<> 149:156823d33999 583 #endif
<> 149:156823d33999 584
<> 149:156823d33999 585 #endif /* __STM32L1xx_HAL_ADC_EX_H */
<> 149:156823d33999 586
<> 149:156823d33999 587
<> 149:156823d33999 588 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/