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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32_hal_legacy.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
184:08ed48f1de7f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32_hal_legacy.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief This file contains aliases definition for the STM32Cube HAL constants
<> 149:156823d33999 6 * macros and functions maintained for legacy purpose.
<> 149:156823d33999 7 ******************************************************************************
<> 149:156823d33999 8 * @attention
<> 149:156823d33999 9 *
AnnaBridge 184:08ed48f1de7f 10 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 11 *
<> 149:156823d33999 12 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 13 * are permitted provided that the following conditions are met:
<> 149:156823d33999 14 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 15 * this list of conditions and the following disclaimer.
<> 149:156823d33999 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 17 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 18 * and/or other materials provided with the distribution.
<> 149:156823d33999 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 20 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 21 * without specific prior written permission.
<> 149:156823d33999 22 *
<> 149:156823d33999 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 33 *
<> 149:156823d33999 34 ******************************************************************************
<> 149:156823d33999 35 */
<> 149:156823d33999 36
<> 149:156823d33999 37 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 38 #ifndef __STM32_HAL_LEGACY
<> 149:156823d33999 39 #define __STM32_HAL_LEGACY
<> 149:156823d33999 40
<> 149:156823d33999 41 #ifdef __cplusplus
<> 149:156823d33999 42 extern "C" {
<> 149:156823d33999 43 #endif
<> 149:156823d33999 44
<> 149:156823d33999 45 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 46 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 47 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 48
<> 149:156823d33999 49 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
<> 149:156823d33999 50 * @{
<> 149:156823d33999 51 */
<> 149:156823d33999 52 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
<> 149:156823d33999 53 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
<> 149:156823d33999 54 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
<> 149:156823d33999 55 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
<> 149:156823d33999 56 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
<> 149:156823d33999 57
<> 149:156823d33999 58 /**
<> 149:156823d33999 59 * @}
<> 149:156823d33999 60 */
<> 149:156823d33999 61
<> 149:156823d33999 62 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
<> 149:156823d33999 63 * @{
<> 149:156823d33999 64 */
<> 149:156823d33999 65 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
<> 149:156823d33999 66 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
<> 149:156823d33999 67 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
<> 149:156823d33999 68 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
<> 149:156823d33999 69 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
<> 149:156823d33999 70 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
<> 149:156823d33999 71 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
<> 149:156823d33999 72 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
<> 149:156823d33999 73 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
<> 149:156823d33999 74 #define REGULAR_GROUP ADC_REGULAR_GROUP
<> 149:156823d33999 75 #define INJECTED_GROUP ADC_INJECTED_GROUP
<> 149:156823d33999 76 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
<> 149:156823d33999 77 #define AWD_EVENT ADC_AWD_EVENT
<> 149:156823d33999 78 #define AWD1_EVENT ADC_AWD1_EVENT
<> 149:156823d33999 79 #define AWD2_EVENT ADC_AWD2_EVENT
<> 149:156823d33999 80 #define AWD3_EVENT ADC_AWD3_EVENT
<> 149:156823d33999 81 #define OVR_EVENT ADC_OVR_EVENT
<> 149:156823d33999 82 #define JQOVF_EVENT ADC_JQOVF_EVENT
<> 149:156823d33999 83 #define ALL_CHANNELS ADC_ALL_CHANNELS
<> 149:156823d33999 84 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
<> 149:156823d33999 85 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
<> 149:156823d33999 86 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
<> 149:156823d33999 87 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
<> 149:156823d33999 88 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
<> 149:156823d33999 89 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
<> 149:156823d33999 90 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
<> 149:156823d33999 91 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
<> 149:156823d33999 92 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
<> 149:156823d33999 93 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
<> 149:156823d33999 94 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
<> 149:156823d33999 95 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
<> 149:156823d33999 96 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
<> 149:156823d33999 97 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
<> 149:156823d33999 98 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
<> 149:156823d33999 99 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
<> 149:156823d33999 100 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
<> 149:156823d33999 101 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
<> 149:156823d33999 102 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
<> 149:156823d33999 103 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
<> 149:156823d33999 104 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
<> 149:156823d33999 105
<> 149:156823d33999 106 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
<> 149:156823d33999 107 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
<> 149:156823d33999 108 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
<> 149:156823d33999 109 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
<> 149:156823d33999 110 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
<> 149:156823d33999 111 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
<> 149:156823d33999 112 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
<> 149:156823d33999 113 /**
<> 149:156823d33999 114 * @}
<> 149:156823d33999 115 */
<> 149:156823d33999 116
<> 149:156823d33999 117 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
<> 149:156823d33999 118 * @{
<> 149:156823d33999 119 */
<> 149:156823d33999 120
<> 149:156823d33999 121 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
<> 149:156823d33999 122
<> 149:156823d33999 123 /**
<> 149:156823d33999 124 * @}
<> 149:156823d33999 125 */
<> 149:156823d33999 126
<> 149:156823d33999 127 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
<> 149:156823d33999 128 * @{
<> 149:156823d33999 129 */
<> 149:156823d33999 130 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
<> 149:156823d33999 131 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
<> 149:156823d33999 132 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
<> 149:156823d33999 133 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
<> 149:156823d33999 134 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
<> 149:156823d33999 135 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
<> 149:156823d33999 136 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
<> 149:156823d33999 137 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
<> 149:156823d33999 138 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
AnnaBridge 184:08ed48f1de7f 139 #if defined(STM32L0)
AnnaBridge 184:08ed48f1de7f 140 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
AnnaBridge 184:08ed48f1de7f 141 #endif
<> 149:156823d33999 142 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
<> 149:156823d33999 143 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 149:156823d33999 144 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
<> 149:156823d33999 145 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
<> 149:156823d33999 146 #endif /* STM32F373xC || STM32F378xx */
<> 149:156823d33999 147
<> 149:156823d33999 148 #if defined(STM32L0) || defined(STM32L4)
<> 149:156823d33999 149 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
<> 149:156823d33999 150
<> 149:156823d33999 151 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
<> 149:156823d33999 152 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
<> 149:156823d33999 153 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
<> 149:156823d33999 154 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
<> 149:156823d33999 155 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
<> 149:156823d33999 156 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
<> 149:156823d33999 157
<> 149:156823d33999 158 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
<> 149:156823d33999 159 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
<> 149:156823d33999 160 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
<> 149:156823d33999 161 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
<> 149:156823d33999 162 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
<> 149:156823d33999 163 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
<> 149:156823d33999 164 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
<> 149:156823d33999 165 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
<> 149:156823d33999 166 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
<> 149:156823d33999 167 #if defined(STM32L0)
<> 149:156823d33999 168 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
<> 149:156823d33999 169 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
<> 149:156823d33999 170 /* to the second dedicated IO (only for COMP2). */
<> 149:156823d33999 171 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
<> 149:156823d33999 172 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
<> 149:156823d33999 173 #else
<> 149:156823d33999 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
<> 149:156823d33999 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
<> 149:156823d33999 176 #endif
<> 149:156823d33999 177 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
<> 149:156823d33999 178 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
<> 149:156823d33999 179
<> 149:156823d33999 180 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
<> 149:156823d33999 181 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
<> 149:156823d33999 182
<> 149:156823d33999 183 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
<> 149:156823d33999 184 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
<> 149:156823d33999 185 #if defined(COMP_CSR_LOCK)
<> 149:156823d33999 186 #define COMP_FLAG_LOCK COMP_CSR_LOCK
<> 149:156823d33999 187 #elif defined(COMP_CSR_COMP1LOCK)
<> 149:156823d33999 188 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
<> 149:156823d33999 189 #elif defined(COMP_CSR_COMPxLOCK)
<> 149:156823d33999 190 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
<> 149:156823d33999 191 #endif
<> 149:156823d33999 192
<> 149:156823d33999 193 #if defined(STM32L4)
<> 149:156823d33999 194 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
<> 149:156823d33999 195 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
<> 149:156823d33999 196 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
<> 149:156823d33999 197 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
<> 149:156823d33999 198 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
<> 149:156823d33999 199 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
<> 149:156823d33999 200 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
<> 149:156823d33999 201 #endif
<> 149:156823d33999 202
<> 149:156823d33999 203 #if defined(STM32L0)
<> 149:156823d33999 204 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
<> 149:156823d33999 205 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
<> 149:156823d33999 206 #else
<> 149:156823d33999 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
<> 149:156823d33999 208 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
<> 149:156823d33999 209 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
<> 149:156823d33999 210 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
<> 149:156823d33999 211 #endif
<> 149:156823d33999 212
<> 149:156823d33999 213 #endif
<> 149:156823d33999 214 /**
<> 149:156823d33999 215 * @}
<> 149:156823d33999 216 */
<> 149:156823d33999 217
<> 149:156823d33999 218 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
<> 149:156823d33999 219 * @{
<> 149:156823d33999 220 */
<> 149:156823d33999 221 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
<> 149:156823d33999 222 /**
<> 149:156823d33999 223 * @}
<> 149:156823d33999 224 */
<> 149:156823d33999 225
<> 149:156823d33999 226 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
<> 149:156823d33999 227 * @{
<> 149:156823d33999 228 */
<> 149:156823d33999 229
<> 149:156823d33999 230 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
<> 149:156823d33999 231 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
<> 149:156823d33999 232
<> 149:156823d33999 233 /**
<> 149:156823d33999 234 * @}
<> 149:156823d33999 235 */
<> 149:156823d33999 236
<> 149:156823d33999 237 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
<> 149:156823d33999 238 * @{
<> 149:156823d33999 239 */
<> 149:156823d33999 240
<> 149:156823d33999 241 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
<> 149:156823d33999 242 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
<> 149:156823d33999 243 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge 184:08ed48f1de7f 244 #define DAC_WAVE_NONE 0x00000000U
AnnaBridge 184:08ed48f1de7f 245 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0
AnnaBridge 184:08ed48f1de7f 246 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
<> 149:156823d33999 247 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
<> 149:156823d33999 248 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
<> 149:156823d33999 249 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
<> 149:156823d33999 250
<> 149:156823d33999 251 /**
<> 149:156823d33999 252 * @}
<> 149:156823d33999 253 */
<> 149:156823d33999 254
<> 149:156823d33999 255 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
<> 149:156823d33999 256 * @{
<> 149:156823d33999 257 */
<> 149:156823d33999 258 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
<> 149:156823d33999 259 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
<> 149:156823d33999 260 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
<> 149:156823d33999 261 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
<> 149:156823d33999 262 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
<> 149:156823d33999 263 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
<> 149:156823d33999 264 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
<> 149:156823d33999 265 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
<> 149:156823d33999 266 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
<> 149:156823d33999 267 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
<> 149:156823d33999 268 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
<> 149:156823d33999 269 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
<> 149:156823d33999 270 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
<> 149:156823d33999 271 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
<> 149:156823d33999 272
<> 149:156823d33999 273 #define IS_HAL_REMAPDMA IS_DMA_REMAP
<> 149:156823d33999 274 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
<> 149:156823d33999 275 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
<> 149:156823d33999 276
<> 149:156823d33999 277
<> 149:156823d33999 278
<> 149:156823d33999 279 /**
<> 149:156823d33999 280 * @}
<> 149:156823d33999 281 */
<> 149:156823d33999 282
<> 149:156823d33999 283 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
<> 149:156823d33999 284 * @{
<> 149:156823d33999 285 */
<> 149:156823d33999 286
<> 149:156823d33999 287 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
<> 149:156823d33999 288 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
<> 149:156823d33999 289 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
<> 149:156823d33999 290 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
<> 149:156823d33999 291 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
<> 149:156823d33999 292 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
<> 149:156823d33999 293 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
<> 149:156823d33999 294 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
<> 149:156823d33999 295 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
<> 149:156823d33999 296 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
<> 149:156823d33999 297 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
<> 149:156823d33999 298 #define OBEX_PCROP OPTIONBYTE_PCROP
<> 149:156823d33999 299 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
<> 149:156823d33999 300 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
<> 149:156823d33999 301 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
<> 149:156823d33999 302 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
<> 149:156823d33999 303 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
<> 149:156823d33999 304 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
<> 149:156823d33999 305 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
<> 149:156823d33999 306 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
<> 149:156823d33999 307 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
<> 149:156823d33999 308 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
<> 149:156823d33999 309 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
<> 149:156823d33999 310 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
<> 149:156823d33999 311 #define PAGESIZE FLASH_PAGE_SIZE
<> 149:156823d33999 312 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
<> 149:156823d33999 313 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
<> 149:156823d33999 314 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
<> 149:156823d33999 315 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
<> 149:156823d33999 316 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
<> 149:156823d33999 317 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
<> 149:156823d33999 318 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
<> 149:156823d33999 319 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
<> 149:156823d33999 320 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
<> 149:156823d33999 321 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
<> 149:156823d33999 322 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
<> 149:156823d33999 323 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
<> 149:156823d33999 324 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
<> 149:156823d33999 325 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
<> 149:156823d33999 326 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
<> 149:156823d33999 327 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
<> 149:156823d33999 328 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
<> 149:156823d33999 329 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
<> 149:156823d33999 330 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
<> 149:156823d33999 331 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
<> 149:156823d33999 332 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
<> 149:156823d33999 333 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
<> 149:156823d33999 334 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
<> 149:156823d33999 335 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
<> 149:156823d33999 336 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
<> 149:156823d33999 337 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
<> 149:156823d33999 338 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
<> 149:156823d33999 339 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
<> 149:156823d33999 340 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
<> 149:156823d33999 341 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
<> 149:156823d33999 342 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
<> 149:156823d33999 343 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
<> 149:156823d33999 344 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
<> 149:156823d33999 345 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
<> 149:156823d33999 346 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
<> 149:156823d33999 347 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
<> 149:156823d33999 348 #define OB_WDG_SW OB_IWDG_SW
<> 149:156823d33999 349 #define OB_WDG_HW OB_IWDG_HW
<> 149:156823d33999 350 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
<> 149:156823d33999 351 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
<> 149:156823d33999 352 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
<> 149:156823d33999 353 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
<> 149:156823d33999 354 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
<> 149:156823d33999 355 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
<> 149:156823d33999 356 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
<> 149:156823d33999 357 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
AnnaBridge 184:08ed48f1de7f 358
<> 149:156823d33999 359 /**
<> 149:156823d33999 360 * @}
<> 149:156823d33999 361 */
<> 149:156823d33999 362
<> 149:156823d33999 363 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
<> 149:156823d33999 364 * @{
<> 149:156823d33999 365 */
<> 149:156823d33999 366
<> 149:156823d33999 367 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
<> 149:156823d33999 368 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
<> 149:156823d33999 369 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
<> 149:156823d33999 370 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
<> 149:156823d33999 371 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
<> 149:156823d33999 372 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
<> 149:156823d33999 373 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
<> 149:156823d33999 374 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
<> 149:156823d33999 375 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
<> 149:156823d33999 376 /**
<> 149:156823d33999 377 * @}
<> 149:156823d33999 378 */
<> 149:156823d33999 379
<> 149:156823d33999 380
<> 149:156823d33999 381 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
<> 149:156823d33999 382 * @{
<> 149:156823d33999 383 */
AnnaBridge 184:08ed48f1de7f 384 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
<> 149:156823d33999 385 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
<> 149:156823d33999 386 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
<> 149:156823d33999 387 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
<> 149:156823d33999 388 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
<> 149:156823d33999 389 #else
<> 149:156823d33999 390 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
<> 149:156823d33999 391 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
<> 149:156823d33999 392 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
<> 149:156823d33999 393 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
<> 149:156823d33999 394 #endif
<> 149:156823d33999 395 /**
<> 149:156823d33999 396 * @}
<> 149:156823d33999 397 */
<> 149:156823d33999 398
<> 149:156823d33999 399 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
<> 149:156823d33999 400 * @{
<> 149:156823d33999 401 */
<> 149:156823d33999 402
<> 149:156823d33999 403 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
<> 149:156823d33999 404 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
<> 149:156823d33999 405 /**
<> 149:156823d33999 406 * @}
<> 149:156823d33999 407 */
<> 149:156823d33999 408
<> 149:156823d33999 409 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
<> 149:156823d33999 410 * @{
<> 149:156823d33999 411 */
<> 149:156823d33999 412 #define GET_GPIO_SOURCE GPIO_GET_INDEX
<> 149:156823d33999 413 #define GET_GPIO_INDEX GPIO_GET_INDEX
<> 149:156823d33999 414
<> 149:156823d33999 415 #if defined(STM32F4)
<> 149:156823d33999 416 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
<> 149:156823d33999 417 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
<> 149:156823d33999 418 #endif
<> 149:156823d33999 419
<> 149:156823d33999 420 #if defined(STM32F7)
<> 149:156823d33999 421 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
<> 149:156823d33999 422 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
<> 149:156823d33999 423 #endif
<> 149:156823d33999 424
<> 149:156823d33999 425 #if defined(STM32L4)
<> 149:156823d33999 426 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
<> 149:156823d33999 427 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
<> 149:156823d33999 428 #endif
<> 149:156823d33999 429
<> 149:156823d33999 430 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
<> 149:156823d33999 431 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
<> 149:156823d33999 432 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
<> 149:156823d33999 433
<> 149:156823d33999 434 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
<> 149:156823d33999 435 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
<> 149:156823d33999 436 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
<> 149:156823d33999 437 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
<> 149:156823d33999 438 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
<> 149:156823d33999 439 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
<> 149:156823d33999 440
<> 149:156823d33999 441 #if defined(STM32L1)
<> 149:156823d33999 442 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
<> 149:156823d33999 443 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
<> 149:156823d33999 444 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
<> 149:156823d33999 445 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
<> 149:156823d33999 446 #endif /* STM32L1 */
<> 149:156823d33999 447
<> 149:156823d33999 448 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
<> 149:156823d33999 449 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
<> 149:156823d33999 450 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
<> 149:156823d33999 451 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
<> 149:156823d33999 452 #endif /* STM32F0 || STM32F3 || STM32F1 */
<> 149:156823d33999 453
<> 149:156823d33999 454 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
<> 149:156823d33999 455 /**
<> 149:156823d33999 456 * @}
<> 149:156823d33999 457 */
<> 149:156823d33999 458
AnnaBridge 184:08ed48f1de7f 459 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
AnnaBridge 184:08ed48f1de7f 460 * @{
AnnaBridge 184:08ed48f1de7f 461 */
AnnaBridge 184:08ed48f1de7f 462
AnnaBridge 184:08ed48f1de7f 463 #if defined(STM32H7)
AnnaBridge 184:08ed48f1de7f 464 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
AnnaBridge 184:08ed48f1de7f 465 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 466 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
AnnaBridge 184:08ed48f1de7f 467 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
AnnaBridge 184:08ed48f1de7f 468 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
AnnaBridge 184:08ed48f1de7f 469 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
AnnaBridge 184:08ed48f1de7f 470
AnnaBridge 184:08ed48f1de7f 471 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
AnnaBridge 184:08ed48f1de7f 472 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
AnnaBridge 184:08ed48f1de7f 473
AnnaBridge 184:08ed48f1de7f 474 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
AnnaBridge 184:08ed48f1de7f 475 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
AnnaBridge 184:08ed48f1de7f 476
AnnaBridge 184:08ed48f1de7f 477 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
AnnaBridge 184:08ed48f1de7f 478 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
AnnaBridge 184:08ed48f1de7f 479 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
AnnaBridge 184:08ed48f1de7f 480 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
AnnaBridge 184:08ed48f1de7f 481 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
AnnaBridge 184:08ed48f1de7f 482 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
AnnaBridge 184:08ed48f1de7f 483 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
AnnaBridge 184:08ed48f1de7f 484 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
AnnaBridge 184:08ed48f1de7f 485
AnnaBridge 184:08ed48f1de7f 486 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
AnnaBridge 184:08ed48f1de7f 487 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
AnnaBridge 184:08ed48f1de7f 488 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
AnnaBridge 184:08ed48f1de7f 489 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
AnnaBridge 184:08ed48f1de7f 490 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
AnnaBridge 184:08ed48f1de7f 491 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
AnnaBridge 184:08ed48f1de7f 492 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
AnnaBridge 184:08ed48f1de7f 493 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
AnnaBridge 184:08ed48f1de7f 494 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
AnnaBridge 184:08ed48f1de7f 495 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
AnnaBridge 184:08ed48f1de7f 496 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
AnnaBridge 184:08ed48f1de7f 497 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
AnnaBridge 184:08ed48f1de7f 498 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
AnnaBridge 184:08ed48f1de7f 499 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
AnnaBridge 184:08ed48f1de7f 500 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
AnnaBridge 184:08ed48f1de7f 501 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
AnnaBridge 184:08ed48f1de7f 502 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
AnnaBridge 184:08ed48f1de7f 503 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
AnnaBridge 184:08ed48f1de7f 504 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
AnnaBridge 184:08ed48f1de7f 505 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
AnnaBridge 184:08ed48f1de7f 506 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
AnnaBridge 184:08ed48f1de7f 507 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
AnnaBridge 184:08ed48f1de7f 508 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
AnnaBridge 184:08ed48f1de7f 509 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
AnnaBridge 184:08ed48f1de7f 510 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
AnnaBridge 184:08ed48f1de7f 511 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
AnnaBridge 184:08ed48f1de7f 512 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
AnnaBridge 184:08ed48f1de7f 513 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
AnnaBridge 184:08ed48f1de7f 514 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
AnnaBridge 184:08ed48f1de7f 515 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
AnnaBridge 184:08ed48f1de7f 516
AnnaBridge 184:08ed48f1de7f 517 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
AnnaBridge 184:08ed48f1de7f 518 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
AnnaBridge 184:08ed48f1de7f 519 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
AnnaBridge 184:08ed48f1de7f 520 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
AnnaBridge 184:08ed48f1de7f 521
AnnaBridge 184:08ed48f1de7f 522
AnnaBridge 184:08ed48f1de7f 523 #endif /* STM32H7 */
AnnaBridge 184:08ed48f1de7f 524
AnnaBridge 184:08ed48f1de7f 525
AnnaBridge 184:08ed48f1de7f 526 /**
AnnaBridge 184:08ed48f1de7f 527 * @}
AnnaBridge 184:08ed48f1de7f 528 */
AnnaBridge 184:08ed48f1de7f 529
AnnaBridge 184:08ed48f1de7f 530
<> 149:156823d33999 531 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
<> 149:156823d33999 532 * @{
<> 149:156823d33999 533 */
<> 149:156823d33999 534 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
<> 149:156823d33999 535 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
<> 149:156823d33999 536 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
<> 149:156823d33999 537 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
<> 149:156823d33999 538 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
<> 149:156823d33999 539 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
<> 149:156823d33999 540 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
<> 149:156823d33999 541 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
<> 149:156823d33999 542 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
<> 149:156823d33999 543
<> 149:156823d33999 544 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
<> 149:156823d33999 545 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
<> 149:156823d33999 546 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
<> 149:156823d33999 547 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
<> 149:156823d33999 548 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
<> 149:156823d33999 549 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
<> 149:156823d33999 550 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
<> 149:156823d33999 551 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
<> 149:156823d33999 552 /**
<> 149:156823d33999 553 * @}
<> 149:156823d33999 554 */
<> 149:156823d33999 555
<> 149:156823d33999 556 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
<> 149:156823d33999 557 * @{
<> 149:156823d33999 558 */
<> 149:156823d33999 559 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
<> 149:156823d33999 560 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
<> 149:156823d33999 561 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
<> 149:156823d33999 562 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
<> 149:156823d33999 563 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
<> 149:156823d33999 564 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
<> 149:156823d33999 565 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
<> 149:156823d33999 566 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
<> 149:156823d33999 567 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
<> 149:156823d33999 568 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
<> 149:156823d33999 569 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
<> 149:156823d33999 570 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
<> 149:156823d33999 571 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
<> 149:156823d33999 572 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
<> 149:156823d33999 573 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
<> 149:156823d33999 574 #endif
<> 149:156823d33999 575 /**
<> 149:156823d33999 576 * @}
<> 149:156823d33999 577 */
<> 149:156823d33999 578
<> 149:156823d33999 579 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
<> 149:156823d33999 580 * @{
<> 149:156823d33999 581 */
<> 149:156823d33999 582 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
<> 149:156823d33999 583 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
<> 149:156823d33999 584
<> 149:156823d33999 585 /**
<> 149:156823d33999 586 * @}
<> 149:156823d33999 587 */
<> 149:156823d33999 588
<> 149:156823d33999 589 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
<> 149:156823d33999 590 * @{
<> 149:156823d33999 591 */
<> 149:156823d33999 592 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
<> 149:156823d33999 593 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
<> 149:156823d33999 594 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
<> 149:156823d33999 595 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
<> 149:156823d33999 596 /**
<> 149:156823d33999 597 * @}
<> 149:156823d33999 598 */
<> 149:156823d33999 599
<> 149:156823d33999 600 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
<> 149:156823d33999 601 * @{
<> 149:156823d33999 602 */
<> 149:156823d33999 603
<> 149:156823d33999 604 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
<> 149:156823d33999 605 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
<> 149:156823d33999 606 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
<> 149:156823d33999 607 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
<> 149:156823d33999 608
<> 149:156823d33999 609 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
<> 149:156823d33999 610 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
<> 149:156823d33999 611 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
<> 149:156823d33999 612
<> 149:156823d33999 613 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
<> 149:156823d33999 614 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
<> 149:156823d33999 615 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
<> 149:156823d33999 616 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
<> 149:156823d33999 617
<> 149:156823d33999 618 /* The following 3 definition have also been present in a temporary version of lptim.h */
<> 149:156823d33999 619 /* They need to be renamed also to the right name, just in case */
<> 149:156823d33999 620 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
<> 149:156823d33999 621 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
<> 149:156823d33999 622 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
<> 149:156823d33999 623
<> 149:156823d33999 624 /**
<> 149:156823d33999 625 * @}
<> 149:156823d33999 626 */
<> 149:156823d33999 627
<> 149:156823d33999 628 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
<> 149:156823d33999 629 * @{
<> 149:156823d33999 630 */
<> 149:156823d33999 631 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
<> 149:156823d33999 632 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
<> 149:156823d33999 633 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
<> 149:156823d33999 634 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
<> 149:156823d33999 635
<> 149:156823d33999 636 #define NAND_AddressTypedef NAND_AddressTypeDef
<> 149:156823d33999 637
<> 149:156823d33999 638 #define __ARRAY_ADDRESS ARRAY_ADDRESS
<> 149:156823d33999 639 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
<> 149:156823d33999 640 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
<> 149:156823d33999 641 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
<> 149:156823d33999 642 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
<> 149:156823d33999 643 /**
<> 149:156823d33999 644 * @}
<> 149:156823d33999 645 */
<> 149:156823d33999 646
<> 149:156823d33999 647 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
<> 149:156823d33999 648 * @{
<> 149:156823d33999 649 */
<> 149:156823d33999 650 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
<> 149:156823d33999 651 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
<> 149:156823d33999 652 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
<> 149:156823d33999 653 #define NOR_ERROR HAL_NOR_STATUS_ERROR
<> 149:156823d33999 654 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
<> 149:156823d33999 655
<> 149:156823d33999 656 #define __NOR_WRITE NOR_WRITE
<> 149:156823d33999 657 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
<> 149:156823d33999 658 /**
<> 149:156823d33999 659 * @}
<> 149:156823d33999 660 */
<> 149:156823d33999 661
<> 149:156823d33999 662 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
<> 149:156823d33999 663 * @{
<> 149:156823d33999 664 */
<> 149:156823d33999 665
<> 149:156823d33999 666 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
<> 149:156823d33999 667 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
<> 149:156823d33999 668 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
<> 149:156823d33999 669 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
<> 149:156823d33999 670
<> 149:156823d33999 671 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
<> 149:156823d33999 672 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
<> 149:156823d33999 673 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
<> 149:156823d33999 674 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
<> 149:156823d33999 675
<> 149:156823d33999 676 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
<> 149:156823d33999 677 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
<> 149:156823d33999 678
<> 149:156823d33999 679 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
<> 149:156823d33999 680 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
<> 149:156823d33999 681
<> 149:156823d33999 682 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
<> 149:156823d33999 683 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
<> 149:156823d33999 684
<> 149:156823d33999 685 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
<> 149:156823d33999 686
<> 149:156823d33999 687 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
<> 149:156823d33999 688 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
<> 149:156823d33999 689 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
<> 149:156823d33999 690
<> 149:156823d33999 691 /**
<> 149:156823d33999 692 * @}
<> 149:156823d33999 693 */
<> 149:156823d33999 694
<> 149:156823d33999 695 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
<> 149:156823d33999 696 * @{
<> 149:156823d33999 697 */
<> 149:156823d33999 698 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
<> 149:156823d33999 699 #if defined(STM32F7)
<> 149:156823d33999 700 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
<> 149:156823d33999 701 #endif
<> 149:156823d33999 702 /**
<> 149:156823d33999 703 * @}
<> 149:156823d33999 704 */
<> 149:156823d33999 705
<> 149:156823d33999 706 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
<> 149:156823d33999 707 * @{
<> 149:156823d33999 708 */
<> 149:156823d33999 709
<> 149:156823d33999 710 /* Compact Flash-ATA registers description */
<> 149:156823d33999 711 #define CF_DATA ATA_DATA
<> 149:156823d33999 712 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
<> 149:156823d33999 713 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
<> 149:156823d33999 714 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
<> 149:156823d33999 715 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
<> 149:156823d33999 716 #define CF_CARD_HEAD ATA_CARD_HEAD
<> 149:156823d33999 717 #define CF_STATUS_CMD ATA_STATUS_CMD
<> 149:156823d33999 718 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
<> 149:156823d33999 719 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
<> 149:156823d33999 720
<> 149:156823d33999 721 /* Compact Flash-ATA commands */
<> 149:156823d33999 722 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
<> 149:156823d33999 723 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
<> 149:156823d33999 724 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
<> 149:156823d33999 725 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
<> 149:156823d33999 726
<> 149:156823d33999 727 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
<> 149:156823d33999 728 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
<> 149:156823d33999 729 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
<> 149:156823d33999 730 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
<> 149:156823d33999 731 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
<> 149:156823d33999 732 /**
<> 149:156823d33999 733 * @}
<> 149:156823d33999 734 */
<> 149:156823d33999 735
<> 149:156823d33999 736 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
<> 149:156823d33999 737 * @{
<> 149:156823d33999 738 */
<> 149:156823d33999 739
<> 149:156823d33999 740 #define FORMAT_BIN RTC_FORMAT_BIN
<> 149:156823d33999 741 #define FORMAT_BCD RTC_FORMAT_BCD
<> 149:156823d33999 742
<> 149:156823d33999 743 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
<> 149:156823d33999 744 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
<> 149:156823d33999 745 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<> 149:156823d33999 746 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<> 149:156823d33999 747
<> 149:156823d33999 748 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<> 149:156823d33999 749 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<> 149:156823d33999 750 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
<> 149:156823d33999 751 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
<> 149:156823d33999 752 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
<> 149:156823d33999 753
<> 149:156823d33999 754 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
<> 149:156823d33999 755 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
<> 149:156823d33999 756 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
<> 149:156823d33999 757 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
<> 149:156823d33999 758
<> 149:156823d33999 759 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
<> 149:156823d33999 760 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
<> 149:156823d33999 761 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
<> 149:156823d33999 762
<> 149:156823d33999 763 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
<> 149:156823d33999 764 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
<> 149:156823d33999 765 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
<> 149:156823d33999 766
<> 149:156823d33999 767 /**
<> 149:156823d33999 768 * @}
<> 149:156823d33999 769 */
<> 149:156823d33999 770
<> 149:156823d33999 771
<> 149:156823d33999 772 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
<> 149:156823d33999 773 * @{
<> 149:156823d33999 774 */
<> 149:156823d33999 775 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
<> 149:156823d33999 776 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
<> 149:156823d33999 777
<> 149:156823d33999 778 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
<> 149:156823d33999 779 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
<> 149:156823d33999 780 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
<> 149:156823d33999 781 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
<> 149:156823d33999 782
<> 149:156823d33999 783 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
<> 149:156823d33999 784 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
<> 149:156823d33999 785
<> 149:156823d33999 786 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
<> 149:156823d33999 787 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
<> 149:156823d33999 788 /**
<> 149:156823d33999 789 * @}
<> 149:156823d33999 790 */
<> 149:156823d33999 791
<> 149:156823d33999 792
<> 149:156823d33999 793 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
<> 149:156823d33999 794 * @{
<> 149:156823d33999 795 */
<> 149:156823d33999 796 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
<> 149:156823d33999 797 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
<> 149:156823d33999 798 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
<> 149:156823d33999 799 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
<> 149:156823d33999 800 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
<> 149:156823d33999 801 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
<> 149:156823d33999 802 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
<> 149:156823d33999 803 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
<> 149:156823d33999 804 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
<> 149:156823d33999 805 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
<> 149:156823d33999 806 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
<> 149:156823d33999 807 /**
<> 149:156823d33999 808 * @}
<> 149:156823d33999 809 */
<> 149:156823d33999 810
<> 149:156823d33999 811 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
<> 149:156823d33999 812 * @{
<> 149:156823d33999 813 */
<> 149:156823d33999 814 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
<> 149:156823d33999 815 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
<> 149:156823d33999 816
<> 149:156823d33999 817 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
<> 149:156823d33999 818 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
<> 149:156823d33999 819
<> 149:156823d33999 820 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
<> 149:156823d33999 821 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
<> 149:156823d33999 822
<> 149:156823d33999 823 /**
<> 149:156823d33999 824 * @}
<> 149:156823d33999 825 */
<> 149:156823d33999 826
<> 149:156823d33999 827 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
<> 149:156823d33999 828 * @{
<> 149:156823d33999 829 */
<> 149:156823d33999 830 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
<> 149:156823d33999 831 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
<> 149:156823d33999 832
<> 149:156823d33999 833 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
<> 149:156823d33999 834 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
<> 149:156823d33999 835 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
<> 149:156823d33999 836 #define TIM_DMABase_DIER TIM_DMABASE_DIER
<> 149:156823d33999 837 #define TIM_DMABase_SR TIM_DMABASE_SR
<> 149:156823d33999 838 #define TIM_DMABase_EGR TIM_DMABASE_EGR
<> 149:156823d33999 839 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
<> 149:156823d33999 840 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
<> 149:156823d33999 841 #define TIM_DMABase_CCER TIM_DMABASE_CCER
<> 149:156823d33999 842 #define TIM_DMABase_CNT TIM_DMABASE_CNT
<> 149:156823d33999 843 #define TIM_DMABase_PSC TIM_DMABASE_PSC
<> 149:156823d33999 844 #define TIM_DMABase_ARR TIM_DMABASE_ARR
<> 149:156823d33999 845 #define TIM_DMABase_RCR TIM_DMABASE_RCR
<> 149:156823d33999 846 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
<> 149:156823d33999 847 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
<> 149:156823d33999 848 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
<> 149:156823d33999 849 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
<> 149:156823d33999 850 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
<> 149:156823d33999 851 #define TIM_DMABase_DCR TIM_DMABASE_DCR
<> 149:156823d33999 852 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
<> 149:156823d33999 853 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
<> 149:156823d33999 854 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
<> 149:156823d33999 855 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
<> 149:156823d33999 856 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
<> 149:156823d33999 857 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
<> 149:156823d33999 858 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
<> 149:156823d33999 859 #define TIM_DMABase_OR TIM_DMABASE_OR
<> 149:156823d33999 860
<> 149:156823d33999 861 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
<> 149:156823d33999 862 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
<> 149:156823d33999 863 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
<> 149:156823d33999 864 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
<> 149:156823d33999 865 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
<> 149:156823d33999 866 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
<> 149:156823d33999 867 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
<> 149:156823d33999 868 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
<> 149:156823d33999 869 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
<> 149:156823d33999 870
<> 149:156823d33999 871 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
<> 149:156823d33999 872 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
<> 149:156823d33999 873 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
<> 149:156823d33999 874 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
<> 149:156823d33999 875 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
<> 149:156823d33999 876 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
<> 149:156823d33999 877 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
<> 149:156823d33999 878 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
<> 149:156823d33999 879 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
<> 149:156823d33999 880 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
<> 149:156823d33999 881 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
<> 149:156823d33999 882 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
<> 149:156823d33999 883 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
<> 149:156823d33999 884 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
<> 149:156823d33999 885 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
<> 149:156823d33999 886 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
<> 149:156823d33999 887 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
<> 149:156823d33999 888 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
<> 149:156823d33999 889
<> 149:156823d33999 890 /**
<> 149:156823d33999 891 * @}
<> 149:156823d33999 892 */
<> 149:156823d33999 893
<> 149:156823d33999 894 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
<> 149:156823d33999 895 * @{
<> 149:156823d33999 896 */
<> 149:156823d33999 897 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
<> 149:156823d33999 898 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
<> 149:156823d33999 899 /**
<> 149:156823d33999 900 * @}
<> 149:156823d33999 901 */
<> 149:156823d33999 902
<> 149:156823d33999 903 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
<> 149:156823d33999 904 * @{
<> 149:156823d33999 905 */
<> 149:156823d33999 906 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<> 149:156823d33999 907 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<> 149:156823d33999 908 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<> 149:156823d33999 909 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<> 149:156823d33999 910
<> 149:156823d33999 911 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
<> 149:156823d33999 912 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
<> 149:156823d33999 913
<> 149:156823d33999 914 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
<> 149:156823d33999 915 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
<> 149:156823d33999 916 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
<> 149:156823d33999 917 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
<> 149:156823d33999 918
<> 149:156823d33999 919 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
<> 149:156823d33999 920 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
<> 149:156823d33999 921 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
<> 149:156823d33999 922 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
<> 149:156823d33999 923
AnnaBridge 184:08ed48f1de7f 924 #define __DIV_LPUART UART_DIV_LPUART
AnnaBridge 184:08ed48f1de7f 925
<> 149:156823d33999 926 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
<> 149:156823d33999 927 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
<> 149:156823d33999 928
<> 149:156823d33999 929 /**
<> 149:156823d33999 930 * @}
<> 149:156823d33999 931 */
<> 149:156823d33999 932
<> 149:156823d33999 933
<> 149:156823d33999 934 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
<> 149:156823d33999 935 * @{
<> 149:156823d33999 936 */
<> 149:156823d33999 937
<> 149:156823d33999 938 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<> 149:156823d33999 939 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<> 149:156823d33999 940
<> 149:156823d33999 941 #define USARTNACK_ENABLED USART_NACK_ENABLE
<> 149:156823d33999 942 #define USARTNACK_DISABLED USART_NACK_DISABLE
<> 149:156823d33999 943 /**
<> 149:156823d33999 944 * @}
<> 149:156823d33999 945 */
<> 149:156823d33999 946
<> 149:156823d33999 947 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
<> 149:156823d33999 948 * @{
<> 149:156823d33999 949 */
<> 149:156823d33999 950 #define CFR_BASE WWDG_CFR_BASE
<> 149:156823d33999 951
<> 149:156823d33999 952 /**
<> 149:156823d33999 953 * @}
<> 149:156823d33999 954 */
<> 149:156823d33999 955
<> 149:156823d33999 956 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
<> 149:156823d33999 957 * @{
<> 149:156823d33999 958 */
<> 149:156823d33999 959 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
<> 149:156823d33999 960 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
<> 149:156823d33999 961 #define CAN_IT_RQCP0 CAN_IT_TME
<> 149:156823d33999 962 #define CAN_IT_RQCP1 CAN_IT_TME
<> 149:156823d33999 963 #define CAN_IT_RQCP2 CAN_IT_TME
<> 149:156823d33999 964 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
<> 149:156823d33999 965 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<> 149:156823d33999 966 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<> 149:156823d33999 967 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
<> 149:156823d33999 968 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<> 149:156823d33999 969
<> 149:156823d33999 970 /**
<> 149:156823d33999 971 * @}
<> 149:156823d33999 972 */
<> 149:156823d33999 973
<> 149:156823d33999 974 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
<> 149:156823d33999 975 * @{
<> 149:156823d33999 976 */
<> 149:156823d33999 977
<> 149:156823d33999 978 #define VLAN_TAG ETH_VLAN_TAG
<> 149:156823d33999 979 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<> 149:156823d33999 980 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<> 149:156823d33999 981 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<> 149:156823d33999 982 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<> 149:156823d33999 983 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<> 149:156823d33999 984 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<> 149:156823d33999 985 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<> 149:156823d33999 986
AnnaBridge 184:08ed48f1de7f 987 #define ETH_MMCCR 0x00000100U
AnnaBridge 184:08ed48f1de7f 988 #define ETH_MMCRIR 0x00000104U
AnnaBridge 184:08ed48f1de7f 989 #define ETH_MMCTIR 0x00000108U
AnnaBridge 184:08ed48f1de7f 990 #define ETH_MMCRIMR 0x0000010CU
AnnaBridge 184:08ed48f1de7f 991 #define ETH_MMCTIMR 0x00000110U
AnnaBridge 184:08ed48f1de7f 992 #define ETH_MMCTGFSCCR 0x0000014CU
AnnaBridge 184:08ed48f1de7f 993 #define ETH_MMCTGFMSCCR 0x00000150U
AnnaBridge 184:08ed48f1de7f 994 #define ETH_MMCTGFCR 0x00000168U
AnnaBridge 184:08ed48f1de7f 995 #define ETH_MMCRFCECR 0x00000194U
AnnaBridge 184:08ed48f1de7f 996 #define ETH_MMCRFAECR 0x00000198U
AnnaBridge 184:08ed48f1de7f 997 #define ETH_MMCRGUFCR 0x000001C4U
<> 149:156823d33999 998
AnnaBridge 184:08ed48f1de7f 999 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
AnnaBridge 184:08ed48f1de7f 1000 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
AnnaBridge 184:08ed48f1de7f 1001 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
AnnaBridge 184:08ed48f1de7f 1002 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
AnnaBridge 184:08ed48f1de7f 1003 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
AnnaBridge 184:08ed48f1de7f 1004 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
AnnaBridge 184:08ed48f1de7f 1005 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge 184:08ed48f1de7f 1006 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
AnnaBridge 184:08ed48f1de7f 1007 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
AnnaBridge 184:08ed48f1de7f 1008 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge 184:08ed48f1de7f 1009 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge 184:08ed48f1de7f 1010 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
AnnaBridge 184:08ed48f1de7f 1011 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
AnnaBridge 184:08ed48f1de7f 1012 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
AnnaBridge 184:08ed48f1de7f 1013 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
AnnaBridge 184:08ed48f1de7f 1014 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
AnnaBridge 184:08ed48f1de7f 1015 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
<> 149:156823d33999 1016 #if defined(STM32F1)
<> 149:156823d33999 1017 #else
AnnaBridge 184:08ed48f1de7f 1018 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
AnnaBridge 184:08ed48f1de7f 1019 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
AnnaBridge 184:08ed48f1de7f 1020 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
<> 149:156823d33999 1021 #endif
AnnaBridge 184:08ed48f1de7f 1022 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
AnnaBridge 184:08ed48f1de7f 1023 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
AnnaBridge 184:08ed48f1de7f 1024 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
AnnaBridge 184:08ed48f1de7f 1025 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
AnnaBridge 184:08ed48f1de7f 1026 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
AnnaBridge 184:08ed48f1de7f 1027 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
AnnaBridge 184:08ed48f1de7f 1028 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
<> 149:156823d33999 1029
<> 149:156823d33999 1030 /**
<> 149:156823d33999 1031 * @}
<> 149:156823d33999 1032 */
<> 149:156823d33999 1033
<> 149:156823d33999 1034 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
<> 149:156823d33999 1035 * @{
<> 149:156823d33999 1036 */
<> 149:156823d33999 1037 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<> 149:156823d33999 1038 #define DCMI_IT_OVF DCMI_IT_OVR
<> 149:156823d33999 1039 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<> 149:156823d33999 1040 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<> 149:156823d33999 1041
<> 149:156823d33999 1042 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<> 149:156823d33999 1043 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<> 149:156823d33999 1044 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<> 149:156823d33999 1045
<> 149:156823d33999 1046 /**
<> 149:156823d33999 1047 * @}
<> 149:156823d33999 1048 */
<> 149:156823d33999 1049
AnnaBridge 184:08ed48f1de7f 1050 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
<> 149:156823d33999 1051 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 149:156823d33999 1052 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
<> 149:156823d33999 1053 * @{
<> 149:156823d33999 1054 */
<> 149:156823d33999 1055 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
<> 149:156823d33999 1056 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
<> 149:156823d33999 1057 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
<> 149:156823d33999 1058 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
<> 149:156823d33999 1059 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
<> 149:156823d33999 1060
<> 149:156823d33999 1061 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
<> 149:156823d33999 1062 #define CM_RGB888 DMA2D_INPUT_RGB888
<> 149:156823d33999 1063 #define CM_RGB565 DMA2D_INPUT_RGB565
<> 149:156823d33999 1064 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
<> 149:156823d33999 1065 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
<> 149:156823d33999 1066 #define CM_L8 DMA2D_INPUT_L8
<> 149:156823d33999 1067 #define CM_AL44 DMA2D_INPUT_AL44
<> 149:156823d33999 1068 #define CM_AL88 DMA2D_INPUT_AL88
<> 149:156823d33999 1069 #define CM_L4 DMA2D_INPUT_L4
<> 149:156823d33999 1070 #define CM_A8 DMA2D_INPUT_A8
<> 149:156823d33999 1071 #define CM_A4 DMA2D_INPUT_A4
<> 149:156823d33999 1072 /**
<> 149:156823d33999 1073 * @}
<> 149:156823d33999 1074 */
AnnaBridge 184:08ed48f1de7f 1075 #endif /* STM32L4 || STM32F7*/
<> 149:156823d33999 1076
<> 149:156823d33999 1077 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
<> 149:156823d33999 1078 * @{
<> 149:156823d33999 1079 */
<> 149:156823d33999 1080
<> 149:156823d33999 1081 /**
<> 149:156823d33999 1082 * @}
<> 149:156823d33999 1083 */
<> 149:156823d33999 1084
<> 149:156823d33999 1085 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 1086
<> 149:156823d33999 1087 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1088 * @{
<> 149:156823d33999 1089 */
<> 149:156823d33999 1090 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<> 149:156823d33999 1091 /**
<> 149:156823d33999 1092 * @}
<> 149:156823d33999 1093 */
<> 149:156823d33999 1094
<> 149:156823d33999 1095 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1096 * @{
<> 149:156823d33999 1097 */
<> 149:156823d33999 1098 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<> 149:156823d33999 1099 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<> 149:156823d33999 1100 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<> 149:156823d33999 1101 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<> 149:156823d33999 1102 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<> 149:156823d33999 1103 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<> 149:156823d33999 1104
<> 149:156823d33999 1105 /*HASH Algorithm Selection*/
<> 149:156823d33999 1106
<> 149:156823d33999 1107 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<> 149:156823d33999 1108 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<> 149:156823d33999 1109 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<> 149:156823d33999 1110 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<> 149:156823d33999 1111
<> 149:156823d33999 1112 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<> 149:156823d33999 1113 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<> 149:156823d33999 1114
<> 149:156823d33999 1115 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<> 149:156823d33999 1116 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<> 149:156823d33999 1117 /**
<> 149:156823d33999 1118 * @}
<> 149:156823d33999 1119 */
<> 149:156823d33999 1120
<> 149:156823d33999 1121 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1122 * @{
<> 149:156823d33999 1123 */
<> 149:156823d33999 1124 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<> 149:156823d33999 1125 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<> 149:156823d33999 1126 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<> 149:156823d33999 1127 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<> 149:156823d33999 1128 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<> 149:156823d33999 1129 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<> 149:156823d33999 1130 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<> 149:156823d33999 1131 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<> 149:156823d33999 1132 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
<> 149:156823d33999 1133 #if defined(STM32L0)
<> 149:156823d33999 1134 #else
<> 149:156823d33999 1135 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
<> 149:156823d33999 1136 #endif
<> 149:156823d33999 1137 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
<> 149:156823d33999 1138 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
<> 149:156823d33999 1139 /**
<> 149:156823d33999 1140 * @}
<> 149:156823d33999 1141 */
<> 149:156823d33999 1142
<> 149:156823d33999 1143 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1144 * @{
<> 149:156823d33999 1145 */
<> 149:156823d33999 1146 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
<> 149:156823d33999 1147 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
<> 149:156823d33999 1148 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
<> 149:156823d33999 1149 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
<> 149:156823d33999 1150 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
<> 149:156823d33999 1151 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
<> 149:156823d33999 1152 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
<> 149:156823d33999 1153
<> 149:156823d33999 1154 /**
<> 149:156823d33999 1155 * @}
<> 149:156823d33999 1156 */
<> 149:156823d33999 1157
<> 149:156823d33999 1158 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1159 * @{
<> 149:156823d33999 1160 */
<> 149:156823d33999 1161 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
<> 149:156823d33999 1162 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
<> 149:156823d33999 1163 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
<> 149:156823d33999 1164 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
<> 149:156823d33999 1165
<> 149:156823d33999 1166 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
<> 149:156823d33999 1167 /**
<> 149:156823d33999 1168 * @}
<> 149:156823d33999 1169 */
<> 149:156823d33999 1170
<> 149:156823d33999 1171 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
<> 149:156823d33999 1172 * @{
<> 149:156823d33999 1173 */
<> 149:156823d33999 1174 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
<> 149:156823d33999 1175 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
<> 149:156823d33999 1176 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
<> 149:156823d33999 1177 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
<> 149:156823d33999 1178 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
<> 149:156823d33999 1179 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
<> 149:156823d33999 1180 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
<> 149:156823d33999 1181 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
<> 149:156823d33999 1182 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
<> 149:156823d33999 1183 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
<> 149:156823d33999 1184 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
<> 149:156823d33999 1185 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
<> 149:156823d33999 1186 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
<> 149:156823d33999 1187 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
<> 149:156823d33999 1188 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
<> 149:156823d33999 1189 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
<> 149:156823d33999 1190
<> 149:156823d33999 1191 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
<> 149:156823d33999 1192 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
<> 149:156823d33999 1193 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
<> 149:156823d33999 1194 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
<> 149:156823d33999 1195 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
<> 149:156823d33999 1196 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
<> 149:156823d33999 1197 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
<> 149:156823d33999 1198
<> 149:156823d33999 1199 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
<> 149:156823d33999 1200 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
<> 149:156823d33999 1201
<> 149:156823d33999 1202 #define DBP_BitNumber DBP_BIT_NUMBER
<> 149:156823d33999 1203 #define PVDE_BitNumber PVDE_BIT_NUMBER
<> 149:156823d33999 1204 #define PMODE_BitNumber PMODE_BIT_NUMBER
<> 149:156823d33999 1205 #define EWUP_BitNumber EWUP_BIT_NUMBER
<> 149:156823d33999 1206 #define FPDS_BitNumber FPDS_BIT_NUMBER
<> 149:156823d33999 1207 #define ODEN_BitNumber ODEN_BIT_NUMBER
<> 149:156823d33999 1208 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
<> 149:156823d33999 1209 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
<> 149:156823d33999 1210 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
<> 149:156823d33999 1211 #define BRE_BitNumber BRE_BIT_NUMBER
<> 149:156823d33999 1212
<> 149:156823d33999 1213 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
<> 149:156823d33999 1214
<> 149:156823d33999 1215 /**
<> 149:156823d33999 1216 * @}
<> 149:156823d33999 1217 */
<> 149:156823d33999 1218
<> 149:156823d33999 1219 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1220 * @{
<> 149:156823d33999 1221 */
<> 149:156823d33999 1222 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
<> 149:156823d33999 1223 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
<> 149:156823d33999 1224 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
<> 149:156823d33999 1225 /**
<> 149:156823d33999 1226 * @}
<> 149:156823d33999 1227 */
<> 149:156823d33999 1228
<> 149:156823d33999 1229 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1230 * @{
<> 149:156823d33999 1231 */
<> 149:156823d33999 1232 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
<> 149:156823d33999 1233 /**
<> 149:156823d33999 1234 * @}
<> 149:156823d33999 1235 */
<> 149:156823d33999 1236
<> 149:156823d33999 1237 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1238 * @{
<> 149:156823d33999 1239 */
<> 149:156823d33999 1240 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
<> 149:156823d33999 1241 #define HAL_TIM_DMAError TIM_DMAError
<> 149:156823d33999 1242 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
<> 149:156823d33999 1243 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
<> 149:156823d33999 1244 /**
<> 149:156823d33999 1245 * @}
<> 149:156823d33999 1246 */
<> 149:156823d33999 1247
<> 149:156823d33999 1248 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1249 * @{
<> 149:156823d33999 1250 */
<> 149:156823d33999 1251 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
<> 149:156823d33999 1252 /**
<> 149:156823d33999 1253 * @}
<> 149:156823d33999 1254 */
<> 149:156823d33999 1255
<> 149:156823d33999 1256 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1257 * @{
<> 149:156823d33999 1258 */
<> 149:156823d33999 1259 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
AnnaBridge 184:08ed48f1de7f 1260 #define HAL_LTDC_Relaod HAL_LTDC_Reload
AnnaBridge 184:08ed48f1de7f 1261 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
AnnaBridge 184:08ed48f1de7f 1262 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
<> 149:156823d33999 1263 /**
<> 149:156823d33999 1264 * @}
<> 149:156823d33999 1265 */
<> 149:156823d33999 1266
<> 149:156823d33999 1267
<> 149:156823d33999 1268 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1269 * @{
<> 149:156823d33999 1270 */
<> 149:156823d33999 1271
<> 149:156823d33999 1272 /**
<> 149:156823d33999 1273 * @}
<> 149:156823d33999 1274 */
<> 149:156823d33999 1275
<> 149:156823d33999 1276 /* Exported macros ------------------------------------------------------------*/
<> 149:156823d33999 1277
<> 149:156823d33999 1278 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1279 * @{
<> 149:156823d33999 1280 */
<> 149:156823d33999 1281 #define AES_IT_CC CRYP_IT_CC
<> 149:156823d33999 1282 #define AES_IT_ERR CRYP_IT_ERR
<> 149:156823d33999 1283 #define AES_FLAG_CCF CRYP_FLAG_CCF
<> 149:156823d33999 1284 /**
<> 149:156823d33999 1285 * @}
<> 149:156823d33999 1286 */
<> 149:156823d33999 1287
<> 149:156823d33999 1288 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1289 * @{
<> 149:156823d33999 1290 */
<> 149:156823d33999 1291 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
<> 149:156823d33999 1292 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
<> 149:156823d33999 1293 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
<> 149:156823d33999 1294 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
<> 149:156823d33999 1295 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
<> 149:156823d33999 1296 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
<> 149:156823d33999 1297 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
<> 149:156823d33999 1298 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
<> 149:156823d33999 1299 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
<> 149:156823d33999 1300 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
<> 149:156823d33999 1301 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
<> 149:156823d33999 1302 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
<> 149:156823d33999 1303 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
AnnaBridge 184:08ed48f1de7f 1304 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
<> 149:156823d33999 1305
<> 149:156823d33999 1306 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
<> 149:156823d33999 1307 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
<> 149:156823d33999 1308 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
<> 149:156823d33999 1309 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
<> 149:156823d33999 1310 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
<> 149:156823d33999 1311
<> 149:156823d33999 1312 /**
<> 149:156823d33999 1313 * @}
<> 149:156823d33999 1314 */
<> 149:156823d33999 1315
<> 149:156823d33999 1316
<> 149:156823d33999 1317 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1318 * @{
<> 149:156823d33999 1319 */
<> 149:156823d33999 1320 #define __ADC_ENABLE __HAL_ADC_ENABLE
<> 149:156823d33999 1321 #define __ADC_DISABLE __HAL_ADC_DISABLE
<> 149:156823d33999 1322 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
<> 149:156823d33999 1323 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
<> 149:156823d33999 1324 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
<> 149:156823d33999 1325 #define __ADC_IS_ENABLED ADC_IS_ENABLE
<> 149:156823d33999 1326 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
<> 149:156823d33999 1327 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
<> 149:156823d33999 1328 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
<> 149:156823d33999 1329 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
<> 149:156823d33999 1330 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
<> 149:156823d33999 1331 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
<> 149:156823d33999 1332 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
<> 149:156823d33999 1333
<> 149:156823d33999 1334 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
<> 149:156823d33999 1335 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
<> 149:156823d33999 1336 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
<> 149:156823d33999 1337 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
<> 149:156823d33999 1338 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
<> 149:156823d33999 1339 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
<> 149:156823d33999 1340 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
<> 149:156823d33999 1341 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
<> 149:156823d33999 1342 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
<> 149:156823d33999 1343 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
<> 149:156823d33999 1344 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
<> 149:156823d33999 1345 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
<> 149:156823d33999 1346 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
<> 149:156823d33999 1347 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
<> 149:156823d33999 1348 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
<> 149:156823d33999 1349 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
<> 149:156823d33999 1350 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
<> 149:156823d33999 1351 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
<> 149:156823d33999 1352 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
<> 149:156823d33999 1353 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
<> 149:156823d33999 1354
<> 149:156823d33999 1355 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
<> 149:156823d33999 1356 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
<> 149:156823d33999 1357 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
<> 149:156823d33999 1358 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
<> 149:156823d33999 1359 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
<> 149:156823d33999 1360 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
<> 149:156823d33999 1361 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
<> 149:156823d33999 1362 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
<> 149:156823d33999 1363 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
<> 149:156823d33999 1364 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
<> 149:156823d33999 1365
<> 149:156823d33999 1366 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
<> 149:156823d33999 1367 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
<> 149:156823d33999 1368 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
<> 149:156823d33999 1369 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
<> 149:156823d33999 1370 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
<> 149:156823d33999 1371 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
<> 149:156823d33999 1372 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
<> 149:156823d33999 1373 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
<> 149:156823d33999 1374
<> 149:156823d33999 1375 #define __HAL_ADC_SQR1 ADC_SQR1
<> 149:156823d33999 1376 #define __HAL_ADC_SMPR1 ADC_SMPR1
<> 149:156823d33999 1377 #define __HAL_ADC_SMPR2 ADC_SMPR2
<> 149:156823d33999 1378 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
<> 149:156823d33999 1379 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
<> 149:156823d33999 1380 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
<> 149:156823d33999 1381 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
<> 149:156823d33999 1382 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
<> 149:156823d33999 1383 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
<> 149:156823d33999 1384 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
<> 149:156823d33999 1385 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
<> 149:156823d33999 1386 #define __HAL_ADC_JSQR ADC_JSQR
<> 149:156823d33999 1387
<> 149:156823d33999 1388 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
<> 149:156823d33999 1389 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
<> 149:156823d33999 1390 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
<> 149:156823d33999 1391 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
<> 149:156823d33999 1392 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
<> 149:156823d33999 1393 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
<> 149:156823d33999 1394 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
<> 149:156823d33999 1395 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
<> 149:156823d33999 1396
<> 149:156823d33999 1397 /**
<> 149:156823d33999 1398 * @}
<> 149:156823d33999 1399 */
<> 149:156823d33999 1400
<> 149:156823d33999 1401 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1402 * @{
<> 149:156823d33999 1403 */
<> 149:156823d33999 1404 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
<> 149:156823d33999 1405 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
<> 149:156823d33999 1406 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
<> 149:156823d33999 1407 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
<> 149:156823d33999 1408
<> 149:156823d33999 1409 /**
<> 149:156823d33999 1410 * @}
<> 149:156823d33999 1411 */
<> 149:156823d33999 1412
<> 149:156823d33999 1413 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1414 * @{
<> 149:156823d33999 1415 */
<> 149:156823d33999 1416 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
<> 149:156823d33999 1417 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
<> 149:156823d33999 1418 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
<> 149:156823d33999 1419 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
<> 149:156823d33999 1420 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
<> 149:156823d33999 1421 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
<> 149:156823d33999 1422 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
<> 149:156823d33999 1423 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
<> 149:156823d33999 1424 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
<> 149:156823d33999 1425 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
<> 149:156823d33999 1426 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
<> 149:156823d33999 1427 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
<> 149:156823d33999 1428 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
<> 149:156823d33999 1429 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
<> 149:156823d33999 1430 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
<> 149:156823d33999 1431 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
<> 149:156823d33999 1432
<> 149:156823d33999 1433 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
<> 149:156823d33999 1434 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
<> 149:156823d33999 1435 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
<> 149:156823d33999 1436 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
<> 149:156823d33999 1437 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
<> 149:156823d33999 1438 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
<> 149:156823d33999 1439 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
<> 149:156823d33999 1440 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
<> 149:156823d33999 1441 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
<> 149:156823d33999 1442 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
<> 149:156823d33999 1443 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
<> 149:156823d33999 1444 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
<> 149:156823d33999 1445 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
<> 149:156823d33999 1446 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
<> 149:156823d33999 1447
<> 149:156823d33999 1448
<> 149:156823d33999 1449 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
<> 149:156823d33999 1450 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
<> 149:156823d33999 1451 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
<> 149:156823d33999 1452 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
<> 149:156823d33999 1453 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
<> 149:156823d33999 1454 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
<> 149:156823d33999 1455 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
<> 149:156823d33999 1456 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
<> 149:156823d33999 1457 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
<> 149:156823d33999 1458 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
<> 149:156823d33999 1459 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
<> 149:156823d33999 1460 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
<> 149:156823d33999 1461 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
<> 149:156823d33999 1462 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
<> 149:156823d33999 1463 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
<> 149:156823d33999 1464 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
<> 149:156823d33999 1465 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
<> 149:156823d33999 1466 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
<> 149:156823d33999 1467 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
<> 149:156823d33999 1468 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
<> 149:156823d33999 1469 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
<> 149:156823d33999 1470 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
<> 149:156823d33999 1471 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
<> 149:156823d33999 1472 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
<> 149:156823d33999 1473
<> 149:156823d33999 1474 /**
<> 149:156823d33999 1475 * @}
<> 149:156823d33999 1476 */
<> 149:156823d33999 1477
<> 149:156823d33999 1478 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1479 * @{
<> 149:156823d33999 1480 */
<> 149:156823d33999 1481 #if defined(STM32F3)
<> 149:156823d33999 1482 #define COMP_START __HAL_COMP_ENABLE
<> 149:156823d33999 1483 #define COMP_STOP __HAL_COMP_DISABLE
<> 149:156823d33999 1484 #define COMP_LOCK __HAL_COMP_LOCK
<> 149:156823d33999 1485
<> 149:156823d33999 1486 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 149:156823d33999 1487 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1488 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1489 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
<> 149:156823d33999 1490 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1491 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1492 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
<> 149:156823d33999 1493 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1494 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1495 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
<> 149:156823d33999 1496 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1497 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1498 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
<> 149:156823d33999 1499 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1500 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1501 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
<> 149:156823d33999 1502 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1503 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1504 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
<> 149:156823d33999 1505 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<> 149:156823d33999 1506 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<> 149:156823d33999 1507 __HAL_COMP_COMP6_EXTI_GET_FLAG())
<> 149:156823d33999 1508 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1509 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1510 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
<> 149:156823d33999 1511 # endif
<> 149:156823d33999 1512 # if defined(STM32F302xE) || defined(STM32F302xC)
<> 149:156823d33999 1513 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1514 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1515 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1516 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
<> 149:156823d33999 1517 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1518 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1519 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1520 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
<> 149:156823d33999 1521 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1522 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1523 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1524 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
<> 149:156823d33999 1525 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1526 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1527 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1528 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
<> 149:156823d33999 1529 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1530 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1531 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1532 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
<> 149:156823d33999 1533 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1534 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1535 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1536 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
<> 149:156823d33999 1537 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 149:156823d33999 1538 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<> 149:156823d33999 1539 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<> 149:156823d33999 1540 __HAL_COMP_COMP6_EXTI_GET_FLAG())
<> 149:156823d33999 1541 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1542 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1543 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1544 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
<> 149:156823d33999 1545 # endif
<> 149:156823d33999 1546 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
<> 149:156823d33999 1547 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1548 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1549 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1550 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1551 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1552 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1553 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
<> 149:156823d33999 1554 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1555 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1556 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1557 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1558 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1559 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1560 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
<> 149:156823d33999 1561 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1562 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1563 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1564 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1565 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1566 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1567 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
<> 149:156823d33999 1568 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1569 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1570 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1571 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1572 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1573 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1574 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
<> 149:156823d33999 1575 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1576 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1577 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1578 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1579 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1580 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1581 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
<> 149:156823d33999 1582 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1583 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1584 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1585 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1586 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1587 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1588 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
<> 149:156823d33999 1589 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 149:156823d33999 1590 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<> 149:156823d33999 1591 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
<> 149:156823d33999 1592 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<> 149:156823d33999 1593 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
<> 149:156823d33999 1594 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
<> 149:156823d33999 1595 __HAL_COMP_COMP7_EXTI_GET_FLAG())
<> 149:156823d33999 1596 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1597 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1598 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1599 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1600 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1601 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1602 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
<> 149:156823d33999 1603 # endif
<> 149:156823d33999 1604 # if defined(STM32F373xC) ||defined(STM32F378xx)
<> 149:156823d33999 1605 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1606 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
<> 149:156823d33999 1607 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1608 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
<> 149:156823d33999 1609 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1610 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
<> 149:156823d33999 1611 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1612 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
<> 149:156823d33999 1613 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1614 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
<> 149:156823d33999 1615 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1616 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
<> 149:156823d33999 1617 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 149:156823d33999 1618 __HAL_COMP_COMP2_EXTI_GET_FLAG())
<> 149:156823d33999 1619 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1620 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
<> 149:156823d33999 1621 # endif
<> 149:156823d33999 1622 #else
<> 149:156823d33999 1623 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 149:156823d33999 1624 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
<> 149:156823d33999 1625 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 149:156823d33999 1626 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
<> 149:156823d33999 1627 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 149:156823d33999 1628 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
<> 149:156823d33999 1629 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 149:156823d33999 1630 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
<> 149:156823d33999 1631 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 149:156823d33999 1632 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
<> 149:156823d33999 1633 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 149:156823d33999 1634 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
<> 149:156823d33999 1635 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 149:156823d33999 1636 __HAL_COMP_COMP2_EXTI_GET_FLAG())
<> 149:156823d33999 1637 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 1638 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
<> 149:156823d33999 1639 #endif
<> 149:156823d33999 1640
<> 149:156823d33999 1641 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
<> 149:156823d33999 1642
<> 149:156823d33999 1643 #if defined(STM32L0) || defined(STM32L4)
<> 149:156823d33999 1644 /* Note: On these STM32 families, the only argument of this macro */
<> 149:156823d33999 1645 /* is COMP_FLAG_LOCK. */
<> 149:156823d33999 1646 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
<> 149:156823d33999 1647 /* argument. */
<> 149:156823d33999 1648 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
<> 149:156823d33999 1649 #endif
<> 149:156823d33999 1650 /**
<> 149:156823d33999 1651 * @}
<> 149:156823d33999 1652 */
<> 149:156823d33999 1653
<> 149:156823d33999 1654 #if defined(STM32L0) || defined(STM32L4)
<> 149:156823d33999 1655 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
<> 149:156823d33999 1656 * @{
<> 149:156823d33999 1657 */
<> 149:156823d33999 1658 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
<> 149:156823d33999 1659 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
<> 149:156823d33999 1660 /**
<> 149:156823d33999 1661 * @}
<> 149:156823d33999 1662 */
<> 149:156823d33999 1663 #endif
<> 149:156823d33999 1664
<> 149:156823d33999 1665 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1666 * @{
<> 149:156823d33999 1667 */
<> 149:156823d33999 1668
<> 149:156823d33999 1669 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
<> 149:156823d33999 1670 ((WAVE) == DAC_WAVE_NOISE)|| \
<> 149:156823d33999 1671 ((WAVE) == DAC_WAVE_TRIANGLE))
<> 149:156823d33999 1672
<> 149:156823d33999 1673 /**
<> 149:156823d33999 1674 * @}
<> 149:156823d33999 1675 */
<> 149:156823d33999 1676
<> 149:156823d33999 1677 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1678 * @{
<> 149:156823d33999 1679 */
<> 149:156823d33999 1680
<> 149:156823d33999 1681 #define IS_WRPAREA IS_OB_WRPAREA
<> 149:156823d33999 1682 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
<> 149:156823d33999 1683 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
<> 149:156823d33999 1684 #define IS_TYPEERASE IS_FLASH_TYPEERASE
<> 149:156823d33999 1685 #define IS_NBSECTORS IS_FLASH_NBSECTORS
<> 149:156823d33999 1686 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
<> 149:156823d33999 1687
<> 149:156823d33999 1688 /**
<> 149:156823d33999 1689 * @}
<> 149:156823d33999 1690 */
<> 149:156823d33999 1691
<> 149:156823d33999 1692 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1693 * @{
<> 149:156823d33999 1694 */
<> 149:156823d33999 1695
<> 149:156823d33999 1696 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
<> 149:156823d33999 1697 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
AnnaBridge 184:08ed48f1de7f 1698 #if defined(STM32F1)
AnnaBridge 184:08ed48f1de7f 1699 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
AnnaBridge 184:08ed48f1de7f 1700 #else
<> 149:156823d33999 1701 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
AnnaBridge 184:08ed48f1de7f 1702 #endif /* STM32F1 */
<> 149:156823d33999 1703 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
<> 149:156823d33999 1704 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
<> 149:156823d33999 1705 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
<> 149:156823d33999 1706 #define __HAL_I2C_SPEED I2C_SPEED
<> 149:156823d33999 1707 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
<> 149:156823d33999 1708 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
<> 149:156823d33999 1709 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
<> 149:156823d33999 1710 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
<> 149:156823d33999 1711 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
<> 149:156823d33999 1712 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
<> 149:156823d33999 1713 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
<> 149:156823d33999 1714 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
<> 149:156823d33999 1715 /**
<> 149:156823d33999 1716 * @}
<> 149:156823d33999 1717 */
<> 149:156823d33999 1718
<> 149:156823d33999 1719 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1720 * @{
<> 149:156823d33999 1721 */
<> 149:156823d33999 1722
<> 149:156823d33999 1723 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
<> 149:156823d33999 1724 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
<> 149:156823d33999 1725
<> 149:156823d33999 1726 /**
<> 149:156823d33999 1727 * @}
<> 149:156823d33999 1728 */
<> 149:156823d33999 1729
<> 149:156823d33999 1730 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1731 * @{
<> 149:156823d33999 1732 */
<> 149:156823d33999 1733
<> 149:156823d33999 1734 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
<> 149:156823d33999 1735 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
<> 149:156823d33999 1736
<> 149:156823d33999 1737 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
<> 149:156823d33999 1738 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
<> 149:156823d33999 1739 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
<> 149:156823d33999 1740 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
<> 149:156823d33999 1741
<> 149:156823d33999 1742 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
<> 149:156823d33999 1743
<> 149:156823d33999 1744
<> 149:156823d33999 1745 /**
<> 149:156823d33999 1746 * @}
<> 149:156823d33999 1747 */
<> 149:156823d33999 1748
<> 149:156823d33999 1749
<> 149:156823d33999 1750 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1751 * @{
<> 149:156823d33999 1752 */
<> 149:156823d33999 1753 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
<> 149:156823d33999 1754 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
<> 149:156823d33999 1755 /**
<> 149:156823d33999 1756 * @}
<> 149:156823d33999 1757 */
<> 149:156823d33999 1758
<> 149:156823d33999 1759
<> 149:156823d33999 1760 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1761 * @{
<> 149:156823d33999 1762 */
<> 149:156823d33999 1763
<> 149:156823d33999 1764 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
<> 149:156823d33999 1765 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
<> 149:156823d33999 1766 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
<> 149:156823d33999 1767
<> 149:156823d33999 1768 /**
<> 149:156823d33999 1769 * @}
<> 149:156823d33999 1770 */
<> 149:156823d33999 1771
<> 149:156823d33999 1772
<> 149:156823d33999 1773 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1774 * @{
<> 149:156823d33999 1775 */
<> 149:156823d33999 1776 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
<> 149:156823d33999 1777 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
<> 149:156823d33999 1778 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
<> 149:156823d33999 1779 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
<> 149:156823d33999 1780 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
<> 149:156823d33999 1781 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
<> 149:156823d33999 1782 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
<> 149:156823d33999 1783 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
<> 149:156823d33999 1784 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
<> 149:156823d33999 1785 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
<> 149:156823d33999 1786 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
<> 149:156823d33999 1787 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
<> 149:156823d33999 1788 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
<> 149:156823d33999 1789
<> 149:156823d33999 1790 /**
<> 149:156823d33999 1791 * @}
<> 149:156823d33999 1792 */
<> 149:156823d33999 1793
<> 149:156823d33999 1794
<> 149:156823d33999 1795 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
<> 149:156823d33999 1796 * @{
<> 149:156823d33999 1797 */
<> 149:156823d33999 1798 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
<> 149:156823d33999 1799 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
<> 149:156823d33999 1800 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
<> 149:156823d33999 1801 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<> 149:156823d33999 1802 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
<> 149:156823d33999 1803 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<> 149:156823d33999 1804 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
<> 149:156823d33999 1805 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
<> 149:156823d33999 1806 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
<> 149:156823d33999 1807 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
<> 149:156823d33999 1808 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
<> 149:156823d33999 1809 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
<> 149:156823d33999 1810 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
<> 149:156823d33999 1811 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
<> 149:156823d33999 1812 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
<> 149:156823d33999 1813 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
<> 149:156823d33999 1814 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
<> 149:156823d33999 1815 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
<> 149:156823d33999 1816 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
<> 149:156823d33999 1817 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
<> 149:156823d33999 1818 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<> 149:156823d33999 1819 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
<> 149:156823d33999 1820 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<> 149:156823d33999 1821 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<> 149:156823d33999 1822 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<> 149:156823d33999 1823 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
<> 149:156823d33999 1824 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
<> 149:156823d33999 1825 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
<> 149:156823d33999 1826 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
<> 149:156823d33999 1827 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
<> 149:156823d33999 1828 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
<> 149:156823d33999 1829 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
<> 149:156823d33999 1830 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
<> 149:156823d33999 1831 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
<> 149:156823d33999 1832 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
<> 149:156823d33999 1833
<> 149:156823d33999 1834 #if defined (STM32F4)
<> 149:156823d33999 1835 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
<> 149:156823d33999 1836 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
<> 149:156823d33999 1837 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
<> 149:156823d33999 1838 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
<> 149:156823d33999 1839 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
<> 149:156823d33999 1840 #else
<> 149:156823d33999 1841 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
<> 149:156823d33999 1842 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
<> 149:156823d33999 1843 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
<> 149:156823d33999 1844 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
<> 149:156823d33999 1845 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
<> 149:156823d33999 1846 #endif /* STM32F4 */
<> 149:156823d33999 1847 /**
<> 149:156823d33999 1848 * @}
<> 149:156823d33999 1849 */
<> 149:156823d33999 1850
<> 149:156823d33999 1851
<> 149:156823d33999 1852 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
<> 149:156823d33999 1853 * @{
<> 149:156823d33999 1854 */
<> 149:156823d33999 1855
<> 149:156823d33999 1856 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
<> 149:156823d33999 1857 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
<> 149:156823d33999 1858
<> 149:156823d33999 1859 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
<> 149:156823d33999 1860 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
<> 149:156823d33999 1861
AnnaBridge 184:08ed48f1de7f 1862 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 1863 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
AnnaBridge 184:08ed48f1de7f 1864 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
AnnaBridge 184:08ed48f1de7f 1865 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
AnnaBridge 184:08ed48f1de7f 1866 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
AnnaBridge 184:08ed48f1de7f 1867 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
AnnaBridge 184:08ed48f1de7f 1868 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 1869 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
AnnaBridge 184:08ed48f1de7f 1870 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
AnnaBridge 184:08ed48f1de7f 1871 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
AnnaBridge 184:08ed48f1de7f 1872 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
AnnaBridge 184:08ed48f1de7f 1873 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
AnnaBridge 184:08ed48f1de7f 1874 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 1875 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
<> 149:156823d33999 1876 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
<> 149:156823d33999 1877 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
<> 149:156823d33999 1878 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
<> 149:156823d33999 1879 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
<> 149:156823d33999 1880 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
<> 149:156823d33999 1881 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
<> 149:156823d33999 1882 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
<> 149:156823d33999 1883 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
<> 149:156823d33999 1884 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
<> 149:156823d33999 1885 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
<> 149:156823d33999 1886 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
<> 149:156823d33999 1887 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
<> 149:156823d33999 1888 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
<> 149:156823d33999 1889 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
<> 149:156823d33999 1890 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
<> 149:156823d33999 1891 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 1892 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
<> 149:156823d33999 1893 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
<> 149:156823d33999 1894 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
<> 149:156823d33999 1895 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
<> 149:156823d33999 1896 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
<> 149:156823d33999 1897 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
<> 149:156823d33999 1898 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
<> 149:156823d33999 1899 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
<> 149:156823d33999 1900 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
<> 149:156823d33999 1901 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
<> 149:156823d33999 1902 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
<> 149:156823d33999 1903 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
<> 149:156823d33999 1904 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
<> 149:156823d33999 1905 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
<> 149:156823d33999 1906 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
<> 149:156823d33999 1907 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
<> 149:156823d33999 1908 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
<> 149:156823d33999 1909 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
<> 149:156823d33999 1910 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
<> 149:156823d33999 1911 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
<> 149:156823d33999 1912 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
<> 149:156823d33999 1913 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
<> 149:156823d33999 1914 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
<> 149:156823d33999 1915 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
<> 149:156823d33999 1916 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
<> 149:156823d33999 1917 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
<> 149:156823d33999 1918 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
<> 149:156823d33999 1919 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
<> 149:156823d33999 1920 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
<> 149:156823d33999 1921 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
<> 149:156823d33999 1922 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
<> 149:156823d33999 1923 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
<> 149:156823d33999 1924 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
<> 149:156823d33999 1925 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
<> 149:156823d33999 1926 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
<> 149:156823d33999 1927 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
<> 149:156823d33999 1928 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
<> 149:156823d33999 1929 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
<> 149:156823d33999 1930 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
<> 149:156823d33999 1931 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
<> 149:156823d33999 1932 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
<> 149:156823d33999 1933 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
<> 149:156823d33999 1934 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
<> 149:156823d33999 1935 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
<> 149:156823d33999 1936 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
<> 149:156823d33999 1937 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
<> 149:156823d33999 1938 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
<> 149:156823d33999 1939 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
<> 149:156823d33999 1940 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
<> 149:156823d33999 1941 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
<> 149:156823d33999 1942 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
<> 149:156823d33999 1943 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
<> 149:156823d33999 1944 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
<> 149:156823d33999 1945 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
<> 149:156823d33999 1946 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
<> 149:156823d33999 1947 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
<> 149:156823d33999 1948 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
<> 149:156823d33999 1949 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
<> 149:156823d33999 1950 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
<> 149:156823d33999 1951 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
<> 149:156823d33999 1952 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
<> 149:156823d33999 1953 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
<> 149:156823d33999 1954 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
<> 149:156823d33999 1955 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
<> 149:156823d33999 1956 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
<> 149:156823d33999 1957 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
<> 149:156823d33999 1958 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
<> 149:156823d33999 1959 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
<> 149:156823d33999 1960 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
<> 149:156823d33999 1961 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
<> 149:156823d33999 1962 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
<> 149:156823d33999 1963 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
<> 149:156823d33999 1964 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
<> 149:156823d33999 1965 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
<> 149:156823d33999 1966 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
<> 149:156823d33999 1967 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
<> 149:156823d33999 1968 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
<> 149:156823d33999 1969 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
<> 149:156823d33999 1970 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
<> 149:156823d33999 1971 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
<> 149:156823d33999 1972 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
<> 149:156823d33999 1973 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
<> 149:156823d33999 1974 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
<> 149:156823d33999 1975 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
<> 149:156823d33999 1976 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
<> 149:156823d33999 1977 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
<> 149:156823d33999 1978 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
<> 149:156823d33999 1979 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
<> 149:156823d33999 1980 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
<> 149:156823d33999 1981 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
<> 149:156823d33999 1982 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
<> 149:156823d33999 1983 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
<> 149:156823d33999 1984 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
<> 149:156823d33999 1985 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
<> 149:156823d33999 1986 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
<> 149:156823d33999 1987 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
<> 149:156823d33999 1988 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
<> 149:156823d33999 1989 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
<> 149:156823d33999 1990 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
<> 149:156823d33999 1991 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
<> 149:156823d33999 1992 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
<> 149:156823d33999 1993 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
<> 149:156823d33999 1994 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
<> 149:156823d33999 1995 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
<> 149:156823d33999 1996 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
<> 149:156823d33999 1997 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
<> 149:156823d33999 1998 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
<> 149:156823d33999 1999 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
<> 149:156823d33999 2000 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
<> 149:156823d33999 2001 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2002 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
<> 149:156823d33999 2003 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
<> 149:156823d33999 2004 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
<> 149:156823d33999 2005 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
<> 149:156823d33999 2006 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
<> 149:156823d33999 2007 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
<> 149:156823d33999 2008 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
<> 149:156823d33999 2009 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
<> 149:156823d33999 2010 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
<> 149:156823d33999 2011 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
<> 149:156823d33999 2012 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
<> 149:156823d33999 2013 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
<> 149:156823d33999 2014 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
<> 149:156823d33999 2015 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
<> 149:156823d33999 2016 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
<> 149:156823d33999 2017 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
<> 149:156823d33999 2018 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
<> 149:156823d33999 2019 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
<> 149:156823d33999 2020 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
<> 149:156823d33999 2021 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2022 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
<> 149:156823d33999 2023 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
<> 149:156823d33999 2024 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
<> 149:156823d33999 2025 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
<> 149:156823d33999 2026 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
<> 149:156823d33999 2027 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
<> 149:156823d33999 2028 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
<> 149:156823d33999 2029 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
<> 149:156823d33999 2030 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
<> 149:156823d33999 2031 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
<> 149:156823d33999 2032 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
<> 149:156823d33999 2033 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
<> 149:156823d33999 2034 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
<> 149:156823d33999 2035 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
<> 149:156823d33999 2036 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
<> 149:156823d33999 2037 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
<> 149:156823d33999 2038 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
<> 149:156823d33999 2039 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
<> 149:156823d33999 2040 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
<> 149:156823d33999 2041 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
<> 149:156823d33999 2042 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
<> 149:156823d33999 2043 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
<> 149:156823d33999 2044 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
<> 149:156823d33999 2045 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
<> 149:156823d33999 2046 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
<> 149:156823d33999 2047 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
<> 149:156823d33999 2048 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
<> 149:156823d33999 2049 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
<> 149:156823d33999 2050 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
<> 149:156823d33999 2051 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
<> 149:156823d33999 2052 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
<> 149:156823d33999 2053 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
<> 149:156823d33999 2054 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
<> 149:156823d33999 2055 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
<> 149:156823d33999 2056 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2057 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2058 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
<> 149:156823d33999 2059 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
<> 149:156823d33999 2060 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
<> 149:156823d33999 2061 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
<> 149:156823d33999 2062 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2063 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2064 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
<> 149:156823d33999 2065 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
<> 149:156823d33999 2066 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
<> 149:156823d33999 2067 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
<> 149:156823d33999 2068 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
<> 149:156823d33999 2069 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
<> 149:156823d33999 2070 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
<> 149:156823d33999 2071 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
<> 149:156823d33999 2072 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
<> 149:156823d33999 2073 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
<> 149:156823d33999 2074 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
<> 149:156823d33999 2075 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
<> 149:156823d33999 2076 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
<> 149:156823d33999 2077 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
<> 149:156823d33999 2078 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
<> 149:156823d33999 2079 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
<> 149:156823d33999 2080 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2081 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2082 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
<> 149:156823d33999 2083 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
<> 149:156823d33999 2084 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
<> 149:156823d33999 2085 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
<> 149:156823d33999 2086 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2087 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2088 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
<> 149:156823d33999 2089 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
<> 149:156823d33999 2090 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
<> 149:156823d33999 2091 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
<> 149:156823d33999 2092 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2093 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2094 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
<> 149:156823d33999 2095 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
<> 149:156823d33999 2096 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
<> 149:156823d33999 2097 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
<> 149:156823d33999 2098 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
<> 149:156823d33999 2099 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
<> 149:156823d33999 2100 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
<> 149:156823d33999 2101 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
<> 149:156823d33999 2102 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
<> 149:156823d33999 2103 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
<> 149:156823d33999 2104 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
<> 149:156823d33999 2105 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
<> 149:156823d33999 2106 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
<> 149:156823d33999 2107 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
<> 149:156823d33999 2108 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
<> 149:156823d33999 2109 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
<> 149:156823d33999 2110 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
<> 149:156823d33999 2111 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
<> 149:156823d33999 2112 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
<> 149:156823d33999 2113 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
<> 149:156823d33999 2114 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
<> 149:156823d33999 2115 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
<> 149:156823d33999 2116 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
<> 149:156823d33999 2117 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
<> 149:156823d33999 2118 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
<> 149:156823d33999 2119 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
<> 149:156823d33999 2120 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
<> 149:156823d33999 2121 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
<> 149:156823d33999 2122 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
<> 149:156823d33999 2123 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
<> 149:156823d33999 2124 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
<> 149:156823d33999 2125 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
<> 149:156823d33999 2126 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
<> 149:156823d33999 2127 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
<> 149:156823d33999 2128 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2129 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2130 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
<> 149:156823d33999 2131 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
<> 149:156823d33999 2132 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
<> 149:156823d33999 2133 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
<> 149:156823d33999 2134 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2135 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2136 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
<> 149:156823d33999 2137 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
<> 149:156823d33999 2138 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
<> 149:156823d33999 2139 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
<> 149:156823d33999 2140 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
<> 149:156823d33999 2141 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
<> 149:156823d33999 2142 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
<> 149:156823d33999 2143 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2144 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
<> 149:156823d33999 2145 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
<> 149:156823d33999 2146 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
<> 149:156823d33999 2147 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
<> 149:156823d33999 2148 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2149 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2150 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
<> 149:156823d33999 2151 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
<> 149:156823d33999 2152 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
<> 149:156823d33999 2153 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
<> 149:156823d33999 2154 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2155 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2156 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
<> 149:156823d33999 2157 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
<> 149:156823d33999 2158 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
<> 149:156823d33999 2159 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
<> 149:156823d33999 2160 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
<> 149:156823d33999 2161 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
<> 149:156823d33999 2162 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
<> 149:156823d33999 2163 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
<> 149:156823d33999 2164 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
<> 149:156823d33999 2165 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
<> 149:156823d33999 2166 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2167 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2168 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2169 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2170 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
<> 149:156823d33999 2171 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
<> 149:156823d33999 2172 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2173 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2174 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
<> 149:156823d33999 2175 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
<> 149:156823d33999 2176 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
<> 149:156823d33999 2177 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
<> 149:156823d33999 2178 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
<> 149:156823d33999 2179 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
<> 149:156823d33999 2180 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
<> 149:156823d33999 2181 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
<> 149:156823d33999 2182 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
<> 149:156823d33999 2183 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
<> 149:156823d33999 2184 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2185 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2186 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
<> 149:156823d33999 2187 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
<> 149:156823d33999 2188 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
<> 149:156823d33999 2189 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
<> 149:156823d33999 2190 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
<> 149:156823d33999 2191 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
<> 149:156823d33999 2192 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
<> 149:156823d33999 2193 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
<> 149:156823d33999 2194 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
<> 149:156823d33999 2195 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
<> 149:156823d33999 2196 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
<> 149:156823d33999 2197 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
<> 149:156823d33999 2198 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
<> 149:156823d33999 2199 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
<> 149:156823d33999 2200 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
<> 149:156823d33999 2201 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
<> 149:156823d33999 2202 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
<> 149:156823d33999 2203 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
<> 149:156823d33999 2204 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
<> 149:156823d33999 2205 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
<> 149:156823d33999 2206 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
<> 149:156823d33999 2207 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
<> 149:156823d33999 2208 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
<> 149:156823d33999 2209 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
<> 149:156823d33999 2210 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
<> 149:156823d33999 2211 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
<> 149:156823d33999 2212 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
<> 149:156823d33999 2213 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
<> 149:156823d33999 2214 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
<> 149:156823d33999 2215 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
<> 149:156823d33999 2216 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
<> 149:156823d33999 2217 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
<> 149:156823d33999 2218 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
<> 149:156823d33999 2219 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
<> 149:156823d33999 2220 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
<> 149:156823d33999 2221 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
<> 149:156823d33999 2222 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
<> 149:156823d33999 2223 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
<> 149:156823d33999 2224 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
<> 149:156823d33999 2225 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
<> 149:156823d33999 2226 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
<> 149:156823d33999 2227 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
<> 149:156823d33999 2228 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2229 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2230 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
<> 149:156823d33999 2231 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
<> 149:156823d33999 2232 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
<> 149:156823d33999 2233 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
<> 149:156823d33999 2234 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
<> 149:156823d33999 2235 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
<> 149:156823d33999 2236 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
<> 149:156823d33999 2237 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
<> 149:156823d33999 2238 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
<> 149:156823d33999 2239 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
<> 149:156823d33999 2240 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
<> 149:156823d33999 2241 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
<> 149:156823d33999 2242 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
<> 149:156823d33999 2243 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
<> 149:156823d33999 2244 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
<> 149:156823d33999 2245 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
<> 149:156823d33999 2246 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
<> 149:156823d33999 2247 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
<> 149:156823d33999 2248 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
<> 149:156823d33999 2249 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
<> 149:156823d33999 2250 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
<> 149:156823d33999 2251 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
<> 149:156823d33999 2252 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
<> 149:156823d33999 2253 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
<> 149:156823d33999 2254 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
<> 149:156823d33999 2255 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
<> 149:156823d33999 2256 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
<> 149:156823d33999 2257 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
<> 149:156823d33999 2258 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
<> 149:156823d33999 2259 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
<> 149:156823d33999 2260 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
<> 149:156823d33999 2261 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
<> 149:156823d33999 2262 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
<> 149:156823d33999 2263 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
<> 149:156823d33999 2264 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
<> 149:156823d33999 2265 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
<> 149:156823d33999 2266 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
<> 149:156823d33999 2267 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
<> 149:156823d33999 2268 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
<> 149:156823d33999 2269 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
<> 149:156823d33999 2270 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
<> 149:156823d33999 2271 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
<> 149:156823d33999 2272 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
<> 149:156823d33999 2273 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
<> 149:156823d33999 2274 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
<> 149:156823d33999 2275 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2276 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
<> 149:156823d33999 2277 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
<> 149:156823d33999 2278 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
<> 149:156823d33999 2279 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
<> 149:156823d33999 2280 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
<> 149:156823d33999 2281 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
<> 149:156823d33999 2282 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
<> 149:156823d33999 2283 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
<> 149:156823d33999 2284 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
<> 149:156823d33999 2285 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
<> 149:156823d33999 2286 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
<> 149:156823d33999 2287 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
<> 149:156823d33999 2288 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
<> 149:156823d33999 2289 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
<> 149:156823d33999 2290 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
<> 149:156823d33999 2291 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
<> 149:156823d33999 2292 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2293 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2294 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
<> 149:156823d33999 2295 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
<> 149:156823d33999 2296 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
<> 149:156823d33999 2297 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
<> 149:156823d33999 2298 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2299 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2300 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
<> 149:156823d33999 2301 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
<> 149:156823d33999 2302 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
<> 149:156823d33999 2303 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
<> 149:156823d33999 2304 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
<> 149:156823d33999 2305 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
<> 149:156823d33999 2306 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
<> 149:156823d33999 2307 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
AnnaBridge 184:08ed48f1de7f 2308 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 2309 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge 184:08ed48f1de7f 2310 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge 184:08ed48f1de7f 2311 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge 184:08ed48f1de7f 2312 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge 184:08ed48f1de7f 2313 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge 184:08ed48f1de7f 2314 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 2315 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge 184:08ed48f1de7f 2316 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge 184:08ed48f1de7f 2317 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge 184:08ed48f1de7f 2318 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge 184:08ed48f1de7f 2319 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge 184:08ed48f1de7f 2320 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 2321 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge 184:08ed48f1de7f 2322 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge 184:08ed48f1de7f 2323 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge 184:08ed48f1de7f 2324 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge 184:08ed48f1de7f 2325 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge 184:08ed48f1de7f 2326 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge 184:08ed48f1de7f 2327 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
<> 149:156823d33999 2328 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
<> 149:156823d33999 2329 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
<> 149:156823d33999 2330 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
<> 149:156823d33999 2331 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
<> 149:156823d33999 2332 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
<> 149:156823d33999 2333 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
<> 149:156823d33999 2334 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
<> 149:156823d33999 2335 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
<> 149:156823d33999 2336 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
<> 149:156823d33999 2337 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
<> 149:156823d33999 2338 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
<> 149:156823d33999 2339 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
<> 149:156823d33999 2340 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
<> 149:156823d33999 2341 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
<> 149:156823d33999 2342 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
<> 149:156823d33999 2343 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
<> 149:156823d33999 2344 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
<> 149:156823d33999 2345 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
<> 149:156823d33999 2346 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
<> 149:156823d33999 2347 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
<> 149:156823d33999 2348 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
<> 149:156823d33999 2349 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
<> 149:156823d33999 2350 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
<> 149:156823d33999 2351 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
<> 149:156823d33999 2352 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
<> 149:156823d33999 2353 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
<> 149:156823d33999 2354 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
<> 149:156823d33999 2355 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
<> 149:156823d33999 2356 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
<> 149:156823d33999 2357 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
<> 149:156823d33999 2358 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
<> 149:156823d33999 2359 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
<> 149:156823d33999 2360 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
<> 149:156823d33999 2361 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
<> 149:156823d33999 2362
<> 149:156823d33999 2363 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
<> 149:156823d33999 2364 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
<> 149:156823d33999 2365 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
<> 149:156823d33999 2366 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
<> 149:156823d33999 2367 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
<> 149:156823d33999 2368 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
<> 149:156823d33999 2369 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
<> 149:156823d33999 2370 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
<> 149:156823d33999 2371 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
<> 149:156823d33999 2372 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
<> 149:156823d33999 2373 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
<> 149:156823d33999 2374 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
<> 149:156823d33999 2375 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
<> 149:156823d33999 2376 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
<> 149:156823d33999 2377 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
<> 149:156823d33999 2378 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
<> 149:156823d33999 2379 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
<> 149:156823d33999 2380 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
<> 149:156823d33999 2381 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
<> 149:156823d33999 2382 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
<> 149:156823d33999 2383 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
<> 149:156823d33999 2384 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
<> 149:156823d33999 2385 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
<> 149:156823d33999 2386 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
<> 149:156823d33999 2387 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
<> 149:156823d33999 2388 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
<> 149:156823d33999 2389 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
<> 149:156823d33999 2390 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
<> 149:156823d33999 2391 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
<> 149:156823d33999 2392 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
<> 149:156823d33999 2393 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
<> 149:156823d33999 2394 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
<> 149:156823d33999 2395 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
<> 149:156823d33999 2396 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
<> 149:156823d33999 2397 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
<> 149:156823d33999 2398 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
<> 149:156823d33999 2399 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
<> 149:156823d33999 2400 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
<> 149:156823d33999 2401 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
<> 149:156823d33999 2402 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
<> 149:156823d33999 2403 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2404 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2405 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
<> 149:156823d33999 2406 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
<> 149:156823d33999 2407 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
<> 149:156823d33999 2408 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
<> 149:156823d33999 2409 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
<> 149:156823d33999 2410 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
<> 149:156823d33999 2411 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
<> 149:156823d33999 2412 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
<> 149:156823d33999 2413 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
<> 149:156823d33999 2414 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
<> 149:156823d33999 2415 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
<> 149:156823d33999 2416 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
<> 149:156823d33999 2417 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
<> 149:156823d33999 2418 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
<> 149:156823d33999 2419 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
<> 149:156823d33999 2420 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
<> 149:156823d33999 2421 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
<> 149:156823d33999 2422 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
<> 149:156823d33999 2423 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
<> 149:156823d33999 2424 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
<> 149:156823d33999 2425 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
<> 149:156823d33999 2426 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
<> 149:156823d33999 2427 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
<> 149:156823d33999 2428 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
<> 149:156823d33999 2429 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
<> 149:156823d33999 2430 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
<> 149:156823d33999 2431 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
<> 149:156823d33999 2432 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
<> 149:156823d33999 2433 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
<> 149:156823d33999 2434 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
<> 149:156823d33999 2435 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
<> 149:156823d33999 2436 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
<> 149:156823d33999 2437 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
<> 149:156823d33999 2438 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
<> 149:156823d33999 2439 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
<> 149:156823d33999 2440 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
<> 149:156823d33999 2441 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
<> 149:156823d33999 2442 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
<> 149:156823d33999 2443 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
<> 149:156823d33999 2444 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
<> 149:156823d33999 2445 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
<> 149:156823d33999 2446 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
<> 149:156823d33999 2447 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
<> 149:156823d33999 2448 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
<> 149:156823d33999 2449 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
<> 149:156823d33999 2450 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
<> 149:156823d33999 2451 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
<> 149:156823d33999 2452 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
<> 149:156823d33999 2453 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
<> 149:156823d33999 2454 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
<> 149:156823d33999 2455 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
<> 149:156823d33999 2456 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
<> 149:156823d33999 2457 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
<> 149:156823d33999 2458 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
<> 149:156823d33999 2459 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
<> 149:156823d33999 2460 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
<> 149:156823d33999 2461 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
<> 149:156823d33999 2462 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
<> 149:156823d33999 2463 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
<> 149:156823d33999 2464 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
<> 149:156823d33999 2465 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
<> 149:156823d33999 2466 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
<> 149:156823d33999 2467 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
<> 149:156823d33999 2468 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
<> 149:156823d33999 2469 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
<> 149:156823d33999 2470 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
<> 149:156823d33999 2471 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
<> 149:156823d33999 2472 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
<> 149:156823d33999 2473 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
<> 149:156823d33999 2474 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
<> 149:156823d33999 2475 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
<> 149:156823d33999 2476 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
<> 149:156823d33999 2477 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
<> 149:156823d33999 2478 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
<> 149:156823d33999 2479 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
<> 149:156823d33999 2480 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
<> 149:156823d33999 2481 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
<> 149:156823d33999 2482 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
<> 149:156823d33999 2483 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
<> 149:156823d33999 2484 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
<> 149:156823d33999 2485 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
<> 149:156823d33999 2486 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
<> 149:156823d33999 2487 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
<> 149:156823d33999 2488 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2489 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2490 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2491 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
<> 149:156823d33999 2492 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
<> 149:156823d33999 2493 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
<> 149:156823d33999 2494 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
<> 149:156823d33999 2495 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
<> 149:156823d33999 2496 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
<> 149:156823d33999 2497 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
<> 149:156823d33999 2498 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
<> 149:156823d33999 2499 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
<> 149:156823d33999 2500 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
<> 149:156823d33999 2501 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
<> 149:156823d33999 2502 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
<> 149:156823d33999 2503 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
<> 149:156823d33999 2504 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
<> 149:156823d33999 2505 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
<> 149:156823d33999 2506 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
<> 149:156823d33999 2507 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
<> 149:156823d33999 2508 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
<> 149:156823d33999 2509 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
<> 149:156823d33999 2510
<> 149:156823d33999 2511 /* alias define maintained for legacy */
<> 149:156823d33999 2512 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
<> 149:156823d33999 2513 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
<> 149:156823d33999 2514
<> 149:156823d33999 2515 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
<> 149:156823d33999 2516 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
<> 149:156823d33999 2517 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
<> 149:156823d33999 2518 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
<> 149:156823d33999 2519 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
<> 149:156823d33999 2520 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
<> 149:156823d33999 2521 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
<> 149:156823d33999 2522 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
<> 149:156823d33999 2523 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
<> 149:156823d33999 2524 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
<> 149:156823d33999 2525 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
<> 149:156823d33999 2526 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
<> 149:156823d33999 2527 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
<> 149:156823d33999 2528 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
<> 149:156823d33999 2529 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
<> 149:156823d33999 2530 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
<> 149:156823d33999 2531 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
<> 149:156823d33999 2532 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
<> 149:156823d33999 2533 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
<> 149:156823d33999 2534 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
<> 149:156823d33999 2535
<> 149:156823d33999 2536 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
<> 149:156823d33999 2537 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
<> 149:156823d33999 2538 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
<> 149:156823d33999 2539 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
<> 149:156823d33999 2540 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
<> 149:156823d33999 2541 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
<> 149:156823d33999 2542 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
<> 149:156823d33999 2543 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
<> 149:156823d33999 2544 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
<> 149:156823d33999 2545 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
<> 149:156823d33999 2546 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
<> 149:156823d33999 2547 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
<> 149:156823d33999 2548 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
<> 149:156823d33999 2549 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
<> 149:156823d33999 2550 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
<> 149:156823d33999 2551 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
<> 149:156823d33999 2552 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
<> 149:156823d33999 2553 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
<> 149:156823d33999 2554 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
<> 149:156823d33999 2555 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
<> 149:156823d33999 2556
<> 149:156823d33999 2557 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
<> 149:156823d33999 2558 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
<> 149:156823d33999 2559 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
<> 149:156823d33999 2560 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
<> 149:156823d33999 2561 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
<> 149:156823d33999 2562 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
<> 149:156823d33999 2563 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
<> 149:156823d33999 2564 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
<> 149:156823d33999 2565 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
<> 149:156823d33999 2566 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
<> 149:156823d33999 2567 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
<> 149:156823d33999 2568 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
<> 149:156823d33999 2569 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
<> 149:156823d33999 2570 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
<> 149:156823d33999 2571 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
<> 149:156823d33999 2572 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
<> 149:156823d33999 2573 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
<> 149:156823d33999 2574 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
<> 149:156823d33999 2575 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
<> 149:156823d33999 2576 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
<> 149:156823d33999 2577 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
<> 149:156823d33999 2578 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
<> 149:156823d33999 2579 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
<> 149:156823d33999 2580 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
<> 149:156823d33999 2581 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
<> 149:156823d33999 2582 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
<> 149:156823d33999 2583 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
<> 149:156823d33999 2584 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
<> 149:156823d33999 2585 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
<> 149:156823d33999 2586 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
<> 149:156823d33999 2587 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
<> 149:156823d33999 2588 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
<> 149:156823d33999 2589 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
<> 149:156823d33999 2590 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
<> 149:156823d33999 2591 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
<> 149:156823d33999 2592 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
<> 149:156823d33999 2593 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
<> 149:156823d33999 2594 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
<> 149:156823d33999 2595 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
<> 149:156823d33999 2596 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
<> 149:156823d33999 2597 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
<> 149:156823d33999 2598 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
<> 149:156823d33999 2599 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
<> 149:156823d33999 2600 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
<> 149:156823d33999 2601 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
<> 149:156823d33999 2602 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
<> 149:156823d33999 2603 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
<> 149:156823d33999 2604 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
<> 149:156823d33999 2605 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
<> 149:156823d33999 2606 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
<> 149:156823d33999 2607 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
<> 149:156823d33999 2608 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
<> 149:156823d33999 2609 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
<> 149:156823d33999 2610 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
<> 149:156823d33999 2611 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
<> 149:156823d33999 2612 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
<> 149:156823d33999 2613 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
<> 149:156823d33999 2614 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
<> 149:156823d33999 2615 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
<> 149:156823d33999 2616 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
<> 149:156823d33999 2617 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
<> 149:156823d33999 2618 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
<> 149:156823d33999 2619 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
<> 149:156823d33999 2620 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
<> 149:156823d33999 2621 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
<> 149:156823d33999 2622 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
<> 149:156823d33999 2623 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
<> 149:156823d33999 2624 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
<> 149:156823d33999 2625 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
<> 149:156823d33999 2626 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
<> 149:156823d33999 2627 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
<> 149:156823d33999 2628 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
<> 149:156823d33999 2629 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
<> 149:156823d33999 2630 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
<> 149:156823d33999 2631 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
<> 149:156823d33999 2632 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
<> 149:156823d33999 2633 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
<> 149:156823d33999 2634 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
<> 149:156823d33999 2635 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
<> 149:156823d33999 2636 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
<> 149:156823d33999 2637 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
<> 149:156823d33999 2638 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
<> 149:156823d33999 2639 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
<> 149:156823d33999 2640 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
<> 149:156823d33999 2641 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
<> 149:156823d33999 2642 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
<> 149:156823d33999 2643 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
<> 149:156823d33999 2644 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
<> 149:156823d33999 2645 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
<> 149:156823d33999 2646 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
<> 149:156823d33999 2647 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
<> 149:156823d33999 2648 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
<> 149:156823d33999 2649 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
<> 149:156823d33999 2650 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
<> 149:156823d33999 2651 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
<> 149:156823d33999 2652 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
<> 149:156823d33999 2653 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
<> 149:156823d33999 2654 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
<> 149:156823d33999 2655 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
<> 149:156823d33999 2656 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
<> 149:156823d33999 2657 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
<> 149:156823d33999 2658 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
<> 149:156823d33999 2659 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
<> 149:156823d33999 2660 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
<> 149:156823d33999 2661 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
<> 149:156823d33999 2662 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
<> 149:156823d33999 2663 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
<> 149:156823d33999 2664 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
<> 149:156823d33999 2665 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
<> 149:156823d33999 2666 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
<> 149:156823d33999 2667 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
<> 149:156823d33999 2668 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
<> 149:156823d33999 2669 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
<> 149:156823d33999 2670 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
<> 149:156823d33999 2671 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
<> 149:156823d33999 2672 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
<> 149:156823d33999 2673
<> 149:156823d33999 2674 #if defined(STM32F4)
<> 149:156823d33999 2675 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
<> 149:156823d33999 2676 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
<> 149:156823d33999 2677 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
<> 149:156823d33999 2678 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
<> 149:156823d33999 2679 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
<> 149:156823d33999 2680 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
<> 149:156823d33999 2681 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
<> 149:156823d33999 2682 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
<> 149:156823d33999 2683 #define Sdmmc1ClockSelection SdioClockSelection
<> 149:156823d33999 2684 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
<> 149:156823d33999 2685 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
<> 149:156823d33999 2686 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
<> 149:156823d33999 2687 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
<> 149:156823d33999 2688 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
<> 149:156823d33999 2689 #endif
<> 149:156823d33999 2690
<> 149:156823d33999 2691 #if defined(STM32F7) || defined(STM32L4)
<> 149:156823d33999 2692 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
<> 149:156823d33999 2693 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
<> 149:156823d33999 2694 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2695 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2696 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
<> 149:156823d33999 2697 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
<> 149:156823d33999 2698 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
<> 149:156823d33999 2699 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
<> 149:156823d33999 2700 #define SdioClockSelection Sdmmc1ClockSelection
<> 149:156823d33999 2701 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
<> 149:156823d33999 2702 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
<> 149:156823d33999 2703 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
<> 149:156823d33999 2704 #endif
<> 149:156823d33999 2705
<> 149:156823d33999 2706 #if defined(STM32F7)
<> 149:156823d33999 2707 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
<> 149:156823d33999 2708 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
<> 149:156823d33999 2709 #endif
<> 149:156823d33999 2710
AnnaBridge 184:08ed48f1de7f 2711 #if defined(STM32H7)
AnnaBridge 184:08ed48f1de7f 2712 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
AnnaBridge 184:08ed48f1de7f 2713 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
AnnaBridge 184:08ed48f1de7f 2714 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
AnnaBridge 184:08ed48f1de7f 2715 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
AnnaBridge 184:08ed48f1de7f 2716 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
AnnaBridge 184:08ed48f1de7f 2717 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
AnnaBridge 184:08ed48f1de7f 2718 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
AnnaBridge 184:08ed48f1de7f 2719 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
AnnaBridge 184:08ed48f1de7f 2720 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
AnnaBridge 184:08ed48f1de7f 2721 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
AnnaBridge 184:08ed48f1de7f 2722
AnnaBridge 184:08ed48f1de7f 2723 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
AnnaBridge 184:08ed48f1de7f 2724 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
AnnaBridge 184:08ed48f1de7f 2725 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
AnnaBridge 184:08ed48f1de7f 2726 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
AnnaBridge 184:08ed48f1de7f 2727 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
AnnaBridge 184:08ed48f1de7f 2728 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
AnnaBridge 184:08ed48f1de7f 2729 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
AnnaBridge 184:08ed48f1de7f 2730 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
AnnaBridge 184:08ed48f1de7f 2731 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
AnnaBridge 184:08ed48f1de7f 2732 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
AnnaBridge 184:08ed48f1de7f 2733 #endif
AnnaBridge 184:08ed48f1de7f 2734
<> 149:156823d33999 2735 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
<> 149:156823d33999 2736 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
<> 149:156823d33999 2737
<> 149:156823d33999 2738 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
<> 149:156823d33999 2739
<> 149:156823d33999 2740 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
<> 149:156823d33999 2741 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
<> 149:156823d33999 2742 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
<> 149:156823d33999 2743 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
<> 149:156823d33999 2744 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
<> 149:156823d33999 2745
<> 149:156823d33999 2746 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
<> 149:156823d33999 2747
AnnaBridge 184:08ed48f1de7f 2748 #define RCC_IT_CSSLSE RCC_IT_LSECSS
AnnaBridge 184:08ed48f1de7f 2749 #define RCC_IT_CSSHSE RCC_IT_CSS
AnnaBridge 184:08ed48f1de7f 2750
AnnaBridge 184:08ed48f1de7f 2751 #define RCC_PLLMUL_3 RCC_PLL_MUL3
AnnaBridge 184:08ed48f1de7f 2752 #define RCC_PLLMUL_4 RCC_PLL_MUL4
AnnaBridge 184:08ed48f1de7f 2753 #define RCC_PLLMUL_6 RCC_PLL_MUL6
AnnaBridge 184:08ed48f1de7f 2754 #define RCC_PLLMUL_8 RCC_PLL_MUL8
AnnaBridge 184:08ed48f1de7f 2755 #define RCC_PLLMUL_12 RCC_PLL_MUL12
AnnaBridge 184:08ed48f1de7f 2756 #define RCC_PLLMUL_16 RCC_PLL_MUL16
AnnaBridge 184:08ed48f1de7f 2757 #define RCC_PLLMUL_24 RCC_PLL_MUL24
AnnaBridge 184:08ed48f1de7f 2758 #define RCC_PLLMUL_32 RCC_PLL_MUL32
AnnaBridge 184:08ed48f1de7f 2759 #define RCC_PLLMUL_48 RCC_PLL_MUL48
AnnaBridge 184:08ed48f1de7f 2760
AnnaBridge 184:08ed48f1de7f 2761 #define RCC_PLLDIV_2 RCC_PLL_DIV2
AnnaBridge 184:08ed48f1de7f 2762 #define RCC_PLLDIV_3 RCC_PLL_DIV3
AnnaBridge 184:08ed48f1de7f 2763 #define RCC_PLLDIV_4 RCC_PLL_DIV4
<> 149:156823d33999 2764
<> 149:156823d33999 2765 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
<> 149:156823d33999 2766 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
<> 149:156823d33999 2767 #define RCC_MCO_NODIV RCC_MCODIV_1
<> 149:156823d33999 2768 #define RCC_MCO_DIV1 RCC_MCODIV_1
<> 149:156823d33999 2769 #define RCC_MCO_DIV2 RCC_MCODIV_2
<> 149:156823d33999 2770 #define RCC_MCO_DIV4 RCC_MCODIV_4
<> 149:156823d33999 2771 #define RCC_MCO_DIV8 RCC_MCODIV_8
<> 149:156823d33999 2772 #define RCC_MCO_DIV16 RCC_MCODIV_16
<> 149:156823d33999 2773 #define RCC_MCO_DIV32 RCC_MCODIV_32
<> 149:156823d33999 2774 #define RCC_MCO_DIV64 RCC_MCODIV_64
<> 149:156823d33999 2775 #define RCC_MCO_DIV128 RCC_MCODIV_128
<> 149:156823d33999 2776 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
<> 149:156823d33999 2777 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
<> 149:156823d33999 2778 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
<> 149:156823d33999 2779 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
<> 149:156823d33999 2780 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
<> 149:156823d33999 2781 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
<> 149:156823d33999 2782 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
<> 149:156823d33999 2783 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
<> 149:156823d33999 2784 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
<> 149:156823d33999 2785 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
<> 149:156823d33999 2786 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
<> 149:156823d33999 2787
AnnaBridge 184:08ed48f1de7f 2788 #if defined(STM32WB) || defined(STM32G0)
AnnaBridge 184:08ed48f1de7f 2789 #else
<> 149:156823d33999 2790 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
AnnaBridge 184:08ed48f1de7f 2791 #endif
<> 149:156823d33999 2792
<> 149:156823d33999 2793 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
<> 149:156823d33999 2794 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
<> 149:156823d33999 2795 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
<> 149:156823d33999 2796 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
<> 149:156823d33999 2797 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
<> 149:156823d33999 2798 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
<> 149:156823d33999 2799 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
<> 149:156823d33999 2800 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
<> 149:156823d33999 2801
<> 149:156823d33999 2802 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
<> 149:156823d33999 2803 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
<> 149:156823d33999 2804 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
<> 149:156823d33999 2805 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
<> 149:156823d33999 2806 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
<> 149:156823d33999 2807 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
<> 149:156823d33999 2808 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
<> 149:156823d33999 2809 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
<> 149:156823d33999 2810 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
<> 149:156823d33999 2811 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
<> 149:156823d33999 2812 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
<> 149:156823d33999 2813 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
<> 149:156823d33999 2814 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
<> 149:156823d33999 2815 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
<> 149:156823d33999 2816 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
<> 149:156823d33999 2817 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
<> 149:156823d33999 2818 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
<> 149:156823d33999 2819 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
<> 149:156823d33999 2820 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
<> 149:156823d33999 2821 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
<> 149:156823d33999 2822 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
<> 149:156823d33999 2823 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
<> 149:156823d33999 2824 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
<> 149:156823d33999 2825 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
<> 149:156823d33999 2826 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
<> 149:156823d33999 2827 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
<> 149:156823d33999 2828 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
<> 149:156823d33999 2829 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
<> 149:156823d33999 2830 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
<> 149:156823d33999 2831 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
<> 149:156823d33999 2832 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
<> 149:156823d33999 2833 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
<> 149:156823d33999 2834
<> 149:156823d33999 2835 #define CR_HSION_BB RCC_CR_HSION_BB
<> 149:156823d33999 2836 #define CR_CSSON_BB RCC_CR_CSSON_BB
<> 149:156823d33999 2837 #define CR_PLLON_BB RCC_CR_PLLON_BB
<> 149:156823d33999 2838 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
<> 149:156823d33999 2839 #define CR_MSION_BB RCC_CR_MSION_BB
<> 149:156823d33999 2840 #define CSR_LSION_BB RCC_CSR_LSION_BB
<> 149:156823d33999 2841 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
<> 149:156823d33999 2842 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
<> 149:156823d33999 2843 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
<> 149:156823d33999 2844 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
<> 149:156823d33999 2845 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
<> 149:156823d33999 2846 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
<> 149:156823d33999 2847 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
<> 149:156823d33999 2848 #define CR_HSEON_BB RCC_CR_HSEON_BB
<> 149:156823d33999 2849 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
<> 149:156823d33999 2850 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
<> 149:156823d33999 2851 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
<> 149:156823d33999 2852
<> 149:156823d33999 2853 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
<> 149:156823d33999 2854 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
<> 149:156823d33999 2855 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
<> 149:156823d33999 2856 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
<> 149:156823d33999 2857 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
<> 149:156823d33999 2858
<> 149:156823d33999 2859 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
<> 149:156823d33999 2860
<> 149:156823d33999 2861 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
<> 149:156823d33999 2862 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
<> 149:156823d33999 2863
<> 149:156823d33999 2864 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
<> 149:156823d33999 2865 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
<> 149:156823d33999 2866 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
<> 149:156823d33999 2867 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
<> 149:156823d33999 2868 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
<> 149:156823d33999 2869 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
<> 149:156823d33999 2870
<> 149:156823d33999 2871 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
<> 149:156823d33999 2872 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
<> 149:156823d33999 2873 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
<> 149:156823d33999 2874 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
<> 149:156823d33999 2875 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
<> 149:156823d33999 2876 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
<> 149:156823d33999 2877 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
<> 149:156823d33999 2878 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
<> 149:156823d33999 2879 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
<> 149:156823d33999 2880 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
<> 149:156823d33999 2881 #define DfsdmClockSelection Dfsdm1ClockSelection
<> 149:156823d33999 2882 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
AnnaBridge 184:08ed48f1de7f 2883 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
<> 149:156823d33999 2884 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
<> 149:156823d33999 2885 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
<> 149:156823d33999 2886 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
AnnaBridge 184:08ed48f1de7f 2887 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge 184:08ed48f1de7f 2888 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
AnnaBridge 184:08ed48f1de7f 2889 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
AnnaBridge 184:08ed48f1de7f 2890 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
AnnaBridge 184:08ed48f1de7f 2891
AnnaBridge 184:08ed48f1de7f 2892 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
AnnaBridge 184:08ed48f1de7f 2893 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
AnnaBridge 184:08ed48f1de7f 2894 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
AnnaBridge 184:08ed48f1de7f 2895 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
AnnaBridge 184:08ed48f1de7f 2896 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge 184:08ed48f1de7f 2897 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
AnnaBridge 184:08ed48f1de7f 2898 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
<> 149:156823d33999 2899
<> 149:156823d33999 2900 /**
<> 149:156823d33999 2901 * @}
<> 149:156823d33999 2902 */
<> 149:156823d33999 2903
<> 149:156823d33999 2904 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
<> 149:156823d33999 2905 * @{
<> 149:156823d33999 2906 */
<> 149:156823d33999 2907 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
<> 149:156823d33999 2908
<> 149:156823d33999 2909 /**
<> 149:156823d33999 2910 * @}
<> 149:156823d33999 2911 */
<> 149:156823d33999 2912
<> 149:156823d33999 2913 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
<> 149:156823d33999 2914 * @{
<> 149:156823d33999 2915 */
AnnaBridge 184:08ed48f1de7f 2916 #if defined (STM32G0)
AnnaBridge 184:08ed48f1de7f 2917 #else
<> 149:156823d33999 2918 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
AnnaBridge 184:08ed48f1de7f 2919 #endif
<> 149:156823d33999 2920 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
<> 149:156823d33999 2921 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
<> 149:156823d33999 2922
<> 149:156823d33999 2923 #if defined (STM32F1)
<> 149:156823d33999 2924 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
<> 149:156823d33999 2925
<> 149:156823d33999 2926 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
<> 149:156823d33999 2927
<> 149:156823d33999 2928 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
<> 149:156823d33999 2929
<> 149:156823d33999 2930 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
<> 149:156823d33999 2931
<> 149:156823d33999 2932 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
<> 149:156823d33999 2933 #else
<> 149:156823d33999 2934 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 2935 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
<> 149:156823d33999 2936 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
<> 149:156823d33999 2937 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
<> 149:156823d33999 2938 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
<> 149:156823d33999 2939 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
<> 149:156823d33999 2940 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
<> 149:156823d33999 2941 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
<> 149:156823d33999 2942 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
<> 149:156823d33999 2943 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
<> 149:156823d33999 2944 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
<> 149:156823d33999 2945 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
<> 149:156823d33999 2946 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
<> 149:156823d33999 2947 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
<> 149:156823d33999 2948 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
<> 149:156823d33999 2949 #endif /* STM32F1 */
<> 149:156823d33999 2950
<> 149:156823d33999 2951 #define IS_ALARM IS_RTC_ALARM
<> 149:156823d33999 2952 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
<> 149:156823d33999 2953 #define IS_TAMPER IS_RTC_TAMPER
<> 149:156823d33999 2954 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
<> 149:156823d33999 2955 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
<> 149:156823d33999 2956 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
<> 149:156823d33999 2957 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
<> 149:156823d33999 2958 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
<> 149:156823d33999 2959 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
<> 149:156823d33999 2960 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
<> 149:156823d33999 2961 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
<> 149:156823d33999 2962 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
<> 149:156823d33999 2963 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
<> 149:156823d33999 2964 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
<> 149:156823d33999 2965
<> 149:156823d33999 2966 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
<> 149:156823d33999 2967 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
<> 149:156823d33999 2968
<> 149:156823d33999 2969 /**
<> 149:156823d33999 2970 * @}
<> 149:156823d33999 2971 */
<> 149:156823d33999 2972
<> 149:156823d33999 2973 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
<> 149:156823d33999 2974 * @{
<> 149:156823d33999 2975 */
<> 149:156823d33999 2976
<> 149:156823d33999 2977 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
<> 149:156823d33999 2978 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
<> 149:156823d33999 2979
AnnaBridge 184:08ed48f1de7f 2980 #if defined(STM32F4) || defined(STM32F2)
<> 149:156823d33999 2981 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
<> 149:156823d33999 2982 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
<> 149:156823d33999 2983 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
<> 149:156823d33999 2984 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
<> 149:156823d33999 2985 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
<> 149:156823d33999 2986 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
<> 149:156823d33999 2987 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
<> 149:156823d33999 2988 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
<> 149:156823d33999 2989 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
<> 149:156823d33999 2990 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
<> 149:156823d33999 2991 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
<> 149:156823d33999 2992 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
<> 149:156823d33999 2993 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
<> 149:156823d33999 2994 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
<> 149:156823d33999 2995 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
<> 149:156823d33999 2996 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
<> 149:156823d33999 2997 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
<> 149:156823d33999 2998 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
<> 149:156823d33999 2999 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
<> 149:156823d33999 3000 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
<> 149:156823d33999 3001 /* alias CMSIS */
<> 149:156823d33999 3002 #define SDMMC1_IRQn SDIO_IRQn
<> 149:156823d33999 3003 #define SDMMC1_IRQHandler SDIO_IRQHandler
<> 149:156823d33999 3004 #endif
<> 149:156823d33999 3005
<> 149:156823d33999 3006 #if defined(STM32F7) || defined(STM32L4)
<> 149:156823d33999 3007 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
<> 149:156823d33999 3008 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
<> 149:156823d33999 3009 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
<> 149:156823d33999 3010 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
<> 149:156823d33999 3011 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
<> 149:156823d33999 3012 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
<> 149:156823d33999 3013 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
<> 149:156823d33999 3014 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
<> 149:156823d33999 3015 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
<> 149:156823d33999 3016 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
<> 149:156823d33999 3017 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
<> 149:156823d33999 3018 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
<> 149:156823d33999 3019 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
<> 149:156823d33999 3020 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
<> 149:156823d33999 3021 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
<> 149:156823d33999 3022 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
<> 149:156823d33999 3023 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
<> 149:156823d33999 3024 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
<> 149:156823d33999 3025 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
<> 149:156823d33999 3026 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
<> 149:156823d33999 3027 /* alias CMSIS for compatibilities */
<> 149:156823d33999 3028 #define SDIO_IRQn SDMMC1_IRQn
<> 149:156823d33999 3029 #define SDIO_IRQHandler SDMMC1_IRQHandler
<> 149:156823d33999 3030 #endif
AnnaBridge 184:08ed48f1de7f 3031
AnnaBridge 184:08ed48f1de7f 3032 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
AnnaBridge 184:08ed48f1de7f 3033 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
AnnaBridge 184:08ed48f1de7f 3034 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
AnnaBridge 184:08ed48f1de7f 3035 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
AnnaBridge 184:08ed48f1de7f 3036 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
AnnaBridge 184:08ed48f1de7f 3037 #endif
AnnaBridge 184:08ed48f1de7f 3038
<> 149:156823d33999 3039 /**
<> 149:156823d33999 3040 * @}
<> 149:156823d33999 3041 */
<> 149:156823d33999 3042
<> 149:156823d33999 3043 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3044 * @{
<> 149:156823d33999 3045 */
<> 149:156823d33999 3046
<> 149:156823d33999 3047 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
<> 149:156823d33999 3048 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
<> 149:156823d33999 3049 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
<> 149:156823d33999 3050 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
<> 149:156823d33999 3051 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
<> 149:156823d33999 3052 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
<> 149:156823d33999 3053
<> 149:156823d33999 3054 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
<> 149:156823d33999 3055 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
<> 149:156823d33999 3056
<> 149:156823d33999 3057 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
<> 149:156823d33999 3058
<> 149:156823d33999 3059 /**
<> 149:156823d33999 3060 * @}
<> 149:156823d33999 3061 */
<> 149:156823d33999 3062
<> 149:156823d33999 3063 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3064 * @{
<> 149:156823d33999 3065 */
<> 149:156823d33999 3066 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
<> 149:156823d33999 3067 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
<> 149:156823d33999 3068 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
<> 149:156823d33999 3069 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
<> 149:156823d33999 3070 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
<> 149:156823d33999 3071 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
<> 149:156823d33999 3072 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
<> 149:156823d33999 3073 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
<> 149:156823d33999 3074 /**
<> 149:156823d33999 3075 * @}
<> 149:156823d33999 3076 */
<> 149:156823d33999 3077
<> 149:156823d33999 3078 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3079 * @{
<> 149:156823d33999 3080 */
<> 149:156823d33999 3081
<> 149:156823d33999 3082 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
<> 149:156823d33999 3083 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
<> 149:156823d33999 3084 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
<> 149:156823d33999 3085
<> 149:156823d33999 3086 /**
<> 149:156823d33999 3087 * @}
<> 149:156823d33999 3088 */
<> 149:156823d33999 3089
<> 149:156823d33999 3090 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3091 * @{
<> 149:156823d33999 3092 */
<> 149:156823d33999 3093
<> 149:156823d33999 3094 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
<> 149:156823d33999 3095 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
<> 149:156823d33999 3096 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
<> 149:156823d33999 3097 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
<> 149:156823d33999 3098
<> 149:156823d33999 3099 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
<> 149:156823d33999 3100
<> 149:156823d33999 3101 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
<> 149:156823d33999 3102 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
<> 149:156823d33999 3103
<> 149:156823d33999 3104 /**
<> 149:156823d33999 3105 * @}
<> 149:156823d33999 3106 */
<> 149:156823d33999 3107
<> 149:156823d33999 3108
<> 149:156823d33999 3109 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3110 * @{
<> 149:156823d33999 3111 */
<> 149:156823d33999 3112
<> 149:156823d33999 3113 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
<> 149:156823d33999 3114 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
<> 149:156823d33999 3115 #define __USART_ENABLE __HAL_USART_ENABLE
<> 149:156823d33999 3116 #define __USART_DISABLE __HAL_USART_DISABLE
<> 149:156823d33999 3117
<> 149:156823d33999 3118 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
<> 149:156823d33999 3119 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
<> 149:156823d33999 3120
<> 149:156823d33999 3121 /**
<> 149:156823d33999 3122 * @}
<> 149:156823d33999 3123 */
<> 149:156823d33999 3124
<> 149:156823d33999 3125 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3126 * @{
<> 149:156823d33999 3127 */
<> 149:156823d33999 3128 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
<> 149:156823d33999 3129
<> 149:156823d33999 3130 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
<> 149:156823d33999 3131 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
<> 149:156823d33999 3132 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
<> 149:156823d33999 3133 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
<> 149:156823d33999 3134
<> 149:156823d33999 3135 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
<> 149:156823d33999 3136 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
<> 149:156823d33999 3137 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
<> 149:156823d33999 3138 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
<> 149:156823d33999 3139
<> 149:156823d33999 3140 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
<> 149:156823d33999 3141 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
<> 149:156823d33999 3142 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
<> 149:156823d33999 3143 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
<> 149:156823d33999 3144 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
<> 149:156823d33999 3145 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<> 149:156823d33999 3146 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<> 149:156823d33999 3147
<> 149:156823d33999 3148 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
<> 149:156823d33999 3149 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
<> 149:156823d33999 3150 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
<> 149:156823d33999 3151 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
<> 149:156823d33999 3152 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
<> 149:156823d33999 3153 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<> 149:156823d33999 3154 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<> 149:156823d33999 3155 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
<> 149:156823d33999 3156
<> 149:156823d33999 3157 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
<> 149:156823d33999 3158 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
<> 149:156823d33999 3159 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
<> 149:156823d33999 3160 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
<> 149:156823d33999 3161 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
<> 149:156823d33999 3162 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<> 149:156823d33999 3163 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<> 149:156823d33999 3164 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
<> 149:156823d33999 3165
<> 149:156823d33999 3166 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
<> 149:156823d33999 3167 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
<> 149:156823d33999 3168
<> 149:156823d33999 3169 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
<> 149:156823d33999 3170 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
<> 149:156823d33999 3171 /**
<> 149:156823d33999 3172 * @}
<> 149:156823d33999 3173 */
<> 149:156823d33999 3174
<> 149:156823d33999 3175 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3176 * @{
<> 149:156823d33999 3177 */
<> 149:156823d33999 3178 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
<> 149:156823d33999 3179 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
<> 149:156823d33999 3180
<> 149:156823d33999 3181 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
<> 149:156823d33999 3182 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
<> 149:156823d33999 3183
<> 149:156823d33999 3184 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
<> 149:156823d33999 3185
<> 149:156823d33999 3186 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
<> 149:156823d33999 3187 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
<> 149:156823d33999 3188 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
<> 149:156823d33999 3189 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
<> 149:156823d33999 3190 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
<> 149:156823d33999 3191 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
<> 149:156823d33999 3192 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
<> 149:156823d33999 3193 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
<> 149:156823d33999 3194 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
<> 149:156823d33999 3195 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
<> 149:156823d33999 3196 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
<> 149:156823d33999 3197 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
<> 149:156823d33999 3198
<> 149:156823d33999 3199 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
<> 149:156823d33999 3200 /**
<> 149:156823d33999 3201 * @}
<> 149:156823d33999 3202 */
<> 149:156823d33999 3203
<> 149:156823d33999 3204 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3205 * @{
<> 149:156823d33999 3206 */
<> 149:156823d33999 3207
<> 149:156823d33999 3208 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
<> 149:156823d33999 3209 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
<> 149:156823d33999 3210 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
<> 149:156823d33999 3211 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
<> 149:156823d33999 3212 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
<> 149:156823d33999 3213 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
<> 149:156823d33999 3214 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
<> 149:156823d33999 3215
<> 149:156823d33999 3216 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
<> 149:156823d33999 3217 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
<> 149:156823d33999 3218 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
<> 149:156823d33999 3219 /**
<> 149:156823d33999 3220 * @}
<> 149:156823d33999 3221 */
<> 149:156823d33999 3222
<> 149:156823d33999 3223 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3224 * @{
<> 149:156823d33999 3225 */
<> 149:156823d33999 3226 #define __HAL_LTDC_LAYER LTDC_LAYER
AnnaBridge 184:08ed48f1de7f 3227 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
<> 149:156823d33999 3228 /**
<> 149:156823d33999 3229 * @}
<> 149:156823d33999 3230 */
<> 149:156823d33999 3231
<> 149:156823d33999 3232 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3233 * @{
<> 149:156823d33999 3234 */
<> 149:156823d33999 3235 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
<> 149:156823d33999 3236 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
<> 149:156823d33999 3237 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
<> 149:156823d33999 3238 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
<> 149:156823d33999 3239 #define SAI_STREOMODE SAI_STEREOMODE
<> 149:156823d33999 3240 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
<> 149:156823d33999 3241 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
<> 149:156823d33999 3242 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
<> 149:156823d33999 3243 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
<> 149:156823d33999 3244 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
<> 149:156823d33999 3245 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
<> 149:156823d33999 3246 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
<> 149:156823d33999 3247 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
<> 149:156823d33999 3248 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
<> 149:156823d33999 3249 /**
<> 149:156823d33999 3250 * @}
<> 149:156823d33999 3251 */
<> 149:156823d33999 3252
<> 149:156823d33999 3253
<> 149:156823d33999 3254 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
<> 149:156823d33999 3255 * @{
<> 149:156823d33999 3256 */
<> 149:156823d33999 3257
<> 149:156823d33999 3258 /**
<> 149:156823d33999 3259 * @}
<> 149:156823d33999 3260 */
<> 149:156823d33999 3261
<> 149:156823d33999 3262 #ifdef __cplusplus
<> 149:156823d33999 3263 }
<> 149:156823d33999 3264 #endif
<> 149:156823d33999 3265
<> 149:156823d33999 3266 #endif /* ___STM32_HAL_LEGACY */
<> 149:156823d33999 3267
<> 149:156823d33999 3268 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 149:156823d33999 3269