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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/**
AnnaBridge	167:e84263d55307	2	******************************************************************************
AnnaBridge	167:e84263d55307	3	* @file stm32f2xx_ll_tim.h
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
AnnaBridge	167:e84263d55307	7	* @brief Header file of TIM LL module.
AnnaBridge	167:e84263d55307	8	******************************************************************************
AnnaBridge	167:e84263d55307	9	* @attention
AnnaBridge	167:e84263d55307	10	*
AnnaBridge	167:e84263d55307	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	167:e84263d55307	12	*
AnnaBridge	167:e84263d55307	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	167:e84263d55307	14	* are permitted provided that the following conditions are met:
AnnaBridge	167:e84263d55307	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	167:e84263d55307	16	* this list of conditions and the following disclaimer.
AnnaBridge	167:e84263d55307	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	167:e84263d55307	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	167:e84263d55307	19	* and/or other materials provided with the distribution.
AnnaBridge	167:e84263d55307	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	167:e84263d55307	21	* may be used to endorse or promote products derived from this software
AnnaBridge	167:e84263d55307	22	* without specific prior written permission.
AnnaBridge	167:e84263d55307	23	*
AnnaBridge	167:e84263d55307	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	167:e84263d55307	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	167:e84263d55307	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	167:e84263d55307	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	167:e84263d55307	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	167:e84263d55307	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	167:e84263d55307	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	167:e84263d55307	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	167:e84263d55307	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	167:e84263d55307	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	167:e84263d55307	34	*
AnnaBridge	167:e84263d55307	35	******************************************************************************
AnnaBridge	167:e84263d55307	36	*/
AnnaBridge	167:e84263d55307	37
AnnaBridge	167:e84263d55307	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	167:e84263d55307	39	#ifndef __STM32F2xx_LL_TIM_H
AnnaBridge	167:e84263d55307	40	#define __STM32F2xx_LL_TIM_H
AnnaBridge	167:e84263d55307	41
AnnaBridge	167:e84263d55307	42	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	43	extern "C" {
AnnaBridge	167:e84263d55307	44	#endif
AnnaBridge	167:e84263d55307	45
AnnaBridge	167:e84263d55307	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	47	#include "stm32f2xx.h"
AnnaBridge	167:e84263d55307	48
AnnaBridge	167:e84263d55307	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	167:e84263d55307	50	* @{
AnnaBridge	167:e84263d55307	51	*/
AnnaBridge	167:e84263d55307	52
AnnaBridge	167:e84263d55307	53	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14)
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/** @defgroup TIM_LL TIM
AnnaBridge	167:e84263d55307	56	* @{
AnnaBridge	167:e84263d55307	57	*/
AnnaBridge	167:e84263d55307	58
AnnaBridge	167:e84263d55307	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	167:e84263d55307	62	* @{
AnnaBridge	167:e84263d55307	63	*/
AnnaBridge	167:e84263d55307	64	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	167:e84263d55307	65	{
AnnaBridge	167:e84263d55307	66	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	167:e84263d55307	67	0x00U, /* 1: TIMx_CH1N */
AnnaBridge	167:e84263d55307	68	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	167:e84263d55307	69	0x00U, /* 3: TIMx_CH2N */
AnnaBridge	167:e84263d55307	70	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	167:e84263d55307	71	0x04U, /* 5: TIMx_CH3N */
AnnaBridge	167:e84263d55307	72	0x04U /* 6: TIMx_CH4 */
AnnaBridge	167:e84263d55307	73	};
AnnaBridge	167:e84263d55307	74
AnnaBridge	167:e84263d55307	75	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	167:e84263d55307	76	{
AnnaBridge	167:e84263d55307	77	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	167:e84263d55307	78	0U, /* 1: - NA */
AnnaBridge	167:e84263d55307	79	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	167:e84263d55307	80	0U, /* 3: - NA */
AnnaBridge	167:e84263d55307	81	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	167:e84263d55307	82	0U, /* 5: - NA */
AnnaBridge	167:e84263d55307	83	8U /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	167:e84263d55307	84	};
AnnaBridge	167:e84263d55307	85
AnnaBridge	167:e84263d55307	86	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	167:e84263d55307	87	{
AnnaBridge	167:e84263d55307	88	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	167:e84263d55307	89	0U, /* 1: - NA */
AnnaBridge	167:e84263d55307	90	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	167:e84263d55307	91	0U, /* 3: - NA */
AnnaBridge	167:e84263d55307	92	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	167:e84263d55307	93	0U, /* 5: - NA */
AnnaBridge	167:e84263d55307	94	8U /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	167:e84263d55307	95	};
AnnaBridge	167:e84263d55307	96
AnnaBridge	167:e84263d55307	97	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	167:e84263d55307	98	{
AnnaBridge	167:e84263d55307	99	0U, /* 0: CC1P */
AnnaBridge	167:e84263d55307	100	2U, /* 1: CC1NP */
AnnaBridge	167:e84263d55307	101	4U, /* 2: CC2P */
AnnaBridge	167:e84263d55307	102	6U, /* 3: CC2NP */
AnnaBridge	167:e84263d55307	103	8U, /* 4: CC3P */
AnnaBridge	167:e84263d55307	104	10U, /* 5: CC3NP */
AnnaBridge	167:e84263d55307	105	12U /* 6: CC4P */
AnnaBridge	167:e84263d55307	106	};
AnnaBridge	167:e84263d55307	107
AnnaBridge	167:e84263d55307	108	static const uint8_t SHIFT_TAB_OISx[] =
AnnaBridge	167:e84263d55307	109	{
AnnaBridge	167:e84263d55307	110	0U, /* 0: OIS1 */
AnnaBridge	167:e84263d55307	111	1U, /* 1: OIS1N */
AnnaBridge	167:e84263d55307	112	2U, /* 2: OIS2 */
AnnaBridge	167:e84263d55307	113	3U, /* 3: OIS2N */
AnnaBridge	167:e84263d55307	114	4U, /* 4: OIS3 */
AnnaBridge	167:e84263d55307	115	5U, /* 5: OIS3N */
AnnaBridge	167:e84263d55307	116	6U /* 6: OIS4 */
AnnaBridge	167:e84263d55307	117	};
AnnaBridge	167:e84263d55307	118	/**
AnnaBridge	167:e84263d55307	119	* @}
AnnaBridge	167:e84263d55307	120	*/
AnnaBridge	167:e84263d55307	121
AnnaBridge	167:e84263d55307	122
AnnaBridge	167:e84263d55307	123	/* Private constants ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	124	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	167:e84263d55307	125	* @{
AnnaBridge	167:e84263d55307	126	*/
AnnaBridge	167:e84263d55307	127
AnnaBridge	167:e84263d55307	128
AnnaBridge	167:e84263d55307	129	/* Remap mask definitions */
AnnaBridge	167:e84263d55307	130	#define TIMx_OR_RMP_SHIFT 16U
AnnaBridge	167:e84263d55307	131	#define TIMx_OR_RMP_MASK 0x0000FFFFU
AnnaBridge	167:e84263d55307	132	#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	167:e84263d55307	133	#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	167:e84263d55307	134	#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	167:e84263d55307	135
AnnaBridge	167:e84263d55307	136	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
AnnaBridge	167:e84263d55307	137	#define DT_DELAY_1 ((uint8_t)0x7FU)
AnnaBridge	167:e84263d55307	138	#define DT_DELAY_2 ((uint8_t)0x3FU)
AnnaBridge	167:e84263d55307	139	#define DT_DELAY_3 ((uint8_t)0x1FU)
AnnaBridge	167:e84263d55307	140	#define DT_DELAY_4 ((uint8_t)0x1FU)
AnnaBridge	167:e84263d55307	141
AnnaBridge	167:e84263d55307	142	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
AnnaBridge	167:e84263d55307	143	#define DT_RANGE_1 ((uint8_t)0x00U)
AnnaBridge	167:e84263d55307	144	#define DT_RANGE_2 ((uint8_t)0x80U)
AnnaBridge	167:e84263d55307	145	#define DT_RANGE_3 ((uint8_t)0xC0U)
AnnaBridge	167:e84263d55307	146	#define DT_RANGE_4 ((uint8_t)0xE0U)
AnnaBridge	167:e84263d55307	147
AnnaBridge	167:e84263d55307	148
AnnaBridge	167:e84263d55307	149	/**
AnnaBridge	167:e84263d55307	150	* @}
AnnaBridge	167:e84263d55307	151	*/
AnnaBridge	167:e84263d55307	152
AnnaBridge	167:e84263d55307	153	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	154	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	167:e84263d55307	155	* @{
AnnaBridge	167:e84263d55307	156	*/
AnnaBridge	167:e84263d55307	157	/** @brief Convert channel id into channel index.
AnnaBridge	167:e84263d55307	158	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	159	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	160	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	161	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	162	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	163	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	164	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	165	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	166	* @retval none
AnnaBridge	167:e84263d55307	167	*/
AnnaBridge	167:e84263d55307	168	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	167:e84263d55307	169	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	167:e84263d55307	170	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	167:e84263d55307	171	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	167:e84263d55307	172	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	167:e84263d55307	173	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	167:e84263d55307	174	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
AnnaBridge	167:e84263d55307	175
AnnaBridge	167:e84263d55307	176	/** @brief Calculate the deadtime sampling period(in ps).
AnnaBridge	167:e84263d55307	177	* @param __TIMCLK__ timer input clock frequency (in Hz).
AnnaBridge	167:e84263d55307	178	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	179	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	167:e84263d55307	180	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	167:e84263d55307	181	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	167:e84263d55307	182	* @retval none
AnnaBridge	167:e84263d55307	183	*/
AnnaBridge	167:e84263d55307	184	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
AnnaBridge	167:e84263d55307	185	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
AnnaBridge	167:e84263d55307	186	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
AnnaBridge	167:e84263d55307	187	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
AnnaBridge	167:e84263d55307	188	/**
AnnaBridge	167:e84263d55307	189	* @}
AnnaBridge	167:e84263d55307	190	*/
AnnaBridge	167:e84263d55307	191
AnnaBridge	167:e84263d55307	192
AnnaBridge	167:e84263d55307	193	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	194	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	195	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	167:e84263d55307	196	* @{
AnnaBridge	167:e84263d55307	197	*/
AnnaBridge	167:e84263d55307	198
AnnaBridge	167:e84263d55307	199	/**
AnnaBridge	167:e84263d55307	200	* @brief TIM Time Base configuration structure definition.
AnnaBridge	167:e84263d55307	201	*/
AnnaBridge	167:e84263d55307	202	typedef struct
AnnaBridge	167:e84263d55307	203	{
AnnaBridge	167:e84263d55307	204	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	167:e84263d55307	205	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	167:e84263d55307	206
AnnaBridge	167:e84263d55307	207	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	167:e84263d55307	208
AnnaBridge	167:e84263d55307	209	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	167:e84263d55307	210	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	167:e84263d55307	211
AnnaBridge	167:e84263d55307	212	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	167:e84263d55307	213
AnnaBridge	167:e84263d55307	214	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	167:e84263d55307	215	Auto-Reload Register at the next update event.
AnnaBridge	167:e84263d55307	216	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	167:e84263d55307	217	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	218
AnnaBridge	167:e84263d55307	219	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	167:e84263d55307	220
AnnaBridge	167:e84263d55307	221	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	167:e84263d55307	222	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	167:e84263d55307	223
AnnaBridge	167:e84263d55307	224	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	167:e84263d55307	225
AnnaBridge	167:e84263d55307	226	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	167:e84263d55307	227	reaches zero, an update event is generated and counting restarts
AnnaBridge	167:e84263d55307	228	from the RCR value (N).
AnnaBridge	167:e84263d55307	229	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	167:e84263d55307	230	- the number of PWM periods in edge-aligned mode
AnnaBridge	167:e84263d55307	231	- the number of half PWM period in center-aligned mode
AnnaBridge	167:e84263d55307	232	This parameter must be a number between 0x00 and 0xFF.
AnnaBridge	167:e84263d55307	233
AnnaBridge	167:e84263d55307	234	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
AnnaBridge	167:e84263d55307	235	} LL_TIM_InitTypeDef;
AnnaBridge	167:e84263d55307	236
AnnaBridge	167:e84263d55307	237	/**
AnnaBridge	167:e84263d55307	238	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	167:e84263d55307	239	*/
AnnaBridge	167:e84263d55307	240	typedef struct
AnnaBridge	167:e84263d55307	241	{
AnnaBridge	167:e84263d55307	242	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	167:e84263d55307	243	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	167:e84263d55307	244
AnnaBridge	167:e84263d55307	245	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	167:e84263d55307	246
AnnaBridge	167:e84263d55307	247	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	167:e84263d55307	248	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	167:e84263d55307	249
AnnaBridge	167:e84263d55307	250	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	167:e84263d55307	251
AnnaBridge	167:e84263d55307	252	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
AnnaBridge	167:e84263d55307	253	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	167:e84263d55307	254
AnnaBridge	167:e84263d55307	255	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	167:e84263d55307	256
AnnaBridge	167:e84263d55307	257	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	167:e84263d55307	258	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	167:e84263d55307	259
AnnaBridge	167:e84263d55307	260	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	167:e84263d55307	261
AnnaBridge	167:e84263d55307	262	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	167:e84263d55307	263	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	167:e84263d55307	264
AnnaBridge	167:e84263d55307	265	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	167:e84263d55307	266
AnnaBridge	167:e84263d55307	267	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	167:e84263d55307	268	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	167:e84263d55307	269
AnnaBridge	167:e84263d55307	270	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	167:e84263d55307	271
AnnaBridge	167:e84263d55307	272
AnnaBridge	167:e84263d55307	273	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	167:e84263d55307	274	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	167:e84263d55307	275
AnnaBridge	167:e84263d55307	276	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	167:e84263d55307	277
AnnaBridge	167:e84263d55307	278	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	167:e84263d55307	279	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	167:e84263d55307	280
AnnaBridge	167:e84263d55307	281	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	167:e84263d55307	282	} LL_TIM_OC_InitTypeDef;
AnnaBridge	167:e84263d55307	283
AnnaBridge	167:e84263d55307	284	/**
AnnaBridge	167:e84263d55307	285	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	167:e84263d55307	286	*/
AnnaBridge	167:e84263d55307	287
AnnaBridge	167:e84263d55307	288	typedef struct
AnnaBridge	167:e84263d55307	289	{
AnnaBridge	167:e84263d55307	290
AnnaBridge	167:e84263d55307	291	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	167:e84263d55307	292	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	167:e84263d55307	293
AnnaBridge	167:e84263d55307	294	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	167:e84263d55307	295
AnnaBridge	167:e84263d55307	296	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	167:e84263d55307	297	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	167:e84263d55307	298
AnnaBridge	167:e84263d55307	299	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	167:e84263d55307	300
AnnaBridge	167:e84263d55307	301	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	167:e84263d55307	302	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	167:e84263d55307	303
AnnaBridge	167:e84263d55307	304	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	167:e84263d55307	305
AnnaBridge	167:e84263d55307	306	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	167:e84263d55307	307	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	167:e84263d55307	308
AnnaBridge	167:e84263d55307	309	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	167:e84263d55307	310	} LL_TIM_IC_InitTypeDef;
AnnaBridge	167:e84263d55307	311
AnnaBridge	167:e84263d55307	312
AnnaBridge	167:e84263d55307	313	/**
AnnaBridge	167:e84263d55307	314	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	167:e84263d55307	315	*/
AnnaBridge	167:e84263d55307	316	typedef struct
AnnaBridge	167:e84263d55307	317	{
AnnaBridge	167:e84263d55307	318	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	167:e84263d55307	319	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	167:e84263d55307	320
AnnaBridge	167:e84263d55307	321	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	167:e84263d55307	322
AnnaBridge	167:e84263d55307	323	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	167:e84263d55307	324	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	167:e84263d55307	325
AnnaBridge	167:e84263d55307	326	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	167:e84263d55307	327
AnnaBridge	167:e84263d55307	328	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	167:e84263d55307	329	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	167:e84263d55307	330
AnnaBridge	167:e84263d55307	331	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	167:e84263d55307	332
AnnaBridge	167:e84263d55307	333	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	167:e84263d55307	334	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	167:e84263d55307	335
AnnaBridge	167:e84263d55307	336	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	167:e84263d55307	337
AnnaBridge	167:e84263d55307	338	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	167:e84263d55307	339	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	167:e84263d55307	340
AnnaBridge	167:e84263d55307	341	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	167:e84263d55307	342
AnnaBridge	167:e84263d55307	343	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	167:e84263d55307	344	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	167:e84263d55307	345
AnnaBridge	167:e84263d55307	346	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	167:e84263d55307	347
AnnaBridge	167:e84263d55307	348	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	167:e84263d55307	349	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	167:e84263d55307	350
AnnaBridge	167:e84263d55307	351	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	167:e84263d55307	352
AnnaBridge	167:e84263d55307	353	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	167:e84263d55307	354	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	167:e84263d55307	355
AnnaBridge	167:e84263d55307	356	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	167:e84263d55307	357
AnnaBridge	167:e84263d55307	358	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	167:e84263d55307	359	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	167:e84263d55307	360
AnnaBridge	167:e84263d55307	361	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	167:e84263d55307	362
AnnaBridge	167:e84263d55307	363	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	167:e84263d55307	364
AnnaBridge	167:e84263d55307	365	/**
AnnaBridge	167:e84263d55307	366	* @brief TIM Hall sensor interface configuration structure definition.
AnnaBridge	167:e84263d55307	367	*/
AnnaBridge	167:e84263d55307	368	typedef struct
AnnaBridge	167:e84263d55307	369	{
AnnaBridge	167:e84263d55307	370
AnnaBridge	167:e84263d55307	371	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	167:e84263d55307	372	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	167:e84263d55307	373
AnnaBridge	167:e84263d55307	374	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	167:e84263d55307	375
AnnaBridge	167:e84263d55307	376	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	167:e84263d55307	377	Prescaler must be set to get a maximum counter period longer than the
AnnaBridge	167:e84263d55307	378	time interval between 2 consecutive changes on the Hall inputs.
AnnaBridge	167:e84263d55307	379	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	167:e84263d55307	380
AnnaBridge	167:e84263d55307	381	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	167:e84263d55307	382
AnnaBridge	167:e84263d55307	383	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	167:e84263d55307	384	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	167:e84263d55307	385
AnnaBridge	167:e84263d55307	386	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	167:e84263d55307	387
AnnaBridge	167:e84263d55307	388	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
AnnaBridge	167:e84263d55307	389	A positive pulse (TRGO event) is generated with a programmable delay every time
AnnaBridge	167:e84263d55307	390	a change occurs on the Hall inputs.
AnnaBridge	167:e84263d55307	391	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
AnnaBridge	167:e84263d55307	392
AnnaBridge	167:e84263d55307	393	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
AnnaBridge	167:e84263d55307	394	} LL_TIM_HALLSENSOR_InitTypeDef;
AnnaBridge	167:e84263d55307	395
AnnaBridge	167:e84263d55307	396	/**
AnnaBridge	167:e84263d55307	397	* @brief BDTR (Break and Dead Time) structure definition
AnnaBridge	167:e84263d55307	398	*/
AnnaBridge	167:e84263d55307	399	typedef struct
AnnaBridge	167:e84263d55307	400	{
AnnaBridge	167:e84263d55307	401	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
AnnaBridge	167:e84263d55307	402	This parameter can be a value of @ref TIM_LL_EC_OSSR
AnnaBridge	167:e84263d55307	403
AnnaBridge	167:e84263d55307	404	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	167:e84263d55307	405
AnnaBridge	167:e84263d55307	406	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	167:e84263d55307	407
AnnaBridge	167:e84263d55307	408	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
AnnaBridge	167:e84263d55307	409	This parameter can be a value of @ref TIM_LL_EC_OSSI
AnnaBridge	167:e84263d55307	410
AnnaBridge	167:e84263d55307	411	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	167:e84263d55307	412
AnnaBridge	167:e84263d55307	413	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	167:e84263d55307	414
AnnaBridge	167:e84263d55307	415	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
AnnaBridge	167:e84263d55307	416	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
AnnaBridge	167:e84263d55307	417
AnnaBridge	167:e84263d55307	418	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
AnnaBridge	167:e84263d55307	419	has been written, their content is frozen until the next reset.*/
AnnaBridge	167:e84263d55307	420
AnnaBridge	167:e84263d55307	421	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
AnnaBridge	167:e84263d55307	422	switching-on of the outputs.
AnnaBridge	167:e84263d55307	423	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	167:e84263d55307	424
AnnaBridge	167:e84263d55307	425	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
AnnaBridge	167:e84263d55307	426
AnnaBridge	167:e84263d55307	427	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
AnnaBridge	167:e84263d55307	428
AnnaBridge	167:e84263d55307	429	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
AnnaBridge	167:e84263d55307	430	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
AnnaBridge	167:e84263d55307	431
AnnaBridge	167:e84263d55307	432	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
AnnaBridge	167:e84263d55307	433
AnnaBridge	167:e84263d55307	434	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	167:e84263d55307	435
AnnaBridge	167:e84263d55307	436	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
AnnaBridge	167:e84263d55307	437	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
AnnaBridge	167:e84263d55307	438
AnnaBridge	167:e84263d55307	439	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	167:e84263d55307	440
AnnaBridge	167:e84263d55307	441	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	167:e84263d55307	442
AnnaBridge	167:e84263d55307	443	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
AnnaBridge	167:e84263d55307	444	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
AnnaBridge	167:e84263d55307	445
AnnaBridge	167:e84263d55307	446	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
AnnaBridge	167:e84263d55307	447
AnnaBridge	167:e84263d55307	448	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	167:e84263d55307	449	} LL_TIM_BDTR_InitTypeDef;
AnnaBridge	167:e84263d55307	450
AnnaBridge	167:e84263d55307	451	/**
AnnaBridge	167:e84263d55307	452	* @}
AnnaBridge	167:e84263d55307	453	*/
AnnaBridge	167:e84263d55307	454	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	455
AnnaBridge	167:e84263d55307	456	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	457	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	167:e84263d55307	458	* @{
AnnaBridge	167:e84263d55307	459	*/
AnnaBridge	167:e84263d55307	460
AnnaBridge	167:e84263d55307	461	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	167:e84263d55307	462	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	167:e84263d55307	463	* @{
AnnaBridge	167:e84263d55307	464	*/
AnnaBridge	167:e84263d55307	465	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	167:e84263d55307	466	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	167:e84263d55307	467	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	167:e84263d55307	468	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	167:e84263d55307	469	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	167:e84263d55307	470	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
AnnaBridge	167:e84263d55307	471	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	167:e84263d55307	472	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
AnnaBridge	167:e84263d55307	473	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	167:e84263d55307	474	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	167:e84263d55307	475	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	167:e84263d55307	476	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	167:e84263d55307	477	/**
AnnaBridge	167:e84263d55307	478	* @}
AnnaBridge	167:e84263d55307	479	*/
AnnaBridge	167:e84263d55307	480
AnnaBridge	167:e84263d55307	481	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	482	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
AnnaBridge	167:e84263d55307	483	* @{
AnnaBridge	167:e84263d55307	484	*/
AnnaBridge	167:e84263d55307	485	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
AnnaBridge	167:e84263d55307	486	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
AnnaBridge	167:e84263d55307	487	/**
AnnaBridge	167:e84263d55307	488	* @}
AnnaBridge	167:e84263d55307	489	*/
AnnaBridge	167:e84263d55307	490
AnnaBridge	167:e84263d55307	491	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
AnnaBridge	167:e84263d55307	492	* @{
AnnaBridge	167:e84263d55307	493	*/
AnnaBridge	167:e84263d55307	494	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
AnnaBridge	167:e84263d55307	495	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
AnnaBridge	167:e84263d55307	496	/**
AnnaBridge	167:e84263d55307	497	* @}
AnnaBridge	167:e84263d55307	498	*/
AnnaBridge	167:e84263d55307	499	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	500
AnnaBridge	167:e84263d55307	501	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	167:e84263d55307	502	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	167:e84263d55307	503	* @{
AnnaBridge	167:e84263d55307	504	*/
AnnaBridge	167:e84263d55307	505	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	167:e84263d55307	506	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	167:e84263d55307	507	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	167:e84263d55307	508	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	167:e84263d55307	509	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	167:e84263d55307	510	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
AnnaBridge	167:e84263d55307	511	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	167:e84263d55307	512	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
AnnaBridge	167:e84263d55307	513	/**
AnnaBridge	167:e84263d55307	514	* @}
AnnaBridge	167:e84263d55307	515	*/
AnnaBridge	167:e84263d55307	516
AnnaBridge	167:e84263d55307	517	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	167:e84263d55307	518	* @{
AnnaBridge	167:e84263d55307	519	*/
AnnaBridge	167:e84263d55307	520	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	167:e84263d55307	521	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	167:e84263d55307	522	/**
AnnaBridge	167:e84263d55307	523	* @}
AnnaBridge	167:e84263d55307	524	*/
AnnaBridge	167:e84263d55307	525
AnnaBridge	167:e84263d55307	526	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	167:e84263d55307	527	* @{
AnnaBridge	167:e84263d55307	528	*/
AnnaBridge	167:e84263d55307	529	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	167:e84263d55307	530	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	167:e84263d55307	531	/**
AnnaBridge	167:e84263d55307	532	* @}
AnnaBridge	167:e84263d55307	533	*/
AnnaBridge	167:e84263d55307	534
AnnaBridge	167:e84263d55307	535	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	167:e84263d55307	536	* @{
AnnaBridge	167:e84263d55307	537	*/
AnnaBridge	167:e84263d55307	538	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	167:e84263d55307	539	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	167:e84263d55307	540	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	167:e84263d55307	541	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	167:e84263d55307	542	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	167:e84263d55307	543	/**
AnnaBridge	167:e84263d55307	544	* @}
AnnaBridge	167:e84263d55307	545	*/
AnnaBridge	167:e84263d55307	546
AnnaBridge	167:e84263d55307	547	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	167:e84263d55307	548	* @{
AnnaBridge	167:e84263d55307	549	*/
AnnaBridge	167:e84263d55307	550	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	167:e84263d55307	551	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	167:e84263d55307	552	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	167:e84263d55307	553	/**
AnnaBridge	167:e84263d55307	554	* @}
AnnaBridge	167:e84263d55307	555	*/
AnnaBridge	167:e84263d55307	556
AnnaBridge	167:e84263d55307	557	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	167:e84263d55307	558	* @{
AnnaBridge	167:e84263d55307	559	*/
AnnaBridge	167:e84263d55307	560	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	167:e84263d55307	561	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	167:e84263d55307	562	/**
AnnaBridge	167:e84263d55307	563	* @}
AnnaBridge	167:e84263d55307	564	*/
AnnaBridge	167:e84263d55307	565
AnnaBridge	167:e84263d55307	566	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
AnnaBridge	167:e84263d55307	567	* @{
AnnaBridge	167:e84263d55307	568	*/
AnnaBridge	167:e84263d55307	569	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
AnnaBridge	167:e84263d55307	570	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
AnnaBridge	167:e84263d55307	571	/**
AnnaBridge	167:e84263d55307	572	* @}
AnnaBridge	167:e84263d55307	573	*/
AnnaBridge	167:e84263d55307	574
AnnaBridge	167:e84263d55307	575	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	167:e84263d55307	576	* @{
AnnaBridge	167:e84263d55307	577	*/
AnnaBridge	167:e84263d55307	578	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	167:e84263d55307	579	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	167:e84263d55307	580	/**
AnnaBridge	167:e84263d55307	581	* @}
AnnaBridge	167:e84263d55307	582	*/
AnnaBridge	167:e84263d55307	583
AnnaBridge	167:e84263d55307	584	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
AnnaBridge	167:e84263d55307	585	* @{
AnnaBridge	167:e84263d55307	586	*/
AnnaBridge	167:e84263d55307	587	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
AnnaBridge	167:e84263d55307	588	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
AnnaBridge	167:e84263d55307	589	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
AnnaBridge	167:e84263d55307	590	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
AnnaBridge	167:e84263d55307	591	/**
AnnaBridge	167:e84263d55307	592	* @}
AnnaBridge	167:e84263d55307	593	*/
AnnaBridge	167:e84263d55307	594
AnnaBridge	167:e84263d55307	595	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	167:e84263d55307	596	* @{
AnnaBridge	167:e84263d55307	597	*/
AnnaBridge	167:e84263d55307	598	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	167:e84263d55307	599	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	167:e84263d55307	600	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	167:e84263d55307	601	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	167:e84263d55307	602	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	167:e84263d55307	603	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	167:e84263d55307	604	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	167:e84263d55307	605	/**
AnnaBridge	167:e84263d55307	606	* @}
AnnaBridge	167:e84263d55307	607	*/
AnnaBridge	167:e84263d55307	608
AnnaBridge	167:e84263d55307	609	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	610	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	167:e84263d55307	611	* @{
AnnaBridge	167:e84263d55307	612	*/
AnnaBridge	167:e84263d55307	613	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	167:e84263d55307	614	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	167:e84263d55307	615	/**
AnnaBridge	167:e84263d55307	616	* @}
AnnaBridge	167:e84263d55307	617	*/
AnnaBridge	167:e84263d55307	618	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	619
AnnaBridge	167:e84263d55307	620	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	167:e84263d55307	621	* @{
AnnaBridge	167:e84263d55307	622	*/
AnnaBridge	167:e84263d55307	623	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	167:e84263d55307	624	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	167:e84263d55307	625	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	167:e84263d55307	626	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	167:e84263d55307	627	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	167:e84263d55307	628	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	167:e84263d55307	629	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	167:e84263d55307	630	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	167:e84263d55307	631	/**
AnnaBridge	167:e84263d55307	632	* @}
AnnaBridge	167:e84263d55307	633	*/
AnnaBridge	167:e84263d55307	634
AnnaBridge	167:e84263d55307	635	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	167:e84263d55307	636	* @{
AnnaBridge	167:e84263d55307	637	*/
AnnaBridge	167:e84263d55307	638	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	167:e84263d55307	639	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	167:e84263d55307	640	/**
AnnaBridge	167:e84263d55307	641	* @}
AnnaBridge	167:e84263d55307	642	*/
AnnaBridge	167:e84263d55307	643
AnnaBridge	167:e84263d55307	644	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
AnnaBridge	167:e84263d55307	645	* @{
AnnaBridge	167:e84263d55307	646	*/
AnnaBridge	167:e84263d55307	647	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	167:e84263d55307	648	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	167:e84263d55307	649	/**
AnnaBridge	167:e84263d55307	650	* @}
AnnaBridge	167:e84263d55307	651	*/
AnnaBridge	167:e84263d55307	652
AnnaBridge	167:e84263d55307	653
AnnaBridge	167:e84263d55307	654	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	167:e84263d55307	655	* @{
AnnaBridge	167:e84263d55307	656	*/
AnnaBridge	167:e84263d55307	657	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	167:e84263d55307	658	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	167:e84263d55307	659	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	167:e84263d55307	660	/**
AnnaBridge	167:e84263d55307	661	* @}
AnnaBridge	167:e84263d55307	662	*/
AnnaBridge	167:e84263d55307	663
AnnaBridge	167:e84263d55307	664	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	167:e84263d55307	665	* @{
AnnaBridge	167:e84263d55307	666	*/
AnnaBridge	167:e84263d55307	667	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	167:e84263d55307	668	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	167:e84263d55307	669	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	167:e84263d55307	670	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	167:e84263d55307	671	/**
AnnaBridge	167:e84263d55307	672	* @}
AnnaBridge	167:e84263d55307	673	*/
AnnaBridge	167:e84263d55307	674
AnnaBridge	167:e84263d55307	675	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	167:e84263d55307	676	* @{
AnnaBridge	167:e84263d55307	677	*/
AnnaBridge	167:e84263d55307	678	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	167:e84263d55307	679	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	167:e84263d55307	680	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	167:e84263d55307	681	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	167:e84263d55307	682	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	167:e84263d55307	683	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	167:e84263d55307	684	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	167:e84263d55307	685	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	167:e84263d55307	686	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	167:e84263d55307	687	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	167:e84263d55307	688	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	167:e84263d55307	689	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	167:e84263d55307	690	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	167:e84263d55307	691	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	167:e84263d55307	692	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	167:e84263d55307	693	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	167:e84263d55307	694	/**
AnnaBridge	167:e84263d55307	695	* @}
AnnaBridge	167:e84263d55307	696	*/
AnnaBridge	167:e84263d55307	697
AnnaBridge	167:e84263d55307	698	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	167:e84263d55307	699	* @{
AnnaBridge	167:e84263d55307	700	*/
AnnaBridge	167:e84263d55307	701	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	167:e84263d55307	702	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	167:e84263d55307	703	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	167:e84263d55307	704	/**
AnnaBridge	167:e84263d55307	705	* @}
AnnaBridge	167:e84263d55307	706	*/
AnnaBridge	167:e84263d55307	707
AnnaBridge	167:e84263d55307	708	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	167:e84263d55307	709	* @{
AnnaBridge	167:e84263d55307	710	*/
AnnaBridge	167:e84263d55307	711	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	167:e84263d55307	712	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
AnnaBridge	167:e84263d55307	713	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	167:e84263d55307	714	/**
AnnaBridge	167:e84263d55307	715	* @}
AnnaBridge	167:e84263d55307	716	*/
AnnaBridge	167:e84263d55307	717
AnnaBridge	167:e84263d55307	718	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	167:e84263d55307	719	* @{
AnnaBridge	167:e84263d55307	720	*/
AnnaBridge	167:e84263d55307	721	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	167:e84263d55307	722	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	167:e84263d55307	723	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
AnnaBridge	167:e84263d55307	724	/**
AnnaBridge	167:e84263d55307	725	* @}
AnnaBridge	167:e84263d55307	726	*/
AnnaBridge	167:e84263d55307	727
AnnaBridge	167:e84263d55307	728	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	167:e84263d55307	729	* @{
AnnaBridge	167:e84263d55307	730	*/
AnnaBridge	167:e84263d55307	731	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	167:e84263d55307	732	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	167:e84263d55307	733	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	167:e84263d55307	734	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	167:e84263d55307	735	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	167:e84263d55307	736	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	167:e84263d55307	737	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	167:e84263d55307	738	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	167:e84263d55307	739	/**
AnnaBridge	167:e84263d55307	740	* @}
AnnaBridge	167:e84263d55307	741	*/
AnnaBridge	167:e84263d55307	742
AnnaBridge	167:e84263d55307	743
AnnaBridge	167:e84263d55307	744	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	167:e84263d55307	745	* @{
AnnaBridge	167:e84263d55307	746	*/
AnnaBridge	167:e84263d55307	747	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	167:e84263d55307	748	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	167:e84263d55307	749	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	167:e84263d55307	750	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	167:e84263d55307	751	/**
AnnaBridge	167:e84263d55307	752	* @}
AnnaBridge	167:e84263d55307	753	*/
AnnaBridge	167:e84263d55307	754
AnnaBridge	167:e84263d55307	755	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	167:e84263d55307	756	* @{
AnnaBridge	167:e84263d55307	757	*/
AnnaBridge	167:e84263d55307	758	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	167:e84263d55307	759	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	167:e84263d55307	760	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	167:e84263d55307	761	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	167:e84263d55307	762	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	167:e84263d55307	763	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	167:e84263d55307	764	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	167:e84263d55307	765	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	167:e84263d55307	766	/**
AnnaBridge	167:e84263d55307	767	* @}
AnnaBridge	167:e84263d55307	768	*/
AnnaBridge	167:e84263d55307	769
AnnaBridge	167:e84263d55307	770	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	167:e84263d55307	771	* @{
AnnaBridge	167:e84263d55307	772	*/
AnnaBridge	167:e84263d55307	773	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	167:e84263d55307	774	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	167:e84263d55307	775	/**
AnnaBridge	167:e84263d55307	776	* @}
AnnaBridge	167:e84263d55307	777	*/
AnnaBridge	167:e84263d55307	778
AnnaBridge	167:e84263d55307	779	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	167:e84263d55307	780	* @{
AnnaBridge	167:e84263d55307	781	*/
AnnaBridge	167:e84263d55307	782	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	167:e84263d55307	783	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	167:e84263d55307	784	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	167:e84263d55307	785	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	167:e84263d55307	786	/**
AnnaBridge	167:e84263d55307	787	* @}
AnnaBridge	167:e84263d55307	788	*/
AnnaBridge	167:e84263d55307	789
AnnaBridge	167:e84263d55307	790	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	167:e84263d55307	791	* @{
AnnaBridge	167:e84263d55307	792	*/
AnnaBridge	167:e84263d55307	793	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	167:e84263d55307	794	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	167:e84263d55307	795	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	167:e84263d55307	796	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	167:e84263d55307	797	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	167:e84263d55307	798	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	167:e84263d55307	799	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	167:e84263d55307	800	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	167:e84263d55307	801	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	167:e84263d55307	802	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	167:e84263d55307	803	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	167:e84263d55307	804	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	167:e84263d55307	805	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	167:e84263d55307	806	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	167:e84263d55307	807	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	167:e84263d55307	808	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	167:e84263d55307	809	/**
AnnaBridge	167:e84263d55307	810	* @}
AnnaBridge	167:e84263d55307	811	*/
AnnaBridge	167:e84263d55307	812
AnnaBridge	167:e84263d55307	813
AnnaBridge	167:e84263d55307	814	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
AnnaBridge	167:e84263d55307	815	* @{
AnnaBridge	167:e84263d55307	816	*/
AnnaBridge	167:e84263d55307	817	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
AnnaBridge	167:e84263d55307	818	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
AnnaBridge	167:e84263d55307	819	/**
AnnaBridge	167:e84263d55307	820	* @}
AnnaBridge	167:e84263d55307	821	*/
AnnaBridge	167:e84263d55307	822
AnnaBridge	167:e84263d55307	823
AnnaBridge	167:e84263d55307	824
AnnaBridge	167:e84263d55307	825
AnnaBridge	167:e84263d55307	826	/** @defgroup TIM_LL_EC_OSSI OSSI
AnnaBridge	167:e84263d55307	827	* @{
AnnaBridge	167:e84263d55307	828	*/
AnnaBridge	167:e84263d55307	829	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	167:e84263d55307	830	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
AnnaBridge	167:e84263d55307	831	/**
AnnaBridge	167:e84263d55307	832	* @}
AnnaBridge	167:e84263d55307	833	*/
AnnaBridge	167:e84263d55307	834
AnnaBridge	167:e84263d55307	835	/** @defgroup TIM_LL_EC_OSSR OSSR
AnnaBridge	167:e84263d55307	836	* @{
AnnaBridge	167:e84263d55307	837	*/
AnnaBridge	167:e84263d55307	838	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	167:e84263d55307	839	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
AnnaBridge	167:e84263d55307	840	/**
AnnaBridge	167:e84263d55307	841	* @}
AnnaBridge	167:e84263d55307	842	*/
AnnaBridge	167:e84263d55307	843
AnnaBridge	167:e84263d55307	844
AnnaBridge	167:e84263d55307	845	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	167:e84263d55307	846	* @{
AnnaBridge	167:e84263d55307	847	*/
AnnaBridge	167:e84263d55307	848	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	849	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	850	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	851	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	852	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	853	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	854	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	855	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	856	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	857	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	858	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	859	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	860	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	861	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	862	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	863	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	864	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	865	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	167:e84263d55307	866	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0)
AnnaBridge	167:e84263d55307	867	/**
AnnaBridge	167:e84263d55307	868	* @}
AnnaBridge	167:e84263d55307	869	*/
AnnaBridge	167:e84263d55307	870
AnnaBridge	167:e84263d55307	871	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	167:e84263d55307	872	* @{
AnnaBridge	167:e84263d55307	873	*/
AnnaBridge	167:e84263d55307	874	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	875	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	876	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	877	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	878	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	879	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	880	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	881	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	882	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	883	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	884	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	885	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	886	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	887	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	888	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	889	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	890	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	891	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	167:e84263d55307	892	/**
AnnaBridge	167:e84263d55307	893	* @}
AnnaBridge	167:e84263d55307	894	*/
AnnaBridge	167:e84263d55307	895
AnnaBridge	167:e84263d55307	896
AnnaBridge	167:e84263d55307	897	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
AnnaBridge	167:e84263d55307	898	* @{
AnnaBridge	167:e84263d55307	899	*/
AnnaBridge	167:e84263d55307	900	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /!< TIM2_ITR1 is connected to TIM8_TRGO /
AnnaBridge	167:e84263d55307	901	#define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to ETH_PTP /
AnnaBridge	167:e84263d55307	902	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
AnnaBridge	167:e84263d55307	903	#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_HS SOF /
AnnaBridge	167:e84263d55307	904	/**
AnnaBridge	167:e84263d55307	905	* @}
AnnaBridge	167:e84263d55307	906	*/
AnnaBridge	167:e84263d55307	907
AnnaBridge	167:e84263d55307	908	/** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
AnnaBridge	167:e84263d55307	909	* @{
AnnaBridge	167:e84263d55307	910	*/
AnnaBridge	167:e84263d55307	911	#define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /!< TIM5 channel 4 is connected to GPIO /
AnnaBridge	167:e84263d55307	912	#define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSI internal clock /
AnnaBridge	167:e84263d55307	913	#define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSE /
AnnaBridge	167:e84263d55307	914	#define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to RTC wakeup interrupt /
AnnaBridge	167:e84263d55307	915	/**
AnnaBridge	167:e84263d55307	916	* @}
AnnaBridge	167:e84263d55307	917	*/
AnnaBridge	167:e84263d55307	918
AnnaBridge	167:e84263d55307	919	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
AnnaBridge	167:e84263d55307	920	* @{
AnnaBridge	167:e84263d55307	921	*/
AnnaBridge	167:e84263d55307	922	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /!< TIM11 channel 1 is connected to GPIO /
AnnaBridge	167:e84263d55307	923	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
AnnaBridge	167:e84263d55307	924	#define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
AnnaBridge	167:e84263d55307	925	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to HSE_RTC /
AnnaBridge	167:e84263d55307	926	/**
AnnaBridge	167:e84263d55307	927	* @}
AnnaBridge	167:e84263d55307	928	*/
AnnaBridge	167:e84263d55307	929
AnnaBridge	167:e84263d55307	930
AnnaBridge	167:e84263d55307	931	/**
AnnaBridge	167:e84263d55307	932	* @}
AnnaBridge	167:e84263d55307	933	*/
AnnaBridge	167:e84263d55307	934
AnnaBridge	167:e84263d55307	935	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	936	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	167:e84263d55307	937	* @{
AnnaBridge	167:e84263d55307	938	*/
AnnaBridge	167:e84263d55307	939
AnnaBridge	167:e84263d55307	940	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	167:e84263d55307	941	* @{
AnnaBridge	167:e84263d55307	942	*/
AnnaBridge	167:e84263d55307	943	/**
AnnaBridge	167:e84263d55307	944	* @brief Write a value in TIM register.
AnnaBridge	167:e84263d55307	945	* @param __INSTANCE__ TIM Instance
AnnaBridge	167:e84263d55307	946	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	947	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	948	* @retval None
AnnaBridge	167:e84263d55307	949	*/
AnnaBridge	167:e84263d55307	950	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	951
AnnaBridge	167:e84263d55307	952	/**
AnnaBridge	167:e84263d55307	953	* @brief Read a value in TIM register.
AnnaBridge	167:e84263d55307	954	* @param __INSTANCE__ TIM Instance
AnnaBridge	167:e84263d55307	955	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	956	* @retval Register value
AnnaBridge	167:e84263d55307	957	*/
AnnaBridge	167:e84263d55307	958	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	167:e84263d55307	959	/**
AnnaBridge	167:e84263d55307	960	* @}
AnnaBridge	167:e84263d55307	961	*/
AnnaBridge	167:e84263d55307	962
AnnaBridge	167:e84263d55307	963	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	167:e84263d55307	964	* @{
AnnaBridge	167:e84263d55307	965	*/
AnnaBridge	167:e84263d55307	966
AnnaBridge	167:e84263d55307	967	/**
AnnaBridge	167:e84263d55307	968	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
AnnaBridge	167:e84263d55307	969	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
AnnaBridge	167:e84263d55307	970	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	167:e84263d55307	971	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	972	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	167:e84263d55307	973	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	167:e84263d55307	974	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	167:e84263d55307	975	* @param __DT__ deadtime duration (in ns)
AnnaBridge	167:e84263d55307	976	* @retval DTG[0:7]
AnnaBridge	167:e84263d55307	977	*/
AnnaBridge	167:e84263d55307	978	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
AnnaBridge	167:e84263d55307	979	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
AnnaBridge	167:e84263d55307	980	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
AnnaBridge	167:e84263d55307	981	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
AnnaBridge	167:e84263d55307	982	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
AnnaBridge	167:e84263d55307	983	0U)
AnnaBridge	167:e84263d55307	984
AnnaBridge	167:e84263d55307	985	/**
AnnaBridge	167:e84263d55307	986	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	167:e84263d55307	987	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	167:e84263d55307	988	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	167:e84263d55307	989	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	167:e84263d55307	990	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	991	*/
AnnaBridge	167:e84263d55307	992	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	167:e84263d55307	993	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	167:e84263d55307	994
AnnaBridge	167:e84263d55307	995	/**
AnnaBridge	167:e84263d55307	996	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	167:e84263d55307	997	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	167:e84263d55307	998	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	167:e84263d55307	999	* @param __PSC__ prescaler
AnnaBridge	167:e84263d55307	1000	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	167:e84263d55307	1001	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	1002	*/
AnnaBridge	167:e84263d55307	1003	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	167:e84263d55307	1004	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	167:e84263d55307	1005
AnnaBridge	167:e84263d55307	1006	/**
AnnaBridge	167:e84263d55307	1007	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	167:e84263d55307	1008	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	167:e84263d55307	1009	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	167:e84263d55307	1010	* @param __PSC__ prescaler
AnnaBridge	167:e84263d55307	1011	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	167:e84263d55307	1012	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	1013	*/
AnnaBridge	167:e84263d55307	1014	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	167:e84263d55307	1015	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	167:e84263d55307	1016	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	167:e84263d55307	1017
AnnaBridge	167:e84263d55307	1018	/**
AnnaBridge	167:e84263d55307	1019	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	167:e84263d55307	1020	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	167:e84263d55307	1021	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	167:e84263d55307	1022	* @param __PSC__ prescaler
AnnaBridge	167:e84263d55307	1023	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	167:e84263d55307	1024	* @param __PULSE__ pulse duration (in us)
AnnaBridge	167:e84263d55307	1025	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	1026	*/
AnnaBridge	167:e84263d55307	1027	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	167:e84263d55307	1028	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	167:e84263d55307	1029	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	167:e84263d55307	1030
AnnaBridge	167:e84263d55307	1031	/**
AnnaBridge	167:e84263d55307	1032	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	167:e84263d55307	1033	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	167:e84263d55307	1034	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1035	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	167:e84263d55307	1036	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	167:e84263d55307	1037	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	167:e84263d55307	1038	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	167:e84263d55307	1039	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	167:e84263d55307	1040	*/
AnnaBridge	167:e84263d55307	1041	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	167:e84263d55307	1042	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	167:e84263d55307	1043
AnnaBridge	167:e84263d55307	1044
AnnaBridge	167:e84263d55307	1045	/**
AnnaBridge	167:e84263d55307	1046	* @}
AnnaBridge	167:e84263d55307	1047	*/
AnnaBridge	167:e84263d55307	1048
AnnaBridge	167:e84263d55307	1049
AnnaBridge	167:e84263d55307	1050	/**
AnnaBridge	167:e84263d55307	1051	* @}
AnnaBridge	167:e84263d55307	1052	*/
AnnaBridge	167:e84263d55307	1053
AnnaBridge	167:e84263d55307	1054	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1055	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	167:e84263d55307	1056	* @{
AnnaBridge	167:e84263d55307	1057	*/
AnnaBridge	167:e84263d55307	1058
AnnaBridge	167:e84263d55307	1059	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	167:e84263d55307	1060	* @{
AnnaBridge	167:e84263d55307	1061	*/
AnnaBridge	167:e84263d55307	1062	/**
AnnaBridge	167:e84263d55307	1063	* @brief Enable timer counter.
AnnaBridge	167:e84263d55307	1064	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	167:e84263d55307	1065	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1066	* @retval None
AnnaBridge	167:e84263d55307	1067	*/
AnnaBridge	167:e84263d55307	1068	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1069	{
AnnaBridge	167:e84263d55307	1070	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	167:e84263d55307	1071	}
AnnaBridge	167:e84263d55307	1072
AnnaBridge	167:e84263d55307	1073	/**
AnnaBridge	167:e84263d55307	1074	* @brief Disable timer counter.
AnnaBridge	167:e84263d55307	1075	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	167:e84263d55307	1076	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1077	* @retval None
AnnaBridge	167:e84263d55307	1078	*/
AnnaBridge	167:e84263d55307	1079	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1080	{
AnnaBridge	167:e84263d55307	1081	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	167:e84263d55307	1082	}
AnnaBridge	167:e84263d55307	1083
AnnaBridge	167:e84263d55307	1084	/**
AnnaBridge	167:e84263d55307	1085	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	167:e84263d55307	1086	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	167:e84263d55307	1087	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1088	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1089	*/
AnnaBridge	167:e84263d55307	1090	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1091	{
AnnaBridge	167:e84263d55307	1092	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	167:e84263d55307	1093	}
AnnaBridge	167:e84263d55307	1094
AnnaBridge	167:e84263d55307	1095	/**
AnnaBridge	167:e84263d55307	1096	* @brief Enable update event generation.
AnnaBridge	167:e84263d55307	1097	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	167:e84263d55307	1098	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1099	* @retval None
AnnaBridge	167:e84263d55307	1100	*/
AnnaBridge	167:e84263d55307	1101	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1102	{
AnnaBridge	167:e84263d55307	1103	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	167:e84263d55307	1104	}
AnnaBridge	167:e84263d55307	1105
AnnaBridge	167:e84263d55307	1106	/**
AnnaBridge	167:e84263d55307	1107	* @brief Disable update event generation.
AnnaBridge	167:e84263d55307	1108	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	167:e84263d55307	1109	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1110	* @retval None
AnnaBridge	167:e84263d55307	1111	*/
AnnaBridge	167:e84263d55307	1112	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1113	{
AnnaBridge	167:e84263d55307	1114	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	167:e84263d55307	1115	}
AnnaBridge	167:e84263d55307	1116
AnnaBridge	167:e84263d55307	1117	/**
AnnaBridge	167:e84263d55307	1118	* @brief Indicates whether update event generation is enabled.
AnnaBridge	167:e84263d55307	1119	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	167:e84263d55307	1120	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1121	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1122	*/
AnnaBridge	167:e84263d55307	1123	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1124	{
AnnaBridge	167:e84263d55307	1125	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
AnnaBridge	167:e84263d55307	1126	}
AnnaBridge	167:e84263d55307	1127
AnnaBridge	167:e84263d55307	1128	/**
AnnaBridge	167:e84263d55307	1129	* @brief Set update event source
AnnaBridge	167:e84263d55307	1130	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	167:e84263d55307	1131	* generate an update interrupt or DMA request if enabled:
AnnaBridge	167:e84263d55307	1132	* - Counter overflow/underflow
AnnaBridge	167:e84263d55307	1133	* - Setting the UG bit
AnnaBridge	167:e84263d55307	1134	* - Update generation through the slave mode controller
AnnaBridge	167:e84263d55307	1135	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	167:e84263d55307	1136	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	167:e84263d55307	1137	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	167:e84263d55307	1138	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1139	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1140	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	167:e84263d55307	1141	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	167:e84263d55307	1142	* @retval None
AnnaBridge	167:e84263d55307	1143	*/
AnnaBridge	167:e84263d55307	1144	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	167:e84263d55307	1145	{
AnnaBridge	167:e84263d55307	1146	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	167:e84263d55307	1147	}
AnnaBridge	167:e84263d55307	1148
AnnaBridge	167:e84263d55307	1149	/**
AnnaBridge	167:e84263d55307	1150	* @brief Get actual event update source
AnnaBridge	167:e84263d55307	1151	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	167:e84263d55307	1152	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1153	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1154	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	167:e84263d55307	1155	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	167:e84263d55307	1156	*/
AnnaBridge	167:e84263d55307	1157	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1158	{
AnnaBridge	167:e84263d55307	1159	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	167:e84263d55307	1160	}
AnnaBridge	167:e84263d55307	1161
AnnaBridge	167:e84263d55307	1162	/**
AnnaBridge	167:e84263d55307	1163	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	167:e84263d55307	1164	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	167:e84263d55307	1165	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1166	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1167	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	167:e84263d55307	1168	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	167:e84263d55307	1169	* @retval None
AnnaBridge	167:e84263d55307	1170	*/
AnnaBridge	167:e84263d55307	1171	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	167:e84263d55307	1172	{
AnnaBridge	167:e84263d55307	1173	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	167:e84263d55307	1174	}
AnnaBridge	167:e84263d55307	1175
AnnaBridge	167:e84263d55307	1176	/**
AnnaBridge	167:e84263d55307	1177	* @brief Get actual one pulse mode.
AnnaBridge	167:e84263d55307	1178	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	167:e84263d55307	1179	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1180	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1181	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	167:e84263d55307	1182	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	167:e84263d55307	1183	*/
AnnaBridge	167:e84263d55307	1184	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1185	{
AnnaBridge	167:e84263d55307	1186	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	167:e84263d55307	1187	}
AnnaBridge	167:e84263d55307	1188
AnnaBridge	167:e84263d55307	1189	/**
AnnaBridge	167:e84263d55307	1190	* @brief Set the timer counter counting mode.
AnnaBridge	167:e84263d55307	1191	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	167:e84263d55307	1192	* check whether or not the counter mode selection feature is supported
AnnaBridge	167:e84263d55307	1193	* by a timer instance.
AnnaBridge	167:e84263d55307	1194	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	167:e84263d55307	1195	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	167:e84263d55307	1196	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1197	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1198	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	167:e84263d55307	1199	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	167:e84263d55307	1200	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	167:e84263d55307	1201	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	167:e84263d55307	1202	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	167:e84263d55307	1203	* @retval None
AnnaBridge	167:e84263d55307	1204	*/
AnnaBridge	167:e84263d55307	1205	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	167:e84263d55307	1206	{
AnnaBridge	167:e84263d55307	1207	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	167:e84263d55307	1208	}
AnnaBridge	167:e84263d55307	1209
AnnaBridge	167:e84263d55307	1210	/**
AnnaBridge	167:e84263d55307	1211	* @brief Get actual counter mode.
AnnaBridge	167:e84263d55307	1212	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	167:e84263d55307	1213	* check whether or not the counter mode selection feature is supported
AnnaBridge	167:e84263d55307	1214	* by a timer instance.
AnnaBridge	167:e84263d55307	1215	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	167:e84263d55307	1216	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	167:e84263d55307	1217	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1218	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1219	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	167:e84263d55307	1220	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	167:e84263d55307	1221	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	167:e84263d55307	1222	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	167:e84263d55307	1223	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	167:e84263d55307	1224	*/
AnnaBridge	167:e84263d55307	1225	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1226	{
AnnaBridge	167:e84263d55307	1227	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	167:e84263d55307	1228	}
AnnaBridge	167:e84263d55307	1229
AnnaBridge	167:e84263d55307	1230	/**
AnnaBridge	167:e84263d55307	1231	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	167:e84263d55307	1232	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	167:e84263d55307	1233	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1234	* @retval None
AnnaBridge	167:e84263d55307	1235	*/
AnnaBridge	167:e84263d55307	1236	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1237	{
AnnaBridge	167:e84263d55307	1238	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	167:e84263d55307	1239	}
AnnaBridge	167:e84263d55307	1240
AnnaBridge	167:e84263d55307	1241	/**
AnnaBridge	167:e84263d55307	1242	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	167:e84263d55307	1243	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	167:e84263d55307	1244	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1245	* @retval None
AnnaBridge	167:e84263d55307	1246	*/
AnnaBridge	167:e84263d55307	1247	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1248	{
AnnaBridge	167:e84263d55307	1249	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	167:e84263d55307	1250	}
AnnaBridge	167:e84263d55307	1251
AnnaBridge	167:e84263d55307	1252	/**
AnnaBridge	167:e84263d55307	1253	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	167:e84263d55307	1254	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	167:e84263d55307	1255	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1256	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1257	*/
AnnaBridge	167:e84263d55307	1258	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1259	{
AnnaBridge	167:e84263d55307	1260	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	167:e84263d55307	1261	}
AnnaBridge	167:e84263d55307	1262
AnnaBridge	167:e84263d55307	1263	/**
AnnaBridge	167:e84263d55307	1264	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	167:e84263d55307	1265	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1266	* whether or not the clock division feature is supported by the timer
AnnaBridge	167:e84263d55307	1267	* instance.
AnnaBridge	167:e84263d55307	1268	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	167:e84263d55307	1269	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1270	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1271	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	167:e84263d55307	1272	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	167:e84263d55307	1273	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	167:e84263d55307	1274	* @retval None
AnnaBridge	167:e84263d55307	1275	*/
AnnaBridge	167:e84263d55307	1276	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	167:e84263d55307	1277	{
AnnaBridge	167:e84263d55307	1278	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	167:e84263d55307	1279	}
AnnaBridge	167:e84263d55307	1280
AnnaBridge	167:e84263d55307	1281	/**
AnnaBridge	167:e84263d55307	1282	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	167:e84263d55307	1283	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1284	* whether or not the clock division feature is supported by the timer
AnnaBridge	167:e84263d55307	1285	* instance.
AnnaBridge	167:e84263d55307	1286	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	167:e84263d55307	1287	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1288	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1289	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	167:e84263d55307	1290	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	167:e84263d55307	1291	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	167:e84263d55307	1292	*/
AnnaBridge	167:e84263d55307	1293	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1294	{
AnnaBridge	167:e84263d55307	1295	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	167:e84263d55307	1296	}
AnnaBridge	167:e84263d55307	1297
AnnaBridge	167:e84263d55307	1298	/**
AnnaBridge	167:e84263d55307	1299	* @brief Set the counter value.
AnnaBridge	167:e84263d55307	1300	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1301	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	1302	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	167:e84263d55307	1303	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1304	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	167:e84263d55307	1305	* @retval None
AnnaBridge	167:e84263d55307	1306	*/
AnnaBridge	167:e84263d55307	1307	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	167:e84263d55307	1308	{
AnnaBridge	167:e84263d55307	1309	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	167:e84263d55307	1310	}
AnnaBridge	167:e84263d55307	1311
AnnaBridge	167:e84263d55307	1312	/**
AnnaBridge	167:e84263d55307	1313	* @brief Get the counter value.
AnnaBridge	167:e84263d55307	1314	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1315	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	1316	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	167:e84263d55307	1317	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1318	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	167:e84263d55307	1319	*/
AnnaBridge	167:e84263d55307	1320	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1321	{
AnnaBridge	167:e84263d55307	1322	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	167:e84263d55307	1323	}
AnnaBridge	167:e84263d55307	1324
AnnaBridge	167:e84263d55307	1325	/**
AnnaBridge	167:e84263d55307	1326	* @brief Get the current direction of the counter
AnnaBridge	167:e84263d55307	1327	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	167:e84263d55307	1328	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1329	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1330	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	167:e84263d55307	1331	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	167:e84263d55307	1332	*/
AnnaBridge	167:e84263d55307	1333	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1334	{
AnnaBridge	167:e84263d55307	1335	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	167:e84263d55307	1336	}
AnnaBridge	167:e84263d55307	1337
AnnaBridge	167:e84263d55307	1338	/**
AnnaBridge	167:e84263d55307	1339	* @brief Set the prescaler value.
AnnaBridge	167:e84263d55307	1340	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	167:e84263d55307	1341	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	167:e84263d55307	1342	* prescaler ratio is taken into account at the next update event.
AnnaBridge	167:e84263d55307	1343	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	167:e84263d55307	1344	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	167:e84263d55307	1345	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1346	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	167:e84263d55307	1347	* @retval None
AnnaBridge	167:e84263d55307	1348	*/
AnnaBridge	167:e84263d55307	1349	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	167:e84263d55307	1350	{
AnnaBridge	167:e84263d55307	1351	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	167:e84263d55307	1352	}
AnnaBridge	167:e84263d55307	1353
AnnaBridge	167:e84263d55307	1354	/**
AnnaBridge	167:e84263d55307	1355	* @brief Get the prescaler value.
AnnaBridge	167:e84263d55307	1356	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	167:e84263d55307	1357	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1358	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	167:e84263d55307	1359	*/
AnnaBridge	167:e84263d55307	1360	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1361	{
AnnaBridge	167:e84263d55307	1362	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	167:e84263d55307	1363	}
AnnaBridge	167:e84263d55307	1364
AnnaBridge	167:e84263d55307	1365	/**
AnnaBridge	167:e84263d55307	1366	* @brief Set the auto-reload value.
AnnaBridge	167:e84263d55307	1367	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	167:e84263d55307	1368	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1369	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	1370	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	167:e84263d55307	1371	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	167:e84263d55307	1372	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1373	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	167:e84263d55307	1374	* @retval None
AnnaBridge	167:e84263d55307	1375	*/
AnnaBridge	167:e84263d55307	1376	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	167:e84263d55307	1377	{
AnnaBridge	167:e84263d55307	1378	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	167:e84263d55307	1379	}
AnnaBridge	167:e84263d55307	1380
AnnaBridge	167:e84263d55307	1381	/**
AnnaBridge	167:e84263d55307	1382	* @brief Get the auto-reload value.
AnnaBridge	167:e84263d55307	1383	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	167:e84263d55307	1384	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1385	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	1386	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1387	* @retval Auto-reload value
AnnaBridge	167:e84263d55307	1388	*/
AnnaBridge	167:e84263d55307	1389	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1390	{
AnnaBridge	167:e84263d55307	1391	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	167:e84263d55307	1392	}
AnnaBridge	167:e84263d55307	1393
AnnaBridge	167:e84263d55307	1394	/**
AnnaBridge	167:e84263d55307	1395	* @brief Set the repetition counter value.
AnnaBridge	167:e84263d55307	1396	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1397	* whether or not a timer instance supports a repetition counter.
AnnaBridge	167:e84263d55307	1398	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
AnnaBridge	167:e84263d55307	1399	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1400	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
AnnaBridge	167:e84263d55307	1401	* @retval None
AnnaBridge	167:e84263d55307	1402	*/
AnnaBridge	167:e84263d55307	1403	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
AnnaBridge	167:e84263d55307	1404	{
AnnaBridge	167:e84263d55307	1405	WRITE_REG(TIMx->RCR, RepetitionCounter);
AnnaBridge	167:e84263d55307	1406	}
AnnaBridge	167:e84263d55307	1407
AnnaBridge	167:e84263d55307	1408	/**
AnnaBridge	167:e84263d55307	1409	* @brief Get the repetition counter value.
AnnaBridge	167:e84263d55307	1410	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1411	* whether or not a timer instance supports a repetition counter.
AnnaBridge	167:e84263d55307	1412	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
AnnaBridge	167:e84263d55307	1413	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1414	* @retval Repetition counter value
AnnaBridge	167:e84263d55307	1415	*/
AnnaBridge	167:e84263d55307	1416	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1417	{
AnnaBridge	167:e84263d55307	1418	return (uint32_t)(READ_REG(TIMx->RCR));
AnnaBridge	167:e84263d55307	1419	}
AnnaBridge	167:e84263d55307	1420
AnnaBridge	167:e84263d55307	1421	/**
AnnaBridge	167:e84263d55307	1422	* @}
AnnaBridge	167:e84263d55307	1423	*/
AnnaBridge	167:e84263d55307	1424
AnnaBridge	167:e84263d55307	1425	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	167:e84263d55307	1426	* @{
AnnaBridge	167:e84263d55307	1427	*/
AnnaBridge	167:e84263d55307	1428	/**
AnnaBridge	167:e84263d55307	1429	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	167:e84263d55307	1430	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
AnnaBridge	167:e84263d55307	1431	* they are updated only when a commutation event (COM) occurs.
AnnaBridge	167:e84263d55307	1432	* @note Only on channels that have a complementary output.
AnnaBridge	167:e84263d55307	1433	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1434	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	167:e84263d55307	1435	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
AnnaBridge	167:e84263d55307	1436	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1437	* @retval None
AnnaBridge	167:e84263d55307	1438	*/
AnnaBridge	167:e84263d55307	1439	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1440	{
AnnaBridge	167:e84263d55307	1441	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	167:e84263d55307	1442	}
AnnaBridge	167:e84263d55307	1443
AnnaBridge	167:e84263d55307	1444	/**
AnnaBridge	167:e84263d55307	1445	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	167:e84263d55307	1446	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1447	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	167:e84263d55307	1448	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
AnnaBridge	167:e84263d55307	1449	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1450	* @retval None
AnnaBridge	167:e84263d55307	1451	*/
AnnaBridge	167:e84263d55307	1452	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1453	{
AnnaBridge	167:e84263d55307	1454	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	167:e84263d55307	1455	}
AnnaBridge	167:e84263d55307	1456
AnnaBridge	167:e84263d55307	1457	/**
AnnaBridge	167:e84263d55307	1458	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
AnnaBridge	167:e84263d55307	1459	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	1460	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	167:e84263d55307	1461	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
AnnaBridge	167:e84263d55307	1462	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1463	* @param CCUpdateSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1464	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
AnnaBridge	167:e84263d55307	1465	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
AnnaBridge	167:e84263d55307	1466	* @retval None
AnnaBridge	167:e84263d55307	1467	*/
AnnaBridge	167:e84263d55307	1468	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
AnnaBridge	167:e84263d55307	1469	{
AnnaBridge	167:e84263d55307	1470	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
AnnaBridge	167:e84263d55307	1471	}
AnnaBridge	167:e84263d55307	1472
AnnaBridge	167:e84263d55307	1473	/**
AnnaBridge	167:e84263d55307	1474	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	167:e84263d55307	1475	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	167:e84263d55307	1476	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1477	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1478	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	167:e84263d55307	1479	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	167:e84263d55307	1480	* @retval None
AnnaBridge	167:e84263d55307	1481	*/
AnnaBridge	167:e84263d55307	1482	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	167:e84263d55307	1483	{
AnnaBridge	167:e84263d55307	1484	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	167:e84263d55307	1485	}
AnnaBridge	167:e84263d55307	1486
AnnaBridge	167:e84263d55307	1487	/**
AnnaBridge	167:e84263d55307	1488	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	167:e84263d55307	1489	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	167:e84263d55307	1490	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1491	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1492	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	167:e84263d55307	1493	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	167:e84263d55307	1494	*/
AnnaBridge	167:e84263d55307	1495	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	1496	{
AnnaBridge	167:e84263d55307	1497	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	167:e84263d55307	1498	}
AnnaBridge	167:e84263d55307	1499
AnnaBridge	167:e84263d55307	1500	/**
AnnaBridge	167:e84263d55307	1501	* @brief Set the lock level to freeze the
AnnaBridge	167:e84263d55307	1502	* configuration of several capture/compare parameters.
AnnaBridge	167:e84263d55307	1503	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1504	* the lock mechanism is supported by a timer instance.
AnnaBridge	167:e84263d55307	1505	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
AnnaBridge	167:e84263d55307	1506	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1507	* @param LockLevel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1508	* @arg @ref LL_TIM_LOCKLEVEL_OFF
AnnaBridge	167:e84263d55307	1509	* @arg @ref LL_TIM_LOCKLEVEL_1
AnnaBridge	167:e84263d55307	1510	* @arg @ref LL_TIM_LOCKLEVEL_2
AnnaBridge	167:e84263d55307	1511	* @arg @ref LL_TIM_LOCKLEVEL_3
AnnaBridge	167:e84263d55307	1512	* @retval None
AnnaBridge	167:e84263d55307	1513	*/
AnnaBridge	167:e84263d55307	1514	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
AnnaBridge	167:e84263d55307	1515	{
AnnaBridge	167:e84263d55307	1516	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
AnnaBridge	167:e84263d55307	1517	}
AnnaBridge	167:e84263d55307	1518
AnnaBridge	167:e84263d55307	1519	/**
AnnaBridge	167:e84263d55307	1520	* @brief Enable capture/compare channels.
AnnaBridge	167:e84263d55307	1521	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	167:e84263d55307	1522	* CCER CC1NE LL_TIM_CC_EnableChannel\n
AnnaBridge	167:e84263d55307	1523	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	167:e84263d55307	1524	* CCER CC2NE LL_TIM_CC_EnableChannel\n
AnnaBridge	167:e84263d55307	1525	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	167:e84263d55307	1526	* CCER CC3NE LL_TIM_CC_EnableChannel\n
AnnaBridge	167:e84263d55307	1527	* CCER CC4E LL_TIM_CC_EnableChannel
AnnaBridge	167:e84263d55307	1528	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1529	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	167:e84263d55307	1530	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1531	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	1532	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1533	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	1534	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1535	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	1536	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1537	* @retval None
AnnaBridge	167:e84263d55307	1538	*/
AnnaBridge	167:e84263d55307	1539	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	167:e84263d55307	1540	{
AnnaBridge	167:e84263d55307	1541	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	167:e84263d55307	1542	}
AnnaBridge	167:e84263d55307	1543
AnnaBridge	167:e84263d55307	1544	/**
AnnaBridge	167:e84263d55307	1545	* @brief Disable capture/compare channels.
AnnaBridge	167:e84263d55307	1546	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	167:e84263d55307	1547	* CCER CC1NE LL_TIM_CC_DisableChannel\n
AnnaBridge	167:e84263d55307	1548	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	167:e84263d55307	1549	* CCER CC2NE LL_TIM_CC_DisableChannel\n
AnnaBridge	167:e84263d55307	1550	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	167:e84263d55307	1551	* CCER CC3NE LL_TIM_CC_DisableChannel\n
AnnaBridge	167:e84263d55307	1552	* CCER CC4E LL_TIM_CC_DisableChannel
AnnaBridge	167:e84263d55307	1553	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1554	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	167:e84263d55307	1555	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1556	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	1557	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1558	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	1559	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1560	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	1561	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1562	* @retval None
AnnaBridge	167:e84263d55307	1563	*/
AnnaBridge	167:e84263d55307	1564	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	167:e84263d55307	1565	{
AnnaBridge	167:e84263d55307	1566	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	167:e84263d55307	1567	}
AnnaBridge	167:e84263d55307	1568
AnnaBridge	167:e84263d55307	1569	/**
AnnaBridge	167:e84263d55307	1570	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	167:e84263d55307	1571	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	167:e84263d55307	1572	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	167:e84263d55307	1573	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	167:e84263d55307	1574	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	167:e84263d55307	1575	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	167:e84263d55307	1576	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	167:e84263d55307	1577	* CCER CC4E LL_TIM_CC_IsEnabledChannel
AnnaBridge	167:e84263d55307	1578	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1579	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	167:e84263d55307	1580	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1581	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	1582	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1583	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	1584	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1585	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	1586	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1587	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1588	*/
AnnaBridge	167:e84263d55307	1589	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	167:e84263d55307	1590	{
AnnaBridge	167:e84263d55307	1591	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	167:e84263d55307	1592	}
AnnaBridge	167:e84263d55307	1593
AnnaBridge	167:e84263d55307	1594	/**
AnnaBridge	167:e84263d55307	1595	* @}
AnnaBridge	167:e84263d55307	1596	*/
AnnaBridge	167:e84263d55307	1597
AnnaBridge	167:e84263d55307	1598	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	167:e84263d55307	1599	* @{
AnnaBridge	167:e84263d55307	1600	*/
AnnaBridge	167:e84263d55307	1601	/**
AnnaBridge	167:e84263d55307	1602	* @brief Configure an output channel.
AnnaBridge	167:e84263d55307	1603	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1604	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1605	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1606	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1607	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1608	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1609	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1610	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1611	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1612	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1613	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
AnnaBridge	167:e84263d55307	1614	* CR2 OIS4 LL_TIM_OC_ConfigOutput
AnnaBridge	167:e84263d55307	1615	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1616	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1617	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1618	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1619	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1620	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1621	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	167:e84263d55307	1622	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	167:e84263d55307	1623	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	167:e84263d55307	1624	* @retval None
AnnaBridge	167:e84263d55307	1625	*/
AnnaBridge	167:e84263d55307	1626	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	167:e84263d55307	1627	{
AnnaBridge	167:e84263d55307	1628	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1629	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1630	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	167:e84263d55307	1631	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	167:e84263d55307	1632	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	167:e84263d55307	1633	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
AnnaBridge	167:e84263d55307	1634	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	167:e84263d55307	1635	}
AnnaBridge	167:e84263d55307	1636
AnnaBridge	167:e84263d55307	1637	/**
AnnaBridge	167:e84263d55307	1638	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	167:e84263d55307	1639	* OCx and OCxN (when relevant) are derived.
AnnaBridge	167:e84263d55307	1640	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	167:e84263d55307	1641	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	167:e84263d55307	1642	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	167:e84263d55307	1643	* CCMR2 OC4M LL_TIM_OC_SetMode
AnnaBridge	167:e84263d55307	1644	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1645	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1646	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1647	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1648	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1649	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1650	* @param Mode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1651	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	167:e84263d55307	1652	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	167:e84263d55307	1653	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	167:e84263d55307	1654	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	167:e84263d55307	1655	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	167:e84263d55307	1656	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	167:e84263d55307	1657	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	167:e84263d55307	1658	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	167:e84263d55307	1659	* @retval None
AnnaBridge	167:e84263d55307	1660	*/
AnnaBridge	167:e84263d55307	1661	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	167:e84263d55307	1662	{
AnnaBridge	167:e84263d55307	1663	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1664	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1665	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	167:e84263d55307	1666	}
AnnaBridge	167:e84263d55307	1667
AnnaBridge	167:e84263d55307	1668	/**
AnnaBridge	167:e84263d55307	1669	* @brief Get the output compare mode of an output channel.
AnnaBridge	167:e84263d55307	1670	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	167:e84263d55307	1671	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	167:e84263d55307	1672	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	167:e84263d55307	1673	* CCMR2 OC4M LL_TIM_OC_GetMode
AnnaBridge	167:e84263d55307	1674	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1675	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1676	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1677	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1678	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1679	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1680	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1681	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	167:e84263d55307	1682	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	167:e84263d55307	1683	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	167:e84263d55307	1684	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	167:e84263d55307	1685	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	167:e84263d55307	1686	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	167:e84263d55307	1687	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	167:e84263d55307	1688	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	167:e84263d55307	1689	*/
AnnaBridge	167:e84263d55307	1690	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1691	{
AnnaBridge	167:e84263d55307	1692	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1693	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1694	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	167:e84263d55307	1695	}
AnnaBridge	167:e84263d55307	1696
AnnaBridge	167:e84263d55307	1697	/**
AnnaBridge	167:e84263d55307	1698	* @brief Set the polarity of an output channel.
AnnaBridge	167:e84263d55307	1699	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	167:e84263d55307	1700	* CCER CC1NP LL_TIM_OC_SetPolarity\n
AnnaBridge	167:e84263d55307	1701	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	167:e84263d55307	1702	* CCER CC2NP LL_TIM_OC_SetPolarity\n
AnnaBridge	167:e84263d55307	1703	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	167:e84263d55307	1704	* CCER CC3NP LL_TIM_OC_SetPolarity\n
AnnaBridge	167:e84263d55307	1705	* CCER CC4P LL_TIM_OC_SetPolarity
AnnaBridge	167:e84263d55307	1706	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1707	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1708	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1709	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	1710	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1711	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	1712	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1713	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	1714	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1715	* @param Polarity This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1716	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	167:e84263d55307	1717	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	167:e84263d55307	1718	* @retval None
AnnaBridge	167:e84263d55307	1719	*/
AnnaBridge	167:e84263d55307	1720	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	167:e84263d55307	1721	{
AnnaBridge	167:e84263d55307	1722	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1723	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	167:e84263d55307	1724	}
AnnaBridge	167:e84263d55307	1725
AnnaBridge	167:e84263d55307	1726	/**
AnnaBridge	167:e84263d55307	1727	* @brief Get the polarity of an output channel.
AnnaBridge	167:e84263d55307	1728	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	167:e84263d55307	1729	* CCER CC1NP LL_TIM_OC_GetPolarity\n
AnnaBridge	167:e84263d55307	1730	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	167:e84263d55307	1731	* CCER CC2NP LL_TIM_OC_GetPolarity\n
AnnaBridge	167:e84263d55307	1732	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	167:e84263d55307	1733	* CCER CC3NP LL_TIM_OC_GetPolarity\n
AnnaBridge	167:e84263d55307	1734	* CCER CC4P LL_TIM_OC_GetPolarity
AnnaBridge	167:e84263d55307	1735	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1736	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1737	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1738	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	1739	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1740	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	1741	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1742	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	1743	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1744	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1745	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	167:e84263d55307	1746	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	167:e84263d55307	1747	*/
AnnaBridge	167:e84263d55307	1748	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1749	{
AnnaBridge	167:e84263d55307	1750	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1751	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	167:e84263d55307	1752	}
AnnaBridge	167:e84263d55307	1753
AnnaBridge	167:e84263d55307	1754	/**
AnnaBridge	167:e84263d55307	1755	* @brief Set the IDLE state of an output channel
AnnaBridge	167:e84263d55307	1756	* @note This function is significant only for the timer instances
AnnaBridge	167:e84263d55307	1757	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
AnnaBridge	167:e84263d55307	1758	* can be used to check whether or not a timer instance provides
AnnaBridge	167:e84263d55307	1759	* a break input.
AnnaBridge	167:e84263d55307	1760	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
AnnaBridge	167:e84263d55307	1761	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
AnnaBridge	167:e84263d55307	1762	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
AnnaBridge	167:e84263d55307	1763	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	167:e84263d55307	1764	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
AnnaBridge	167:e84263d55307	1765	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
AnnaBridge	167:e84263d55307	1766	* CR2 OIS4 LL_TIM_OC_SetIdleState
AnnaBridge	167:e84263d55307	1767	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1768	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1769	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1770	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	1771	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1772	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	1773	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1774	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	1775	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1776	* @param IdleState This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1777	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	167:e84263d55307	1778	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	167:e84263d55307	1779	* @retval None
AnnaBridge	167:e84263d55307	1780	*/
AnnaBridge	167:e84263d55307	1781	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
AnnaBridge	167:e84263d55307	1782	{
AnnaBridge	167:e84263d55307	1783	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1784	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	167:e84263d55307	1785	}
AnnaBridge	167:e84263d55307	1786
AnnaBridge	167:e84263d55307	1787	/**
AnnaBridge	167:e84263d55307	1788	* @brief Get the IDLE state of an output channel
AnnaBridge	167:e84263d55307	1789	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
AnnaBridge	167:e84263d55307	1790	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
AnnaBridge	167:e84263d55307	1791	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
AnnaBridge	167:e84263d55307	1792	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	167:e84263d55307	1793	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
AnnaBridge	167:e84263d55307	1794	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
AnnaBridge	167:e84263d55307	1795	* CR2 OIS4 LL_TIM_OC_GetIdleState
AnnaBridge	167:e84263d55307	1796	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1797	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1798	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1799	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	167:e84263d55307	1800	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1801	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	167:e84263d55307	1802	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1803	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	167:e84263d55307	1804	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1805	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1806	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	167:e84263d55307	1807	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	167:e84263d55307	1808	*/
AnnaBridge	167:e84263d55307	1809	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1810	{
AnnaBridge	167:e84263d55307	1811	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1812	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
AnnaBridge	167:e84263d55307	1813	}
AnnaBridge	167:e84263d55307	1814
AnnaBridge	167:e84263d55307	1815	/**
AnnaBridge	167:e84263d55307	1816	* @brief Enable fast mode for the output channel.
AnnaBridge	167:e84263d55307	1817	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	167:e84263d55307	1818	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	167:e84263d55307	1819	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	167:e84263d55307	1820	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	167:e84263d55307	1821	* CCMR2 OC4FE LL_TIM_OC_EnableFast
AnnaBridge	167:e84263d55307	1822	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1823	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1824	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1825	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1826	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1827	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1828	* @retval None
AnnaBridge	167:e84263d55307	1829	*/
AnnaBridge	167:e84263d55307	1830	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1831	{
AnnaBridge	167:e84263d55307	1832	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1833	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1834	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	167:e84263d55307	1835
AnnaBridge	167:e84263d55307	1836	}
AnnaBridge	167:e84263d55307	1837
AnnaBridge	167:e84263d55307	1838	/**
AnnaBridge	167:e84263d55307	1839	* @brief Disable fast mode for the output channel.
AnnaBridge	167:e84263d55307	1840	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	167:e84263d55307	1841	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	167:e84263d55307	1842	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	167:e84263d55307	1843	* CCMR2 OC4FE LL_TIM_OC_DisableFast
AnnaBridge	167:e84263d55307	1844	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1845	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1846	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1847	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1848	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1849	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1850	* @retval None
AnnaBridge	167:e84263d55307	1851	*/
AnnaBridge	167:e84263d55307	1852	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1853	{
AnnaBridge	167:e84263d55307	1854	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1855	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1856	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	167:e84263d55307	1857
AnnaBridge	167:e84263d55307	1858	}
AnnaBridge	167:e84263d55307	1859
AnnaBridge	167:e84263d55307	1860	/**
AnnaBridge	167:e84263d55307	1861	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	167:e84263d55307	1862	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	167:e84263d55307	1863	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	167:e84263d55307	1864	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	167:e84263d55307	1865	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	167:e84263d55307	1866	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1867	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1868	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1869	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1870	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1871	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1872	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1873	*/
AnnaBridge	167:e84263d55307	1874	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1875	{
AnnaBridge	167:e84263d55307	1876	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1877	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1878	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	167:e84263d55307	1879	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	167:e84263d55307	1880	}
AnnaBridge	167:e84263d55307	1881
AnnaBridge	167:e84263d55307	1882	/**
AnnaBridge	167:e84263d55307	1883	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	167:e84263d55307	1884	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	167:e84263d55307	1885	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	167:e84263d55307	1886	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	167:e84263d55307	1887	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
AnnaBridge	167:e84263d55307	1888	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1889	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1890	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1891	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1892	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1893	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1894	* @retval None
AnnaBridge	167:e84263d55307	1895	*/
AnnaBridge	167:e84263d55307	1896	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1897	{
AnnaBridge	167:e84263d55307	1898	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1899	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1900	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	167:e84263d55307	1901	}
AnnaBridge	167:e84263d55307	1902
AnnaBridge	167:e84263d55307	1903	/**
AnnaBridge	167:e84263d55307	1904	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	167:e84263d55307	1905	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	167:e84263d55307	1906	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	167:e84263d55307	1907	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	167:e84263d55307	1908	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
AnnaBridge	167:e84263d55307	1909	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1910	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1911	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1912	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1913	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1914	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1915	* @retval None
AnnaBridge	167:e84263d55307	1916	*/
AnnaBridge	167:e84263d55307	1917	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1918	{
AnnaBridge	167:e84263d55307	1919	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1920	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1921	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	167:e84263d55307	1922	}
AnnaBridge	167:e84263d55307	1923
AnnaBridge	167:e84263d55307	1924	/**
AnnaBridge	167:e84263d55307	1925	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	167:e84263d55307	1926	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	167:e84263d55307	1927	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	167:e84263d55307	1928	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	167:e84263d55307	1929	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	167:e84263d55307	1930	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1931	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1932	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1933	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1934	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1935	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1936	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1937	*/
AnnaBridge	167:e84263d55307	1938	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1939	{
AnnaBridge	167:e84263d55307	1940	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1941	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1942	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	167:e84263d55307	1943	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	167:e84263d55307	1944	}
AnnaBridge	167:e84263d55307	1945
AnnaBridge	167:e84263d55307	1946	/**
AnnaBridge	167:e84263d55307	1947	* @brief Enable clearing the output channel on an external event.
AnnaBridge	167:e84263d55307	1948	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	167:e84263d55307	1949	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	167:e84263d55307	1950	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	167:e84263d55307	1951	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	167:e84263d55307	1952	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	167:e84263d55307	1953	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	167:e84263d55307	1954	* CCMR2 OC4CE LL_TIM_OC_EnableClear
AnnaBridge	167:e84263d55307	1955	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1956	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1957	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1958	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1959	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1960	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1961	* @retval None
AnnaBridge	167:e84263d55307	1962	*/
AnnaBridge	167:e84263d55307	1963	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1964	{
AnnaBridge	167:e84263d55307	1965	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1966	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1967	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	167:e84263d55307	1968	}
AnnaBridge	167:e84263d55307	1969
AnnaBridge	167:e84263d55307	1970	/**
AnnaBridge	167:e84263d55307	1971	* @brief Disable clearing the output channel on an external event.
AnnaBridge	167:e84263d55307	1972	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	167:e84263d55307	1973	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	167:e84263d55307	1974	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	167:e84263d55307	1975	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	167:e84263d55307	1976	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	167:e84263d55307	1977	* CCMR2 OC4CE LL_TIM_OC_DisableClear
AnnaBridge	167:e84263d55307	1978	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	1979	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1980	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	1981	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	1982	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	1983	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	1984	* @retval None
AnnaBridge	167:e84263d55307	1985	*/
AnnaBridge	167:e84263d55307	1986	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	1987	{
AnnaBridge	167:e84263d55307	1988	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	1989	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	1990	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	167:e84263d55307	1991	}
AnnaBridge	167:e84263d55307	1992
AnnaBridge	167:e84263d55307	1993	/**
AnnaBridge	167:e84263d55307	1994	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	167:e84263d55307	1995	* @note This function enables clearing the output channel on an external event.
AnnaBridge	167:e84263d55307	1996	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	167:e84263d55307	1997	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	167:e84263d55307	1998	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	167:e84263d55307	1999	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	167:e84263d55307	2000	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	167:e84263d55307	2001	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	167:e84263d55307	2002	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	167:e84263d55307	2003	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2004	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2005	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2006	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2007	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2008	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2009	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2010	*/
AnnaBridge	167:e84263d55307	2011	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	2012	{
AnnaBridge	167:e84263d55307	2013	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2014	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2015	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	167:e84263d55307	2016	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	167:e84263d55307	2017	}
AnnaBridge	167:e84263d55307	2018
AnnaBridge	167:e84263d55307	2019	/**
AnnaBridge	167:e84263d55307	2020	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
AnnaBridge	167:e84263d55307	2021	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2022	* dead-time insertion feature is supported by a timer instance.
AnnaBridge	167:e84263d55307	2023	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
AnnaBridge	167:e84263d55307	2024	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
AnnaBridge	167:e84263d55307	2025	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2026	* @param DeadTime between Min_Data=0 and Max_Data=255
AnnaBridge	167:e84263d55307	2027	* @retval None
AnnaBridge	167:e84263d55307	2028	*/
AnnaBridge	167:e84263d55307	2029	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
AnnaBridge	167:e84263d55307	2030	{
AnnaBridge	167:e84263d55307	2031	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
AnnaBridge	167:e84263d55307	2032	}
AnnaBridge	167:e84263d55307	2033
AnnaBridge	167:e84263d55307	2034	/**
AnnaBridge	167:e84263d55307	2035	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	167:e84263d55307	2036	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2037	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2038	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2039	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2040	* output channel 1 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2041	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	167:e84263d55307	2042	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2043	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	167:e84263d55307	2044	* @retval None
AnnaBridge	167:e84263d55307	2045	*/
AnnaBridge	167:e84263d55307	2046	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	167:e84263d55307	2047	{
AnnaBridge	167:e84263d55307	2048	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	167:e84263d55307	2049	}
AnnaBridge	167:e84263d55307	2050
AnnaBridge	167:e84263d55307	2051	/**
AnnaBridge	167:e84263d55307	2052	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	167:e84263d55307	2053	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2054	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2055	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2056	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2057	* output channel 2 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2058	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	167:e84263d55307	2059	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2060	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	167:e84263d55307	2061	* @retval None
AnnaBridge	167:e84263d55307	2062	*/
AnnaBridge	167:e84263d55307	2063	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	167:e84263d55307	2064	{
AnnaBridge	167:e84263d55307	2065	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	167:e84263d55307	2066	}
AnnaBridge	167:e84263d55307	2067
AnnaBridge	167:e84263d55307	2068	/**
AnnaBridge	167:e84263d55307	2069	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	167:e84263d55307	2070	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2071	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2072	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2073	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2074	* output channel is supported by a timer instance.
AnnaBridge	167:e84263d55307	2075	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	167:e84263d55307	2076	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2077	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	167:e84263d55307	2078	* @retval None
AnnaBridge	167:e84263d55307	2079	*/
AnnaBridge	167:e84263d55307	2080	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	167:e84263d55307	2081	{
AnnaBridge	167:e84263d55307	2082	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	167:e84263d55307	2083	}
AnnaBridge	167:e84263d55307	2084
AnnaBridge	167:e84263d55307	2085	/**
AnnaBridge	167:e84263d55307	2086	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	167:e84263d55307	2087	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2088	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2089	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2090	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2091	* output channel 4 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2092	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	167:e84263d55307	2093	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2094	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	167:e84263d55307	2095	* @retval None
AnnaBridge	167:e84263d55307	2096	*/
AnnaBridge	167:e84263d55307	2097	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	167:e84263d55307	2098	{
AnnaBridge	167:e84263d55307	2099	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	167:e84263d55307	2100	}
AnnaBridge	167:e84263d55307	2101
AnnaBridge	167:e84263d55307	2102	/**
AnnaBridge	167:e84263d55307	2103	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	167:e84263d55307	2104	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2105	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2106	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2107	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2108	* output channel 1 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2109	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	167:e84263d55307	2110	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2111	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2112	*/
AnnaBridge	167:e84263d55307	2113	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2114	{
AnnaBridge	167:e84263d55307	2115	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	167:e84263d55307	2116	}
AnnaBridge	167:e84263d55307	2117
AnnaBridge	167:e84263d55307	2118	/**
AnnaBridge	167:e84263d55307	2119	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	167:e84263d55307	2120	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2121	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2122	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2123	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2124	* output channel 2 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2125	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	167:e84263d55307	2126	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2127	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2128	*/
AnnaBridge	167:e84263d55307	2129	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2130	{
AnnaBridge	167:e84263d55307	2131	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	167:e84263d55307	2132	}
AnnaBridge	167:e84263d55307	2133
AnnaBridge	167:e84263d55307	2134	/**
AnnaBridge	167:e84263d55307	2135	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	167:e84263d55307	2136	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2137	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2138	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2139	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2140	* output channel 3 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2141	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	167:e84263d55307	2142	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2143	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2144	*/
AnnaBridge	167:e84263d55307	2145	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2146	{
AnnaBridge	167:e84263d55307	2147	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	167:e84263d55307	2148	}
AnnaBridge	167:e84263d55307	2149
AnnaBridge	167:e84263d55307	2150	/**
AnnaBridge	167:e84263d55307	2151	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	167:e84263d55307	2152	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2153	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2154	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2155	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2156	* output channel 4 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2157	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	167:e84263d55307	2158	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2159	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2160	*/
AnnaBridge	167:e84263d55307	2161	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2162	{
AnnaBridge	167:e84263d55307	2163	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	167:e84263d55307	2164	}
AnnaBridge	167:e84263d55307	2165
AnnaBridge	167:e84263d55307	2166	/**
AnnaBridge	167:e84263d55307	2167	* @}
AnnaBridge	167:e84263d55307	2168	*/
AnnaBridge	167:e84263d55307	2169
AnnaBridge	167:e84263d55307	2170	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	167:e84263d55307	2171	* @{
AnnaBridge	167:e84263d55307	2172	*/
AnnaBridge	167:e84263d55307	2173	/**
AnnaBridge	167:e84263d55307	2174	* @brief Configure input channel.
AnnaBridge	167:e84263d55307	2175	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2176	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2177	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2178	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2179	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2180	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2181	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2182	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2183	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2184	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2185	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2186	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2187	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2188	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2189	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2190	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2191	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2192	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2193	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	167:e84263d55307	2194	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	167:e84263d55307	2195	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2196	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2197	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2198	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2199	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2200	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2201	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	167:e84263d55307	2202	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	167:e84263d55307	2203	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	167:e84263d55307	2204	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	167:e84263d55307	2205	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	167:e84263d55307	2206	* @retval None
AnnaBridge	167:e84263d55307	2207	*/
AnnaBridge	167:e84263d55307	2208	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	167:e84263d55307	2209	{
AnnaBridge	167:e84263d55307	2210	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2211	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2212	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	167:e84263d55307	2213	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	167:e84263d55307	2214	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	167:e84263d55307	2215	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	167:e84263d55307	2216	}
AnnaBridge	167:e84263d55307	2217
AnnaBridge	167:e84263d55307	2218	/**
AnnaBridge	167:e84263d55307	2219	* @brief Set the active input.
AnnaBridge	167:e84263d55307	2220	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	167:e84263d55307	2221	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	167:e84263d55307	2222	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	167:e84263d55307	2223	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	167:e84263d55307	2224	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2225	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2226	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2227	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2228	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2229	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2230	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2231	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	167:e84263d55307	2232	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	167:e84263d55307	2233	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	167:e84263d55307	2234	* @retval None
AnnaBridge	167:e84263d55307	2235	*/
AnnaBridge	167:e84263d55307	2236	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	167:e84263d55307	2237	{
AnnaBridge	167:e84263d55307	2238	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2239	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2240	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	167:e84263d55307	2241	}
AnnaBridge	167:e84263d55307	2242
AnnaBridge	167:e84263d55307	2243	/**
AnnaBridge	167:e84263d55307	2244	* @brief Get the current active input.
AnnaBridge	167:e84263d55307	2245	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	167:e84263d55307	2246	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	167:e84263d55307	2247	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	167:e84263d55307	2248	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	167:e84263d55307	2249	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2250	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2251	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2252	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2253	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2254	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2255	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	2256	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	167:e84263d55307	2257	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	167:e84263d55307	2258	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	167:e84263d55307	2259	*/
AnnaBridge	167:e84263d55307	2260	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	2261	{
AnnaBridge	167:e84263d55307	2262	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2263	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2264	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	167:e84263d55307	2265	}
AnnaBridge	167:e84263d55307	2266
AnnaBridge	167:e84263d55307	2267	/**
AnnaBridge	167:e84263d55307	2268	* @brief Set the prescaler of input channel.
AnnaBridge	167:e84263d55307	2269	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	167:e84263d55307	2270	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	167:e84263d55307	2271	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	167:e84263d55307	2272	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	167:e84263d55307	2273	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2274	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2275	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2276	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2277	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2278	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2279	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2280	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	167:e84263d55307	2281	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	167:e84263d55307	2282	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	167:e84263d55307	2283	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	167:e84263d55307	2284	* @retval None
AnnaBridge	167:e84263d55307	2285	*/
AnnaBridge	167:e84263d55307	2286	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	167:e84263d55307	2287	{
AnnaBridge	167:e84263d55307	2288	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2289	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2290	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	167:e84263d55307	2291	}
AnnaBridge	167:e84263d55307	2292
AnnaBridge	167:e84263d55307	2293	/**
AnnaBridge	167:e84263d55307	2294	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	167:e84263d55307	2295	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	167:e84263d55307	2296	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	167:e84263d55307	2297	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	167:e84263d55307	2298	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	167:e84263d55307	2299	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2300	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2301	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2302	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2303	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2304	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2305	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	2306	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	167:e84263d55307	2307	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	167:e84263d55307	2308	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	167:e84263d55307	2309	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	167:e84263d55307	2310	*/
AnnaBridge	167:e84263d55307	2311	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	2312	{
AnnaBridge	167:e84263d55307	2313	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2314	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2315	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	167:e84263d55307	2316	}
AnnaBridge	167:e84263d55307	2317
AnnaBridge	167:e84263d55307	2318	/**
AnnaBridge	167:e84263d55307	2319	* @brief Set the input filter duration.
AnnaBridge	167:e84263d55307	2320	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	167:e84263d55307	2321	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	167:e84263d55307	2322	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	167:e84263d55307	2323	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	167:e84263d55307	2324	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2325	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2326	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2327	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2328	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2329	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2330	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2331	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	167:e84263d55307	2332	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	167:e84263d55307	2333	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	167:e84263d55307	2334	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	167:e84263d55307	2335	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	167:e84263d55307	2336	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	167:e84263d55307	2337	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	167:e84263d55307	2338	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	167:e84263d55307	2339	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	167:e84263d55307	2340	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	167:e84263d55307	2341	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	167:e84263d55307	2342	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	167:e84263d55307	2343	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	167:e84263d55307	2344	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	167:e84263d55307	2345	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	167:e84263d55307	2346	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	167:e84263d55307	2347	* @retval None
AnnaBridge	167:e84263d55307	2348	*/
AnnaBridge	167:e84263d55307	2349	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	167:e84263d55307	2350	{
AnnaBridge	167:e84263d55307	2351	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2352	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2353	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	167:e84263d55307	2354	}
AnnaBridge	167:e84263d55307	2355
AnnaBridge	167:e84263d55307	2356	/**
AnnaBridge	167:e84263d55307	2357	* @brief Get the input filter duration.
AnnaBridge	167:e84263d55307	2358	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	167:e84263d55307	2359	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	167:e84263d55307	2360	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	167:e84263d55307	2361	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	167:e84263d55307	2362	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2363	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2364	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2365	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2366	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2367	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2368	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	2369	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	167:e84263d55307	2370	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	167:e84263d55307	2371	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	167:e84263d55307	2372	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	167:e84263d55307	2373	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	167:e84263d55307	2374	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	167:e84263d55307	2375	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	167:e84263d55307	2376	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	167:e84263d55307	2377	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	167:e84263d55307	2378	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	167:e84263d55307	2379	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	167:e84263d55307	2380	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	167:e84263d55307	2381	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	167:e84263d55307	2382	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	167:e84263d55307	2383	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	167:e84263d55307	2384	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	167:e84263d55307	2385	*/
AnnaBridge	167:e84263d55307	2386	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	2387	{
AnnaBridge	167:e84263d55307	2388	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2389	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	167:e84263d55307	2390	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	167:e84263d55307	2391	}
AnnaBridge	167:e84263d55307	2392
AnnaBridge	167:e84263d55307	2393	/**
AnnaBridge	167:e84263d55307	2394	* @brief Set the input channel polarity.
AnnaBridge	167:e84263d55307	2395	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	167:e84263d55307	2396	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	167:e84263d55307	2397	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	167:e84263d55307	2398	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	167:e84263d55307	2399	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	167:e84263d55307	2400	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	167:e84263d55307	2401	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	167:e84263d55307	2402	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	167:e84263d55307	2403	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2404	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2405	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2406	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2407	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2408	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2409	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2410	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	167:e84263d55307	2411	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	167:e84263d55307	2412	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	167:e84263d55307	2413	* @retval None
AnnaBridge	167:e84263d55307	2414	*/
AnnaBridge	167:e84263d55307	2415	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	167:e84263d55307	2416	{
AnnaBridge	167:e84263d55307	2417	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2418	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	167:e84263d55307	2419	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	167:e84263d55307	2420	}
AnnaBridge	167:e84263d55307	2421
AnnaBridge	167:e84263d55307	2422	/**
AnnaBridge	167:e84263d55307	2423	* @brief Get the current input channel polarity.
AnnaBridge	167:e84263d55307	2424	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	167:e84263d55307	2425	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	167:e84263d55307	2426	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	167:e84263d55307	2427	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	167:e84263d55307	2428	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	167:e84263d55307	2429	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	167:e84263d55307	2430	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	167:e84263d55307	2431	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	167:e84263d55307	2432	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2433	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2434	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	167:e84263d55307	2435	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	167:e84263d55307	2436	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	167:e84263d55307	2437	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	167:e84263d55307	2438	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	2439	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	167:e84263d55307	2440	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	167:e84263d55307	2441	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	167:e84263d55307	2442	*/
AnnaBridge	167:e84263d55307	2443	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	167:e84263d55307	2444	{
AnnaBridge	167:e84263d55307	2445	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	167:e84263d55307	2446	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	167:e84263d55307	2447	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	167:e84263d55307	2448	}
AnnaBridge	167:e84263d55307	2449
AnnaBridge	167:e84263d55307	2450	/**
AnnaBridge	167:e84263d55307	2451	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	167:e84263d55307	2452	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2453	* a timer instance provides an XOR input.
AnnaBridge	167:e84263d55307	2454	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	167:e84263d55307	2455	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2456	* @retval None
AnnaBridge	167:e84263d55307	2457	*/
AnnaBridge	167:e84263d55307	2458	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2459	{
AnnaBridge	167:e84263d55307	2460	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	167:e84263d55307	2461	}
AnnaBridge	167:e84263d55307	2462
AnnaBridge	167:e84263d55307	2463	/**
AnnaBridge	167:e84263d55307	2464	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	167:e84263d55307	2465	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2466	* a timer instance provides an XOR input.
AnnaBridge	167:e84263d55307	2467	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	167:e84263d55307	2468	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2469	* @retval None
AnnaBridge	167:e84263d55307	2470	*/
AnnaBridge	167:e84263d55307	2471	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2472	{
AnnaBridge	167:e84263d55307	2473	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	167:e84263d55307	2474	}
AnnaBridge	167:e84263d55307	2475
AnnaBridge	167:e84263d55307	2476	/**
AnnaBridge	167:e84263d55307	2477	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	167:e84263d55307	2478	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2479	* a timer instance provides an XOR input.
AnnaBridge	167:e84263d55307	2480	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	167:e84263d55307	2481	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2482	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2483	*/
AnnaBridge	167:e84263d55307	2484	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2485	{
AnnaBridge	167:e84263d55307	2486	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	167:e84263d55307	2487	}
AnnaBridge	167:e84263d55307	2488
AnnaBridge	167:e84263d55307	2489	/**
AnnaBridge	167:e84263d55307	2490	* @brief Get captured value for input channel 1.
AnnaBridge	167:e84263d55307	2491	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2492	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2493	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2494	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2495	* input channel 1 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2496	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	167:e84263d55307	2497	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2498	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2499	*/
AnnaBridge	167:e84263d55307	2500	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2501	{
AnnaBridge	167:e84263d55307	2502	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	167:e84263d55307	2503	}
AnnaBridge	167:e84263d55307	2504
AnnaBridge	167:e84263d55307	2505	/**
AnnaBridge	167:e84263d55307	2506	* @brief Get captured value for input channel 2.
AnnaBridge	167:e84263d55307	2507	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2508	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2509	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2510	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2511	* input channel 2 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2512	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	167:e84263d55307	2513	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2514	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2515	*/
AnnaBridge	167:e84263d55307	2516	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2517	{
AnnaBridge	167:e84263d55307	2518	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	167:e84263d55307	2519	}
AnnaBridge	167:e84263d55307	2520
AnnaBridge	167:e84263d55307	2521	/**
AnnaBridge	167:e84263d55307	2522	* @brief Get captured value for input channel 3.
AnnaBridge	167:e84263d55307	2523	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2524	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2525	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2526	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2527	* input channel 3 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2528	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	167:e84263d55307	2529	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2530	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2531	*/
AnnaBridge	167:e84263d55307	2532	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2533	{
AnnaBridge	167:e84263d55307	2534	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	167:e84263d55307	2535	}
AnnaBridge	167:e84263d55307	2536
AnnaBridge	167:e84263d55307	2537	/**
AnnaBridge	167:e84263d55307	2538	* @brief Get captured value for input channel 4.
AnnaBridge	167:e84263d55307	2539	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	167:e84263d55307	2540	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2541	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	167:e84263d55307	2542	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2543	* input channel 4 is supported by a timer instance.
AnnaBridge	167:e84263d55307	2544	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	167:e84263d55307	2545	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2546	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	167:e84263d55307	2547	*/
AnnaBridge	167:e84263d55307	2548	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2549	{
AnnaBridge	167:e84263d55307	2550	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	167:e84263d55307	2551	}
AnnaBridge	167:e84263d55307	2552
AnnaBridge	167:e84263d55307	2553	/**
AnnaBridge	167:e84263d55307	2554	* @}
AnnaBridge	167:e84263d55307	2555	*/
AnnaBridge	167:e84263d55307	2556
AnnaBridge	167:e84263d55307	2557	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	167:e84263d55307	2558	* @{
AnnaBridge	167:e84263d55307	2559	*/
AnnaBridge	167:e84263d55307	2560	/**
AnnaBridge	167:e84263d55307	2561	* @brief Enable external clock mode 2.
AnnaBridge	167:e84263d55307	2562	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	167:e84263d55307	2563	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2564	* whether or not a timer instance supports external clock mode2.
AnnaBridge	167:e84263d55307	2565	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	167:e84263d55307	2566	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2567	* @retval None
AnnaBridge	167:e84263d55307	2568	*/
AnnaBridge	167:e84263d55307	2569	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2570	{
AnnaBridge	167:e84263d55307	2571	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	167:e84263d55307	2572	}
AnnaBridge	167:e84263d55307	2573
AnnaBridge	167:e84263d55307	2574	/**
AnnaBridge	167:e84263d55307	2575	* @brief Disable external clock mode 2.
AnnaBridge	167:e84263d55307	2576	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2577	* whether or not a timer instance supports external clock mode2.
AnnaBridge	167:e84263d55307	2578	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	167:e84263d55307	2579	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2580	* @retval None
AnnaBridge	167:e84263d55307	2581	*/
AnnaBridge	167:e84263d55307	2582	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2583	{
AnnaBridge	167:e84263d55307	2584	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	167:e84263d55307	2585	}
AnnaBridge	167:e84263d55307	2586
AnnaBridge	167:e84263d55307	2587	/**
AnnaBridge	167:e84263d55307	2588	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	167:e84263d55307	2589	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2590	* whether or not a timer instance supports external clock mode2.
AnnaBridge	167:e84263d55307	2591	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	167:e84263d55307	2592	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2593	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2594	*/
AnnaBridge	167:e84263d55307	2595	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2596	{
AnnaBridge	167:e84263d55307	2597	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	167:e84263d55307	2598	}
AnnaBridge	167:e84263d55307	2599
AnnaBridge	167:e84263d55307	2600	/**
AnnaBridge	167:e84263d55307	2601	* @brief Set the clock source of the counter clock.
AnnaBridge	167:e84263d55307	2602	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	167:e84263d55307	2603	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	167:e84263d55307	2604	* function. This timer input must be configured by calling
AnnaBridge	167:e84263d55307	2605	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	167:e84263d55307	2606	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2607	* whether or not a timer instance supports external clock mode1.
AnnaBridge	167:e84263d55307	2608	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2609	* whether or not a timer instance supports external clock mode2.
AnnaBridge	167:e84263d55307	2610	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	167:e84263d55307	2611	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	167:e84263d55307	2612	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2613	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2614	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	167:e84263d55307	2615	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	167:e84263d55307	2616	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	167:e84263d55307	2617	* @retval None
AnnaBridge	167:e84263d55307	2618	*/
AnnaBridge	167:e84263d55307	2619	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	167:e84263d55307	2620	{
AnnaBridge	167:e84263d55307	2621	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	167:e84263d55307	2622	}
AnnaBridge	167:e84263d55307	2623
AnnaBridge	167:e84263d55307	2624	/**
AnnaBridge	167:e84263d55307	2625	* @brief Set the encoder interface mode.
AnnaBridge	167:e84263d55307	2626	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2627	* whether or not a timer instance supports the encoder mode.
AnnaBridge	167:e84263d55307	2628	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	167:e84263d55307	2629	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2630	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2631	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	167:e84263d55307	2632	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	167:e84263d55307	2633	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	167:e84263d55307	2634	* @retval None
AnnaBridge	167:e84263d55307	2635	*/
AnnaBridge	167:e84263d55307	2636	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	167:e84263d55307	2637	{
AnnaBridge	167:e84263d55307	2638	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	167:e84263d55307	2639	}
AnnaBridge	167:e84263d55307	2640
AnnaBridge	167:e84263d55307	2641	/**
AnnaBridge	167:e84263d55307	2642	* @}
AnnaBridge	167:e84263d55307	2643	*/
AnnaBridge	167:e84263d55307	2644
AnnaBridge	167:e84263d55307	2645	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	167:e84263d55307	2646	* @{
AnnaBridge	167:e84263d55307	2647	*/
AnnaBridge	167:e84263d55307	2648	/**
AnnaBridge	167:e84263d55307	2649	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	167:e84263d55307	2650	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	167:e84263d55307	2651	* whether or not a timer instance can operate as a master timer.
AnnaBridge	167:e84263d55307	2652	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	167:e84263d55307	2653	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2654	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2655	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	167:e84263d55307	2656	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	167:e84263d55307	2657	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	167:e84263d55307	2658	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	167:e84263d55307	2659	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	167:e84263d55307	2660	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	167:e84263d55307	2661	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	167:e84263d55307	2662	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	167:e84263d55307	2663	* @retval None
AnnaBridge	167:e84263d55307	2664	*/
AnnaBridge	167:e84263d55307	2665	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	167:e84263d55307	2666	{
AnnaBridge	167:e84263d55307	2667	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	167:e84263d55307	2668	}
AnnaBridge	167:e84263d55307	2669
AnnaBridge	167:e84263d55307	2670	/**
AnnaBridge	167:e84263d55307	2671	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	167:e84263d55307	2672	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2673	* a timer instance can operate as a slave timer.
AnnaBridge	167:e84263d55307	2674	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	167:e84263d55307	2675	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2676	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2677	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	167:e84263d55307	2678	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	167:e84263d55307	2679	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	167:e84263d55307	2680	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	167:e84263d55307	2681	* @retval None
AnnaBridge	167:e84263d55307	2682	*/
AnnaBridge	167:e84263d55307	2683	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	167:e84263d55307	2684	{
AnnaBridge	167:e84263d55307	2685	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	167:e84263d55307	2686	}
AnnaBridge	167:e84263d55307	2687
AnnaBridge	167:e84263d55307	2688	/**
AnnaBridge	167:e84263d55307	2689	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	167:e84263d55307	2690	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2691	* a timer instance can operate as a slave timer.
AnnaBridge	167:e84263d55307	2692	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	167:e84263d55307	2693	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2694	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2695	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	167:e84263d55307	2696	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	167:e84263d55307	2697	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	167:e84263d55307	2698	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	167:e84263d55307	2699	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	167:e84263d55307	2700	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	167:e84263d55307	2701	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	167:e84263d55307	2702	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	167:e84263d55307	2703	* @retval None
AnnaBridge	167:e84263d55307	2704	*/
AnnaBridge	167:e84263d55307	2705	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	167:e84263d55307	2706	{
AnnaBridge	167:e84263d55307	2707	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	167:e84263d55307	2708	}
AnnaBridge	167:e84263d55307	2709
AnnaBridge	167:e84263d55307	2710	/**
AnnaBridge	167:e84263d55307	2711	* @brief Enable the Master/Slave mode.
AnnaBridge	167:e84263d55307	2712	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2713	* a timer instance can operate as a slave timer.
AnnaBridge	167:e84263d55307	2714	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	167:e84263d55307	2715	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2716	* @retval None
AnnaBridge	167:e84263d55307	2717	*/
AnnaBridge	167:e84263d55307	2718	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2719	{
AnnaBridge	167:e84263d55307	2720	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	167:e84263d55307	2721	}
AnnaBridge	167:e84263d55307	2722
AnnaBridge	167:e84263d55307	2723	/**
AnnaBridge	167:e84263d55307	2724	* @brief Disable the Master/Slave mode.
AnnaBridge	167:e84263d55307	2725	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2726	* a timer instance can operate as a slave timer.
AnnaBridge	167:e84263d55307	2727	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	167:e84263d55307	2728	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2729	* @retval None
AnnaBridge	167:e84263d55307	2730	*/
AnnaBridge	167:e84263d55307	2731	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2732	{
AnnaBridge	167:e84263d55307	2733	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	167:e84263d55307	2734	}
AnnaBridge	167:e84263d55307	2735
AnnaBridge	167:e84263d55307	2736	/**
AnnaBridge	167:e84263d55307	2737	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	167:e84263d55307	2738	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2739	* a timer instance can operate as a slave timer.
AnnaBridge	167:e84263d55307	2740	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	167:e84263d55307	2741	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2742	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2743	*/
AnnaBridge	167:e84263d55307	2744	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2745	{
AnnaBridge	167:e84263d55307	2746	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	167:e84263d55307	2747	}
AnnaBridge	167:e84263d55307	2748
AnnaBridge	167:e84263d55307	2749	/**
AnnaBridge	167:e84263d55307	2750	* @brief Configure the external trigger (ETR) input.
AnnaBridge	167:e84263d55307	2751	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2752	* a timer instance provides an external trigger input.
AnnaBridge	167:e84263d55307	2753	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	167:e84263d55307	2754	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	167:e84263d55307	2755	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	167:e84263d55307	2756	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2757	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2758	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	167:e84263d55307	2759	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	167:e84263d55307	2760	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2761	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	167:e84263d55307	2762	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	167:e84263d55307	2763	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	167:e84263d55307	2764	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	167:e84263d55307	2765	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2766	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	167:e84263d55307	2767	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	167:e84263d55307	2768	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	167:e84263d55307	2769	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	167:e84263d55307	2770	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	167:e84263d55307	2771	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	167:e84263d55307	2772	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	167:e84263d55307	2773	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	167:e84263d55307	2774	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	167:e84263d55307	2775	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	167:e84263d55307	2776	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	167:e84263d55307	2777	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	167:e84263d55307	2778	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	167:e84263d55307	2779	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	167:e84263d55307	2780	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	167:e84263d55307	2781	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	167:e84263d55307	2782	* @retval None
AnnaBridge	167:e84263d55307	2783	*/
AnnaBridge	167:e84263d55307	2784	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	167:e84263d55307	2785	uint32_t ETRFilter)
AnnaBridge	167:e84263d55307	2786	{
AnnaBridge	167:e84263d55307	2787	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	167:e84263d55307	2788	}
AnnaBridge	167:e84263d55307	2789
AnnaBridge	167:e84263d55307	2790	/**
AnnaBridge	167:e84263d55307	2791	* @}
AnnaBridge	167:e84263d55307	2792	*/
AnnaBridge	167:e84263d55307	2793
AnnaBridge	167:e84263d55307	2794	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
AnnaBridge	167:e84263d55307	2795	* @{
AnnaBridge	167:e84263d55307	2796	*/
AnnaBridge	167:e84263d55307	2797	/**
AnnaBridge	167:e84263d55307	2798	* @brief Enable the break function.
AnnaBridge	167:e84263d55307	2799	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2800	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2801	* @rmtoll BDTR BKE LL_TIM_EnableBRK
AnnaBridge	167:e84263d55307	2802	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2803	* @retval None
AnnaBridge	167:e84263d55307	2804	*/
AnnaBridge	167:e84263d55307	2805	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2806	{
AnnaBridge	167:e84263d55307	2807	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	167:e84263d55307	2808	}
AnnaBridge	167:e84263d55307	2809
AnnaBridge	167:e84263d55307	2810	/**
AnnaBridge	167:e84263d55307	2811	* @brief Disable the break function.
AnnaBridge	167:e84263d55307	2812	* @rmtoll BDTR BKE LL_TIM_DisableBRK
AnnaBridge	167:e84263d55307	2813	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2814	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2815	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2816	* @retval None
AnnaBridge	167:e84263d55307	2817	*/
AnnaBridge	167:e84263d55307	2818	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2819	{
AnnaBridge	167:e84263d55307	2820	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	167:e84263d55307	2821	}
AnnaBridge	167:e84263d55307	2822
AnnaBridge	167:e84263d55307	2823	/**
AnnaBridge	167:e84263d55307	2824	* @brief Configure the break input.
AnnaBridge	167:e84263d55307	2825	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2826	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2827	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
AnnaBridge	167:e84263d55307	2828	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2829	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2830	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	167:e84263d55307	2831	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	167:e84263d55307	2832	* @retval None
AnnaBridge	167:e84263d55307	2833	*/
AnnaBridge	167:e84263d55307	2834	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
AnnaBridge	167:e84263d55307	2835	{
AnnaBridge	167:e84263d55307	2836	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
AnnaBridge	167:e84263d55307	2837	}
AnnaBridge	167:e84263d55307	2838
AnnaBridge	167:e84263d55307	2839	/**
AnnaBridge	167:e84263d55307	2840	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
AnnaBridge	167:e84263d55307	2841	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2842	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2843	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
AnnaBridge	167:e84263d55307	2844	* BDTR OSSR LL_TIM_SetOffStates
AnnaBridge	167:e84263d55307	2845	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2846	* @param OffStateIdle This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2847	* @arg @ref LL_TIM_OSSI_DISABLE
AnnaBridge	167:e84263d55307	2848	* @arg @ref LL_TIM_OSSI_ENABLE
AnnaBridge	167:e84263d55307	2849	* @param OffStateRun This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2850	* @arg @ref LL_TIM_OSSR_DISABLE
AnnaBridge	167:e84263d55307	2851	* @arg @ref LL_TIM_OSSR_ENABLE
AnnaBridge	167:e84263d55307	2852	* @retval None
AnnaBridge	167:e84263d55307	2853	*/
AnnaBridge	167:e84263d55307	2854	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
AnnaBridge	167:e84263d55307	2855	{
AnnaBridge	167:e84263d55307	2856	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
AnnaBridge	167:e84263d55307	2857	}
AnnaBridge	167:e84263d55307	2858
AnnaBridge	167:e84263d55307	2859	/**
AnnaBridge	167:e84263d55307	2860	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
AnnaBridge	167:e84263d55307	2861	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2862	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2863	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
AnnaBridge	167:e84263d55307	2864	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2865	* @retval None
AnnaBridge	167:e84263d55307	2866	*/
AnnaBridge	167:e84263d55307	2867	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2868	{
AnnaBridge	167:e84263d55307	2869	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	167:e84263d55307	2870	}
AnnaBridge	167:e84263d55307	2871
AnnaBridge	167:e84263d55307	2872	/**
AnnaBridge	167:e84263d55307	2873	* @brief Disable automatic output (MOE can be set only by software).
AnnaBridge	167:e84263d55307	2874	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2875	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2876	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
AnnaBridge	167:e84263d55307	2877	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2878	* @retval None
AnnaBridge	167:e84263d55307	2879	*/
AnnaBridge	167:e84263d55307	2880	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2881	{
AnnaBridge	167:e84263d55307	2882	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	167:e84263d55307	2883	}
AnnaBridge	167:e84263d55307	2884
AnnaBridge	167:e84263d55307	2885	/**
AnnaBridge	167:e84263d55307	2886	* @brief Indicate whether automatic output is enabled.
AnnaBridge	167:e84263d55307	2887	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2888	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2889	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
AnnaBridge	167:e84263d55307	2890	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2891	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2892	*/
AnnaBridge	167:e84263d55307	2893	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2894	{
AnnaBridge	167:e84263d55307	2895	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
AnnaBridge	167:e84263d55307	2896	}
AnnaBridge	167:e84263d55307	2897
AnnaBridge	167:e84263d55307	2898	/**
AnnaBridge	167:e84263d55307	2899	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
AnnaBridge	167:e84263d55307	2900	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	167:e84263d55307	2901	* software and is reset in case of break or break2 event
AnnaBridge	167:e84263d55307	2902	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2903	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2904	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
AnnaBridge	167:e84263d55307	2905	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2906	* @retval None
AnnaBridge	167:e84263d55307	2907	*/
AnnaBridge	167:e84263d55307	2908	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2909	{
AnnaBridge	167:e84263d55307	2910	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	167:e84263d55307	2911	}
AnnaBridge	167:e84263d55307	2912
AnnaBridge	167:e84263d55307	2913	/**
AnnaBridge	167:e84263d55307	2914	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
AnnaBridge	167:e84263d55307	2915	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	167:e84263d55307	2916	* software and is reset in case of break or break2 event.
AnnaBridge	167:e84263d55307	2917	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2918	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2919	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
AnnaBridge	167:e84263d55307	2920	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2921	* @retval None
AnnaBridge	167:e84263d55307	2922	*/
AnnaBridge	167:e84263d55307	2923	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2924	{
AnnaBridge	167:e84263d55307	2925	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	167:e84263d55307	2926	}
AnnaBridge	167:e84263d55307	2927
AnnaBridge	167:e84263d55307	2928	/**
AnnaBridge	167:e84263d55307	2929	* @brief Indicates whether outputs are enabled.
AnnaBridge	167:e84263d55307	2930	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	2931	* a timer instance provides a break input.
AnnaBridge	167:e84263d55307	2932	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
AnnaBridge	167:e84263d55307	2933	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2934	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2935	*/
AnnaBridge	167:e84263d55307	2936	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	2937	{
AnnaBridge	167:e84263d55307	2938	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
AnnaBridge	167:e84263d55307	2939	}
AnnaBridge	167:e84263d55307	2940
AnnaBridge	167:e84263d55307	2941	/**
AnnaBridge	167:e84263d55307	2942	* @}
AnnaBridge	167:e84263d55307	2943	*/
AnnaBridge	167:e84263d55307	2944
AnnaBridge	167:e84263d55307	2945	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	167:e84263d55307	2946	* @{
AnnaBridge	167:e84263d55307	2947	*/
AnnaBridge	167:e84263d55307	2948	/**
AnnaBridge	167:e84263d55307	2949	* @brief Configures the timer DMA burst feature.
AnnaBridge	167:e84263d55307	2950	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	167:e84263d55307	2951	* not a timer instance supports the DMA burst mode.
AnnaBridge	167:e84263d55307	2952	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	167:e84263d55307	2953	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	167:e84263d55307	2954	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	2955	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2956	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	167:e84263d55307	2957	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	167:e84263d55307	2958	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	167:e84263d55307	2959	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	167:e84263d55307	2960	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	167:e84263d55307	2961	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	167:e84263d55307	2962	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	167:e84263d55307	2963	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	167:e84263d55307	2964	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	167:e84263d55307	2965	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	167:e84263d55307	2966	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	167:e84263d55307	2967	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	167:e84263d55307	2968	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	167:e84263d55307	2969	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	167:e84263d55307	2970	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	167:e84263d55307	2971	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	167:e84263d55307	2972	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	167:e84263d55307	2973	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	167:e84263d55307	2974	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
AnnaBridge	167:e84263d55307	2975	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2976	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	167:e84263d55307	2977	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	167:e84263d55307	2978	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	167:e84263d55307	2979	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	167:e84263d55307	2980	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	167:e84263d55307	2981	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	167:e84263d55307	2982	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	167:e84263d55307	2983	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	167:e84263d55307	2984	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	167:e84263d55307	2985	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	167:e84263d55307	2986	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	167:e84263d55307	2987	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	167:e84263d55307	2988	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	167:e84263d55307	2989	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	167:e84263d55307	2990	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	167:e84263d55307	2991	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	167:e84263d55307	2992	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	167:e84263d55307	2993	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	167:e84263d55307	2994	* @retval None
AnnaBridge	167:e84263d55307	2995	*/
AnnaBridge	167:e84263d55307	2996	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	167:e84263d55307	2997	{
AnnaBridge	167:e84263d55307	2998	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	167:e84263d55307	2999	}
AnnaBridge	167:e84263d55307	3000
AnnaBridge	167:e84263d55307	3001	/**
AnnaBridge	167:e84263d55307	3002	* @}
AnnaBridge	167:e84263d55307	3003	*/
AnnaBridge	167:e84263d55307	3004
AnnaBridge	167:e84263d55307	3005	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	167:e84263d55307	3006	* @{
AnnaBridge	167:e84263d55307	3007	*/
AnnaBridge	167:e84263d55307	3008	/**
AnnaBridge	167:e84263d55307	3009	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	167:e84263d55307	3010	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	167:e84263d55307	3011	* a some timer inputs can be remapped.
AnnaBridge	167:e84263d55307	3012	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
AnnaBridge	167:e84263d55307	3013	* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
AnnaBridge	167:e84263d55307	3014	* TIM11_OR TI1_RMP LL_TIM_SetRemap
AnnaBridge	167:e84263d55307	3015	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3016	* @param Remap Remap param depends on the TIMx. Description available only
AnnaBridge	167:e84263d55307	3017	* in CHM version of the User Manual (not in .pdf).
AnnaBridge	167:e84263d55307	3018	* Otherwise see Reference Manual description of OR registers.
AnnaBridge	167:e84263d55307	3019	*
AnnaBridge	167:e84263d55307	3020	* Below description summarizes "Timer Instance" and "Remap" param combinations:
AnnaBridge	167:e84263d55307	3021	*
AnnaBridge	167:e84263d55307	3022	* TIM2: one of the following values
AnnaBridge	167:e84263d55307	3023	*
AnnaBridge	167:e84263d55307	3024	* ITR1_RMP can be one of the following values
AnnaBridge	167:e84263d55307	3025	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
AnnaBridge	167:e84263d55307	3026	* @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
AnnaBridge	167:e84263d55307	3027	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
AnnaBridge	167:e84263d55307	3028	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
AnnaBridge	167:e84263d55307	3029	*
AnnaBridge	167:e84263d55307	3030	* TIM5: one of the following values
AnnaBridge	167:e84263d55307	3031	*
AnnaBridge	167:e84263d55307	3032	* @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
AnnaBridge	167:e84263d55307	3033	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
AnnaBridge	167:e84263d55307	3034	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
AnnaBridge	167:e84263d55307	3035	* @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
AnnaBridge	167:e84263d55307	3036	*
AnnaBridge	167:e84263d55307	3037	* TIM11: one of the following values
AnnaBridge	167:e84263d55307	3038	*
AnnaBridge	167:e84263d55307	3039	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
AnnaBridge	167:e84263d55307	3040	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1
AnnaBridge	167:e84263d55307	3041	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
AnnaBridge	167:e84263d55307	3042	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
AnnaBridge	167:e84263d55307	3043	*
AnnaBridge	167:e84263d55307	3044	* @retval None
AnnaBridge	167:e84263d55307	3045	*/
AnnaBridge	167:e84263d55307	3046	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
AnnaBridge	167:e84263d55307	3047	{
AnnaBridge	167:e84263d55307	3048	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
AnnaBridge	167:e84263d55307	3049	}
AnnaBridge	167:e84263d55307	3050
AnnaBridge	167:e84263d55307	3051	/**
AnnaBridge	167:e84263d55307	3052	* @}
AnnaBridge	167:e84263d55307	3053	*/
AnnaBridge	167:e84263d55307	3054
AnnaBridge	167:e84263d55307	3055
AnnaBridge	167:e84263d55307	3056	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	167:e84263d55307	3057	* @{
AnnaBridge	167:e84263d55307	3058	*/
AnnaBridge	167:e84263d55307	3059	/**
AnnaBridge	167:e84263d55307	3060	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	167:e84263d55307	3061	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	167:e84263d55307	3062	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3063	* @retval None
AnnaBridge	167:e84263d55307	3064	*/
AnnaBridge	167:e84263d55307	3065	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3066	{
AnnaBridge	167:e84263d55307	3067	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	167:e84263d55307	3068	}
AnnaBridge	167:e84263d55307	3069
AnnaBridge	167:e84263d55307	3070	/**
AnnaBridge	167:e84263d55307	3071	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	167:e84263d55307	3072	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	167:e84263d55307	3073	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3074	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3075	*/
AnnaBridge	167:e84263d55307	3076	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3077	{
AnnaBridge	167:e84263d55307	3078	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	167:e84263d55307	3079	}
AnnaBridge	167:e84263d55307	3080
AnnaBridge	167:e84263d55307	3081	/**
AnnaBridge	167:e84263d55307	3082	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	167:e84263d55307	3083	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	167:e84263d55307	3084	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3085	* @retval None
AnnaBridge	167:e84263d55307	3086	*/
AnnaBridge	167:e84263d55307	3087	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3088	{
AnnaBridge	167:e84263d55307	3089	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	167:e84263d55307	3090	}
AnnaBridge	167:e84263d55307	3091
AnnaBridge	167:e84263d55307	3092	/**
AnnaBridge	167:e84263d55307	3093	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	167:e84263d55307	3094	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	167:e84263d55307	3095	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3096	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3097	*/
AnnaBridge	167:e84263d55307	3098	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3099	{
AnnaBridge	167:e84263d55307	3100	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	167:e84263d55307	3101	}
AnnaBridge	167:e84263d55307	3102
AnnaBridge	167:e84263d55307	3103	/**
AnnaBridge	167:e84263d55307	3104	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	167:e84263d55307	3105	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	167:e84263d55307	3106	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3107	* @retval None
AnnaBridge	167:e84263d55307	3108	*/
AnnaBridge	167:e84263d55307	3109	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3110	{
AnnaBridge	167:e84263d55307	3111	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	167:e84263d55307	3112	}
AnnaBridge	167:e84263d55307	3113
AnnaBridge	167:e84263d55307	3114	/**
AnnaBridge	167:e84263d55307	3115	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	167:e84263d55307	3116	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	167:e84263d55307	3117	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3118	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3119	*/
AnnaBridge	167:e84263d55307	3120	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3121	{
AnnaBridge	167:e84263d55307	3122	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	167:e84263d55307	3123	}
AnnaBridge	167:e84263d55307	3124
AnnaBridge	167:e84263d55307	3125	/**
AnnaBridge	167:e84263d55307	3126	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	167:e84263d55307	3127	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	167:e84263d55307	3128	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3129	* @retval None
AnnaBridge	167:e84263d55307	3130	*/
AnnaBridge	167:e84263d55307	3131	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3132	{
AnnaBridge	167:e84263d55307	3133	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	167:e84263d55307	3134	}
AnnaBridge	167:e84263d55307	3135
AnnaBridge	167:e84263d55307	3136	/**
AnnaBridge	167:e84263d55307	3137	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	167:e84263d55307	3138	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	167:e84263d55307	3139	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3140	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3141	*/
AnnaBridge	167:e84263d55307	3142	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3143	{
AnnaBridge	167:e84263d55307	3144	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	167:e84263d55307	3145	}
AnnaBridge	167:e84263d55307	3146
AnnaBridge	167:e84263d55307	3147	/**
AnnaBridge	167:e84263d55307	3148	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	167:e84263d55307	3149	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	167:e84263d55307	3150	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3151	* @retval None
AnnaBridge	167:e84263d55307	3152	*/
AnnaBridge	167:e84263d55307	3153	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3154	{
AnnaBridge	167:e84263d55307	3155	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	167:e84263d55307	3156	}
AnnaBridge	167:e84263d55307	3157
AnnaBridge	167:e84263d55307	3158	/**
AnnaBridge	167:e84263d55307	3159	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	167:e84263d55307	3160	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	167:e84263d55307	3161	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3162	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3163	*/
AnnaBridge	167:e84263d55307	3164	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3165	{
AnnaBridge	167:e84263d55307	3166	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	167:e84263d55307	3167	}
AnnaBridge	167:e84263d55307	3168
AnnaBridge	167:e84263d55307	3169	/**
AnnaBridge	167:e84263d55307	3170	* @brief Clear the commutation interrupt flag (COMIF).
AnnaBridge	167:e84263d55307	3171	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
AnnaBridge	167:e84263d55307	3172	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3173	* @retval None
AnnaBridge	167:e84263d55307	3174	*/
AnnaBridge	167:e84263d55307	3175	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3176	{
AnnaBridge	167:e84263d55307	3177	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
AnnaBridge	167:e84263d55307	3178	}
AnnaBridge	167:e84263d55307	3179
AnnaBridge	167:e84263d55307	3180	/**
AnnaBridge	167:e84263d55307	3181	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
AnnaBridge	167:e84263d55307	3182	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
AnnaBridge	167:e84263d55307	3183	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3184	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3185	*/
AnnaBridge	167:e84263d55307	3186	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3187	{
AnnaBridge	167:e84263d55307	3188	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
AnnaBridge	167:e84263d55307	3189	}
AnnaBridge	167:e84263d55307	3190
AnnaBridge	167:e84263d55307	3191	/**
AnnaBridge	167:e84263d55307	3192	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	167:e84263d55307	3193	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	167:e84263d55307	3194	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3195	* @retval None
AnnaBridge	167:e84263d55307	3196	*/
AnnaBridge	167:e84263d55307	3197	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3198	{
AnnaBridge	167:e84263d55307	3199	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	167:e84263d55307	3200	}
AnnaBridge	167:e84263d55307	3201
AnnaBridge	167:e84263d55307	3202	/**
AnnaBridge	167:e84263d55307	3203	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	167:e84263d55307	3204	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	167:e84263d55307	3205	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3206	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3207	*/
AnnaBridge	167:e84263d55307	3208	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3209	{
AnnaBridge	167:e84263d55307	3210	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	167:e84263d55307	3211	}
AnnaBridge	167:e84263d55307	3212
AnnaBridge	167:e84263d55307	3213	/**
AnnaBridge	167:e84263d55307	3214	* @brief Clear the break interrupt flag (BIF).
AnnaBridge	167:e84263d55307	3215	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
AnnaBridge	167:e84263d55307	3216	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3217	* @retval None
AnnaBridge	167:e84263d55307	3218	*/
AnnaBridge	167:e84263d55307	3219	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3220	{
AnnaBridge	167:e84263d55307	3221	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
AnnaBridge	167:e84263d55307	3222	}
AnnaBridge	167:e84263d55307	3223
AnnaBridge	167:e84263d55307	3224	/**
AnnaBridge	167:e84263d55307	3225	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
AnnaBridge	167:e84263d55307	3226	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
AnnaBridge	167:e84263d55307	3227	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3228	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3229	*/
AnnaBridge	167:e84263d55307	3230	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3231	{
AnnaBridge	167:e84263d55307	3232	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
AnnaBridge	167:e84263d55307	3233	}
AnnaBridge	167:e84263d55307	3234
AnnaBridge	167:e84263d55307	3235	/**
AnnaBridge	167:e84263d55307	3236	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	167:e84263d55307	3237	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	167:e84263d55307	3238	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3239	* @retval None
AnnaBridge	167:e84263d55307	3240	*/
AnnaBridge	167:e84263d55307	3241	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3242	{
AnnaBridge	167:e84263d55307	3243	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	167:e84263d55307	3244	}
AnnaBridge	167:e84263d55307	3245
AnnaBridge	167:e84263d55307	3246	/**
AnnaBridge	167:e84263d55307	3247	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	167:e84263d55307	3248	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	167:e84263d55307	3249	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3250	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3251	*/
AnnaBridge	167:e84263d55307	3252	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3253	{
AnnaBridge	167:e84263d55307	3254	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	167:e84263d55307	3255	}
AnnaBridge	167:e84263d55307	3256
AnnaBridge	167:e84263d55307	3257	/**
AnnaBridge	167:e84263d55307	3258	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	167:e84263d55307	3259	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	167:e84263d55307	3260	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3261	* @retval None
AnnaBridge	167:e84263d55307	3262	*/
AnnaBridge	167:e84263d55307	3263	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3264	{
AnnaBridge	167:e84263d55307	3265	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	167:e84263d55307	3266	}
AnnaBridge	167:e84263d55307	3267
AnnaBridge	167:e84263d55307	3268	/**
AnnaBridge	167:e84263d55307	3269	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	167:e84263d55307	3270	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	167:e84263d55307	3271	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3272	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3273	*/
AnnaBridge	167:e84263d55307	3274	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3275	{
AnnaBridge	167:e84263d55307	3276	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	167:e84263d55307	3277	}
AnnaBridge	167:e84263d55307	3278
AnnaBridge	167:e84263d55307	3279	/**
AnnaBridge	167:e84263d55307	3280	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	167:e84263d55307	3281	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	167:e84263d55307	3282	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3283	* @retval None
AnnaBridge	167:e84263d55307	3284	*/
AnnaBridge	167:e84263d55307	3285	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3286	{
AnnaBridge	167:e84263d55307	3287	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	167:e84263d55307	3288	}
AnnaBridge	167:e84263d55307	3289
AnnaBridge	167:e84263d55307	3290	/**
AnnaBridge	167:e84263d55307	3291	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	167:e84263d55307	3292	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	167:e84263d55307	3293	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3294	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3295	*/
AnnaBridge	167:e84263d55307	3296	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3297	{
AnnaBridge	167:e84263d55307	3298	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	167:e84263d55307	3299	}
AnnaBridge	167:e84263d55307	3300
AnnaBridge	167:e84263d55307	3301	/**
AnnaBridge	167:e84263d55307	3302	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	167:e84263d55307	3303	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	167:e84263d55307	3304	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3305	* @retval None
AnnaBridge	167:e84263d55307	3306	*/
AnnaBridge	167:e84263d55307	3307	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3308	{
AnnaBridge	167:e84263d55307	3309	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	167:e84263d55307	3310	}
AnnaBridge	167:e84263d55307	3311
AnnaBridge	167:e84263d55307	3312	/**
AnnaBridge	167:e84263d55307	3313	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	167:e84263d55307	3314	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	167:e84263d55307	3315	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3316	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3317	*/
AnnaBridge	167:e84263d55307	3318	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3319	{
AnnaBridge	167:e84263d55307	3320	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	167:e84263d55307	3321	}
AnnaBridge	167:e84263d55307	3322
AnnaBridge	167:e84263d55307	3323	/**
AnnaBridge	167:e84263d55307	3324	* @}
AnnaBridge	167:e84263d55307	3325	*/
AnnaBridge	167:e84263d55307	3326
AnnaBridge	167:e84263d55307	3327	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	167:e84263d55307	3328	* @{
AnnaBridge	167:e84263d55307	3329	*/
AnnaBridge	167:e84263d55307	3330	/**
AnnaBridge	167:e84263d55307	3331	* @brief Enable update interrupt (UIE).
AnnaBridge	167:e84263d55307	3332	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	167:e84263d55307	3333	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3334	* @retval None
AnnaBridge	167:e84263d55307	3335	*/
AnnaBridge	167:e84263d55307	3336	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3337	{
AnnaBridge	167:e84263d55307	3338	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	167:e84263d55307	3339	}
AnnaBridge	167:e84263d55307	3340
AnnaBridge	167:e84263d55307	3341	/**
AnnaBridge	167:e84263d55307	3342	* @brief Disable update interrupt (UIE).
AnnaBridge	167:e84263d55307	3343	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	167:e84263d55307	3344	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3345	* @retval None
AnnaBridge	167:e84263d55307	3346	*/
AnnaBridge	167:e84263d55307	3347	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3348	{
AnnaBridge	167:e84263d55307	3349	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	167:e84263d55307	3350	}
AnnaBridge	167:e84263d55307	3351
AnnaBridge	167:e84263d55307	3352	/**
AnnaBridge	167:e84263d55307	3353	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	167:e84263d55307	3354	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	167:e84263d55307	3355	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3356	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3357	*/
AnnaBridge	167:e84263d55307	3358	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3359	{
AnnaBridge	167:e84263d55307	3360	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	167:e84263d55307	3361	}
AnnaBridge	167:e84263d55307	3362
AnnaBridge	167:e84263d55307	3363	/**
AnnaBridge	167:e84263d55307	3364	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	167:e84263d55307	3365	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	167:e84263d55307	3366	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3367	* @retval None
AnnaBridge	167:e84263d55307	3368	*/
AnnaBridge	167:e84263d55307	3369	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3370	{
AnnaBridge	167:e84263d55307	3371	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	167:e84263d55307	3372	}
AnnaBridge	167:e84263d55307	3373
AnnaBridge	167:e84263d55307	3374	/**
AnnaBridge	167:e84263d55307	3375	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	167:e84263d55307	3376	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	167:e84263d55307	3377	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3378	* @retval None
AnnaBridge	167:e84263d55307	3379	*/
AnnaBridge	167:e84263d55307	3380	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3381	{
AnnaBridge	167:e84263d55307	3382	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	167:e84263d55307	3383	}
AnnaBridge	167:e84263d55307	3384
AnnaBridge	167:e84263d55307	3385	/**
AnnaBridge	167:e84263d55307	3386	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	167:e84263d55307	3387	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	167:e84263d55307	3388	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3389	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3390	*/
AnnaBridge	167:e84263d55307	3391	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3392	{
AnnaBridge	167:e84263d55307	3393	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	167:e84263d55307	3394	}
AnnaBridge	167:e84263d55307	3395
AnnaBridge	167:e84263d55307	3396	/**
AnnaBridge	167:e84263d55307	3397	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	167:e84263d55307	3398	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	167:e84263d55307	3399	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3400	* @retval None
AnnaBridge	167:e84263d55307	3401	*/
AnnaBridge	167:e84263d55307	3402	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3403	{
AnnaBridge	167:e84263d55307	3404	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	167:e84263d55307	3405	}
AnnaBridge	167:e84263d55307	3406
AnnaBridge	167:e84263d55307	3407	/**
AnnaBridge	167:e84263d55307	3408	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	167:e84263d55307	3409	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	167:e84263d55307	3410	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3411	* @retval None
AnnaBridge	167:e84263d55307	3412	*/
AnnaBridge	167:e84263d55307	3413	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3414	{
AnnaBridge	167:e84263d55307	3415	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	167:e84263d55307	3416	}
AnnaBridge	167:e84263d55307	3417
AnnaBridge	167:e84263d55307	3418	/**
AnnaBridge	167:e84263d55307	3419	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	167:e84263d55307	3420	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	167:e84263d55307	3421	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3422	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3423	*/
AnnaBridge	167:e84263d55307	3424	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3425	{
AnnaBridge	167:e84263d55307	3426	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	167:e84263d55307	3427	}
AnnaBridge	167:e84263d55307	3428
AnnaBridge	167:e84263d55307	3429	/**
AnnaBridge	167:e84263d55307	3430	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	167:e84263d55307	3431	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	167:e84263d55307	3432	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3433	* @retval None
AnnaBridge	167:e84263d55307	3434	*/
AnnaBridge	167:e84263d55307	3435	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3436	{
AnnaBridge	167:e84263d55307	3437	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	167:e84263d55307	3438	}
AnnaBridge	167:e84263d55307	3439
AnnaBridge	167:e84263d55307	3440	/**
AnnaBridge	167:e84263d55307	3441	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	167:e84263d55307	3442	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	167:e84263d55307	3443	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3444	* @retval None
AnnaBridge	167:e84263d55307	3445	*/
AnnaBridge	167:e84263d55307	3446	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3447	{
AnnaBridge	167:e84263d55307	3448	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	167:e84263d55307	3449	}
AnnaBridge	167:e84263d55307	3450
AnnaBridge	167:e84263d55307	3451	/**
AnnaBridge	167:e84263d55307	3452	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	167:e84263d55307	3453	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	167:e84263d55307	3454	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3455	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3456	*/
AnnaBridge	167:e84263d55307	3457	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3458	{
AnnaBridge	167:e84263d55307	3459	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	167:e84263d55307	3460	}
AnnaBridge	167:e84263d55307	3461
AnnaBridge	167:e84263d55307	3462	/**
AnnaBridge	167:e84263d55307	3463	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	167:e84263d55307	3464	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	167:e84263d55307	3465	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3466	* @retval None
AnnaBridge	167:e84263d55307	3467	*/
AnnaBridge	167:e84263d55307	3468	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3469	{
AnnaBridge	167:e84263d55307	3470	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	167:e84263d55307	3471	}
AnnaBridge	167:e84263d55307	3472
AnnaBridge	167:e84263d55307	3473	/**
AnnaBridge	167:e84263d55307	3474	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	167:e84263d55307	3475	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	167:e84263d55307	3476	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3477	* @retval None
AnnaBridge	167:e84263d55307	3478	*/
AnnaBridge	167:e84263d55307	3479	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3480	{
AnnaBridge	167:e84263d55307	3481	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	167:e84263d55307	3482	}
AnnaBridge	167:e84263d55307	3483
AnnaBridge	167:e84263d55307	3484	/**
AnnaBridge	167:e84263d55307	3485	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	167:e84263d55307	3486	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	167:e84263d55307	3487	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3488	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3489	*/
AnnaBridge	167:e84263d55307	3490	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3491	{
AnnaBridge	167:e84263d55307	3492	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	167:e84263d55307	3493	}
AnnaBridge	167:e84263d55307	3494
AnnaBridge	167:e84263d55307	3495	/**
AnnaBridge	167:e84263d55307	3496	* @brief Enable commutation interrupt (COMIE).
AnnaBridge	167:e84263d55307	3497	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
AnnaBridge	167:e84263d55307	3498	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3499	* @retval None
AnnaBridge	167:e84263d55307	3500	*/
AnnaBridge	167:e84263d55307	3501	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3502	{
AnnaBridge	167:e84263d55307	3503	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	167:e84263d55307	3504	}
AnnaBridge	167:e84263d55307	3505
AnnaBridge	167:e84263d55307	3506	/**
AnnaBridge	167:e84263d55307	3507	* @brief Disable commutation interrupt (COMIE).
AnnaBridge	167:e84263d55307	3508	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
AnnaBridge	167:e84263d55307	3509	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3510	* @retval None
AnnaBridge	167:e84263d55307	3511	*/
AnnaBridge	167:e84263d55307	3512	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3513	{
AnnaBridge	167:e84263d55307	3514	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	167:e84263d55307	3515	}
AnnaBridge	167:e84263d55307	3516
AnnaBridge	167:e84263d55307	3517	/**
AnnaBridge	167:e84263d55307	3518	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
AnnaBridge	167:e84263d55307	3519	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
AnnaBridge	167:e84263d55307	3520	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3521	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3522	*/
AnnaBridge	167:e84263d55307	3523	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3524	{
AnnaBridge	167:e84263d55307	3525	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
AnnaBridge	167:e84263d55307	3526	}
AnnaBridge	167:e84263d55307	3527
AnnaBridge	167:e84263d55307	3528	/**
AnnaBridge	167:e84263d55307	3529	* @brief Enable trigger interrupt (TIE).
AnnaBridge	167:e84263d55307	3530	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	167:e84263d55307	3531	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3532	* @retval None
AnnaBridge	167:e84263d55307	3533	*/
AnnaBridge	167:e84263d55307	3534	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3535	{
AnnaBridge	167:e84263d55307	3536	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	167:e84263d55307	3537	}
AnnaBridge	167:e84263d55307	3538
AnnaBridge	167:e84263d55307	3539	/**
AnnaBridge	167:e84263d55307	3540	* @brief Disable trigger interrupt (TIE).
AnnaBridge	167:e84263d55307	3541	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	167:e84263d55307	3542	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3543	* @retval None
AnnaBridge	167:e84263d55307	3544	*/
AnnaBridge	167:e84263d55307	3545	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3546	{
AnnaBridge	167:e84263d55307	3547	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	167:e84263d55307	3548	}
AnnaBridge	167:e84263d55307	3549
AnnaBridge	167:e84263d55307	3550	/**
AnnaBridge	167:e84263d55307	3551	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	167:e84263d55307	3552	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	167:e84263d55307	3553	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3554	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3555	*/
AnnaBridge	167:e84263d55307	3556	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3557	{
AnnaBridge	167:e84263d55307	3558	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	167:e84263d55307	3559	}
AnnaBridge	167:e84263d55307	3560
AnnaBridge	167:e84263d55307	3561	/**
AnnaBridge	167:e84263d55307	3562	* @brief Enable break interrupt (BIE).
AnnaBridge	167:e84263d55307	3563	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
AnnaBridge	167:e84263d55307	3564	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3565	* @retval None
AnnaBridge	167:e84263d55307	3566	*/
AnnaBridge	167:e84263d55307	3567	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3568	{
AnnaBridge	167:e84263d55307	3569	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	167:e84263d55307	3570	}
AnnaBridge	167:e84263d55307	3571
AnnaBridge	167:e84263d55307	3572	/**
AnnaBridge	167:e84263d55307	3573	* @brief Disable break interrupt (BIE).
AnnaBridge	167:e84263d55307	3574	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
AnnaBridge	167:e84263d55307	3575	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3576	* @retval None
AnnaBridge	167:e84263d55307	3577	*/
AnnaBridge	167:e84263d55307	3578	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3579	{
AnnaBridge	167:e84263d55307	3580	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	167:e84263d55307	3581	}
AnnaBridge	167:e84263d55307	3582
AnnaBridge	167:e84263d55307	3583	/**
AnnaBridge	167:e84263d55307	3584	* @brief Indicates whether the break interrupt (BIE) is enabled.
AnnaBridge	167:e84263d55307	3585	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
AnnaBridge	167:e84263d55307	3586	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3587	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3588	*/
AnnaBridge	167:e84263d55307	3589	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3590	{
AnnaBridge	167:e84263d55307	3591	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
AnnaBridge	167:e84263d55307	3592	}
AnnaBridge	167:e84263d55307	3593
AnnaBridge	167:e84263d55307	3594	/**
AnnaBridge	167:e84263d55307	3595	* @}
AnnaBridge	167:e84263d55307	3596	*/
AnnaBridge	167:e84263d55307	3597
AnnaBridge	167:e84263d55307	3598	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	167:e84263d55307	3599	* @{
AnnaBridge	167:e84263d55307	3600	*/
AnnaBridge	167:e84263d55307	3601	/**
AnnaBridge	167:e84263d55307	3602	* @brief Enable update DMA request (UDE).
AnnaBridge	167:e84263d55307	3603	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	167:e84263d55307	3604	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3605	* @retval None
AnnaBridge	167:e84263d55307	3606	*/
AnnaBridge	167:e84263d55307	3607	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3608	{
AnnaBridge	167:e84263d55307	3609	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	167:e84263d55307	3610	}
AnnaBridge	167:e84263d55307	3611
AnnaBridge	167:e84263d55307	3612	/**
AnnaBridge	167:e84263d55307	3613	* @brief Disable update DMA request (UDE).
AnnaBridge	167:e84263d55307	3614	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	167:e84263d55307	3615	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3616	* @retval None
AnnaBridge	167:e84263d55307	3617	*/
AnnaBridge	167:e84263d55307	3618	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3619	{
AnnaBridge	167:e84263d55307	3620	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	167:e84263d55307	3621	}
AnnaBridge	167:e84263d55307	3622
AnnaBridge	167:e84263d55307	3623	/**
AnnaBridge	167:e84263d55307	3624	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	167:e84263d55307	3625	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	167:e84263d55307	3626	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3627	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3628	*/
AnnaBridge	167:e84263d55307	3629	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3630	{
AnnaBridge	167:e84263d55307	3631	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	167:e84263d55307	3632	}
AnnaBridge	167:e84263d55307	3633
AnnaBridge	167:e84263d55307	3634	/**
AnnaBridge	167:e84263d55307	3635	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	167:e84263d55307	3636	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	167:e84263d55307	3637	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3638	* @retval None
AnnaBridge	167:e84263d55307	3639	*/
AnnaBridge	167:e84263d55307	3640	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3641	{
AnnaBridge	167:e84263d55307	3642	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	167:e84263d55307	3643	}
AnnaBridge	167:e84263d55307	3644
AnnaBridge	167:e84263d55307	3645	/**
AnnaBridge	167:e84263d55307	3646	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	167:e84263d55307	3647	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	167:e84263d55307	3648	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3649	* @retval None
AnnaBridge	167:e84263d55307	3650	*/
AnnaBridge	167:e84263d55307	3651	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3652	{
AnnaBridge	167:e84263d55307	3653	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	167:e84263d55307	3654	}
AnnaBridge	167:e84263d55307	3655
AnnaBridge	167:e84263d55307	3656	/**
AnnaBridge	167:e84263d55307	3657	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	167:e84263d55307	3658	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	167:e84263d55307	3659	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3660	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3661	*/
AnnaBridge	167:e84263d55307	3662	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3663	{
AnnaBridge	167:e84263d55307	3664	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	167:e84263d55307	3665	}
AnnaBridge	167:e84263d55307	3666
AnnaBridge	167:e84263d55307	3667	/**
AnnaBridge	167:e84263d55307	3668	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	167:e84263d55307	3669	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	167:e84263d55307	3670	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3671	* @retval None
AnnaBridge	167:e84263d55307	3672	*/
AnnaBridge	167:e84263d55307	3673	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3674	{
AnnaBridge	167:e84263d55307	3675	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	167:e84263d55307	3676	}
AnnaBridge	167:e84263d55307	3677
AnnaBridge	167:e84263d55307	3678	/**
AnnaBridge	167:e84263d55307	3679	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	167:e84263d55307	3680	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	167:e84263d55307	3681	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3682	* @retval None
AnnaBridge	167:e84263d55307	3683	*/
AnnaBridge	167:e84263d55307	3684	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3685	{
AnnaBridge	167:e84263d55307	3686	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	167:e84263d55307	3687	}
AnnaBridge	167:e84263d55307	3688
AnnaBridge	167:e84263d55307	3689	/**
AnnaBridge	167:e84263d55307	3690	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	167:e84263d55307	3691	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	167:e84263d55307	3692	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3693	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3694	*/
AnnaBridge	167:e84263d55307	3695	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3696	{
AnnaBridge	167:e84263d55307	3697	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	167:e84263d55307	3698	}
AnnaBridge	167:e84263d55307	3699
AnnaBridge	167:e84263d55307	3700	/**
AnnaBridge	167:e84263d55307	3701	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	167:e84263d55307	3702	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	167:e84263d55307	3703	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3704	* @retval None
AnnaBridge	167:e84263d55307	3705	*/
AnnaBridge	167:e84263d55307	3706	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3707	{
AnnaBridge	167:e84263d55307	3708	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	167:e84263d55307	3709	}
AnnaBridge	167:e84263d55307	3710
AnnaBridge	167:e84263d55307	3711	/**
AnnaBridge	167:e84263d55307	3712	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	167:e84263d55307	3713	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	167:e84263d55307	3714	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3715	* @retval None
AnnaBridge	167:e84263d55307	3716	*/
AnnaBridge	167:e84263d55307	3717	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3718	{
AnnaBridge	167:e84263d55307	3719	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	167:e84263d55307	3720	}
AnnaBridge	167:e84263d55307	3721
AnnaBridge	167:e84263d55307	3722	/**
AnnaBridge	167:e84263d55307	3723	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	167:e84263d55307	3724	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	167:e84263d55307	3725	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3726	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3727	*/
AnnaBridge	167:e84263d55307	3728	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3729	{
AnnaBridge	167:e84263d55307	3730	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	167:e84263d55307	3731	}
AnnaBridge	167:e84263d55307	3732
AnnaBridge	167:e84263d55307	3733	/**
AnnaBridge	167:e84263d55307	3734	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	167:e84263d55307	3735	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	167:e84263d55307	3736	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3737	* @retval None
AnnaBridge	167:e84263d55307	3738	*/
AnnaBridge	167:e84263d55307	3739	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3740	{
AnnaBridge	167:e84263d55307	3741	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	167:e84263d55307	3742	}
AnnaBridge	167:e84263d55307	3743
AnnaBridge	167:e84263d55307	3744	/**
AnnaBridge	167:e84263d55307	3745	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	167:e84263d55307	3746	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	167:e84263d55307	3747	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3748	* @retval None
AnnaBridge	167:e84263d55307	3749	*/
AnnaBridge	167:e84263d55307	3750	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3751	{
AnnaBridge	167:e84263d55307	3752	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	167:e84263d55307	3753	}
AnnaBridge	167:e84263d55307	3754
AnnaBridge	167:e84263d55307	3755	/**
AnnaBridge	167:e84263d55307	3756	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	167:e84263d55307	3757	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	167:e84263d55307	3758	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3759	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3760	*/
AnnaBridge	167:e84263d55307	3761	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3762	{
AnnaBridge	167:e84263d55307	3763	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	167:e84263d55307	3764	}
AnnaBridge	167:e84263d55307	3765
AnnaBridge	167:e84263d55307	3766	/**
AnnaBridge	167:e84263d55307	3767	* @brief Enable commutation DMA request (COMDE).
AnnaBridge	167:e84263d55307	3768	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
AnnaBridge	167:e84263d55307	3769	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3770	* @retval None
AnnaBridge	167:e84263d55307	3771	*/
AnnaBridge	167:e84263d55307	3772	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3773	{
AnnaBridge	167:e84263d55307	3774	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	167:e84263d55307	3775	}
AnnaBridge	167:e84263d55307	3776
AnnaBridge	167:e84263d55307	3777	/**
AnnaBridge	167:e84263d55307	3778	* @brief Disable commutation DMA request (COMDE).
AnnaBridge	167:e84263d55307	3779	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
AnnaBridge	167:e84263d55307	3780	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3781	* @retval None
AnnaBridge	167:e84263d55307	3782	*/
AnnaBridge	167:e84263d55307	3783	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3784	{
AnnaBridge	167:e84263d55307	3785	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	167:e84263d55307	3786	}
AnnaBridge	167:e84263d55307	3787
AnnaBridge	167:e84263d55307	3788	/**
AnnaBridge	167:e84263d55307	3789	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
AnnaBridge	167:e84263d55307	3790	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
AnnaBridge	167:e84263d55307	3791	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3792	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3793	*/
AnnaBridge	167:e84263d55307	3794	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3795	{
AnnaBridge	167:e84263d55307	3796	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
AnnaBridge	167:e84263d55307	3797	}
AnnaBridge	167:e84263d55307	3798
AnnaBridge	167:e84263d55307	3799	/**
AnnaBridge	167:e84263d55307	3800	* @brief Enable trigger interrupt (TDE).
AnnaBridge	167:e84263d55307	3801	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	167:e84263d55307	3802	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3803	* @retval None
AnnaBridge	167:e84263d55307	3804	*/
AnnaBridge	167:e84263d55307	3805	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3806	{
AnnaBridge	167:e84263d55307	3807	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	167:e84263d55307	3808	}
AnnaBridge	167:e84263d55307	3809
AnnaBridge	167:e84263d55307	3810	/**
AnnaBridge	167:e84263d55307	3811	* @brief Disable trigger interrupt (TDE).
AnnaBridge	167:e84263d55307	3812	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	167:e84263d55307	3813	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3814	* @retval None
AnnaBridge	167:e84263d55307	3815	*/
AnnaBridge	167:e84263d55307	3816	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3817	{
AnnaBridge	167:e84263d55307	3818	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	167:e84263d55307	3819	}
AnnaBridge	167:e84263d55307	3820
AnnaBridge	167:e84263d55307	3821	/**
AnnaBridge	167:e84263d55307	3822	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	167:e84263d55307	3823	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	167:e84263d55307	3824	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3825	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	3826	*/
AnnaBridge	167:e84263d55307	3827	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3828	{
AnnaBridge	167:e84263d55307	3829	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	167:e84263d55307	3830	}
AnnaBridge	167:e84263d55307	3831
AnnaBridge	167:e84263d55307	3832	/**
AnnaBridge	167:e84263d55307	3833	* @}
AnnaBridge	167:e84263d55307	3834	*/
AnnaBridge	167:e84263d55307	3835
AnnaBridge	167:e84263d55307	3836	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	167:e84263d55307	3837	* @{
AnnaBridge	167:e84263d55307	3838	*/
AnnaBridge	167:e84263d55307	3839	/**
AnnaBridge	167:e84263d55307	3840	* @brief Generate an update event.
AnnaBridge	167:e84263d55307	3841	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	167:e84263d55307	3842	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3843	* @retval None
AnnaBridge	167:e84263d55307	3844	*/
AnnaBridge	167:e84263d55307	3845	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3846	{
AnnaBridge	167:e84263d55307	3847	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	167:e84263d55307	3848	}
AnnaBridge	167:e84263d55307	3849
AnnaBridge	167:e84263d55307	3850	/**
AnnaBridge	167:e84263d55307	3851	* @brief Generate Capture/Compare 1 event.
AnnaBridge	167:e84263d55307	3852	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	167:e84263d55307	3853	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3854	* @retval None
AnnaBridge	167:e84263d55307	3855	*/
AnnaBridge	167:e84263d55307	3856	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3857	{
AnnaBridge	167:e84263d55307	3858	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	167:e84263d55307	3859	}
AnnaBridge	167:e84263d55307	3860
AnnaBridge	167:e84263d55307	3861	/**
AnnaBridge	167:e84263d55307	3862	* @brief Generate Capture/Compare 2 event.
AnnaBridge	167:e84263d55307	3863	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	167:e84263d55307	3864	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3865	* @retval None
AnnaBridge	167:e84263d55307	3866	*/
AnnaBridge	167:e84263d55307	3867	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3868	{
AnnaBridge	167:e84263d55307	3869	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	167:e84263d55307	3870	}
AnnaBridge	167:e84263d55307	3871
AnnaBridge	167:e84263d55307	3872	/**
AnnaBridge	167:e84263d55307	3873	* @brief Generate Capture/Compare 3 event.
AnnaBridge	167:e84263d55307	3874	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	167:e84263d55307	3875	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3876	* @retval None
AnnaBridge	167:e84263d55307	3877	*/
AnnaBridge	167:e84263d55307	3878	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3879	{
AnnaBridge	167:e84263d55307	3880	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	167:e84263d55307	3881	}
AnnaBridge	167:e84263d55307	3882
AnnaBridge	167:e84263d55307	3883	/**
AnnaBridge	167:e84263d55307	3884	* @brief Generate Capture/Compare 4 event.
AnnaBridge	167:e84263d55307	3885	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	167:e84263d55307	3886	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3887	* @retval None
AnnaBridge	167:e84263d55307	3888	*/
AnnaBridge	167:e84263d55307	3889	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3890	{
AnnaBridge	167:e84263d55307	3891	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	167:e84263d55307	3892	}
AnnaBridge	167:e84263d55307	3893
AnnaBridge	167:e84263d55307	3894	/**
AnnaBridge	167:e84263d55307	3895	* @brief Generate commutation event.
AnnaBridge	167:e84263d55307	3896	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
AnnaBridge	167:e84263d55307	3897	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3898	* @retval None
AnnaBridge	167:e84263d55307	3899	*/
AnnaBridge	167:e84263d55307	3900	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3901	{
AnnaBridge	167:e84263d55307	3902	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
AnnaBridge	167:e84263d55307	3903	}
AnnaBridge	167:e84263d55307	3904
AnnaBridge	167:e84263d55307	3905	/**
AnnaBridge	167:e84263d55307	3906	* @brief Generate trigger event.
AnnaBridge	167:e84263d55307	3907	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	167:e84263d55307	3908	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3909	* @retval None
AnnaBridge	167:e84263d55307	3910	*/
AnnaBridge	167:e84263d55307	3911	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3912	{
AnnaBridge	167:e84263d55307	3913	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	167:e84263d55307	3914	}
AnnaBridge	167:e84263d55307	3915
AnnaBridge	167:e84263d55307	3916	/**
AnnaBridge	167:e84263d55307	3917	* @brief Generate break event.
AnnaBridge	167:e84263d55307	3918	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
AnnaBridge	167:e84263d55307	3919	* @param TIMx Timer instance
AnnaBridge	167:e84263d55307	3920	* @retval None
AnnaBridge	167:e84263d55307	3921	*/
AnnaBridge	167:e84263d55307	3922	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
AnnaBridge	167:e84263d55307	3923	{
AnnaBridge	167:e84263d55307	3924	SET_BIT(TIMx->EGR, TIM_EGR_BG);
AnnaBridge	167:e84263d55307	3925	}
AnnaBridge	167:e84263d55307	3926
AnnaBridge	167:e84263d55307	3927	/**
AnnaBridge	167:e84263d55307	3928	* @}
AnnaBridge	167:e84263d55307	3929	*/
AnnaBridge	167:e84263d55307	3930
AnnaBridge	167:e84263d55307	3931	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	3932	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	167:e84263d55307	3933	* @{
AnnaBridge	167:e84263d55307	3934	*/
AnnaBridge	167:e84263d55307	3935
AnnaBridge	167:e84263d55307	3936	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	167:e84263d55307	3937	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	167:e84263d55307	3938	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	167:e84263d55307	3939	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	167:e84263d55307	3940	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	167:e84263d55307	3941	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	167:e84263d55307	3942	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	167:e84263d55307	3943	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	167:e84263d55307	3944	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	167:e84263d55307	3945	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
AnnaBridge	167:e84263d55307	3946	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
AnnaBridge	167:e84263d55307	3947	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
AnnaBridge	167:e84263d55307	3948	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
AnnaBridge	167:e84263d55307	3949	/**
AnnaBridge	167:e84263d55307	3950	* @}
AnnaBridge	167:e84263d55307	3951	*/
AnnaBridge	167:e84263d55307	3952	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	3953
AnnaBridge	167:e84263d55307	3954	/**
AnnaBridge	167:e84263d55307	3955	* @}
AnnaBridge	167:e84263d55307	3956	*/
AnnaBridge	167:e84263d55307	3957
AnnaBridge	167:e84263d55307	3958	/**
AnnaBridge	167:e84263d55307	3959	* @}
AnnaBridge	167:e84263d55307	3960	*/
AnnaBridge	167:e84263d55307	3961
AnnaBridge	167:e84263d55307	3962	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 */
AnnaBridge	167:e84263d55307	3963
AnnaBridge	167:e84263d55307	3964	/**
AnnaBridge	167:e84263d55307	3965	* @}
AnnaBridge	167:e84263d55307	3966	*/
AnnaBridge	167:e84263d55307	3967
AnnaBridge	167:e84263d55307	3968	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	3969	}
AnnaBridge	167:e84263d55307	3970	#endif
AnnaBridge	167:e84263d55307	3971
AnnaBridge	167:e84263d55307	3972	#endif /* __STM32F2xx_LL_TIM_H */
AnnaBridge	167:e84263d55307	3973	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/