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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_tim.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:e84263d55307 1 /**
AnnaBridge 167:e84263d55307 2 ******************************************************************************
AnnaBridge 167:e84263d55307 3 * @file stm32f2xx_ll_tim.c
AnnaBridge 167:e84263d55307 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
AnnaBridge 167:e84263d55307 7 * @brief TIM LL module driver.
AnnaBridge 167:e84263d55307 8 ******************************************************************************
AnnaBridge 167:e84263d55307 9 * @attention
AnnaBridge 167:e84263d55307 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 167:e84263d55307 12 *
AnnaBridge 167:e84263d55307 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 167:e84263d55307 14 * are permitted provided that the following conditions are met:
AnnaBridge 167:e84263d55307 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 167:e84263d55307 16 * this list of conditions and the following disclaimer.
AnnaBridge 167:e84263d55307 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 167:e84263d55307 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 167:e84263d55307 19 * and/or other materials provided with the distribution.
AnnaBridge 167:e84263d55307 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 167:e84263d55307 21 * may be used to endorse or promote products derived from this software
AnnaBridge 167:e84263d55307 22 * without specific prior written permission.
AnnaBridge 167:e84263d55307 23 *
AnnaBridge 167:e84263d55307 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 167:e84263d55307 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 167:e84263d55307 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 167:e84263d55307 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 167:e84263d55307 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 167:e84263d55307 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 167:e84263d55307 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 167:e84263d55307 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 167:e84263d55307 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 167:e84263d55307 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 167:e84263d55307 34 *
AnnaBridge 167:e84263d55307 35 ******************************************************************************
AnnaBridge 167:e84263d55307 36 */
AnnaBridge 167:e84263d55307 37 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 167:e84263d55307 38
AnnaBridge 167:e84263d55307 39 /* Includes ------------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 40 #include "stm32f2xx_ll_tim.h"
AnnaBridge 167:e84263d55307 41 #include "stm32f2xx_ll_bus.h"
AnnaBridge 167:e84263d55307 42
AnnaBridge 167:e84263d55307 43 #ifdef USE_FULL_ASSERT
AnnaBridge 167:e84263d55307 44 #include "stm32_assert.h"
AnnaBridge 167:e84263d55307 45 #else
AnnaBridge 167:e84263d55307 46 #define assert_param(expr) ((void)0U)
AnnaBridge 167:e84263d55307 47 #endif
AnnaBridge 167:e84263d55307 48
AnnaBridge 167:e84263d55307 49 /** @addtogroup STM32F2xx_LL_Driver
AnnaBridge 167:e84263d55307 50 * @{
AnnaBridge 167:e84263d55307 51 */
AnnaBridge 167:e84263d55307 52
AnnaBridge 167:e84263d55307 53 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
AnnaBridge 167:e84263d55307 54
AnnaBridge 167:e84263d55307 55 /** @addtogroup TIM_LL
AnnaBridge 167:e84263d55307 56 * @{
AnnaBridge 167:e84263d55307 57 */
AnnaBridge 167:e84263d55307 58
AnnaBridge 167:e84263d55307 59 /* Private types -------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 60 /* Private variables ---------------------------------------------------------*/
AnnaBridge 167:e84263d55307 61 /* Private constants ---------------------------------------------------------*/
AnnaBridge 167:e84263d55307 62 /* Private macros ------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 63 /** @addtogroup TIM_LL_Private_Macros
AnnaBridge 167:e84263d55307 64 * @{
AnnaBridge 167:e84263d55307 65 */
AnnaBridge 167:e84263d55307 66 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
AnnaBridge 167:e84263d55307 67 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
AnnaBridge 167:e84263d55307 68 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
AnnaBridge 167:e84263d55307 69 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
AnnaBridge 167:e84263d55307 70 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
AnnaBridge 167:e84263d55307 71
AnnaBridge 167:e84263d55307 72 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
AnnaBridge 167:e84263d55307 73 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
AnnaBridge 167:e84263d55307 74 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
AnnaBridge 167:e84263d55307 75
AnnaBridge 167:e84263d55307 76 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
AnnaBridge 167:e84263d55307 77 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
AnnaBridge 167:e84263d55307 78 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
AnnaBridge 167:e84263d55307 79 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
AnnaBridge 167:e84263d55307 80 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
AnnaBridge 167:e84263d55307 81 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
AnnaBridge 167:e84263d55307 82 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
AnnaBridge 167:e84263d55307 83 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
AnnaBridge 167:e84263d55307 84
AnnaBridge 167:e84263d55307 85 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
AnnaBridge 167:e84263d55307 86 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
AnnaBridge 167:e84263d55307 87
AnnaBridge 167:e84263d55307 88 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
AnnaBridge 167:e84263d55307 89 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
AnnaBridge 167:e84263d55307 90
AnnaBridge 167:e84263d55307 91 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
AnnaBridge 167:e84263d55307 92 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
AnnaBridge 167:e84263d55307 93
AnnaBridge 167:e84263d55307 94 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
AnnaBridge 167:e84263d55307 95 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
AnnaBridge 167:e84263d55307 96 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
AnnaBridge 167:e84263d55307 97
AnnaBridge 167:e84263d55307 98 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
AnnaBridge 167:e84263d55307 99 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
AnnaBridge 167:e84263d55307 100 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
AnnaBridge 167:e84263d55307 101 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
AnnaBridge 167:e84263d55307 102
AnnaBridge 167:e84263d55307 103 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
AnnaBridge 167:e84263d55307 104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
AnnaBridge 167:e84263d55307 105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
AnnaBridge 167:e84263d55307 106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
AnnaBridge 167:e84263d55307 107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
AnnaBridge 167:e84263d55307 108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
AnnaBridge 167:e84263d55307 109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
AnnaBridge 167:e84263d55307 110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
AnnaBridge 167:e84263d55307 111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
AnnaBridge 167:e84263d55307 112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
AnnaBridge 167:e84263d55307 113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
AnnaBridge 167:e84263d55307 114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
AnnaBridge 167:e84263d55307 115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
AnnaBridge 167:e84263d55307 116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
AnnaBridge 167:e84263d55307 117 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
AnnaBridge 167:e84263d55307 118 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
AnnaBridge 167:e84263d55307 119
AnnaBridge 167:e84263d55307 120 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
AnnaBridge 167:e84263d55307 121 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
AnnaBridge 167:e84263d55307 122 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
AnnaBridge 167:e84263d55307 123
AnnaBridge 167:e84263d55307 124 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
AnnaBridge 167:e84263d55307 125 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
AnnaBridge 167:e84263d55307 126 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
AnnaBridge 167:e84263d55307 127
AnnaBridge 167:e84263d55307 128 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
AnnaBridge 167:e84263d55307 129 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
AnnaBridge 167:e84263d55307 130
AnnaBridge 167:e84263d55307 131 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
AnnaBridge 167:e84263d55307 132 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
AnnaBridge 167:e84263d55307 133
AnnaBridge 167:e84263d55307 134 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
AnnaBridge 167:e84263d55307 135 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
AnnaBridge 167:e84263d55307 136
AnnaBridge 167:e84263d55307 137 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
AnnaBridge 167:e84263d55307 138 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
AnnaBridge 167:e84263d55307 139 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
AnnaBridge 167:e84263d55307 140 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
AnnaBridge 167:e84263d55307 141
AnnaBridge 167:e84263d55307 142 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
AnnaBridge 167:e84263d55307 143 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
AnnaBridge 167:e84263d55307 144
AnnaBridge 167:e84263d55307 145 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
AnnaBridge 167:e84263d55307 146 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
AnnaBridge 167:e84263d55307 147
AnnaBridge 167:e84263d55307 148 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
AnnaBridge 167:e84263d55307 149 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
AnnaBridge 167:e84263d55307 150 /**
AnnaBridge 167:e84263d55307 151 * @}
AnnaBridge 167:e84263d55307 152 */
AnnaBridge 167:e84263d55307 153
AnnaBridge 167:e84263d55307 154
AnnaBridge 167:e84263d55307 155 /* Private function prototypes -----------------------------------------------*/
AnnaBridge 167:e84263d55307 156 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
AnnaBridge 167:e84263d55307 157 * @{
AnnaBridge 167:e84263d55307 158 */
AnnaBridge 167:e84263d55307 159 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
AnnaBridge 167:e84263d55307 160 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
AnnaBridge 167:e84263d55307 161 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
AnnaBridge 167:e84263d55307 162 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
AnnaBridge 167:e84263d55307 163 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge 167:e84263d55307 164 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge 167:e84263d55307 165 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge 167:e84263d55307 166 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge 167:e84263d55307 167 /**
AnnaBridge 167:e84263d55307 168 * @}
AnnaBridge 167:e84263d55307 169 */
AnnaBridge 167:e84263d55307 170
AnnaBridge 167:e84263d55307 171 /* Exported functions --------------------------------------------------------*/
AnnaBridge 167:e84263d55307 172 /** @addtogroup TIM_LL_Exported_Functions
AnnaBridge 167:e84263d55307 173 * @{
AnnaBridge 167:e84263d55307 174 */
AnnaBridge 167:e84263d55307 175
AnnaBridge 167:e84263d55307 176 /** @addtogroup TIM_LL_EF_Init
AnnaBridge 167:e84263d55307 177 * @{
AnnaBridge 167:e84263d55307 178 */
AnnaBridge 167:e84263d55307 179
AnnaBridge 167:e84263d55307 180 /**
AnnaBridge 167:e84263d55307 181 * @brief Set TIMx registers to their reset values.
AnnaBridge 167:e84263d55307 182 * @param TIMx Timer instance
AnnaBridge 167:e84263d55307 183 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 184 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 185 * - ERROR: invalid TIMx instance
AnnaBridge 167:e84263d55307 186 */
AnnaBridge 167:e84263d55307 187 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
AnnaBridge 167:e84263d55307 188 {
AnnaBridge 167:e84263d55307 189 ErrorStatus result = SUCCESS;
AnnaBridge 167:e84263d55307 190
AnnaBridge 167:e84263d55307 191 /* Check the parameters */
AnnaBridge 167:e84263d55307 192 assert_param(IS_TIM_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 193
AnnaBridge 167:e84263d55307 194 if (TIMx == TIM1)
AnnaBridge 167:e84263d55307 195 {
AnnaBridge 167:e84263d55307 196 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
AnnaBridge 167:e84263d55307 197 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
AnnaBridge 167:e84263d55307 198 }
AnnaBridge 167:e84263d55307 199 #if defined(TIM2)
AnnaBridge 167:e84263d55307 200 else if (TIMx == TIM2)
AnnaBridge 167:e84263d55307 201 {
AnnaBridge 167:e84263d55307 202 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
AnnaBridge 167:e84263d55307 203 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
AnnaBridge 167:e84263d55307 204 }
AnnaBridge 167:e84263d55307 205 #endif
AnnaBridge 167:e84263d55307 206 #if defined(TIM3)
AnnaBridge 167:e84263d55307 207 else if (TIMx == TIM3)
AnnaBridge 167:e84263d55307 208 {
AnnaBridge 167:e84263d55307 209 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
AnnaBridge 167:e84263d55307 210 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
AnnaBridge 167:e84263d55307 211 }
AnnaBridge 167:e84263d55307 212 #endif
AnnaBridge 167:e84263d55307 213 #if defined(TIM4)
AnnaBridge 167:e84263d55307 214 else if (TIMx == TIM4)
AnnaBridge 167:e84263d55307 215 {
AnnaBridge 167:e84263d55307 216 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
AnnaBridge 167:e84263d55307 217 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
AnnaBridge 167:e84263d55307 218 }
AnnaBridge 167:e84263d55307 219 #endif
AnnaBridge 167:e84263d55307 220 #if defined(TIM5)
AnnaBridge 167:e84263d55307 221 else if (TIMx == TIM5)
AnnaBridge 167:e84263d55307 222 {
AnnaBridge 167:e84263d55307 223 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
AnnaBridge 167:e84263d55307 224 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
AnnaBridge 167:e84263d55307 225 }
AnnaBridge 167:e84263d55307 226 #endif
AnnaBridge 167:e84263d55307 227 #if defined(TIM6)
AnnaBridge 167:e84263d55307 228 else if (TIMx == TIM6)
AnnaBridge 167:e84263d55307 229 {
AnnaBridge 167:e84263d55307 230 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
AnnaBridge 167:e84263d55307 231 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
AnnaBridge 167:e84263d55307 232 }
AnnaBridge 167:e84263d55307 233 #endif
AnnaBridge 167:e84263d55307 234 #if defined (TIM7)
AnnaBridge 167:e84263d55307 235 else if (TIMx == TIM7)
AnnaBridge 167:e84263d55307 236 {
AnnaBridge 167:e84263d55307 237 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
AnnaBridge 167:e84263d55307 238 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
AnnaBridge 167:e84263d55307 239 }
AnnaBridge 167:e84263d55307 240 #endif
AnnaBridge 167:e84263d55307 241 #if defined(TIM8)
AnnaBridge 167:e84263d55307 242 else if (TIMx == TIM8)
AnnaBridge 167:e84263d55307 243 {
AnnaBridge 167:e84263d55307 244 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
AnnaBridge 167:e84263d55307 245 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
AnnaBridge 167:e84263d55307 246 }
AnnaBridge 167:e84263d55307 247 #endif
AnnaBridge 167:e84263d55307 248 #if defined(TIM9)
AnnaBridge 167:e84263d55307 249 else if (TIMx == TIM9)
AnnaBridge 167:e84263d55307 250 {
AnnaBridge 167:e84263d55307 251 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
AnnaBridge 167:e84263d55307 252 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
AnnaBridge 167:e84263d55307 253 }
AnnaBridge 167:e84263d55307 254 #endif
AnnaBridge 167:e84263d55307 255 #if defined(TIM10)
AnnaBridge 167:e84263d55307 256 else if (TIMx == TIM10)
AnnaBridge 167:e84263d55307 257 {
AnnaBridge 167:e84263d55307 258 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
AnnaBridge 167:e84263d55307 259 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
AnnaBridge 167:e84263d55307 260 }
AnnaBridge 167:e84263d55307 261 #endif
AnnaBridge 167:e84263d55307 262 #if defined(TIM11)
AnnaBridge 167:e84263d55307 263 else if (TIMx == TIM11)
AnnaBridge 167:e84263d55307 264 {
AnnaBridge 167:e84263d55307 265 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
AnnaBridge 167:e84263d55307 266 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
AnnaBridge 167:e84263d55307 267 }
AnnaBridge 167:e84263d55307 268 #endif
AnnaBridge 167:e84263d55307 269 #if defined(TIM12)
AnnaBridge 167:e84263d55307 270 else if (TIMx == TIM12)
AnnaBridge 167:e84263d55307 271 {
AnnaBridge 167:e84263d55307 272 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
AnnaBridge 167:e84263d55307 273 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
AnnaBridge 167:e84263d55307 274 }
AnnaBridge 167:e84263d55307 275 #endif
AnnaBridge 167:e84263d55307 276 #if defined(TIM13)
AnnaBridge 167:e84263d55307 277 else if (TIMx == TIM13)
AnnaBridge 167:e84263d55307 278 {
AnnaBridge 167:e84263d55307 279 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
AnnaBridge 167:e84263d55307 280 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
AnnaBridge 167:e84263d55307 281 }
AnnaBridge 167:e84263d55307 282 #endif
AnnaBridge 167:e84263d55307 283 #if defined(TIM14)
AnnaBridge 167:e84263d55307 284 else if (TIMx == TIM14)
AnnaBridge 167:e84263d55307 285 {
AnnaBridge 167:e84263d55307 286 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
AnnaBridge 167:e84263d55307 287 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
AnnaBridge 167:e84263d55307 288 }
AnnaBridge 167:e84263d55307 289 #endif
AnnaBridge 167:e84263d55307 290 else
AnnaBridge 167:e84263d55307 291 {
AnnaBridge 167:e84263d55307 292 result = ERROR;
AnnaBridge 167:e84263d55307 293 }
AnnaBridge 167:e84263d55307 294
AnnaBridge 167:e84263d55307 295 return result;
AnnaBridge 167:e84263d55307 296 }
AnnaBridge 167:e84263d55307 297
AnnaBridge 167:e84263d55307 298 /**
AnnaBridge 167:e84263d55307 299 * @brief Set the fields of the time base unit configuration data structure
AnnaBridge 167:e84263d55307 300 * to their default values.
AnnaBridge 167:e84263d55307 301 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
AnnaBridge 167:e84263d55307 302 * @retval None
AnnaBridge 167:e84263d55307 303 */
AnnaBridge 167:e84263d55307 304 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
AnnaBridge 167:e84263d55307 305 {
AnnaBridge 167:e84263d55307 306 /* Set the default configuration */
AnnaBridge 167:e84263d55307 307 TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
AnnaBridge 167:e84263d55307 308 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
AnnaBridge 167:e84263d55307 309 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
AnnaBridge 167:e84263d55307 310 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
AnnaBridge 167:e84263d55307 311 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
AnnaBridge 167:e84263d55307 312 }
AnnaBridge 167:e84263d55307 313
AnnaBridge 167:e84263d55307 314 /**
AnnaBridge 167:e84263d55307 315 * @brief Configure the TIMx time base unit.
AnnaBridge 167:e84263d55307 316 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 317 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
AnnaBridge 167:e84263d55307 318 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 319 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 320 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 321 */
AnnaBridge 167:e84263d55307 322 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
AnnaBridge 167:e84263d55307 323 {
AnnaBridge 167:e84263d55307 324 uint32_t tmpcr1 = 0U;
AnnaBridge 167:e84263d55307 325
AnnaBridge 167:e84263d55307 326 /* Check the parameters */
AnnaBridge 167:e84263d55307 327 assert_param(IS_TIM_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 328 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
AnnaBridge 167:e84263d55307 329 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
AnnaBridge 167:e84263d55307 330
AnnaBridge 167:e84263d55307 331 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
AnnaBridge 167:e84263d55307 332
AnnaBridge 167:e84263d55307 333 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
AnnaBridge 167:e84263d55307 334 {
AnnaBridge 167:e84263d55307 335 /* Select the Counter Mode */
AnnaBridge 167:e84263d55307 336 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
AnnaBridge 167:e84263d55307 337 }
AnnaBridge 167:e84263d55307 338
AnnaBridge 167:e84263d55307 339 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
AnnaBridge 167:e84263d55307 340 {
AnnaBridge 167:e84263d55307 341 /* Set the clock division */
AnnaBridge 167:e84263d55307 342 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
AnnaBridge 167:e84263d55307 343 }
AnnaBridge 167:e84263d55307 344
AnnaBridge 167:e84263d55307 345 /* Write to TIMx CR1 */
AnnaBridge 167:e84263d55307 346 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
AnnaBridge 167:e84263d55307 347
AnnaBridge 167:e84263d55307 348 /* Set the Autoreload value */
AnnaBridge 167:e84263d55307 349 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
AnnaBridge 167:e84263d55307 350
AnnaBridge 167:e84263d55307 351 /* Set the Prescaler value */
AnnaBridge 167:e84263d55307 352 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
AnnaBridge 167:e84263d55307 353
AnnaBridge 167:e84263d55307 354 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
AnnaBridge 167:e84263d55307 355 {
AnnaBridge 167:e84263d55307 356 /* Set the Repetition Counter value */
AnnaBridge 167:e84263d55307 357 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
AnnaBridge 167:e84263d55307 358 }
AnnaBridge 167:e84263d55307 359
AnnaBridge 167:e84263d55307 360 /* Generate an update event to reload the Prescaler
AnnaBridge 167:e84263d55307 361 and the repetition counter value (if applicable) immediately */
AnnaBridge 167:e84263d55307 362 LL_TIM_GenerateEvent_UPDATE(TIMx);
AnnaBridge 167:e84263d55307 363
AnnaBridge 167:e84263d55307 364 return SUCCESS;
AnnaBridge 167:e84263d55307 365 }
AnnaBridge 167:e84263d55307 366
AnnaBridge 167:e84263d55307 367 /**
AnnaBridge 167:e84263d55307 368 * @brief Set the fields of the TIMx output channel configuration data
AnnaBridge 167:e84263d55307 369 * structure to their default values.
AnnaBridge 167:e84263d55307 370 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
AnnaBridge 167:e84263d55307 371 * @retval None
AnnaBridge 167:e84263d55307 372 */
AnnaBridge 167:e84263d55307 373 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
AnnaBridge 167:e84263d55307 374 {
AnnaBridge 167:e84263d55307 375 /* Set the default configuration */
AnnaBridge 167:e84263d55307 376 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
AnnaBridge 167:e84263d55307 377 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
AnnaBridge 167:e84263d55307 378 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
AnnaBridge 167:e84263d55307 379 TIM_OC_InitStruct->CompareValue = 0x00000000U;
AnnaBridge 167:e84263d55307 380 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
AnnaBridge 167:e84263d55307 381 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
AnnaBridge 167:e84263d55307 382 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
AnnaBridge 167:e84263d55307 383 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
AnnaBridge 167:e84263d55307 384 }
AnnaBridge 167:e84263d55307 385
AnnaBridge 167:e84263d55307 386 /**
AnnaBridge 167:e84263d55307 387 * @brief Configure the TIMx output channel.
AnnaBridge 167:e84263d55307 388 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 389 * @param Channel This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 390 * @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge 167:e84263d55307 391 * @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge 167:e84263d55307 392 * @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge 167:e84263d55307 393 * @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge 167:e84263d55307 394 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
AnnaBridge 167:e84263d55307 395 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 396 * - SUCCESS: TIMx output channel is initialized
AnnaBridge 167:e84263d55307 397 * - ERROR: TIMx output channel is not initialized
AnnaBridge 167:e84263d55307 398 */
AnnaBridge 167:e84263d55307 399 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
AnnaBridge 167:e84263d55307 400 {
AnnaBridge 167:e84263d55307 401 ErrorStatus result = ERROR;
AnnaBridge 167:e84263d55307 402
AnnaBridge 167:e84263d55307 403 switch (Channel)
AnnaBridge 167:e84263d55307 404 {
AnnaBridge 167:e84263d55307 405 case LL_TIM_CHANNEL_CH1:
AnnaBridge 167:e84263d55307 406 result = OC1Config(TIMx, TIM_OC_InitStruct);
AnnaBridge 167:e84263d55307 407 break;
AnnaBridge 167:e84263d55307 408 case LL_TIM_CHANNEL_CH2:
AnnaBridge 167:e84263d55307 409 result = OC2Config(TIMx, TIM_OC_InitStruct);
AnnaBridge 167:e84263d55307 410 break;
AnnaBridge 167:e84263d55307 411 case LL_TIM_CHANNEL_CH3:
AnnaBridge 167:e84263d55307 412 result = OC3Config(TIMx, TIM_OC_InitStruct);
AnnaBridge 167:e84263d55307 413 break;
AnnaBridge 167:e84263d55307 414 case LL_TIM_CHANNEL_CH4:
AnnaBridge 167:e84263d55307 415 result = OC4Config(TIMx, TIM_OC_InitStruct);
AnnaBridge 167:e84263d55307 416 break;
AnnaBridge 167:e84263d55307 417 default:
AnnaBridge 167:e84263d55307 418 break;
AnnaBridge 167:e84263d55307 419 }
AnnaBridge 167:e84263d55307 420
AnnaBridge 167:e84263d55307 421 return result;
AnnaBridge 167:e84263d55307 422 }
AnnaBridge 167:e84263d55307 423
AnnaBridge 167:e84263d55307 424 /**
AnnaBridge 167:e84263d55307 425 * @brief Set the fields of the TIMx input channel configuration data
AnnaBridge 167:e84263d55307 426 * structure to their default values.
AnnaBridge 167:e84263d55307 427 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
AnnaBridge 167:e84263d55307 428 * @retval None
AnnaBridge 167:e84263d55307 429 */
AnnaBridge 167:e84263d55307 430 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
AnnaBridge 167:e84263d55307 431 {
AnnaBridge 167:e84263d55307 432 /* Set the default configuration */
AnnaBridge 167:e84263d55307 433 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
AnnaBridge 167:e84263d55307 434 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
AnnaBridge 167:e84263d55307 435 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
AnnaBridge 167:e84263d55307 436 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
AnnaBridge 167:e84263d55307 437 }
AnnaBridge 167:e84263d55307 438
AnnaBridge 167:e84263d55307 439 /**
AnnaBridge 167:e84263d55307 440 * @brief Configure the TIMx input channel.
AnnaBridge 167:e84263d55307 441 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 442 * @param Channel This parameter can be one of the following values:
AnnaBridge 167:e84263d55307 443 * @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge 167:e84263d55307 444 * @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge 167:e84263d55307 445 * @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge 167:e84263d55307 446 * @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge 167:e84263d55307 447 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
AnnaBridge 167:e84263d55307 448 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 449 * - SUCCESS: TIMx output channel is initialized
AnnaBridge 167:e84263d55307 450 * - ERROR: TIMx output channel is not initialized
AnnaBridge 167:e84263d55307 451 */
AnnaBridge 167:e84263d55307 452 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
AnnaBridge 167:e84263d55307 453 {
AnnaBridge 167:e84263d55307 454 ErrorStatus result = ERROR;
AnnaBridge 167:e84263d55307 455
AnnaBridge 167:e84263d55307 456 switch (Channel)
AnnaBridge 167:e84263d55307 457 {
AnnaBridge 167:e84263d55307 458 case LL_TIM_CHANNEL_CH1:
AnnaBridge 167:e84263d55307 459 result = IC1Config(TIMx, TIM_IC_InitStruct);
AnnaBridge 167:e84263d55307 460 break;
AnnaBridge 167:e84263d55307 461 case LL_TIM_CHANNEL_CH2:
AnnaBridge 167:e84263d55307 462 result = IC2Config(TIMx, TIM_IC_InitStruct);
AnnaBridge 167:e84263d55307 463 break;
AnnaBridge 167:e84263d55307 464 case LL_TIM_CHANNEL_CH3:
AnnaBridge 167:e84263d55307 465 result = IC3Config(TIMx, TIM_IC_InitStruct);
AnnaBridge 167:e84263d55307 466 break;
AnnaBridge 167:e84263d55307 467 case LL_TIM_CHANNEL_CH4:
AnnaBridge 167:e84263d55307 468 result = IC4Config(TIMx, TIM_IC_InitStruct);
AnnaBridge 167:e84263d55307 469 break;
AnnaBridge 167:e84263d55307 470 default:
AnnaBridge 167:e84263d55307 471 break;
AnnaBridge 167:e84263d55307 472 }
AnnaBridge 167:e84263d55307 473
AnnaBridge 167:e84263d55307 474 return result;
AnnaBridge 167:e84263d55307 475 }
AnnaBridge 167:e84263d55307 476
AnnaBridge 167:e84263d55307 477 /**
AnnaBridge 167:e84263d55307 478 * @brief Fills each TIM_EncoderInitStruct field with its default value
AnnaBridge 167:e84263d55307 479 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
AnnaBridge 167:e84263d55307 480 * @retval None
AnnaBridge 167:e84263d55307 481 */
AnnaBridge 167:e84263d55307 482 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
AnnaBridge 167:e84263d55307 483 {
AnnaBridge 167:e84263d55307 484 /* Set the default configuration */
AnnaBridge 167:e84263d55307 485 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
AnnaBridge 167:e84263d55307 486 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
AnnaBridge 167:e84263d55307 487 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
AnnaBridge 167:e84263d55307 488 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
AnnaBridge 167:e84263d55307 489 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
AnnaBridge 167:e84263d55307 490 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
AnnaBridge 167:e84263d55307 491 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
AnnaBridge 167:e84263d55307 492 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
AnnaBridge 167:e84263d55307 493 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
AnnaBridge 167:e84263d55307 494 }
AnnaBridge 167:e84263d55307 495
AnnaBridge 167:e84263d55307 496 /**
AnnaBridge 167:e84263d55307 497 * @brief Configure the encoder interface of the timer instance.
AnnaBridge 167:e84263d55307 498 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 499 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
AnnaBridge 167:e84263d55307 500 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 501 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 502 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 503 */
AnnaBridge 167:e84263d55307 504 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
AnnaBridge 167:e84263d55307 505 {
AnnaBridge 167:e84263d55307 506 uint32_t tmpccmr1 = 0U;
AnnaBridge 167:e84263d55307 507 uint32_t tmpccer = 0U;
AnnaBridge 167:e84263d55307 508
AnnaBridge 167:e84263d55307 509 /* Check the parameters */
AnnaBridge 167:e84263d55307 510 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 511 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
AnnaBridge 167:e84263d55307 512 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
AnnaBridge 167:e84263d55307 513 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
AnnaBridge 167:e84263d55307 514 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
AnnaBridge 167:e84263d55307 515 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
AnnaBridge 167:e84263d55307 516 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
AnnaBridge 167:e84263d55307 517 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
AnnaBridge 167:e84263d55307 518 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
AnnaBridge 167:e84263d55307 519 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
AnnaBridge 167:e84263d55307 520
AnnaBridge 167:e84263d55307 521 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
AnnaBridge 167:e84263d55307 522 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
AnnaBridge 167:e84263d55307 523
AnnaBridge 167:e84263d55307 524 /* Get the TIMx CCMR1 register value */
AnnaBridge 167:e84263d55307 525 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
AnnaBridge 167:e84263d55307 526
AnnaBridge 167:e84263d55307 527 /* Get the TIMx CCER register value */
AnnaBridge 167:e84263d55307 528 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
AnnaBridge 167:e84263d55307 529
AnnaBridge 167:e84263d55307 530 /* Configure TI1 */
AnnaBridge 167:e84263d55307 531 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
AnnaBridge 167:e84263d55307 532 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
AnnaBridge 167:e84263d55307 533 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
AnnaBridge 167:e84263d55307 534 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
AnnaBridge 167:e84263d55307 535
AnnaBridge 167:e84263d55307 536 /* Configure TI2 */
AnnaBridge 167:e84263d55307 537 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
AnnaBridge 167:e84263d55307 538 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
AnnaBridge 167:e84263d55307 539 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
AnnaBridge 167:e84263d55307 540 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
AnnaBridge 167:e84263d55307 541
AnnaBridge 167:e84263d55307 542 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
AnnaBridge 167:e84263d55307 543 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
AnnaBridge 167:e84263d55307 544 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
AnnaBridge 167:e84263d55307 545 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
AnnaBridge 167:e84263d55307 546 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
AnnaBridge 167:e84263d55307 547
AnnaBridge 167:e84263d55307 548 /* Set encoder mode */
AnnaBridge 167:e84263d55307 549 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
AnnaBridge 167:e84263d55307 550
AnnaBridge 167:e84263d55307 551 /* Write to TIMx CCMR1 */
AnnaBridge 167:e84263d55307 552 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
AnnaBridge 167:e84263d55307 553
AnnaBridge 167:e84263d55307 554 /* Write to TIMx CCER */
AnnaBridge 167:e84263d55307 555 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
AnnaBridge 167:e84263d55307 556
AnnaBridge 167:e84263d55307 557 return SUCCESS;
AnnaBridge 167:e84263d55307 558 }
AnnaBridge 167:e84263d55307 559
AnnaBridge 167:e84263d55307 560 /**
AnnaBridge 167:e84263d55307 561 * @brief Set the fields of the TIMx Hall sensor interface configuration data
AnnaBridge 167:e84263d55307 562 * structure to their default values.
AnnaBridge 167:e84263d55307 563 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
AnnaBridge 167:e84263d55307 564 * @retval None
AnnaBridge 167:e84263d55307 565 */
AnnaBridge 167:e84263d55307 566 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
AnnaBridge 167:e84263d55307 567 {
AnnaBridge 167:e84263d55307 568 /* Set the default configuration */
AnnaBridge 167:e84263d55307 569 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
AnnaBridge 167:e84263d55307 570 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
AnnaBridge 167:e84263d55307 571 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
AnnaBridge 167:e84263d55307 572 TIM_HallSensorInitStruct->CommutationDelay = 0U;
AnnaBridge 167:e84263d55307 573 }
AnnaBridge 167:e84263d55307 574
AnnaBridge 167:e84263d55307 575 /**
AnnaBridge 167:e84263d55307 576 * @brief Configure the Hall sensor interface of the timer instance.
AnnaBridge 167:e84263d55307 577 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
AnnaBridge 167:e84263d55307 578 * to the TI1 input channel
AnnaBridge 167:e84263d55307 579 * @note TIMx slave mode controller is configured in reset mode.
AnnaBridge 167:e84263d55307 580 Selected internal trigger is TI1F_ED.
AnnaBridge 167:e84263d55307 581 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
AnnaBridge 167:e84263d55307 582 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
AnnaBridge 167:e84263d55307 583 * between 2 changes on the inputs. It gives information about motor speed.
AnnaBridge 167:e84263d55307 584 * @note Channel 2 is configured in output PWM 2 mode.
AnnaBridge 167:e84263d55307 585 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
AnnaBridge 167:e84263d55307 586 * @note OC2REF is selected as trigger output on TRGO.
AnnaBridge 167:e84263d55307 587 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
AnnaBridge 167:e84263d55307 588 * when TIMx operates in Hall sensor interface mode.
AnnaBridge 167:e84263d55307 589 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 590 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
AnnaBridge 167:e84263d55307 591 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 592 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 593 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 594 */
AnnaBridge 167:e84263d55307 595 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
AnnaBridge 167:e84263d55307 596 {
AnnaBridge 167:e84263d55307 597 uint32_t tmpcr2 = 0U;
AnnaBridge 167:e84263d55307 598 uint32_t tmpccmr1 = 0U;
AnnaBridge 167:e84263d55307 599 uint32_t tmpccer = 0U;
AnnaBridge 167:e84263d55307 600 uint32_t tmpsmcr = 0U;
AnnaBridge 167:e84263d55307 601
AnnaBridge 167:e84263d55307 602 /* Check the parameters */
AnnaBridge 167:e84263d55307 603 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 604 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
AnnaBridge 167:e84263d55307 605 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
AnnaBridge 167:e84263d55307 606 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
AnnaBridge 167:e84263d55307 607
AnnaBridge 167:e84263d55307 608 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
AnnaBridge 167:e84263d55307 609 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
AnnaBridge 167:e84263d55307 610
AnnaBridge 167:e84263d55307 611 /* Get the TIMx CR2 register value */
AnnaBridge 167:e84263d55307 612 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
AnnaBridge 167:e84263d55307 613
AnnaBridge 167:e84263d55307 614 /* Get the TIMx CCMR1 register value */
AnnaBridge 167:e84263d55307 615 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
AnnaBridge 167:e84263d55307 616
AnnaBridge 167:e84263d55307 617 /* Get the TIMx CCER register value */
AnnaBridge 167:e84263d55307 618 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
AnnaBridge 167:e84263d55307 619
AnnaBridge 167:e84263d55307 620 /* Get the TIMx SMCR register value */
AnnaBridge 167:e84263d55307 621 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
AnnaBridge 167:e84263d55307 622
AnnaBridge 167:e84263d55307 623 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
AnnaBridge 167:e84263d55307 624 tmpcr2 |= TIM_CR2_TI1S;
AnnaBridge 167:e84263d55307 625
AnnaBridge 167:e84263d55307 626 /* OC2REF signal is used as trigger output (TRGO) */
AnnaBridge 167:e84263d55307 627 tmpcr2 |= LL_TIM_TRGO_OC2REF;
AnnaBridge 167:e84263d55307 628
AnnaBridge 167:e84263d55307 629 /* Configure the slave mode controller */
AnnaBridge 167:e84263d55307 630 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
AnnaBridge 167:e84263d55307 631 tmpsmcr |= LL_TIM_TS_TI1F_ED;
AnnaBridge 167:e84263d55307 632 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
AnnaBridge 167:e84263d55307 633
AnnaBridge 167:e84263d55307 634 /* Configure input channel 1 */
AnnaBridge 167:e84263d55307 635 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
AnnaBridge 167:e84263d55307 636 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
AnnaBridge 167:e84263d55307 637 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
AnnaBridge 167:e84263d55307 638 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
AnnaBridge 167:e84263d55307 639
AnnaBridge 167:e84263d55307 640 /* Configure input channel 2 */
AnnaBridge 167:e84263d55307 641 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
AnnaBridge 167:e84263d55307 642 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
AnnaBridge 167:e84263d55307 643
AnnaBridge 167:e84263d55307 644 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
AnnaBridge 167:e84263d55307 645 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
AnnaBridge 167:e84263d55307 646 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
AnnaBridge 167:e84263d55307 647 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
AnnaBridge 167:e84263d55307 648
AnnaBridge 167:e84263d55307 649 /* Write to TIMx CR2 */
AnnaBridge 167:e84263d55307 650 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
AnnaBridge 167:e84263d55307 651
AnnaBridge 167:e84263d55307 652 /* Write to TIMx SMCR */
AnnaBridge 167:e84263d55307 653 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
AnnaBridge 167:e84263d55307 654
AnnaBridge 167:e84263d55307 655 /* Write to TIMx CCMR1 */
AnnaBridge 167:e84263d55307 656 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
AnnaBridge 167:e84263d55307 657
AnnaBridge 167:e84263d55307 658 /* Write to TIMx CCER */
AnnaBridge 167:e84263d55307 659 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
AnnaBridge 167:e84263d55307 660
AnnaBridge 167:e84263d55307 661 /* Write to TIMx CCR2 */
AnnaBridge 167:e84263d55307 662 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
AnnaBridge 167:e84263d55307 663
AnnaBridge 167:e84263d55307 664 return SUCCESS;
AnnaBridge 167:e84263d55307 665 }
AnnaBridge 167:e84263d55307 666
AnnaBridge 167:e84263d55307 667 /**
AnnaBridge 167:e84263d55307 668 * @brief Set the fields of the Break and Dead Time configuration data structure
AnnaBridge 167:e84263d55307 669 * to their default values.
AnnaBridge 167:e84263d55307 670 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
AnnaBridge 167:e84263d55307 671 * @retval None
AnnaBridge 167:e84263d55307 672 */
AnnaBridge 167:e84263d55307 673 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
AnnaBridge 167:e84263d55307 674 {
AnnaBridge 167:e84263d55307 675 /* Set the default configuration */
AnnaBridge 167:e84263d55307 676 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
AnnaBridge 167:e84263d55307 677 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
AnnaBridge 167:e84263d55307 678 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
AnnaBridge 167:e84263d55307 679 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
AnnaBridge 167:e84263d55307 680 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
AnnaBridge 167:e84263d55307 681 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
AnnaBridge 167:e84263d55307 682 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
AnnaBridge 167:e84263d55307 683 }
AnnaBridge 167:e84263d55307 684
AnnaBridge 167:e84263d55307 685 /**
AnnaBridge 167:e84263d55307 686 * @brief Configure the Break and Dead Time feature of the timer instance.
AnnaBridge 167:e84263d55307 687 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
AnnaBridge 167:e84263d55307 688 * depending on the LOCK configuration, it can be necessary to configure all of
AnnaBridge 167:e84263d55307 689 * them during the first write access to the TIMx_BDTR register.
AnnaBridge 167:e84263d55307 690 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge 167:e84263d55307 691 * a timer instance provides a break input.
AnnaBridge 167:e84263d55307 692 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 693 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
AnnaBridge 167:e84263d55307 694 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 695 * - SUCCESS: Break and Dead Time is initialized
AnnaBridge 167:e84263d55307 696 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 697 */
AnnaBridge 167:e84263d55307 698 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
AnnaBridge 167:e84263d55307 699 {
AnnaBridge 167:e84263d55307 700 uint32_t tmpbdtr = 0;
AnnaBridge 167:e84263d55307 701
AnnaBridge 167:e84263d55307 702 /* Check the parameters */
AnnaBridge 167:e84263d55307 703 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 704 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
AnnaBridge 167:e84263d55307 705 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
AnnaBridge 167:e84263d55307 706 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
AnnaBridge 167:e84263d55307 707 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
AnnaBridge 167:e84263d55307 708 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
AnnaBridge 167:e84263d55307 709 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
AnnaBridge 167:e84263d55307 710
AnnaBridge 167:e84263d55307 711 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
AnnaBridge 167:e84263d55307 712 the OSSI State, the dead time value and the Automatic Output Enable Bit */
AnnaBridge 167:e84263d55307 713
AnnaBridge 167:e84263d55307 714 /* Set the BDTR bits */
AnnaBridge 167:e84263d55307 715 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
AnnaBridge 167:e84263d55307 716 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
AnnaBridge 167:e84263d55307 717 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
AnnaBridge 167:e84263d55307 718 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
AnnaBridge 167:e84263d55307 719 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
AnnaBridge 167:e84263d55307 720 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
AnnaBridge 167:e84263d55307 721 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
AnnaBridge 167:e84263d55307 722 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
AnnaBridge 167:e84263d55307 723
AnnaBridge 167:e84263d55307 724 /* Set TIMx_BDTR */
AnnaBridge 167:e84263d55307 725 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
AnnaBridge 167:e84263d55307 726
AnnaBridge 167:e84263d55307 727 return SUCCESS;
AnnaBridge 167:e84263d55307 728 }
AnnaBridge 167:e84263d55307 729 /**
AnnaBridge 167:e84263d55307 730 * @}
AnnaBridge 167:e84263d55307 731 */
AnnaBridge 167:e84263d55307 732
AnnaBridge 167:e84263d55307 733 /**
AnnaBridge 167:e84263d55307 734 * @}
AnnaBridge 167:e84263d55307 735 */
AnnaBridge 167:e84263d55307 736
AnnaBridge 167:e84263d55307 737 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
AnnaBridge 167:e84263d55307 738 * @brief Private functions
AnnaBridge 167:e84263d55307 739 * @{
AnnaBridge 167:e84263d55307 740 */
AnnaBridge 167:e84263d55307 741 /**
AnnaBridge 167:e84263d55307 742 * @brief Configure the TIMx output channel 1.
AnnaBridge 167:e84263d55307 743 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 744 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
AnnaBridge 167:e84263d55307 745 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 746 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 747 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 748 */
AnnaBridge 167:e84263d55307 749 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
AnnaBridge 167:e84263d55307 750 {
AnnaBridge 167:e84263d55307 751 uint32_t tmpccmr1 = 0U;
AnnaBridge 167:e84263d55307 752 uint32_t tmpccer = 0U;
AnnaBridge 167:e84263d55307 753 uint32_t tmpcr2 = 0U;
AnnaBridge 167:e84263d55307 754
AnnaBridge 167:e84263d55307 755 /* Check the parameters */
AnnaBridge 167:e84263d55307 756 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 757 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
AnnaBridge 167:e84263d55307 758 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
AnnaBridge 167:e84263d55307 759 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
AnnaBridge 167:e84263d55307 760 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
AnnaBridge 167:e84263d55307 761 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
AnnaBridge 167:e84263d55307 762
AnnaBridge 167:e84263d55307 763 /* Disable the Channel 1: Reset the CC1E Bit */
AnnaBridge 167:e84263d55307 764 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
AnnaBridge 167:e84263d55307 765
AnnaBridge 167:e84263d55307 766 /* Get the TIMx CCER register value */
AnnaBridge 167:e84263d55307 767 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
AnnaBridge 167:e84263d55307 768
AnnaBridge 167:e84263d55307 769 /* Get the TIMx CR2 register value */
AnnaBridge 167:e84263d55307 770 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
AnnaBridge 167:e84263d55307 771
AnnaBridge 167:e84263d55307 772 /* Get the TIMx CCMR1 register value */
AnnaBridge 167:e84263d55307 773 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
AnnaBridge 167:e84263d55307 774
AnnaBridge 167:e84263d55307 775 /* Reset Capture/Compare selection Bits */
AnnaBridge 167:e84263d55307 776 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
AnnaBridge 167:e84263d55307 777
AnnaBridge 167:e84263d55307 778 /* Set the Output Compare Mode */
AnnaBridge 167:e84263d55307 779 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
AnnaBridge 167:e84263d55307 780
AnnaBridge 167:e84263d55307 781 /* Set the Output Compare Polarity */
AnnaBridge 167:e84263d55307 782 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
AnnaBridge 167:e84263d55307 783
AnnaBridge 167:e84263d55307 784 /* Set the Output State */
AnnaBridge 167:e84263d55307 785 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
AnnaBridge 167:e84263d55307 786
AnnaBridge 167:e84263d55307 787 if (IS_TIM_BREAK_INSTANCE(TIMx))
AnnaBridge 167:e84263d55307 788 {
AnnaBridge 167:e84263d55307 789 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
AnnaBridge 167:e84263d55307 790 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
AnnaBridge 167:e84263d55307 791
AnnaBridge 167:e84263d55307 792 /* Set the complementary output Polarity */
AnnaBridge 167:e84263d55307 793 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
AnnaBridge 167:e84263d55307 794
AnnaBridge 167:e84263d55307 795 /* Set the complementary output State */
AnnaBridge 167:e84263d55307 796 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
AnnaBridge 167:e84263d55307 797
AnnaBridge 167:e84263d55307 798 /* Set the Output Idle state */
AnnaBridge 167:e84263d55307 799 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
AnnaBridge 167:e84263d55307 800
AnnaBridge 167:e84263d55307 801 /* Set the complementary output Idle state */
AnnaBridge 167:e84263d55307 802 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
AnnaBridge 167:e84263d55307 803 }
AnnaBridge 167:e84263d55307 804
AnnaBridge 167:e84263d55307 805 /* Write to TIMx CR2 */
AnnaBridge 167:e84263d55307 806 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
AnnaBridge 167:e84263d55307 807
AnnaBridge 167:e84263d55307 808 /* Write to TIMx CCMR1 */
AnnaBridge 167:e84263d55307 809 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
AnnaBridge 167:e84263d55307 810
AnnaBridge 167:e84263d55307 811 /* Set the Capture Compare Register value */
AnnaBridge 167:e84263d55307 812 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
AnnaBridge 167:e84263d55307 813
AnnaBridge 167:e84263d55307 814 /* Write to TIMx CCER */
AnnaBridge 167:e84263d55307 815 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
AnnaBridge 167:e84263d55307 816
AnnaBridge 167:e84263d55307 817 return SUCCESS;
AnnaBridge 167:e84263d55307 818 }
AnnaBridge 167:e84263d55307 819
AnnaBridge 167:e84263d55307 820 /**
AnnaBridge 167:e84263d55307 821 * @brief Configure the TIMx output channel 2.
AnnaBridge 167:e84263d55307 822 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 823 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
AnnaBridge 167:e84263d55307 824 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 825 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 826 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 827 */
AnnaBridge 167:e84263d55307 828 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
AnnaBridge 167:e84263d55307 829 {
AnnaBridge 167:e84263d55307 830 uint32_t tmpccmr1 = 0U;
AnnaBridge 167:e84263d55307 831 uint32_t tmpccer = 0U;
AnnaBridge 167:e84263d55307 832 uint32_t tmpcr2 = 0U;
AnnaBridge 167:e84263d55307 833
AnnaBridge 167:e84263d55307 834 /* Check the parameters */
AnnaBridge 167:e84263d55307 835 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 836 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
AnnaBridge 167:e84263d55307 837 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
AnnaBridge 167:e84263d55307 838 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
AnnaBridge 167:e84263d55307 839 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
AnnaBridge 167:e84263d55307 840 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
AnnaBridge 167:e84263d55307 841
AnnaBridge 167:e84263d55307 842 /* Disable the Channel 2: Reset the CC2E Bit */
AnnaBridge 167:e84263d55307 843 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
AnnaBridge 167:e84263d55307 844
AnnaBridge 167:e84263d55307 845 /* Get the TIMx CCER register value */
AnnaBridge 167:e84263d55307 846 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
AnnaBridge 167:e84263d55307 847
AnnaBridge 167:e84263d55307 848 /* Get the TIMx CR2 register value */
AnnaBridge 167:e84263d55307 849 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
AnnaBridge 167:e84263d55307 850
AnnaBridge 167:e84263d55307 851 /* Get the TIMx CCMR1 register value */
AnnaBridge 167:e84263d55307 852 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
AnnaBridge 167:e84263d55307 853
AnnaBridge 167:e84263d55307 854 /* Reset Capture/Compare selection Bits */
AnnaBridge 167:e84263d55307 855 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
AnnaBridge 167:e84263d55307 856
AnnaBridge 167:e84263d55307 857 /* Select the Output Compare Mode */
AnnaBridge 167:e84263d55307 858 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
AnnaBridge 167:e84263d55307 859
AnnaBridge 167:e84263d55307 860 /* Set the Output Compare Polarity */
AnnaBridge 167:e84263d55307 861 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
AnnaBridge 167:e84263d55307 862
AnnaBridge 167:e84263d55307 863 /* Set the Output State */
AnnaBridge 167:e84263d55307 864 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
AnnaBridge 167:e84263d55307 865
AnnaBridge 167:e84263d55307 866 if (IS_TIM_BREAK_INSTANCE(TIMx))
AnnaBridge 167:e84263d55307 867 {
AnnaBridge 167:e84263d55307 868 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
AnnaBridge 167:e84263d55307 869 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
AnnaBridge 167:e84263d55307 870
AnnaBridge 167:e84263d55307 871 /* Set the complementary output Polarity */
AnnaBridge 167:e84263d55307 872 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
AnnaBridge 167:e84263d55307 873
AnnaBridge 167:e84263d55307 874 /* Set the complementary output State */
AnnaBridge 167:e84263d55307 875 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
AnnaBridge 167:e84263d55307 876
AnnaBridge 167:e84263d55307 877 /* Set the Output Idle state */
AnnaBridge 167:e84263d55307 878 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
AnnaBridge 167:e84263d55307 879
AnnaBridge 167:e84263d55307 880 /* Set the complementary output Idle state */
AnnaBridge 167:e84263d55307 881 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
AnnaBridge 167:e84263d55307 882 }
AnnaBridge 167:e84263d55307 883
AnnaBridge 167:e84263d55307 884 /* Write to TIMx CR2 */
AnnaBridge 167:e84263d55307 885 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
AnnaBridge 167:e84263d55307 886
AnnaBridge 167:e84263d55307 887 /* Write to TIMx CCMR1 */
AnnaBridge 167:e84263d55307 888 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
AnnaBridge 167:e84263d55307 889
AnnaBridge 167:e84263d55307 890 /* Set the Capture Compare Register value */
AnnaBridge 167:e84263d55307 891 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
AnnaBridge 167:e84263d55307 892
AnnaBridge 167:e84263d55307 893 /* Write to TIMx CCER */
AnnaBridge 167:e84263d55307 894 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
AnnaBridge 167:e84263d55307 895
AnnaBridge 167:e84263d55307 896 return SUCCESS;
AnnaBridge 167:e84263d55307 897 }
AnnaBridge 167:e84263d55307 898
AnnaBridge 167:e84263d55307 899 /**
AnnaBridge 167:e84263d55307 900 * @brief Configure the TIMx output channel 3.
AnnaBridge 167:e84263d55307 901 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 902 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
AnnaBridge 167:e84263d55307 903 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 904 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 905 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 906 */
AnnaBridge 167:e84263d55307 907 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
AnnaBridge 167:e84263d55307 908 {
AnnaBridge 167:e84263d55307 909 uint32_t tmpccmr2 = 0U;
AnnaBridge 167:e84263d55307 910 uint32_t tmpccer = 0U;
AnnaBridge 167:e84263d55307 911 uint32_t tmpcr2 = 0U;
AnnaBridge 167:e84263d55307 912
AnnaBridge 167:e84263d55307 913 /* Check the parameters */
AnnaBridge 167:e84263d55307 914 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 915 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
AnnaBridge 167:e84263d55307 916 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
AnnaBridge 167:e84263d55307 917 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
AnnaBridge 167:e84263d55307 918 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
AnnaBridge 167:e84263d55307 919 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
AnnaBridge 167:e84263d55307 920
AnnaBridge 167:e84263d55307 921 /* Disable the Channel 3: Reset the CC3E Bit */
AnnaBridge 167:e84263d55307 922 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
AnnaBridge 167:e84263d55307 923
AnnaBridge 167:e84263d55307 924 /* Get the TIMx CCER register value */
AnnaBridge 167:e84263d55307 925 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
AnnaBridge 167:e84263d55307 926
AnnaBridge 167:e84263d55307 927 /* Get the TIMx CR2 register value */
AnnaBridge 167:e84263d55307 928 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
AnnaBridge 167:e84263d55307 929
AnnaBridge 167:e84263d55307 930 /* Get the TIMx CCMR2 register value */
AnnaBridge 167:e84263d55307 931 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
AnnaBridge 167:e84263d55307 932
AnnaBridge 167:e84263d55307 933 /* Reset Capture/Compare selection Bits */
AnnaBridge 167:e84263d55307 934 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
AnnaBridge 167:e84263d55307 935
AnnaBridge 167:e84263d55307 936 /* Select the Output Compare Mode */
AnnaBridge 167:e84263d55307 937 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
AnnaBridge 167:e84263d55307 938
AnnaBridge 167:e84263d55307 939 /* Set the Output Compare Polarity */
AnnaBridge 167:e84263d55307 940 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
AnnaBridge 167:e84263d55307 941
AnnaBridge 167:e84263d55307 942 /* Set the Output State */
AnnaBridge 167:e84263d55307 943 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
AnnaBridge 167:e84263d55307 944
AnnaBridge 167:e84263d55307 945 if (IS_TIM_BREAK_INSTANCE(TIMx))
AnnaBridge 167:e84263d55307 946 {
AnnaBridge 167:e84263d55307 947 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
AnnaBridge 167:e84263d55307 948 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
AnnaBridge 167:e84263d55307 949
AnnaBridge 167:e84263d55307 950 /* Set the complementary output Polarity */
AnnaBridge 167:e84263d55307 951 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
AnnaBridge 167:e84263d55307 952
AnnaBridge 167:e84263d55307 953 /* Set the complementary output State */
AnnaBridge 167:e84263d55307 954 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
AnnaBridge 167:e84263d55307 955
AnnaBridge 167:e84263d55307 956 /* Set the Output Idle state */
AnnaBridge 167:e84263d55307 957 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
AnnaBridge 167:e84263d55307 958
AnnaBridge 167:e84263d55307 959 /* Set the complementary output Idle state */
AnnaBridge 167:e84263d55307 960 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
AnnaBridge 167:e84263d55307 961 }
AnnaBridge 167:e84263d55307 962
AnnaBridge 167:e84263d55307 963 /* Write to TIMx CR2 */
AnnaBridge 167:e84263d55307 964 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
AnnaBridge 167:e84263d55307 965
AnnaBridge 167:e84263d55307 966 /* Write to TIMx CCMR2 */
AnnaBridge 167:e84263d55307 967 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
AnnaBridge 167:e84263d55307 968
AnnaBridge 167:e84263d55307 969 /* Set the Capture Compare Register value */
AnnaBridge 167:e84263d55307 970 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
AnnaBridge 167:e84263d55307 971
AnnaBridge 167:e84263d55307 972 /* Write to TIMx CCER */
AnnaBridge 167:e84263d55307 973 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
AnnaBridge 167:e84263d55307 974
AnnaBridge 167:e84263d55307 975 return SUCCESS;
AnnaBridge 167:e84263d55307 976 }
AnnaBridge 167:e84263d55307 977
AnnaBridge 167:e84263d55307 978 /**
AnnaBridge 167:e84263d55307 979 * @brief Configure the TIMx output channel 4.
AnnaBridge 167:e84263d55307 980 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 981 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
AnnaBridge 167:e84263d55307 982 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 983 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 984 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 985 */
AnnaBridge 167:e84263d55307 986 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
AnnaBridge 167:e84263d55307 987 {
AnnaBridge 167:e84263d55307 988 uint32_t tmpccmr2 = 0U;
AnnaBridge 167:e84263d55307 989 uint32_t tmpccer = 0U;
AnnaBridge 167:e84263d55307 990 uint32_t tmpcr2 = 0U;
AnnaBridge 167:e84263d55307 991
AnnaBridge 167:e84263d55307 992 /* Check the parameters */
AnnaBridge 167:e84263d55307 993 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 994 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
AnnaBridge 167:e84263d55307 995 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
AnnaBridge 167:e84263d55307 996 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
AnnaBridge 167:e84263d55307 997 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
AnnaBridge 167:e84263d55307 998 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
AnnaBridge 167:e84263d55307 999
AnnaBridge 167:e84263d55307 1000 /* Disable the Channel 4: Reset the CC4E Bit */
AnnaBridge 167:e84263d55307 1001 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
AnnaBridge 167:e84263d55307 1002
AnnaBridge 167:e84263d55307 1003 /* Get the TIMx CCER register value */
AnnaBridge 167:e84263d55307 1004 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
AnnaBridge 167:e84263d55307 1005
AnnaBridge 167:e84263d55307 1006 /* Get the TIMx CR2 register value */
AnnaBridge 167:e84263d55307 1007 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
AnnaBridge 167:e84263d55307 1008
AnnaBridge 167:e84263d55307 1009 /* Get the TIMx CCMR2 register value */
AnnaBridge 167:e84263d55307 1010 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
AnnaBridge 167:e84263d55307 1011
AnnaBridge 167:e84263d55307 1012 /* Reset Capture/Compare selection Bits */
AnnaBridge 167:e84263d55307 1013 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
AnnaBridge 167:e84263d55307 1014
AnnaBridge 167:e84263d55307 1015 /* Select the Output Compare Mode */
AnnaBridge 167:e84263d55307 1016 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
AnnaBridge 167:e84263d55307 1017
AnnaBridge 167:e84263d55307 1018 /* Set the Output Compare Polarity */
AnnaBridge 167:e84263d55307 1019 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
AnnaBridge 167:e84263d55307 1020
AnnaBridge 167:e84263d55307 1021 /* Set the Output State */
AnnaBridge 167:e84263d55307 1022 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
AnnaBridge 167:e84263d55307 1023
AnnaBridge 167:e84263d55307 1024 if (IS_TIM_BREAK_INSTANCE(TIMx))
AnnaBridge 167:e84263d55307 1025 {
AnnaBridge 167:e84263d55307 1026 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
AnnaBridge 167:e84263d55307 1027 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
AnnaBridge 167:e84263d55307 1028
AnnaBridge 167:e84263d55307 1029 /* Set the Output Idle state */
AnnaBridge 167:e84263d55307 1030 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
AnnaBridge 167:e84263d55307 1031 }
AnnaBridge 167:e84263d55307 1032
AnnaBridge 167:e84263d55307 1033 /* Write to TIMx CR2 */
AnnaBridge 167:e84263d55307 1034 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
AnnaBridge 167:e84263d55307 1035
AnnaBridge 167:e84263d55307 1036 /* Write to TIMx CCMR2 */
AnnaBridge 167:e84263d55307 1037 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
AnnaBridge 167:e84263d55307 1038
AnnaBridge 167:e84263d55307 1039 /* Set the Capture Compare Register value */
AnnaBridge 167:e84263d55307 1040 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
AnnaBridge 167:e84263d55307 1041
AnnaBridge 167:e84263d55307 1042 /* Write to TIMx CCER */
AnnaBridge 167:e84263d55307 1043 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
AnnaBridge 167:e84263d55307 1044
AnnaBridge 167:e84263d55307 1045 return SUCCESS;
AnnaBridge 167:e84263d55307 1046 }
AnnaBridge 167:e84263d55307 1047
AnnaBridge 167:e84263d55307 1048
AnnaBridge 167:e84263d55307 1049 /**
AnnaBridge 167:e84263d55307 1050 * @brief Configure the TIMx input channel 1.
AnnaBridge 167:e84263d55307 1051 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 1052 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
AnnaBridge 167:e84263d55307 1053 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 1054 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 1055 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 1056 */
AnnaBridge 167:e84263d55307 1057 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
AnnaBridge 167:e84263d55307 1058 {
AnnaBridge 167:e84263d55307 1059 /* Check the parameters */
AnnaBridge 167:e84263d55307 1060 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 1061 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
AnnaBridge 167:e84263d55307 1062 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
AnnaBridge 167:e84263d55307 1063 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
AnnaBridge 167:e84263d55307 1064 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
AnnaBridge 167:e84263d55307 1065
AnnaBridge 167:e84263d55307 1066 /* Disable the Channel 1: Reset the CC1E Bit */
AnnaBridge 167:e84263d55307 1067 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
AnnaBridge 167:e84263d55307 1068
AnnaBridge 167:e84263d55307 1069 /* Select the Input and set the filter and the prescaler value */
AnnaBridge 167:e84263d55307 1070 MODIFY_REG(TIMx->CCMR1,
AnnaBridge 167:e84263d55307 1071 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
AnnaBridge 167:e84263d55307 1072 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
AnnaBridge 167:e84263d55307 1073
AnnaBridge 167:e84263d55307 1074 /* Select the Polarity and set the CC1E Bit */
AnnaBridge 167:e84263d55307 1075 MODIFY_REG(TIMx->CCER,
AnnaBridge 167:e84263d55307 1076 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
AnnaBridge 167:e84263d55307 1077 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
AnnaBridge 167:e84263d55307 1078
AnnaBridge 167:e84263d55307 1079 return SUCCESS;
AnnaBridge 167:e84263d55307 1080 }
AnnaBridge 167:e84263d55307 1081
AnnaBridge 167:e84263d55307 1082 /**
AnnaBridge 167:e84263d55307 1083 * @brief Configure the TIMx input channel 2.
AnnaBridge 167:e84263d55307 1084 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 1085 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
AnnaBridge 167:e84263d55307 1086 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 1087 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 1088 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 1089 */
AnnaBridge 167:e84263d55307 1090 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
AnnaBridge 167:e84263d55307 1091 {
AnnaBridge 167:e84263d55307 1092 /* Check the parameters */
AnnaBridge 167:e84263d55307 1093 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 1094 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
AnnaBridge 167:e84263d55307 1095 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
AnnaBridge 167:e84263d55307 1096 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
AnnaBridge 167:e84263d55307 1097 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
AnnaBridge 167:e84263d55307 1098
AnnaBridge 167:e84263d55307 1099 /* Disable the Channel 2: Reset the CC2E Bit */
AnnaBridge 167:e84263d55307 1100 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
AnnaBridge 167:e84263d55307 1101
AnnaBridge 167:e84263d55307 1102 /* Select the Input and set the filter and the prescaler value */
AnnaBridge 167:e84263d55307 1103 MODIFY_REG(TIMx->CCMR1,
AnnaBridge 167:e84263d55307 1104 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
AnnaBridge 167:e84263d55307 1105 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
AnnaBridge 167:e84263d55307 1106
AnnaBridge 167:e84263d55307 1107 /* Select the Polarity and set the CC2E Bit */
AnnaBridge 167:e84263d55307 1108 MODIFY_REG(TIMx->CCER,
AnnaBridge 167:e84263d55307 1109 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
AnnaBridge 167:e84263d55307 1110 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
AnnaBridge 167:e84263d55307 1111
AnnaBridge 167:e84263d55307 1112 return SUCCESS;
AnnaBridge 167:e84263d55307 1113 }
AnnaBridge 167:e84263d55307 1114
AnnaBridge 167:e84263d55307 1115 /**
AnnaBridge 167:e84263d55307 1116 * @brief Configure the TIMx input channel 3.
AnnaBridge 167:e84263d55307 1117 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 1118 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
AnnaBridge 167:e84263d55307 1119 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 1120 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 1121 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 1122 */
AnnaBridge 167:e84263d55307 1123 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
AnnaBridge 167:e84263d55307 1124 {
AnnaBridge 167:e84263d55307 1125 /* Check the parameters */
AnnaBridge 167:e84263d55307 1126 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 1127 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
AnnaBridge 167:e84263d55307 1128 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
AnnaBridge 167:e84263d55307 1129 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
AnnaBridge 167:e84263d55307 1130 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
AnnaBridge 167:e84263d55307 1131
AnnaBridge 167:e84263d55307 1132 /* Disable the Channel 3: Reset the CC3E Bit */
AnnaBridge 167:e84263d55307 1133 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
AnnaBridge 167:e84263d55307 1134
AnnaBridge 167:e84263d55307 1135 /* Select the Input and set the filter and the prescaler value */
AnnaBridge 167:e84263d55307 1136 MODIFY_REG(TIMx->CCMR2,
AnnaBridge 167:e84263d55307 1137 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
AnnaBridge 167:e84263d55307 1138 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
AnnaBridge 167:e84263d55307 1139
AnnaBridge 167:e84263d55307 1140 /* Select the Polarity and set the CC3E Bit */
AnnaBridge 167:e84263d55307 1141 MODIFY_REG(TIMx->CCER,
AnnaBridge 167:e84263d55307 1142 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
AnnaBridge 167:e84263d55307 1143 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
AnnaBridge 167:e84263d55307 1144
AnnaBridge 167:e84263d55307 1145 return SUCCESS;
AnnaBridge 167:e84263d55307 1146 }
AnnaBridge 167:e84263d55307 1147
AnnaBridge 167:e84263d55307 1148 /**
AnnaBridge 167:e84263d55307 1149 * @brief Configure the TIMx input channel 4.
AnnaBridge 167:e84263d55307 1150 * @param TIMx Timer Instance
AnnaBridge 167:e84263d55307 1151 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
AnnaBridge 167:e84263d55307 1152 * @retval An ErrorStatus enumeration value:
AnnaBridge 167:e84263d55307 1153 * - SUCCESS: TIMx registers are de-initialized
AnnaBridge 167:e84263d55307 1154 * - ERROR: not applicable
AnnaBridge 167:e84263d55307 1155 */
AnnaBridge 167:e84263d55307 1156 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
AnnaBridge 167:e84263d55307 1157 {
AnnaBridge 167:e84263d55307 1158 /* Check the parameters */
AnnaBridge 167:e84263d55307 1159 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
AnnaBridge 167:e84263d55307 1160 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
AnnaBridge 167:e84263d55307 1161 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
AnnaBridge 167:e84263d55307 1162 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
AnnaBridge 167:e84263d55307 1163 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
AnnaBridge 167:e84263d55307 1164
AnnaBridge 167:e84263d55307 1165 /* Disable the Channel 4: Reset the CC4E Bit */
AnnaBridge 167:e84263d55307 1166 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
AnnaBridge 167:e84263d55307 1167
AnnaBridge 167:e84263d55307 1168 /* Select the Input and set the filter and the prescaler value */
AnnaBridge 167:e84263d55307 1169 MODIFY_REG(TIMx->CCMR2,
AnnaBridge 167:e84263d55307 1170 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
AnnaBridge 167:e84263d55307 1171 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
AnnaBridge 167:e84263d55307 1172
AnnaBridge 167:e84263d55307 1173 /* Select the Polarity and set the CC2E Bit */
AnnaBridge 167:e84263d55307 1174 MODIFY_REG(TIMx->CCER,
AnnaBridge 167:e84263d55307 1175 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
AnnaBridge 167:e84263d55307 1176 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
AnnaBridge 167:e84263d55307 1177
AnnaBridge 167:e84263d55307 1178 return SUCCESS;
AnnaBridge 167:e84263d55307 1179 }
AnnaBridge 167:e84263d55307 1180
AnnaBridge 167:e84263d55307 1181
AnnaBridge 167:e84263d55307 1182 /**
AnnaBridge 167:e84263d55307 1183 * @}
AnnaBridge 167:e84263d55307 1184 */
AnnaBridge 167:e84263d55307 1185
AnnaBridge 167:e84263d55307 1186 /**
AnnaBridge 167:e84263d55307 1187 * @}
AnnaBridge 167:e84263d55307 1188 */
AnnaBridge 167:e84263d55307 1189
AnnaBridge 167:e84263d55307 1190 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
AnnaBridge 167:e84263d55307 1191
AnnaBridge 167:e84263d55307 1192 /**
AnnaBridge 167:e84263d55307 1193 * @}
AnnaBridge 167:e84263d55307 1194 */
AnnaBridge 167:e84263d55307 1195
AnnaBridge 167:e84263d55307 1196 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 167:e84263d55307 1197
AnnaBridge 167:e84263d55307 1198 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/