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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/**
AnnaBridge	167:e84263d55307	2	******************************************************************************
AnnaBridge	167:e84263d55307	3	* @file stm32f2xx_ll_spi.h
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
AnnaBridge	167:e84263d55307	7	* @brief Header file of SPI LL module.
AnnaBridge	167:e84263d55307	8	******************************************************************************
AnnaBridge	167:e84263d55307	9	* @attention
AnnaBridge	167:e84263d55307	10	*
AnnaBridge	167:e84263d55307	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	167:e84263d55307	12	*
AnnaBridge	167:e84263d55307	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	167:e84263d55307	14	* are permitted provided that the following conditions are met:
AnnaBridge	167:e84263d55307	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	167:e84263d55307	16	* this list of conditions and the following disclaimer.
AnnaBridge	167:e84263d55307	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	167:e84263d55307	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	167:e84263d55307	19	* and/or other materials provided with the distribution.
AnnaBridge	167:e84263d55307	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	167:e84263d55307	21	* may be used to endorse or promote products derived from this software
AnnaBridge	167:e84263d55307	22	* without specific prior written permission.
AnnaBridge	167:e84263d55307	23	*
AnnaBridge	167:e84263d55307	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	167:e84263d55307	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	167:e84263d55307	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	167:e84263d55307	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	167:e84263d55307	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	167:e84263d55307	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	167:e84263d55307	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	167:e84263d55307	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	167:e84263d55307	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	167:e84263d55307	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	167:e84263d55307	34	*
AnnaBridge	167:e84263d55307	35	******************************************************************************
AnnaBridge	167:e84263d55307	36	*/
AnnaBridge	167:e84263d55307	37
AnnaBridge	167:e84263d55307	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	167:e84263d55307	39	#ifndef __STM32F2xx_LL_SPI_H
AnnaBridge	167:e84263d55307	40	#define __STM32F2xx_LL_SPI_H
AnnaBridge	167:e84263d55307	41
AnnaBridge	167:e84263d55307	42	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	43	extern "C" {
AnnaBridge	167:e84263d55307	44	#endif
AnnaBridge	167:e84263d55307	45
AnnaBridge	167:e84263d55307	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	47	#include "stm32f2xx.h"
AnnaBridge	167:e84263d55307	48
AnnaBridge	167:e84263d55307	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	167:e84263d55307	50	* @{
AnnaBridge	167:e84263d55307	51	*/
AnnaBridge	167:e84263d55307	52
AnnaBridge	167:e84263d55307	53	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3)
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/** @defgroup SPI_LL SPI
AnnaBridge	167:e84263d55307	56	* @{
AnnaBridge	167:e84263d55307	57	*/
AnnaBridge	167:e84263d55307	58
AnnaBridge	167:e84263d55307	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	61	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	62
AnnaBridge	167:e84263d55307	63	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	64	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	65	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	167:e84263d55307	66	* @{
AnnaBridge	167:e84263d55307	67	*/
AnnaBridge	167:e84263d55307	68
AnnaBridge	167:e84263d55307	69	/**
AnnaBridge	167:e84263d55307	70	* @brief SPI Init structures definition
AnnaBridge	167:e84263d55307	71	*/
AnnaBridge	167:e84263d55307	72	typedef struct
AnnaBridge	167:e84263d55307	73	{
AnnaBridge	167:e84263d55307	74	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	167:e84263d55307	75	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	167:e84263d55307	76
AnnaBridge	167:e84263d55307	77	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	167:e84263d55307	78
AnnaBridge	167:e84263d55307	79	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	167:e84263d55307	80	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	167:e84263d55307	81
AnnaBridge	167:e84263d55307	82	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	167:e84263d55307	83
AnnaBridge	167:e84263d55307	84	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	167:e84263d55307	85	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	167:e84263d55307	86
AnnaBridge	167:e84263d55307	87	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	167:e84263d55307	88
AnnaBridge	167:e84263d55307	89	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	167:e84263d55307	90	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	167:e84263d55307	91
AnnaBridge	167:e84263d55307	92	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	167:e84263d55307	93
AnnaBridge	167:e84263d55307	94	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	167:e84263d55307	95	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	167:e84263d55307	96
AnnaBridge	167:e84263d55307	97	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	167:e84263d55307	98
AnnaBridge	167:e84263d55307	99	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	167:e84263d55307	100	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	167:e84263d55307	101
AnnaBridge	167:e84263d55307	102	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	167:e84263d55307	103
AnnaBridge	167:e84263d55307	104	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	167:e84263d55307	105	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	167:e84263d55307	106	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	167:e84263d55307	107
AnnaBridge	167:e84263d55307	108	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	167:e84263d55307	109
AnnaBridge	167:e84263d55307	110	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	167:e84263d55307	111	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	167:e84263d55307	112
AnnaBridge	167:e84263d55307	113	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	167:e84263d55307	114
AnnaBridge	167:e84263d55307	115	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	167:e84263d55307	116	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	167:e84263d55307	117
AnnaBridge	167:e84263d55307	118	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	167:e84263d55307	119
AnnaBridge	167:e84263d55307	120	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	167:e84263d55307	121	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	167:e84263d55307	122
AnnaBridge	167:e84263d55307	123	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	167:e84263d55307	124
AnnaBridge	167:e84263d55307	125	} LL_SPI_InitTypeDef;
AnnaBridge	167:e84263d55307	126
AnnaBridge	167:e84263d55307	127	/**
AnnaBridge	167:e84263d55307	128	* @}
AnnaBridge	167:e84263d55307	129	*/
AnnaBridge	167:e84263d55307	130	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	131
AnnaBridge	167:e84263d55307	132	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	133	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	167:e84263d55307	134	* @{
AnnaBridge	167:e84263d55307	135	*/
AnnaBridge	167:e84263d55307	136
AnnaBridge	167:e84263d55307	137	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	167:e84263d55307	138	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	167:e84263d55307	139	* @{
AnnaBridge	167:e84263d55307	140	*/
AnnaBridge	167:e84263d55307	141	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	167:e84263d55307	142	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	167:e84263d55307	143	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	167:e84263d55307	144	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	167:e84263d55307	145	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	167:e84263d55307	146	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	167:e84263d55307	147	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	167:e84263d55307	148	/**
AnnaBridge	167:e84263d55307	149	* @}
AnnaBridge	167:e84263d55307	150	*/
AnnaBridge	167:e84263d55307	151
AnnaBridge	167:e84263d55307	152	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	167:e84263d55307	153	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	167:e84263d55307	154	* @{
AnnaBridge	167:e84263d55307	155	*/
AnnaBridge	167:e84263d55307	156	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	167:e84263d55307	157	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	167:e84263d55307	158	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	167:e84263d55307	159	/**
AnnaBridge	167:e84263d55307	160	* @}
AnnaBridge	167:e84263d55307	161	*/
AnnaBridge	167:e84263d55307	162
AnnaBridge	167:e84263d55307	163	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	167:e84263d55307	164	* @{
AnnaBridge	167:e84263d55307	165	*/
AnnaBridge	167:e84263d55307	166	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	167:e84263d55307	167	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	167:e84263d55307	168	/**
AnnaBridge	167:e84263d55307	169	* @}
AnnaBridge	167:e84263d55307	170	*/
AnnaBridge	167:e84263d55307	171
AnnaBridge	167:e84263d55307	172	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	167:e84263d55307	173	* @{
AnnaBridge	167:e84263d55307	174	*/
AnnaBridge	167:e84263d55307	175	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
AnnaBridge	167:e84263d55307	176	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	167:e84263d55307	177	/**
AnnaBridge	167:e84263d55307	178	* @}
AnnaBridge	167:e84263d55307	179	*/
AnnaBridge	167:e84263d55307	180
AnnaBridge	167:e84263d55307	181	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	167:e84263d55307	182	* @{
AnnaBridge	167:e84263d55307	183	*/
AnnaBridge	167:e84263d55307	184	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	167:e84263d55307	185	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	167:e84263d55307	186	/**
AnnaBridge	167:e84263d55307	187	* @}
AnnaBridge	167:e84263d55307	188	*/
AnnaBridge	167:e84263d55307	189
AnnaBridge	167:e84263d55307	190	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	167:e84263d55307	191	* @{
AnnaBridge	167:e84263d55307	192	*/
AnnaBridge	167:e84263d55307	193	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	167:e84263d55307	194	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	167:e84263d55307	195	/**
AnnaBridge	167:e84263d55307	196	* @}
AnnaBridge	167:e84263d55307	197	*/
AnnaBridge	167:e84263d55307	198
AnnaBridge	167:e84263d55307	199	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	167:e84263d55307	200	* @{
AnnaBridge	167:e84263d55307	201	*/
AnnaBridge	167:e84263d55307	202	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	167:e84263d55307	203	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	167:e84263d55307	204	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	167:e84263d55307	205	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	167:e84263d55307	206	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	167:e84263d55307	207	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	167:e84263d55307	208	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	167:e84263d55307	209	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	167:e84263d55307	210	/**
AnnaBridge	167:e84263d55307	211	* @}
AnnaBridge	167:e84263d55307	212	*/
AnnaBridge	167:e84263d55307	213
AnnaBridge	167:e84263d55307	214	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	167:e84263d55307	215	* @{
AnnaBridge	167:e84263d55307	216	*/
AnnaBridge	167:e84263d55307	217	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	167:e84263d55307	218	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	167:e84263d55307	219	/**
AnnaBridge	167:e84263d55307	220	* @}
AnnaBridge	167:e84263d55307	221	*/
AnnaBridge	167:e84263d55307	222
AnnaBridge	167:e84263d55307	223	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	167:e84263d55307	224	* @{
AnnaBridge	167:e84263d55307	225	*/
AnnaBridge	167:e84263d55307	226	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	167:e84263d55307	227	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	167:e84263d55307	228	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	167:e84263d55307	229	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	167:e84263d55307	230	/**
AnnaBridge	167:e84263d55307	231	* @}
AnnaBridge	167:e84263d55307	232	*/
AnnaBridge	167:e84263d55307	233
AnnaBridge	167:e84263d55307	234	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	167:e84263d55307	235	* @{
AnnaBridge	167:e84263d55307	236	*/
AnnaBridge	167:e84263d55307	237	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	167:e84263d55307	238	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	167:e84263d55307	239	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	167:e84263d55307	240	/**
AnnaBridge	167:e84263d55307	241	* @}
AnnaBridge	167:e84263d55307	242	*/
AnnaBridge	167:e84263d55307	243
AnnaBridge	167:e84263d55307	244	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	167:e84263d55307	245	* @{
AnnaBridge	167:e84263d55307	246	*/
AnnaBridge	167:e84263d55307	247	#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /!< Data length for SPI transfer: 8 bits /
AnnaBridge	167:e84263d55307	248	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	167:e84263d55307	249	/**
AnnaBridge	167:e84263d55307	250	* @}
AnnaBridge	167:e84263d55307	251	*/
AnnaBridge	167:e84263d55307	252	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	253
AnnaBridge	167:e84263d55307	254	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	167:e84263d55307	255	* @{
AnnaBridge	167:e84263d55307	256	*/
AnnaBridge	167:e84263d55307	257	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	167:e84263d55307	258	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	167:e84263d55307	259	/**
AnnaBridge	167:e84263d55307	260	* @}
AnnaBridge	167:e84263d55307	261	*/
AnnaBridge	167:e84263d55307	262	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	263
AnnaBridge	167:e84263d55307	264	/**
AnnaBridge	167:e84263d55307	265	* @}
AnnaBridge	167:e84263d55307	266	*/
AnnaBridge	167:e84263d55307	267
AnnaBridge	167:e84263d55307	268	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	269	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	167:e84263d55307	270	* @{
AnnaBridge	167:e84263d55307	271	*/
AnnaBridge	167:e84263d55307	272
AnnaBridge	167:e84263d55307	273	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	167:e84263d55307	274	* @{
AnnaBridge	167:e84263d55307	275	*/
AnnaBridge	167:e84263d55307	276
AnnaBridge	167:e84263d55307	277	/**
AnnaBridge	167:e84263d55307	278	* @brief Write a value in SPI register
AnnaBridge	167:e84263d55307	279	* @param __INSTANCE__ SPI Instance
AnnaBridge	167:e84263d55307	280	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	281	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	282	* @retval None
AnnaBridge	167:e84263d55307	283	*/
AnnaBridge	167:e84263d55307	284	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	285
AnnaBridge	167:e84263d55307	286	/**
AnnaBridge	167:e84263d55307	287	* @brief Read a value in SPI register
AnnaBridge	167:e84263d55307	288	* @param __INSTANCE__ SPI Instance
AnnaBridge	167:e84263d55307	289	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	290	* @retval Register value
AnnaBridge	167:e84263d55307	291	*/
AnnaBridge	167:e84263d55307	292	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	167:e84263d55307	293	/**
AnnaBridge	167:e84263d55307	294	* @}
AnnaBridge	167:e84263d55307	295	*/
AnnaBridge	167:e84263d55307	296
AnnaBridge	167:e84263d55307	297	/**
AnnaBridge	167:e84263d55307	298	* @}
AnnaBridge	167:e84263d55307	299	*/
AnnaBridge	167:e84263d55307	300
AnnaBridge	167:e84263d55307	301	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	302	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	167:e84263d55307	303	* @{
AnnaBridge	167:e84263d55307	304	*/
AnnaBridge	167:e84263d55307	305
AnnaBridge	167:e84263d55307	306	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	167:e84263d55307	307	* @{
AnnaBridge	167:e84263d55307	308	*/
AnnaBridge	167:e84263d55307	309
AnnaBridge	167:e84263d55307	310	/**
AnnaBridge	167:e84263d55307	311	* @brief Enable SPI peripheral
AnnaBridge	167:e84263d55307	312	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	167:e84263d55307	313	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	314	* @retval None
AnnaBridge	167:e84263d55307	315	*/
AnnaBridge	167:e84263d55307	316	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	317	{
AnnaBridge	167:e84263d55307	318	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	167:e84263d55307	319	}
AnnaBridge	167:e84263d55307	320
AnnaBridge	167:e84263d55307	321	/**
AnnaBridge	167:e84263d55307	322	* @brief Disable SPI peripheral
AnnaBridge	167:e84263d55307	323	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	167:e84263d55307	324	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	167:e84263d55307	325	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	326	* @retval None
AnnaBridge	167:e84263d55307	327	*/
AnnaBridge	167:e84263d55307	328	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	329	{
AnnaBridge	167:e84263d55307	330	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	167:e84263d55307	331	}
AnnaBridge	167:e84263d55307	332
AnnaBridge	167:e84263d55307	333	/**
AnnaBridge	167:e84263d55307	334	* @brief Check if SPI peripheral is enabled
AnnaBridge	167:e84263d55307	335	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	167:e84263d55307	336	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	337	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	338	*/
AnnaBridge	167:e84263d55307	339	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	340	{
AnnaBridge	167:e84263d55307	341	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	167:e84263d55307	342	}
AnnaBridge	167:e84263d55307	343
AnnaBridge	167:e84263d55307	344	/**
AnnaBridge	167:e84263d55307	345	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	167:e84263d55307	346	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	167:e84263d55307	347	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	167:e84263d55307	348	* CR1 SSI LL_SPI_SetMode
AnnaBridge	167:e84263d55307	349	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	350	* @param Mode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	351	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	167:e84263d55307	352	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	167:e84263d55307	353	* @retval None
AnnaBridge	167:e84263d55307	354	*/
AnnaBridge	167:e84263d55307	355	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	167:e84263d55307	356	{
AnnaBridge	167:e84263d55307	357	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	167:e84263d55307	358	}
AnnaBridge	167:e84263d55307	359
AnnaBridge	167:e84263d55307	360	/**
AnnaBridge	167:e84263d55307	361	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	167:e84263d55307	362	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	167:e84263d55307	363	* CR1 SSI LL_SPI_GetMode
AnnaBridge	167:e84263d55307	364	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	365	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	366	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	167:e84263d55307	367	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	167:e84263d55307	368	*/
AnnaBridge	167:e84263d55307	369	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	370	{
AnnaBridge	167:e84263d55307	371	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	167:e84263d55307	372	}
AnnaBridge	167:e84263d55307	373
AnnaBridge	167:e84263d55307	374	/**
AnnaBridge	167:e84263d55307	375	* @brief Set serial protocol used
AnnaBridge	167:e84263d55307	376	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	167:e84263d55307	377	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	167:e84263d55307	378	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	379	* @param Standard This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	380	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	167:e84263d55307	381	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	167:e84263d55307	382	* @retval None
AnnaBridge	167:e84263d55307	383	*/
AnnaBridge	167:e84263d55307	384	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	167:e84263d55307	385	{
AnnaBridge	167:e84263d55307	386	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	167:e84263d55307	387	}
AnnaBridge	167:e84263d55307	388
AnnaBridge	167:e84263d55307	389	/**
AnnaBridge	167:e84263d55307	390	* @brief Get serial protocol used
AnnaBridge	167:e84263d55307	391	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	167:e84263d55307	392	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	393	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	394	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	167:e84263d55307	395	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	167:e84263d55307	396	*/
AnnaBridge	167:e84263d55307	397	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	398	{
AnnaBridge	167:e84263d55307	399	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	167:e84263d55307	400	}
AnnaBridge	167:e84263d55307	401
AnnaBridge	167:e84263d55307	402	/**
AnnaBridge	167:e84263d55307	403	* @brief Set clock phase
AnnaBridge	167:e84263d55307	404	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	167:e84263d55307	405	* This bit is not used in SPI TI mode.
AnnaBridge	167:e84263d55307	406	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	167:e84263d55307	407	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	408	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	409	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	167:e84263d55307	410	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	167:e84263d55307	411	* @retval None
AnnaBridge	167:e84263d55307	412	*/
AnnaBridge	167:e84263d55307	413	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	167:e84263d55307	414	{
AnnaBridge	167:e84263d55307	415	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	167:e84263d55307	416	}
AnnaBridge	167:e84263d55307	417
AnnaBridge	167:e84263d55307	418	/**
AnnaBridge	167:e84263d55307	419	* @brief Get clock phase
AnnaBridge	167:e84263d55307	420	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	167:e84263d55307	421	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	422	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	423	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	167:e84263d55307	424	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	167:e84263d55307	425	*/
AnnaBridge	167:e84263d55307	426	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	427	{
AnnaBridge	167:e84263d55307	428	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	167:e84263d55307	429	}
AnnaBridge	167:e84263d55307	430
AnnaBridge	167:e84263d55307	431	/**
AnnaBridge	167:e84263d55307	432	* @brief Set clock polarity
AnnaBridge	167:e84263d55307	433	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	167:e84263d55307	434	* This bit is not used in SPI TI mode.
AnnaBridge	167:e84263d55307	435	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	167:e84263d55307	436	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	437	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	438	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	167:e84263d55307	439	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	167:e84263d55307	440	* @retval None
AnnaBridge	167:e84263d55307	441	*/
AnnaBridge	167:e84263d55307	442	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	167:e84263d55307	443	{
AnnaBridge	167:e84263d55307	444	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	167:e84263d55307	445	}
AnnaBridge	167:e84263d55307	446
AnnaBridge	167:e84263d55307	447	/**
AnnaBridge	167:e84263d55307	448	* @brief Get clock polarity
AnnaBridge	167:e84263d55307	449	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	167:e84263d55307	450	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	451	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	452	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	167:e84263d55307	453	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	167:e84263d55307	454	*/
AnnaBridge	167:e84263d55307	455	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	456	{
AnnaBridge	167:e84263d55307	457	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	167:e84263d55307	458	}
AnnaBridge	167:e84263d55307	459
AnnaBridge	167:e84263d55307	460	/**
AnnaBridge	167:e84263d55307	461	* @brief Set baud rate prescaler
AnnaBridge	167:e84263d55307	462	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	167:e84263d55307	463	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	167:e84263d55307	464	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	465	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	466	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	167:e84263d55307	467	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	167:e84263d55307	468	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	167:e84263d55307	469	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	167:e84263d55307	470	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	167:e84263d55307	471	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	167:e84263d55307	472	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	167:e84263d55307	473	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	167:e84263d55307	474	* @retval None
AnnaBridge	167:e84263d55307	475	*/
AnnaBridge	167:e84263d55307	476	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	167:e84263d55307	477	{
AnnaBridge	167:e84263d55307	478	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	167:e84263d55307	479	}
AnnaBridge	167:e84263d55307	480
AnnaBridge	167:e84263d55307	481	/**
AnnaBridge	167:e84263d55307	482	* @brief Get baud rate prescaler
AnnaBridge	167:e84263d55307	483	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	167:e84263d55307	484	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	485	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	486	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	167:e84263d55307	487	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	167:e84263d55307	488	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	167:e84263d55307	489	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	167:e84263d55307	490	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	167:e84263d55307	491	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	167:e84263d55307	492	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	167:e84263d55307	493	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	167:e84263d55307	494	*/
AnnaBridge	167:e84263d55307	495	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	496	{
AnnaBridge	167:e84263d55307	497	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	167:e84263d55307	498	}
AnnaBridge	167:e84263d55307	499
AnnaBridge	167:e84263d55307	500	/**
AnnaBridge	167:e84263d55307	501	* @brief Set transfer bit order
AnnaBridge	167:e84263d55307	502	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	167:e84263d55307	503	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	167:e84263d55307	504	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	505	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	506	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	167:e84263d55307	507	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	167:e84263d55307	508	* @retval None
AnnaBridge	167:e84263d55307	509	*/
AnnaBridge	167:e84263d55307	510	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	167:e84263d55307	511	{
AnnaBridge	167:e84263d55307	512	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	167:e84263d55307	513	}
AnnaBridge	167:e84263d55307	514
AnnaBridge	167:e84263d55307	515	/**
AnnaBridge	167:e84263d55307	516	* @brief Get transfer bit order
AnnaBridge	167:e84263d55307	517	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	167:e84263d55307	518	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	519	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	520	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	167:e84263d55307	521	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	167:e84263d55307	522	*/
AnnaBridge	167:e84263d55307	523	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	524	{
AnnaBridge	167:e84263d55307	525	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	167:e84263d55307	526	}
AnnaBridge	167:e84263d55307	527
AnnaBridge	167:e84263d55307	528	/**
AnnaBridge	167:e84263d55307	529	* @brief Set transfer direction mode
AnnaBridge	167:e84263d55307	530	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	167:e84263d55307	531	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	167:e84263d55307	532	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	167:e84263d55307	533	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	167:e84263d55307	534	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	167:e84263d55307	535	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	536	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	537	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	167:e84263d55307	538	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	167:e84263d55307	539	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	167:e84263d55307	540	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	167:e84263d55307	541	* @retval None
AnnaBridge	167:e84263d55307	542	*/
AnnaBridge	167:e84263d55307	543	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	167:e84263d55307	544	{
AnnaBridge	167:e84263d55307	545	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	167:e84263d55307	546	}
AnnaBridge	167:e84263d55307	547
AnnaBridge	167:e84263d55307	548	/**
AnnaBridge	167:e84263d55307	549	* @brief Get transfer direction mode
AnnaBridge	167:e84263d55307	550	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	167:e84263d55307	551	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	167:e84263d55307	552	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	167:e84263d55307	553	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	554	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	555	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	167:e84263d55307	556	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	167:e84263d55307	557	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	167:e84263d55307	558	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	167:e84263d55307	559	*/
AnnaBridge	167:e84263d55307	560	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	561	{
AnnaBridge	167:e84263d55307	562	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	167:e84263d55307	563	}
AnnaBridge	167:e84263d55307	564
AnnaBridge	167:e84263d55307	565	/**
AnnaBridge	167:e84263d55307	566	* @brief Set frame data width
AnnaBridge	167:e84263d55307	567	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
AnnaBridge	167:e84263d55307	568	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	569	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	570	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	167:e84263d55307	571	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	167:e84263d55307	572	* @retval None
AnnaBridge	167:e84263d55307	573	*/
AnnaBridge	167:e84263d55307	574	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	167:e84263d55307	575	{
AnnaBridge	167:e84263d55307	576	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
AnnaBridge	167:e84263d55307	577	}
AnnaBridge	167:e84263d55307	578
AnnaBridge	167:e84263d55307	579	/**
AnnaBridge	167:e84263d55307	580	* @brief Get frame data width
AnnaBridge	167:e84263d55307	581	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
AnnaBridge	167:e84263d55307	582	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	583	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	584	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	167:e84263d55307	585	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	167:e84263d55307	586	*/
AnnaBridge	167:e84263d55307	587	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	588	{
AnnaBridge	167:e84263d55307	589	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
AnnaBridge	167:e84263d55307	590	}
AnnaBridge	167:e84263d55307	591
AnnaBridge	167:e84263d55307	592	/**
AnnaBridge	167:e84263d55307	593	* @}
AnnaBridge	167:e84263d55307	594	*/
AnnaBridge	167:e84263d55307	595
AnnaBridge	167:e84263d55307	596	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	167:e84263d55307	597	* @{
AnnaBridge	167:e84263d55307	598	*/
AnnaBridge	167:e84263d55307	599
AnnaBridge	167:e84263d55307	600	/**
AnnaBridge	167:e84263d55307	601	* @brief Enable CRC
AnnaBridge	167:e84263d55307	602	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	167:e84263d55307	603	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	167:e84263d55307	604	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	605	* @retval None
AnnaBridge	167:e84263d55307	606	*/
AnnaBridge	167:e84263d55307	607	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	608	{
AnnaBridge	167:e84263d55307	609	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	167:e84263d55307	610	}
AnnaBridge	167:e84263d55307	611
AnnaBridge	167:e84263d55307	612	/**
AnnaBridge	167:e84263d55307	613	* @brief Disable CRC
AnnaBridge	167:e84263d55307	614	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	167:e84263d55307	615	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	167:e84263d55307	616	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	617	* @retval None
AnnaBridge	167:e84263d55307	618	*/
AnnaBridge	167:e84263d55307	619	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	620	{
AnnaBridge	167:e84263d55307	621	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	167:e84263d55307	622	}
AnnaBridge	167:e84263d55307	623
AnnaBridge	167:e84263d55307	624	/**
AnnaBridge	167:e84263d55307	625	* @brief Check if CRC is enabled
AnnaBridge	167:e84263d55307	626	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	167:e84263d55307	627	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	167:e84263d55307	628	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	629	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	630	*/
AnnaBridge	167:e84263d55307	631	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	632	{
AnnaBridge	167:e84263d55307	633	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	167:e84263d55307	634	}
AnnaBridge	167:e84263d55307	635
AnnaBridge	167:e84263d55307	636	/**
AnnaBridge	167:e84263d55307	637	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	167:e84263d55307	638	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	167:e84263d55307	639	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	167:e84263d55307	640	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	641	* @retval None
AnnaBridge	167:e84263d55307	642	*/
AnnaBridge	167:e84263d55307	643	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	644	{
AnnaBridge	167:e84263d55307	645	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	167:e84263d55307	646	}
AnnaBridge	167:e84263d55307	647
AnnaBridge	167:e84263d55307	648	/**
AnnaBridge	167:e84263d55307	649	* @brief Set polynomial for CRC calculation
AnnaBridge	167:e84263d55307	650	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	167:e84263d55307	651	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	652	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	167:e84263d55307	653	* @retval None
AnnaBridge	167:e84263d55307	654	*/
AnnaBridge	167:e84263d55307	655	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	167:e84263d55307	656	{
AnnaBridge	167:e84263d55307	657	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	167:e84263d55307	658	}
AnnaBridge	167:e84263d55307	659
AnnaBridge	167:e84263d55307	660	/**
AnnaBridge	167:e84263d55307	661	* @brief Get polynomial for CRC calculation
AnnaBridge	167:e84263d55307	662	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	167:e84263d55307	663	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	664	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	167:e84263d55307	665	*/
AnnaBridge	167:e84263d55307	666	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	667	{
AnnaBridge	167:e84263d55307	668	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	167:e84263d55307	669	}
AnnaBridge	167:e84263d55307	670
AnnaBridge	167:e84263d55307	671	/**
AnnaBridge	167:e84263d55307	672	* @brief Get Rx CRC
AnnaBridge	167:e84263d55307	673	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	167:e84263d55307	674	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	675	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	167:e84263d55307	676	*/
AnnaBridge	167:e84263d55307	677	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	678	{
AnnaBridge	167:e84263d55307	679	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	167:e84263d55307	680	}
AnnaBridge	167:e84263d55307	681
AnnaBridge	167:e84263d55307	682	/**
AnnaBridge	167:e84263d55307	683	* @brief Get Tx CRC
AnnaBridge	167:e84263d55307	684	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	167:e84263d55307	685	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	686	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	167:e84263d55307	687	*/
AnnaBridge	167:e84263d55307	688	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	689	{
AnnaBridge	167:e84263d55307	690	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	167:e84263d55307	691	}
AnnaBridge	167:e84263d55307	692
AnnaBridge	167:e84263d55307	693	/**
AnnaBridge	167:e84263d55307	694	* @}
AnnaBridge	167:e84263d55307	695	*/
AnnaBridge	167:e84263d55307	696
AnnaBridge	167:e84263d55307	697	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	167:e84263d55307	698	* @{
AnnaBridge	167:e84263d55307	699	*/
AnnaBridge	167:e84263d55307	700
AnnaBridge	167:e84263d55307	701	/**
AnnaBridge	167:e84263d55307	702	* @brief Set NSS mode
AnnaBridge	167:e84263d55307	703	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	167:e84263d55307	704	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	167:e84263d55307	705	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	167:e84263d55307	706	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	707	* @param NSS This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	708	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	167:e84263d55307	709	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	167:e84263d55307	710	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	167:e84263d55307	711	* @retval None
AnnaBridge	167:e84263d55307	712	*/
AnnaBridge	167:e84263d55307	713	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	167:e84263d55307	714	{
AnnaBridge	167:e84263d55307	715	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	167:e84263d55307	716	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	167:e84263d55307	717	}
AnnaBridge	167:e84263d55307	718
AnnaBridge	167:e84263d55307	719	/**
AnnaBridge	167:e84263d55307	720	* @brief Get NSS mode
AnnaBridge	167:e84263d55307	721	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	167:e84263d55307	722	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	167:e84263d55307	723	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	724	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	725	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	167:e84263d55307	726	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	167:e84263d55307	727	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	167:e84263d55307	728	*/
AnnaBridge	167:e84263d55307	729	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	730	{
AnnaBridge	167:e84263d55307	731	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	167:e84263d55307	732	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	167:e84263d55307	733	return (Ssm \| Ssoe);
AnnaBridge	167:e84263d55307	734	}
AnnaBridge	167:e84263d55307	735
AnnaBridge	167:e84263d55307	736	/**
AnnaBridge	167:e84263d55307	737	* @}
AnnaBridge	167:e84263d55307	738	*/
AnnaBridge	167:e84263d55307	739
AnnaBridge	167:e84263d55307	740	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	167:e84263d55307	741	* @{
AnnaBridge	167:e84263d55307	742	*/
AnnaBridge	167:e84263d55307	743
AnnaBridge	167:e84263d55307	744	/**
AnnaBridge	167:e84263d55307	745	* @brief Check if Rx buffer is not empty
AnnaBridge	167:e84263d55307	746	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	167:e84263d55307	747	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	748	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	749	*/
AnnaBridge	167:e84263d55307	750	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	751	{
AnnaBridge	167:e84263d55307	752	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	167:e84263d55307	753	}
AnnaBridge	167:e84263d55307	754
AnnaBridge	167:e84263d55307	755	/**
AnnaBridge	167:e84263d55307	756	* @brief Check if Tx buffer is empty
AnnaBridge	167:e84263d55307	757	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	167:e84263d55307	758	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	759	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	760	*/
AnnaBridge	167:e84263d55307	761	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	762	{
AnnaBridge	167:e84263d55307	763	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	167:e84263d55307	764	}
AnnaBridge	167:e84263d55307	765
AnnaBridge	167:e84263d55307	766	/**
AnnaBridge	167:e84263d55307	767	* @brief Get CRC error flag
AnnaBridge	167:e84263d55307	768	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	167:e84263d55307	769	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	770	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	771	*/
AnnaBridge	167:e84263d55307	772	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	773	{
AnnaBridge	167:e84263d55307	774	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	167:e84263d55307	775	}
AnnaBridge	167:e84263d55307	776
AnnaBridge	167:e84263d55307	777	/**
AnnaBridge	167:e84263d55307	778	* @brief Get mode fault error flag
AnnaBridge	167:e84263d55307	779	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	167:e84263d55307	780	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	781	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	782	*/
AnnaBridge	167:e84263d55307	783	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	784	{
AnnaBridge	167:e84263d55307	785	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	167:e84263d55307	786	}
AnnaBridge	167:e84263d55307	787
AnnaBridge	167:e84263d55307	788	/**
AnnaBridge	167:e84263d55307	789	* @brief Get overrun error flag
AnnaBridge	167:e84263d55307	790	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	167:e84263d55307	791	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	792	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	793	*/
AnnaBridge	167:e84263d55307	794	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	795	{
AnnaBridge	167:e84263d55307	796	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	167:e84263d55307	797	}
AnnaBridge	167:e84263d55307	798
AnnaBridge	167:e84263d55307	799	/**
AnnaBridge	167:e84263d55307	800	* @brief Get busy flag
AnnaBridge	167:e84263d55307	801	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	167:e84263d55307	802	* -When the SPI is correctly disabled
AnnaBridge	167:e84263d55307	803	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	167:e84263d55307	804	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	167:e84263d55307	805	* sent
AnnaBridge	167:e84263d55307	806	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	167:e84263d55307	807	* each data transfer.
AnnaBridge	167:e84263d55307	808	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	167:e84263d55307	809	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	810	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	811	*/
AnnaBridge	167:e84263d55307	812	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	813	{
AnnaBridge	167:e84263d55307	814	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	167:e84263d55307	815	}
AnnaBridge	167:e84263d55307	816
AnnaBridge	167:e84263d55307	817	/**
AnnaBridge	167:e84263d55307	818	* @brief Get frame format error flag
AnnaBridge	167:e84263d55307	819	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	167:e84263d55307	820	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	821	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	822	*/
AnnaBridge	167:e84263d55307	823	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	824	{
AnnaBridge	167:e84263d55307	825	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	167:e84263d55307	826	}
AnnaBridge	167:e84263d55307	827
AnnaBridge	167:e84263d55307	828	/**
AnnaBridge	167:e84263d55307	829	* @brief Clear CRC error flag
AnnaBridge	167:e84263d55307	830	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	167:e84263d55307	831	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	832	* @retval None
AnnaBridge	167:e84263d55307	833	*/
AnnaBridge	167:e84263d55307	834	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	835	{
AnnaBridge	167:e84263d55307	836	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	167:e84263d55307	837	}
AnnaBridge	167:e84263d55307	838
AnnaBridge	167:e84263d55307	839	/**
AnnaBridge	167:e84263d55307	840	* @brief Clear mode fault error flag
AnnaBridge	167:e84263d55307	841	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	167:e84263d55307	842	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	167:e84263d55307	843	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	167:e84263d55307	844	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	845	* @retval None
AnnaBridge	167:e84263d55307	846	*/
AnnaBridge	167:e84263d55307	847	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	848	{
AnnaBridge	167:e84263d55307	849	__IO uint32_t tmpreg;
AnnaBridge	167:e84263d55307	850	tmpreg = SPIx->SR;
AnnaBridge	167:e84263d55307	851	(void) tmpreg;
AnnaBridge	167:e84263d55307	852	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	167:e84263d55307	853	(void) tmpreg;
AnnaBridge	167:e84263d55307	854	}
AnnaBridge	167:e84263d55307	855
AnnaBridge	167:e84263d55307	856	/**
AnnaBridge	167:e84263d55307	857	* @brief Clear overrun error flag
AnnaBridge	167:e84263d55307	858	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	167:e84263d55307	859	* register followed by a read access to the SPIx_SR register
AnnaBridge	167:e84263d55307	860	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	167:e84263d55307	861	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	862	* @retval None
AnnaBridge	167:e84263d55307	863	*/
AnnaBridge	167:e84263d55307	864	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	865	{
AnnaBridge	167:e84263d55307	866	__IO uint32_t tmpreg;
AnnaBridge	167:e84263d55307	867	tmpreg = SPIx->DR;
AnnaBridge	167:e84263d55307	868	(void) tmpreg;
AnnaBridge	167:e84263d55307	869	tmpreg = SPIx->SR;
AnnaBridge	167:e84263d55307	870	(void) tmpreg;
AnnaBridge	167:e84263d55307	871	}
AnnaBridge	167:e84263d55307	872
AnnaBridge	167:e84263d55307	873	/**
AnnaBridge	167:e84263d55307	874	* @brief Clear frame format error flag
AnnaBridge	167:e84263d55307	875	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	167:e84263d55307	876	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	167:e84263d55307	877	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	878	* @retval None
AnnaBridge	167:e84263d55307	879	*/
AnnaBridge	167:e84263d55307	880	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	881	{
AnnaBridge	167:e84263d55307	882	__IO uint32_t tmpreg;
AnnaBridge	167:e84263d55307	883	tmpreg = SPIx->SR;
AnnaBridge	167:e84263d55307	884	(void) tmpreg;
AnnaBridge	167:e84263d55307	885	}
AnnaBridge	167:e84263d55307	886
AnnaBridge	167:e84263d55307	887	/**
AnnaBridge	167:e84263d55307	888	* @}
AnnaBridge	167:e84263d55307	889	*/
AnnaBridge	167:e84263d55307	890
AnnaBridge	167:e84263d55307	891	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	167:e84263d55307	892	* @{
AnnaBridge	167:e84263d55307	893	*/
AnnaBridge	167:e84263d55307	894
AnnaBridge	167:e84263d55307	895	/**
AnnaBridge	167:e84263d55307	896	* @brief Enable error interrupt
AnnaBridge	167:e84263d55307	897	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	167:e84263d55307	898	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	167:e84263d55307	899	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	900	* @retval None
AnnaBridge	167:e84263d55307	901	*/
AnnaBridge	167:e84263d55307	902	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	903	{
AnnaBridge	167:e84263d55307	904	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	167:e84263d55307	905	}
AnnaBridge	167:e84263d55307	906
AnnaBridge	167:e84263d55307	907	/**
AnnaBridge	167:e84263d55307	908	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	167:e84263d55307	909	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	167:e84263d55307	910	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	911	* @retval None
AnnaBridge	167:e84263d55307	912	*/
AnnaBridge	167:e84263d55307	913	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	914	{
AnnaBridge	167:e84263d55307	915	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	167:e84263d55307	916	}
AnnaBridge	167:e84263d55307	917
AnnaBridge	167:e84263d55307	918	/**
AnnaBridge	167:e84263d55307	919	* @brief Enable Tx buffer empty interrupt
AnnaBridge	167:e84263d55307	920	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	167:e84263d55307	921	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	922	* @retval None
AnnaBridge	167:e84263d55307	923	*/
AnnaBridge	167:e84263d55307	924	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	925	{
AnnaBridge	167:e84263d55307	926	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	167:e84263d55307	927	}
AnnaBridge	167:e84263d55307	928
AnnaBridge	167:e84263d55307	929	/**
AnnaBridge	167:e84263d55307	930	* @brief Disable error interrupt
AnnaBridge	167:e84263d55307	931	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	167:e84263d55307	932	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	167:e84263d55307	933	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	934	* @retval None
AnnaBridge	167:e84263d55307	935	*/
AnnaBridge	167:e84263d55307	936	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	937	{
AnnaBridge	167:e84263d55307	938	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	167:e84263d55307	939	}
AnnaBridge	167:e84263d55307	940
AnnaBridge	167:e84263d55307	941	/**
AnnaBridge	167:e84263d55307	942	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	167:e84263d55307	943	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	167:e84263d55307	944	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	945	* @retval None
AnnaBridge	167:e84263d55307	946	*/
AnnaBridge	167:e84263d55307	947	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	948	{
AnnaBridge	167:e84263d55307	949	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	167:e84263d55307	950	}
AnnaBridge	167:e84263d55307	951
AnnaBridge	167:e84263d55307	952	/**
AnnaBridge	167:e84263d55307	953	* @brief Disable Tx buffer empty interrupt
AnnaBridge	167:e84263d55307	954	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	167:e84263d55307	955	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	956	* @retval None
AnnaBridge	167:e84263d55307	957	*/
AnnaBridge	167:e84263d55307	958	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	959	{
AnnaBridge	167:e84263d55307	960	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	167:e84263d55307	961	}
AnnaBridge	167:e84263d55307	962
AnnaBridge	167:e84263d55307	963	/**
AnnaBridge	167:e84263d55307	964	* @brief Check if error interrupt is enabled
AnnaBridge	167:e84263d55307	965	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	167:e84263d55307	966	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	967	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	968	*/
AnnaBridge	167:e84263d55307	969	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	970	{
AnnaBridge	167:e84263d55307	971	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	167:e84263d55307	972	}
AnnaBridge	167:e84263d55307	973
AnnaBridge	167:e84263d55307	974	/**
AnnaBridge	167:e84263d55307	975	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	167:e84263d55307	976	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	167:e84263d55307	977	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	978	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	979	*/
AnnaBridge	167:e84263d55307	980	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	981	{
AnnaBridge	167:e84263d55307	982	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	167:e84263d55307	983	}
AnnaBridge	167:e84263d55307	984
AnnaBridge	167:e84263d55307	985	/**
AnnaBridge	167:e84263d55307	986	* @brief Check if Tx buffer empty interrupt
AnnaBridge	167:e84263d55307	987	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	167:e84263d55307	988	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	989	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	990	*/
AnnaBridge	167:e84263d55307	991	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	992	{
AnnaBridge	167:e84263d55307	993	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	167:e84263d55307	994	}
AnnaBridge	167:e84263d55307	995
AnnaBridge	167:e84263d55307	996	/**
AnnaBridge	167:e84263d55307	997	* @}
AnnaBridge	167:e84263d55307	998	*/
AnnaBridge	167:e84263d55307	999
AnnaBridge	167:e84263d55307	1000	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	167:e84263d55307	1001	* @{
AnnaBridge	167:e84263d55307	1002	*/
AnnaBridge	167:e84263d55307	1003
AnnaBridge	167:e84263d55307	1004	/**
AnnaBridge	167:e84263d55307	1005	* @brief Enable DMA Rx
AnnaBridge	167:e84263d55307	1006	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	167:e84263d55307	1007	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1008	* @retval None
AnnaBridge	167:e84263d55307	1009	*/
AnnaBridge	167:e84263d55307	1010	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1011	{
AnnaBridge	167:e84263d55307	1012	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	167:e84263d55307	1013	}
AnnaBridge	167:e84263d55307	1014
AnnaBridge	167:e84263d55307	1015	/**
AnnaBridge	167:e84263d55307	1016	* @brief Disable DMA Rx
AnnaBridge	167:e84263d55307	1017	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	167:e84263d55307	1018	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1019	* @retval None
AnnaBridge	167:e84263d55307	1020	*/
AnnaBridge	167:e84263d55307	1021	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1022	{
AnnaBridge	167:e84263d55307	1023	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	167:e84263d55307	1024	}
AnnaBridge	167:e84263d55307	1025
AnnaBridge	167:e84263d55307	1026	/**
AnnaBridge	167:e84263d55307	1027	* @brief Check if DMA Rx is enabled
AnnaBridge	167:e84263d55307	1028	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	167:e84263d55307	1029	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1030	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1031	*/
AnnaBridge	167:e84263d55307	1032	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1033	{
AnnaBridge	167:e84263d55307	1034	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	167:e84263d55307	1035	}
AnnaBridge	167:e84263d55307	1036
AnnaBridge	167:e84263d55307	1037	/**
AnnaBridge	167:e84263d55307	1038	* @brief Enable DMA Tx
AnnaBridge	167:e84263d55307	1039	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	167:e84263d55307	1040	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1041	* @retval None
AnnaBridge	167:e84263d55307	1042	*/
AnnaBridge	167:e84263d55307	1043	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1044	{
AnnaBridge	167:e84263d55307	1045	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	167:e84263d55307	1046	}
AnnaBridge	167:e84263d55307	1047
AnnaBridge	167:e84263d55307	1048	/**
AnnaBridge	167:e84263d55307	1049	* @brief Disable DMA Tx
AnnaBridge	167:e84263d55307	1050	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	167:e84263d55307	1051	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1052	* @retval None
AnnaBridge	167:e84263d55307	1053	*/
AnnaBridge	167:e84263d55307	1054	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1055	{
AnnaBridge	167:e84263d55307	1056	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	167:e84263d55307	1057	}
AnnaBridge	167:e84263d55307	1058
AnnaBridge	167:e84263d55307	1059	/**
AnnaBridge	167:e84263d55307	1060	* @brief Check if DMA Tx is enabled
AnnaBridge	167:e84263d55307	1061	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	167:e84263d55307	1062	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1063	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1064	*/
AnnaBridge	167:e84263d55307	1065	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1066	{
AnnaBridge	167:e84263d55307	1067	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	167:e84263d55307	1068	}
AnnaBridge	167:e84263d55307	1069
AnnaBridge	167:e84263d55307	1070	/**
AnnaBridge	167:e84263d55307	1071	* @brief Get the data register address used for DMA transfer
AnnaBridge	167:e84263d55307	1072	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	167:e84263d55307	1073	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1074	* @retval Address of data register
AnnaBridge	167:e84263d55307	1075	*/
AnnaBridge	167:e84263d55307	1076	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1077	{
AnnaBridge	167:e84263d55307	1078	return (uint32_t) & (SPIx->DR);
AnnaBridge	167:e84263d55307	1079	}
AnnaBridge	167:e84263d55307	1080
AnnaBridge	167:e84263d55307	1081	/**
AnnaBridge	167:e84263d55307	1082	* @}
AnnaBridge	167:e84263d55307	1083	*/
AnnaBridge	167:e84263d55307	1084
AnnaBridge	167:e84263d55307	1085	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	167:e84263d55307	1086	* @{
AnnaBridge	167:e84263d55307	1087	*/
AnnaBridge	167:e84263d55307	1088
AnnaBridge	167:e84263d55307	1089	/**
AnnaBridge	167:e84263d55307	1090	* @brief Read 8-Bits in the data register
AnnaBridge	167:e84263d55307	1091	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	167:e84263d55307	1092	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1093	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1094	*/
AnnaBridge	167:e84263d55307	1095	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1096	{
AnnaBridge	167:e84263d55307	1097	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	167:e84263d55307	1098	}
AnnaBridge	167:e84263d55307	1099
AnnaBridge	167:e84263d55307	1100	/**
AnnaBridge	167:e84263d55307	1101	* @brief Read 16-Bits in the data register
AnnaBridge	167:e84263d55307	1102	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	167:e84263d55307	1103	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1104	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	167:e84263d55307	1105	*/
AnnaBridge	167:e84263d55307	1106	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1107	{
AnnaBridge	167:e84263d55307	1108	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	167:e84263d55307	1109	}
AnnaBridge	167:e84263d55307	1110
AnnaBridge	167:e84263d55307	1111	/**
AnnaBridge	167:e84263d55307	1112	* @brief Write 8-Bits in the data register
AnnaBridge	167:e84263d55307	1113	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	167:e84263d55307	1114	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1115	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1116	* @retval None
AnnaBridge	167:e84263d55307	1117	*/
AnnaBridge	167:e84263d55307	1118	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	167:e84263d55307	1119	{
AnnaBridge	167:e84263d55307	1120	SPIx->DR = TxData;
AnnaBridge	167:e84263d55307	1121	}
AnnaBridge	167:e84263d55307	1122
AnnaBridge	167:e84263d55307	1123	/**
AnnaBridge	167:e84263d55307	1124	* @brief Write 16-Bits in the data register
AnnaBridge	167:e84263d55307	1125	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	167:e84263d55307	1126	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1127	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	167:e84263d55307	1128	* @retval None
AnnaBridge	167:e84263d55307	1129	*/
AnnaBridge	167:e84263d55307	1130	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	167:e84263d55307	1131	{
AnnaBridge	167:e84263d55307	1132	SPIx->DR = TxData;
AnnaBridge	167:e84263d55307	1133	}
AnnaBridge	167:e84263d55307	1134
AnnaBridge	167:e84263d55307	1135	/**
AnnaBridge	167:e84263d55307	1136	* @}
AnnaBridge	167:e84263d55307	1137	*/
AnnaBridge	167:e84263d55307	1138	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	1139	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	1140	* @{
AnnaBridge	167:e84263d55307	1141	*/
AnnaBridge	167:e84263d55307	1142
AnnaBridge	167:e84263d55307	1143	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	167:e84263d55307	1144	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	167:e84263d55307	1145	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	167:e84263d55307	1146
AnnaBridge	167:e84263d55307	1147	/**
AnnaBridge	167:e84263d55307	1148	* @}
AnnaBridge	167:e84263d55307	1149	*/
AnnaBridge	167:e84263d55307	1150	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	1151	/**
AnnaBridge	167:e84263d55307	1152	* @}
AnnaBridge	167:e84263d55307	1153	*/
AnnaBridge	167:e84263d55307	1154
AnnaBridge	167:e84263d55307	1155	/**
AnnaBridge	167:e84263d55307	1156	* @}
AnnaBridge	167:e84263d55307	1157	*/
AnnaBridge	167:e84263d55307	1158
AnnaBridge	167:e84263d55307	1159	/** @defgroup I2S_LL I2S
AnnaBridge	167:e84263d55307	1160	* @{
AnnaBridge	167:e84263d55307	1161	*/
AnnaBridge	167:e84263d55307	1162
AnnaBridge	167:e84263d55307	1163	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1164	/* Private constants ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1165	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1166
AnnaBridge	167:e84263d55307	1167	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1168	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	1169	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	167:e84263d55307	1170	* @{
AnnaBridge	167:e84263d55307	1171	*/
AnnaBridge	167:e84263d55307	1172
AnnaBridge	167:e84263d55307	1173	/**
AnnaBridge	167:e84263d55307	1174	* @brief I2S Init structure definition
AnnaBridge	167:e84263d55307	1175	*/
AnnaBridge	167:e84263d55307	1176
AnnaBridge	167:e84263d55307	1177	typedef struct
AnnaBridge	167:e84263d55307	1178	{
AnnaBridge	167:e84263d55307	1179	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	167:e84263d55307	1180	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	167:e84263d55307	1181
AnnaBridge	167:e84263d55307	1182	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	167:e84263d55307	1183
AnnaBridge	167:e84263d55307	1184	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	167:e84263d55307	1185	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	167:e84263d55307	1186
AnnaBridge	167:e84263d55307	1187	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	167:e84263d55307	1188
AnnaBridge	167:e84263d55307	1189
AnnaBridge	167:e84263d55307	1190	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	167:e84263d55307	1191	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	167:e84263d55307	1192
AnnaBridge	167:e84263d55307	1193	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	167:e84263d55307	1194
AnnaBridge	167:e84263d55307	1195
AnnaBridge	167:e84263d55307	1196	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	167:e84263d55307	1197	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	167:e84263d55307	1198
AnnaBridge	167:e84263d55307	1199	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	167:e84263d55307	1200
AnnaBridge	167:e84263d55307	1201
AnnaBridge	167:e84263d55307	1202	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	167:e84263d55307	1203	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	167:e84263d55307	1204
AnnaBridge	167:e84263d55307	1205	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	167:e84263d55307	1206	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	167:e84263d55307	1207
AnnaBridge	167:e84263d55307	1208
AnnaBridge	167:e84263d55307	1209	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	167:e84263d55307	1210	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	167:e84263d55307	1211
AnnaBridge	167:e84263d55307	1212	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	167:e84263d55307	1213
AnnaBridge	167:e84263d55307	1214	} LL_I2S_InitTypeDef;
AnnaBridge	167:e84263d55307	1215
AnnaBridge	167:e84263d55307	1216	/**
AnnaBridge	167:e84263d55307	1217	* @}
AnnaBridge	167:e84263d55307	1218	*/
AnnaBridge	167:e84263d55307	1219	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	167:e84263d55307	1220
AnnaBridge	167:e84263d55307	1221	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1222	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	167:e84263d55307	1223	* @{
AnnaBridge	167:e84263d55307	1224	*/
AnnaBridge	167:e84263d55307	1225
AnnaBridge	167:e84263d55307	1226	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	167:e84263d55307	1227	* @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge	167:e84263d55307	1228	* @{
AnnaBridge	167:e84263d55307	1229	*/
AnnaBridge	167:e84263d55307	1230	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	167:e84263d55307	1231	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	167:e84263d55307	1232	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
AnnaBridge	167:e84263d55307	1233	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
AnnaBridge	167:e84263d55307	1234	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
AnnaBridge	167:e84263d55307	1235	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	167:e84263d55307	1236	/**
AnnaBridge	167:e84263d55307	1237	* @}
AnnaBridge	167:e84263d55307	1238	*/
AnnaBridge	167:e84263d55307	1239
AnnaBridge	167:e84263d55307	1240	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	167:e84263d55307	1241	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	167:e84263d55307	1242	* @{
AnnaBridge	167:e84263d55307	1243	*/
AnnaBridge	167:e84263d55307	1244	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	167:e84263d55307	1245	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	167:e84263d55307	1246	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	167:e84263d55307	1247	/**
AnnaBridge	167:e84263d55307	1248	* @}
AnnaBridge	167:e84263d55307	1249	*/
AnnaBridge	167:e84263d55307	1250
AnnaBridge	167:e84263d55307	1251	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge	167:e84263d55307	1252	* @{
AnnaBridge	167:e84263d55307	1253	*/
AnnaBridge	167:e84263d55307	1254	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
AnnaBridge	167:e84263d55307	1255	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	167:e84263d55307	1256	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
AnnaBridge	167:e84263d55307	1257	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	167:e84263d55307	1258	/**
AnnaBridge	167:e84263d55307	1259	* @}
AnnaBridge	167:e84263d55307	1260	*/
AnnaBridge	167:e84263d55307	1261
AnnaBridge	167:e84263d55307	1262	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	167:e84263d55307	1263	* @{
AnnaBridge	167:e84263d55307	1264	*/
AnnaBridge	167:e84263d55307	1265	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
AnnaBridge	167:e84263d55307	1266	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
AnnaBridge	167:e84263d55307	1267	/**
AnnaBridge	167:e84263d55307	1268	* @}
AnnaBridge	167:e84263d55307	1269	*/
AnnaBridge	167:e84263d55307	1270
AnnaBridge	167:e84263d55307	1271	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge	167:e84263d55307	1272	* @{
AnnaBridge	167:e84263d55307	1273	*/
AnnaBridge	167:e84263d55307	1274	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
AnnaBridge	167:e84263d55307	1275	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
AnnaBridge	167:e84263d55307	1276	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
AnnaBridge	167:e84263d55307	1277	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
AnnaBridge	167:e84263d55307	1278	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
AnnaBridge	167:e84263d55307	1279	/**
AnnaBridge	167:e84263d55307	1280	* @}
AnnaBridge	167:e84263d55307	1281	*/
AnnaBridge	167:e84263d55307	1282
AnnaBridge	167:e84263d55307	1283	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	167:e84263d55307	1284	* @{
AnnaBridge	167:e84263d55307	1285	*/
AnnaBridge	167:e84263d55307	1286	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
AnnaBridge	167:e84263d55307	1287	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
AnnaBridge	167:e84263d55307	1288	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
AnnaBridge	167:e84263d55307	1289	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
AnnaBridge	167:e84263d55307	1290	/**
AnnaBridge	167:e84263d55307	1291	* @}
AnnaBridge	167:e84263d55307	1292	*/
AnnaBridge	167:e84263d55307	1293
AnnaBridge	167:e84263d55307	1294	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge	167:e84263d55307	1295	* @{
AnnaBridge	167:e84263d55307	1296	*/
AnnaBridge	167:e84263d55307	1297	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	167:e84263d55307	1298	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	167:e84263d55307	1299	/**
AnnaBridge	167:e84263d55307	1300	* @}
AnnaBridge	167:e84263d55307	1301	*/
AnnaBridge	167:e84263d55307	1302
AnnaBridge	167:e84263d55307	1303	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	1304
AnnaBridge	167:e84263d55307	1305	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	167:e84263d55307	1306	* @{
AnnaBridge	167:e84263d55307	1307	*/
AnnaBridge	167:e84263d55307	1308	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
AnnaBridge	167:e84263d55307	1309	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
AnnaBridge	167:e84263d55307	1310	/**
AnnaBridge	167:e84263d55307	1311	* @}
AnnaBridge	167:e84263d55307	1312	*/
AnnaBridge	167:e84263d55307	1313
AnnaBridge	167:e84263d55307	1314	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	167:e84263d55307	1315	* @{
AnnaBridge	167:e84263d55307	1316	*/
AnnaBridge	167:e84263d55307	1317
AnnaBridge	167:e84263d55307	1318	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	167:e84263d55307	1319	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	167:e84263d55307	1320	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	167:e84263d55307	1321	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	167:e84263d55307	1322	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	167:e84263d55307	1323	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	167:e84263d55307	1324	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	167:e84263d55307	1325	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	167:e84263d55307	1326	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	167:e84263d55307	1327	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
AnnaBridge	167:e84263d55307	1328	/**
AnnaBridge	167:e84263d55307	1329	* @}
AnnaBridge	167:e84263d55307	1330	*/
AnnaBridge	167:e84263d55307	1331	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	1332
AnnaBridge	167:e84263d55307	1333	/**
AnnaBridge	167:e84263d55307	1334	* @}
AnnaBridge	167:e84263d55307	1335	*/
AnnaBridge	167:e84263d55307	1336
AnnaBridge	167:e84263d55307	1337	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1338	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	167:e84263d55307	1339	* @{
AnnaBridge	167:e84263d55307	1340	*/
AnnaBridge	167:e84263d55307	1341
AnnaBridge	167:e84263d55307	1342	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	167:e84263d55307	1343	* @{
AnnaBridge	167:e84263d55307	1344	*/
AnnaBridge	167:e84263d55307	1345
AnnaBridge	167:e84263d55307	1346	/**
AnnaBridge	167:e84263d55307	1347	* @brief Write a value in I2S register
AnnaBridge	167:e84263d55307	1348	* @param __INSTANCE__ I2S Instance
AnnaBridge	167:e84263d55307	1349	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	1350	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	1351	* @retval None
AnnaBridge	167:e84263d55307	1352	*/
AnnaBridge	167:e84263d55307	1353	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	1354
AnnaBridge	167:e84263d55307	1355	/**
AnnaBridge	167:e84263d55307	1356	* @brief Read a value in I2S register
AnnaBridge	167:e84263d55307	1357	* @param __INSTANCE__ I2S Instance
AnnaBridge	167:e84263d55307	1358	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	1359	* @retval Register value
AnnaBridge	167:e84263d55307	1360	*/
AnnaBridge	167:e84263d55307	1361	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	167:e84263d55307	1362	/**
AnnaBridge	167:e84263d55307	1363	* @}
AnnaBridge	167:e84263d55307	1364	*/
AnnaBridge	167:e84263d55307	1365
AnnaBridge	167:e84263d55307	1366	/**
AnnaBridge	167:e84263d55307	1367	* @}
AnnaBridge	167:e84263d55307	1368	*/
AnnaBridge	167:e84263d55307	1369
AnnaBridge	167:e84263d55307	1370
AnnaBridge	167:e84263d55307	1371	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	1372
AnnaBridge	167:e84263d55307	1373	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	167:e84263d55307	1374	* @{
AnnaBridge	167:e84263d55307	1375	*/
AnnaBridge	167:e84263d55307	1376
AnnaBridge	167:e84263d55307	1377	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	167:e84263d55307	1378	* @{
AnnaBridge	167:e84263d55307	1379	*/
AnnaBridge	167:e84263d55307	1380
AnnaBridge	167:e84263d55307	1381	/**
AnnaBridge	167:e84263d55307	1382	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	167:e84263d55307	1383	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	167:e84263d55307	1384	* I2SCFGR I2SE LL_I2S_Enable
AnnaBridge	167:e84263d55307	1385	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1386	* @retval None
AnnaBridge	167:e84263d55307	1387	*/
AnnaBridge	167:e84263d55307	1388	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1389	{
AnnaBridge	167:e84263d55307	1390	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	167:e84263d55307	1391	}
AnnaBridge	167:e84263d55307	1392
AnnaBridge	167:e84263d55307	1393	/**
AnnaBridge	167:e84263d55307	1394	* @brief Disable I2S peripheral
AnnaBridge	167:e84263d55307	1395	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge	167:e84263d55307	1396	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1397	* @retval None
AnnaBridge	167:e84263d55307	1398	*/
AnnaBridge	167:e84263d55307	1399	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1400	{
AnnaBridge	167:e84263d55307	1401	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	167:e84263d55307	1402	}
AnnaBridge	167:e84263d55307	1403
AnnaBridge	167:e84263d55307	1404	/**
AnnaBridge	167:e84263d55307	1405	* @brief Check if I2S peripheral is enabled
AnnaBridge	167:e84263d55307	1406	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge	167:e84263d55307	1407	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1408	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1409	*/
AnnaBridge	167:e84263d55307	1410	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1411	{
AnnaBridge	167:e84263d55307	1412	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge	167:e84263d55307	1413	}
AnnaBridge	167:e84263d55307	1414
AnnaBridge	167:e84263d55307	1415	/**
AnnaBridge	167:e84263d55307	1416	* @brief Set I2S data frame length
AnnaBridge	167:e84263d55307	1417	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	167:e84263d55307	1418	* I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge	167:e84263d55307	1419	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1420	* @param DataFormat This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1421	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	167:e84263d55307	1422	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	167:e84263d55307	1423	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	167:e84263d55307	1424	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	167:e84263d55307	1425	* @retval None
AnnaBridge	167:e84263d55307	1426	*/
AnnaBridge	167:e84263d55307	1427	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge	167:e84263d55307	1428	{
AnnaBridge	167:e84263d55307	1429	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge	167:e84263d55307	1430	}
AnnaBridge	167:e84263d55307	1431
AnnaBridge	167:e84263d55307	1432	/**
AnnaBridge	167:e84263d55307	1433	* @brief Get I2S data frame length
AnnaBridge	167:e84263d55307	1434	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	167:e84263d55307	1435	* I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge	167:e84263d55307	1436	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1437	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1438	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	167:e84263d55307	1439	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	167:e84263d55307	1440	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	167:e84263d55307	1441	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	167:e84263d55307	1442	*/
AnnaBridge	167:e84263d55307	1443	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1444	{
AnnaBridge	167:e84263d55307	1445	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
AnnaBridge	167:e84263d55307	1446	}
AnnaBridge	167:e84263d55307	1447
AnnaBridge	167:e84263d55307	1448	/**
AnnaBridge	167:e84263d55307	1449	* @brief Set I2S clock polarity
AnnaBridge	167:e84263d55307	1450	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	167:e84263d55307	1451	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1452	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1453	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	167:e84263d55307	1454	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	167:e84263d55307	1455	* @retval None
AnnaBridge	167:e84263d55307	1456	*/
AnnaBridge	167:e84263d55307	1457	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	167:e84263d55307	1458	{
AnnaBridge	167:e84263d55307	1459	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge	167:e84263d55307	1460	}
AnnaBridge	167:e84263d55307	1461
AnnaBridge	167:e84263d55307	1462	/**
AnnaBridge	167:e84263d55307	1463	* @brief Get I2S clock polarity
AnnaBridge	167:e84263d55307	1464	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	167:e84263d55307	1465	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1466	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1467	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	167:e84263d55307	1468	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	167:e84263d55307	1469	*/
AnnaBridge	167:e84263d55307	1470	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1471	{
AnnaBridge	167:e84263d55307	1472	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	167:e84263d55307	1473	}
AnnaBridge	167:e84263d55307	1474
AnnaBridge	167:e84263d55307	1475	/**
AnnaBridge	167:e84263d55307	1476	* @brief Set I2S standard protocol
AnnaBridge	167:e84263d55307	1477	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	167:e84263d55307	1478	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	167:e84263d55307	1479	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1480	* @param Standard This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1481	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	167:e84263d55307	1482	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	167:e84263d55307	1483	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	167:e84263d55307	1484	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	167:e84263d55307	1485	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	167:e84263d55307	1486	* @retval None
AnnaBridge	167:e84263d55307	1487	*/
AnnaBridge	167:e84263d55307	1488	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	167:e84263d55307	1489	{
AnnaBridge	167:e84263d55307	1490	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	167:e84263d55307	1491	}
AnnaBridge	167:e84263d55307	1492
AnnaBridge	167:e84263d55307	1493	/**
AnnaBridge	167:e84263d55307	1494	* @brief Get I2S standard protocol
AnnaBridge	167:e84263d55307	1495	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	167:e84263d55307	1496	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	167:e84263d55307	1497	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1498	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1499	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	167:e84263d55307	1500	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	167:e84263d55307	1501	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	167:e84263d55307	1502	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	167:e84263d55307	1503	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	167:e84263d55307	1504	*/
AnnaBridge	167:e84263d55307	1505	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1506	{
AnnaBridge	167:e84263d55307	1507	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	167:e84263d55307	1508	}
AnnaBridge	167:e84263d55307	1509
AnnaBridge	167:e84263d55307	1510	/**
AnnaBridge	167:e84263d55307	1511	* @brief Set I2S transfer mode
AnnaBridge	167:e84263d55307	1512	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	167:e84263d55307	1513	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1514	* @param Mode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1515	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	167:e84263d55307	1516	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	167:e84263d55307	1517	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	167:e84263d55307	1518	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	167:e84263d55307	1519	* @retval None
AnnaBridge	167:e84263d55307	1520	*/
AnnaBridge	167:e84263d55307	1521	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	167:e84263d55307	1522	{
AnnaBridge	167:e84263d55307	1523	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge	167:e84263d55307	1524	}
AnnaBridge	167:e84263d55307	1525
AnnaBridge	167:e84263d55307	1526	/**
AnnaBridge	167:e84263d55307	1527	* @brief Get I2S transfer mode
AnnaBridge	167:e84263d55307	1528	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	167:e84263d55307	1529	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1530	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1531	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	167:e84263d55307	1532	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	167:e84263d55307	1533	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	167:e84263d55307	1534	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	167:e84263d55307	1535	*/
AnnaBridge	167:e84263d55307	1536	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1537	{
AnnaBridge	167:e84263d55307	1538	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	167:e84263d55307	1539	}
AnnaBridge	167:e84263d55307	1540
AnnaBridge	167:e84263d55307	1541	/**
AnnaBridge	167:e84263d55307	1542	* @brief Set I2S linear prescaler
AnnaBridge	167:e84263d55307	1543	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	167:e84263d55307	1544	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1545	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1546	* @retval None
AnnaBridge	167:e84263d55307	1547	*/
AnnaBridge	167:e84263d55307	1548	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge	167:e84263d55307	1549	{
AnnaBridge	167:e84263d55307	1550	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge	167:e84263d55307	1551	}
AnnaBridge	167:e84263d55307	1552
AnnaBridge	167:e84263d55307	1553	/**
AnnaBridge	167:e84263d55307	1554	* @brief Get I2S linear prescaler
AnnaBridge	167:e84263d55307	1555	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	167:e84263d55307	1556	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1557	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1558	*/
AnnaBridge	167:e84263d55307	1559	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1560	{
AnnaBridge	167:e84263d55307	1561	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge	167:e84263d55307	1562	}
AnnaBridge	167:e84263d55307	1563
AnnaBridge	167:e84263d55307	1564	/**
AnnaBridge	167:e84263d55307	1565	* @brief Set I2S parity prescaler
AnnaBridge	167:e84263d55307	1566	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge	167:e84263d55307	1567	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1568	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1569	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	167:e84263d55307	1570	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	167:e84263d55307	1571	* @retval None
AnnaBridge	167:e84263d55307	1572	*/
AnnaBridge	167:e84263d55307	1573	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	167:e84263d55307	1574	{
AnnaBridge	167:e84263d55307	1575	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge	167:e84263d55307	1576	}
AnnaBridge	167:e84263d55307	1577
AnnaBridge	167:e84263d55307	1578	/**
AnnaBridge	167:e84263d55307	1579	* @brief Get I2S parity prescaler
AnnaBridge	167:e84263d55307	1580	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge	167:e84263d55307	1581	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1582	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1583	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	167:e84263d55307	1584	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	167:e84263d55307	1585	*/
AnnaBridge	167:e84263d55307	1586	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1587	{
AnnaBridge	167:e84263d55307	1588	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge	167:e84263d55307	1589	}
AnnaBridge	167:e84263d55307	1590
AnnaBridge	167:e84263d55307	1591	/**
AnnaBridge	167:e84263d55307	1592	* @brief Enable the master clock ouput (Pin MCK)
AnnaBridge	167:e84263d55307	1593	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	167:e84263d55307	1594	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1595	* @retval None
AnnaBridge	167:e84263d55307	1596	*/
AnnaBridge	167:e84263d55307	1597	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1598	{
AnnaBridge	167:e84263d55307	1599	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	167:e84263d55307	1600	}
AnnaBridge	167:e84263d55307	1601
AnnaBridge	167:e84263d55307	1602	/**
AnnaBridge	167:e84263d55307	1603	* @brief Disable the master clock ouput (Pin MCK)
AnnaBridge	167:e84263d55307	1604	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	167:e84263d55307	1605	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1606	* @retval None
AnnaBridge	167:e84263d55307	1607	*/
AnnaBridge	167:e84263d55307	1608	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1609	{
AnnaBridge	167:e84263d55307	1610	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	167:e84263d55307	1611	}
AnnaBridge	167:e84263d55307	1612
AnnaBridge	167:e84263d55307	1613	/**
AnnaBridge	167:e84263d55307	1614	* @brief Check if the master clock ouput (Pin MCK) is enabled
AnnaBridge	167:e84263d55307	1615	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	167:e84263d55307	1616	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1617	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1618	*/
AnnaBridge	167:e84263d55307	1619	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1620	{
AnnaBridge	167:e84263d55307	1621	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge	167:e84263d55307	1622	}
AnnaBridge	167:e84263d55307	1623
AnnaBridge	167:e84263d55307	1624	/**
AnnaBridge	167:e84263d55307	1625	* @}
AnnaBridge	167:e84263d55307	1626	*/
AnnaBridge	167:e84263d55307	1627
AnnaBridge	167:e84263d55307	1628	/** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge	167:e84263d55307	1629	* @{
AnnaBridge	167:e84263d55307	1630	*/
AnnaBridge	167:e84263d55307	1631
AnnaBridge	167:e84263d55307	1632	/**
AnnaBridge	167:e84263d55307	1633	* @brief Check if Rx buffer is not empty
AnnaBridge	167:e84263d55307	1634	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge	167:e84263d55307	1635	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1636	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1637	*/
AnnaBridge	167:e84263d55307	1638	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1639	{
AnnaBridge	167:e84263d55307	1640	return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge	167:e84263d55307	1641	}
AnnaBridge	167:e84263d55307	1642
AnnaBridge	167:e84263d55307	1643	/**
AnnaBridge	167:e84263d55307	1644	* @brief Check if Tx buffer is empty
AnnaBridge	167:e84263d55307	1645	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge	167:e84263d55307	1646	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1647	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1648	*/
AnnaBridge	167:e84263d55307	1649	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1650	{
AnnaBridge	167:e84263d55307	1651	return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge	167:e84263d55307	1652	}
AnnaBridge	167:e84263d55307	1653
AnnaBridge	167:e84263d55307	1654	/**
AnnaBridge	167:e84263d55307	1655	* @brief Get busy flag
AnnaBridge	167:e84263d55307	1656	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge	167:e84263d55307	1657	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1658	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1659	*/
AnnaBridge	167:e84263d55307	1660	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1661	{
AnnaBridge	167:e84263d55307	1662	return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge	167:e84263d55307	1663	}
AnnaBridge	167:e84263d55307	1664
AnnaBridge	167:e84263d55307	1665	/**
AnnaBridge	167:e84263d55307	1666	* @brief Get overrun error flag
AnnaBridge	167:e84263d55307	1667	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	167:e84263d55307	1668	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1669	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1670	*/
AnnaBridge	167:e84263d55307	1671	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1672	{
AnnaBridge	167:e84263d55307	1673	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	167:e84263d55307	1674	}
AnnaBridge	167:e84263d55307	1675
AnnaBridge	167:e84263d55307	1676	/**
AnnaBridge	167:e84263d55307	1677	* @brief Get underrun error flag
AnnaBridge	167:e84263d55307	1678	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	167:e84263d55307	1679	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1680	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1681	*/
AnnaBridge	167:e84263d55307	1682	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1683	{
AnnaBridge	167:e84263d55307	1684	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge	167:e84263d55307	1685	}
AnnaBridge	167:e84263d55307	1686
AnnaBridge	167:e84263d55307	1687	/**
AnnaBridge	167:e84263d55307	1688	* @brief Get frame format error flag
AnnaBridge	167:e84263d55307	1689	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
AnnaBridge	167:e84263d55307	1690	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1691	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1692	*/
AnnaBridge	167:e84263d55307	1693	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1694	{
AnnaBridge	167:e84263d55307	1695	return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge	167:e84263d55307	1696	}
AnnaBridge	167:e84263d55307	1697
AnnaBridge	167:e84263d55307	1698	/**
AnnaBridge	167:e84263d55307	1699	* @brief Get channel side flag.
AnnaBridge	167:e84263d55307	1700	* @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge	167:e84263d55307	1701	* 1: Channel Right has to be transmitted or has been received\n
AnnaBridge	167:e84263d55307	1702	* It has no significance in PCM mode.
AnnaBridge	167:e84263d55307	1703	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge	167:e84263d55307	1704	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1705	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1706	*/
AnnaBridge	167:e84263d55307	1707	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1708	{
AnnaBridge	167:e84263d55307	1709	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge	167:e84263d55307	1710	}
AnnaBridge	167:e84263d55307	1711
AnnaBridge	167:e84263d55307	1712	/**
AnnaBridge	167:e84263d55307	1713	* @brief Clear overrun error flag
AnnaBridge	167:e84263d55307	1714	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge	167:e84263d55307	1715	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1716	* @retval None
AnnaBridge	167:e84263d55307	1717	*/
AnnaBridge	167:e84263d55307	1718	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1719	{
AnnaBridge	167:e84263d55307	1720	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	167:e84263d55307	1721	}
AnnaBridge	167:e84263d55307	1722
AnnaBridge	167:e84263d55307	1723	/**
AnnaBridge	167:e84263d55307	1724	* @brief Clear underrun error flag
AnnaBridge	167:e84263d55307	1725	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge	167:e84263d55307	1726	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1727	* @retval None
AnnaBridge	167:e84263d55307	1728	*/
AnnaBridge	167:e84263d55307	1729	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1730	{
AnnaBridge	167:e84263d55307	1731	__IO uint32_t tmpreg;
AnnaBridge	167:e84263d55307	1732	tmpreg = SPIx->SR;
AnnaBridge	167:e84263d55307	1733	(void)tmpreg;
AnnaBridge	167:e84263d55307	1734	}
AnnaBridge	167:e84263d55307	1735
AnnaBridge	167:e84263d55307	1736	/**
AnnaBridge	167:e84263d55307	1737	* @brief Clear frame format error flag
AnnaBridge	167:e84263d55307	1738	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
AnnaBridge	167:e84263d55307	1739	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1740	* @retval None
AnnaBridge	167:e84263d55307	1741	*/
AnnaBridge	167:e84263d55307	1742	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1743	{
AnnaBridge	167:e84263d55307	1744	LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge	167:e84263d55307	1745	}
AnnaBridge	167:e84263d55307	1746
AnnaBridge	167:e84263d55307	1747	/**
AnnaBridge	167:e84263d55307	1748	* @}
AnnaBridge	167:e84263d55307	1749	*/
AnnaBridge	167:e84263d55307	1750
AnnaBridge	167:e84263d55307	1751	/** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge	167:e84263d55307	1752	* @{
AnnaBridge	167:e84263d55307	1753	*/
AnnaBridge	167:e84263d55307	1754
AnnaBridge	167:e84263d55307	1755	/**
AnnaBridge	167:e84263d55307	1756	* @brief Enable error IT
AnnaBridge	167:e84263d55307	1757	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	167:e84263d55307	1758	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge	167:e84263d55307	1759	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1760	* @retval None
AnnaBridge	167:e84263d55307	1761	*/
AnnaBridge	167:e84263d55307	1762	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1763	{
AnnaBridge	167:e84263d55307	1764	LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge	167:e84263d55307	1765	}
AnnaBridge	167:e84263d55307	1766
AnnaBridge	167:e84263d55307	1767	/**
AnnaBridge	167:e84263d55307	1768	* @brief Enable Rx buffer not empty IT
AnnaBridge	167:e84263d55307	1769	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge	167:e84263d55307	1770	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1771	* @retval None
AnnaBridge	167:e84263d55307	1772	*/
AnnaBridge	167:e84263d55307	1773	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1774	{
AnnaBridge	167:e84263d55307	1775	LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge	167:e84263d55307	1776	}
AnnaBridge	167:e84263d55307	1777
AnnaBridge	167:e84263d55307	1778	/**
AnnaBridge	167:e84263d55307	1779	* @brief Enable Tx buffer empty IT
AnnaBridge	167:e84263d55307	1780	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge	167:e84263d55307	1781	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1782	* @retval None
AnnaBridge	167:e84263d55307	1783	*/
AnnaBridge	167:e84263d55307	1784	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1785	{
AnnaBridge	167:e84263d55307	1786	LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge	167:e84263d55307	1787	}
AnnaBridge	167:e84263d55307	1788
AnnaBridge	167:e84263d55307	1789	/**
AnnaBridge	167:e84263d55307	1790	* @brief Disable error IT
AnnaBridge	167:e84263d55307	1791	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	167:e84263d55307	1792	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge	167:e84263d55307	1793	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1794	* @retval None
AnnaBridge	167:e84263d55307	1795	*/
AnnaBridge	167:e84263d55307	1796	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1797	{
AnnaBridge	167:e84263d55307	1798	LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge	167:e84263d55307	1799	}
AnnaBridge	167:e84263d55307	1800
AnnaBridge	167:e84263d55307	1801	/**
AnnaBridge	167:e84263d55307	1802	* @brief Disable Rx buffer not empty IT
AnnaBridge	167:e84263d55307	1803	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge	167:e84263d55307	1804	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1805	* @retval None
AnnaBridge	167:e84263d55307	1806	*/
AnnaBridge	167:e84263d55307	1807	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1808	{
AnnaBridge	167:e84263d55307	1809	LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge	167:e84263d55307	1810	}
AnnaBridge	167:e84263d55307	1811
AnnaBridge	167:e84263d55307	1812	/**
AnnaBridge	167:e84263d55307	1813	* @brief Disable Tx buffer empty IT
AnnaBridge	167:e84263d55307	1814	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge	167:e84263d55307	1815	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1816	* @retval None
AnnaBridge	167:e84263d55307	1817	*/
AnnaBridge	167:e84263d55307	1818	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1819	{
AnnaBridge	167:e84263d55307	1820	LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge	167:e84263d55307	1821	}
AnnaBridge	167:e84263d55307	1822
AnnaBridge	167:e84263d55307	1823	/**
AnnaBridge	167:e84263d55307	1824	* @brief Check if ERR IT is enabled
AnnaBridge	167:e84263d55307	1825	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge	167:e84263d55307	1826	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1827	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1828	*/
AnnaBridge	167:e84263d55307	1829	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1830	{
AnnaBridge	167:e84263d55307	1831	return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge	167:e84263d55307	1832	}
AnnaBridge	167:e84263d55307	1833
AnnaBridge	167:e84263d55307	1834	/**
AnnaBridge	167:e84263d55307	1835	* @brief Check if RXNE IT is enabled
AnnaBridge	167:e84263d55307	1836	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge	167:e84263d55307	1837	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1838	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1839	*/
AnnaBridge	167:e84263d55307	1840	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1841	{
AnnaBridge	167:e84263d55307	1842	return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge	167:e84263d55307	1843	}
AnnaBridge	167:e84263d55307	1844
AnnaBridge	167:e84263d55307	1845	/**
AnnaBridge	167:e84263d55307	1846	* @brief Check if TXE IT is enabled
AnnaBridge	167:e84263d55307	1847	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge	167:e84263d55307	1848	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1849	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1850	*/
AnnaBridge	167:e84263d55307	1851	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1852	{
AnnaBridge	167:e84263d55307	1853	return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge	167:e84263d55307	1854	}
AnnaBridge	167:e84263d55307	1855
AnnaBridge	167:e84263d55307	1856	/**
AnnaBridge	167:e84263d55307	1857	* @}
AnnaBridge	167:e84263d55307	1858	*/
AnnaBridge	167:e84263d55307	1859
AnnaBridge	167:e84263d55307	1860	/** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge	167:e84263d55307	1861	* @{
AnnaBridge	167:e84263d55307	1862	*/
AnnaBridge	167:e84263d55307	1863
AnnaBridge	167:e84263d55307	1864	/**
AnnaBridge	167:e84263d55307	1865	* @brief Enable DMA Rx
AnnaBridge	167:e84263d55307	1866	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	167:e84263d55307	1867	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1868	* @retval None
AnnaBridge	167:e84263d55307	1869	*/
AnnaBridge	167:e84263d55307	1870	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1871	{
AnnaBridge	167:e84263d55307	1872	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	167:e84263d55307	1873	}
AnnaBridge	167:e84263d55307	1874
AnnaBridge	167:e84263d55307	1875	/**
AnnaBridge	167:e84263d55307	1876	* @brief Disable DMA Rx
AnnaBridge	167:e84263d55307	1877	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	167:e84263d55307	1878	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1879	* @retval None
AnnaBridge	167:e84263d55307	1880	*/
AnnaBridge	167:e84263d55307	1881	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1882	{
AnnaBridge	167:e84263d55307	1883	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	167:e84263d55307	1884	}
AnnaBridge	167:e84263d55307	1885
AnnaBridge	167:e84263d55307	1886	/**
AnnaBridge	167:e84263d55307	1887	* @brief Check if DMA Rx is enabled
AnnaBridge	167:e84263d55307	1888	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	167:e84263d55307	1889	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1890	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1891	*/
AnnaBridge	167:e84263d55307	1892	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1893	{
AnnaBridge	167:e84263d55307	1894	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	167:e84263d55307	1895	}
AnnaBridge	167:e84263d55307	1896
AnnaBridge	167:e84263d55307	1897	/**
AnnaBridge	167:e84263d55307	1898	* @brief Enable DMA Tx
AnnaBridge	167:e84263d55307	1899	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	167:e84263d55307	1900	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1901	* @retval None
AnnaBridge	167:e84263d55307	1902	*/
AnnaBridge	167:e84263d55307	1903	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1904	{
AnnaBridge	167:e84263d55307	1905	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	167:e84263d55307	1906	}
AnnaBridge	167:e84263d55307	1907
AnnaBridge	167:e84263d55307	1908	/**
AnnaBridge	167:e84263d55307	1909	* @brief Disable DMA Tx
AnnaBridge	167:e84263d55307	1910	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	167:e84263d55307	1911	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1912	* @retval None
AnnaBridge	167:e84263d55307	1913	*/
AnnaBridge	167:e84263d55307	1914	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1915	{
AnnaBridge	167:e84263d55307	1916	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	167:e84263d55307	1917	}
AnnaBridge	167:e84263d55307	1918
AnnaBridge	167:e84263d55307	1919	/**
AnnaBridge	167:e84263d55307	1920	* @brief Check if DMA Tx is enabled
AnnaBridge	167:e84263d55307	1921	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	167:e84263d55307	1922	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1923	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1924	*/
AnnaBridge	167:e84263d55307	1925	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1926	{
AnnaBridge	167:e84263d55307	1927	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	167:e84263d55307	1928	}
AnnaBridge	167:e84263d55307	1929
AnnaBridge	167:e84263d55307	1930	/**
AnnaBridge	167:e84263d55307	1931	* @}
AnnaBridge	167:e84263d55307	1932	*/
AnnaBridge	167:e84263d55307	1933
AnnaBridge	167:e84263d55307	1934	/** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge	167:e84263d55307	1935	* @{
AnnaBridge	167:e84263d55307	1936	*/
AnnaBridge	167:e84263d55307	1937
AnnaBridge	167:e84263d55307	1938	/**
AnnaBridge	167:e84263d55307	1939	* @brief Read 16-Bits in data register
AnnaBridge	167:e84263d55307	1940	* @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge	167:e84263d55307	1941	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1942	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	167:e84263d55307	1943	*/
AnnaBridge	167:e84263d55307	1944	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	167:e84263d55307	1945	{
AnnaBridge	167:e84263d55307	1946	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	167:e84263d55307	1947	}
AnnaBridge	167:e84263d55307	1948
AnnaBridge	167:e84263d55307	1949	/**
AnnaBridge	167:e84263d55307	1950	* @brief Write 16-Bits in data register
AnnaBridge	167:e84263d55307	1951	* @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge	167:e84263d55307	1952	* @param SPIx SPI Instance
AnnaBridge	167:e84263d55307	1953	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	167:e84263d55307	1954	* @retval None
AnnaBridge	167:e84263d55307	1955	*/
AnnaBridge	167:e84263d55307	1956	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	167:e84263d55307	1957	{
AnnaBridge	167:e84263d55307	1958	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	167:e84263d55307	1959	}
AnnaBridge	167:e84263d55307	1960
AnnaBridge	167:e84263d55307	1961	/**
AnnaBridge	167:e84263d55307	1962	* @}
AnnaBridge	167:e84263d55307	1963	*/
AnnaBridge	167:e84263d55307	1964
AnnaBridge	167:e84263d55307	1965	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	1966	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	1967	* @{
AnnaBridge	167:e84263d55307	1968	*/
AnnaBridge	167:e84263d55307	1969
AnnaBridge	167:e84263d55307	1970	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	167:e84263d55307	1971	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	167:e84263d55307	1972	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	167:e84263d55307	1973	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	167:e84263d55307	1974
AnnaBridge	167:e84263d55307	1975	/**
AnnaBridge	167:e84263d55307	1976	* @}
AnnaBridge	167:e84263d55307	1977	*/
AnnaBridge	167:e84263d55307	1978	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	1979
AnnaBridge	167:e84263d55307	1980	/**
AnnaBridge	167:e84263d55307	1981	* @}
AnnaBridge	167:e84263d55307	1982	*/
AnnaBridge	167:e84263d55307	1983
AnnaBridge	167:e84263d55307	1984	/**
AnnaBridge	167:e84263d55307	1985	* @}
AnnaBridge	167:e84263d55307	1986	*/
AnnaBridge	167:e84263d55307	1987
AnnaBridge	167:e84263d55307	1988	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) */
AnnaBridge	167:e84263d55307	1989
AnnaBridge	167:e84263d55307	1990	/**
AnnaBridge	167:e84263d55307	1991	* @}
AnnaBridge	167:e84263d55307	1992	*/
AnnaBridge	167:e84263d55307	1993
AnnaBridge	167:e84263d55307	1994	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	1995	}
AnnaBridge	167:e84263d55307	1996	#endif
AnnaBridge	167:e84263d55307	1997
AnnaBridge	167:e84263d55307	1998	#endif /* __STM32F2xx_LL_SPI_H */
AnnaBridge	167:e84263d55307	1999
AnnaBridge	167:e84263d55307	2000	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/