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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/**
AnnaBridge	167:e84263d55307	2	******************************************************************************
AnnaBridge	167:e84263d55307	3	* @file stm32f2xx_ll_rcc.h
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
AnnaBridge	167:e84263d55307	7	* @brief Header file of RCC LL module.
AnnaBridge	167:e84263d55307	8	******************************************************************************
AnnaBridge	167:e84263d55307	9	* @attention
AnnaBridge	167:e84263d55307	10	*
AnnaBridge	167:e84263d55307	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	167:e84263d55307	12	*
AnnaBridge	167:e84263d55307	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	167:e84263d55307	14	* are permitted provided that the following conditions are met:
AnnaBridge	167:e84263d55307	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	167:e84263d55307	16	* this list of conditions and the following disclaimer.
AnnaBridge	167:e84263d55307	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	167:e84263d55307	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	167:e84263d55307	19	* and/or other materials provided with the distribution.
AnnaBridge	167:e84263d55307	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	167:e84263d55307	21	* may be used to endorse or promote products derived from this software
AnnaBridge	167:e84263d55307	22	* without specific prior written permission.
AnnaBridge	167:e84263d55307	23	*
AnnaBridge	167:e84263d55307	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	167:e84263d55307	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	167:e84263d55307	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	167:e84263d55307	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	167:e84263d55307	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	167:e84263d55307	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	167:e84263d55307	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	167:e84263d55307	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	167:e84263d55307	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	167:e84263d55307	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	167:e84263d55307	34	*
AnnaBridge	167:e84263d55307	35	******************************************************************************
AnnaBridge	167:e84263d55307	36	*/
AnnaBridge	167:e84263d55307	37
AnnaBridge	167:e84263d55307	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	167:e84263d55307	39	#ifndef __STM32F2xx_LL_RCC_H
AnnaBridge	167:e84263d55307	40	#define __STM32F2xx_LL_RCC_H
AnnaBridge	167:e84263d55307	41
AnnaBridge	167:e84263d55307	42	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	43	extern "C" {
AnnaBridge	167:e84263d55307	44	#endif
AnnaBridge	167:e84263d55307	45
AnnaBridge	167:e84263d55307	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	47	#include "stm32f2xx.h"
AnnaBridge	167:e84263d55307	48
AnnaBridge	167:e84263d55307	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	167:e84263d55307	50	* @{
AnnaBridge	167:e84263d55307	51	*/
AnnaBridge	167:e84263d55307	52
AnnaBridge	167:e84263d55307	53	#if defined(RCC)
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/** @defgroup RCC_LL RCC
AnnaBridge	167:e84263d55307	56	* @{
AnnaBridge	167:e84263d55307	57	*/
AnnaBridge	167:e84263d55307	58
AnnaBridge	167:e84263d55307	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	167:e84263d55307	62	* @{
AnnaBridge	167:e84263d55307	63	*/
AnnaBridge	167:e84263d55307	64
AnnaBridge	167:e84263d55307	65	/**
AnnaBridge	167:e84263d55307	66	* @}
AnnaBridge	167:e84263d55307	67	*/
AnnaBridge	167:e84263d55307	68	/* Private constants ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	69	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	70	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	71	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	167:e84263d55307	72	* @{
AnnaBridge	167:e84263d55307	73	*/
AnnaBridge	167:e84263d55307	74	/**
AnnaBridge	167:e84263d55307	75	* @}
AnnaBridge	167:e84263d55307	76	*/
AnnaBridge	167:e84263d55307	77	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	167:e84263d55307	78
AnnaBridge	167:e84263d55307	79	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	80	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	81	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	167:e84263d55307	82	* @{
AnnaBridge	167:e84263d55307	83	*/
AnnaBridge	167:e84263d55307	84
AnnaBridge	167:e84263d55307	85	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	167:e84263d55307	86	* @{
AnnaBridge	167:e84263d55307	87	*/
AnnaBridge	167:e84263d55307	88
AnnaBridge	167:e84263d55307	89	/**
AnnaBridge	167:e84263d55307	90	* @brief RCC Clocks Frequency Structure
AnnaBridge	167:e84263d55307	91	*/
AnnaBridge	167:e84263d55307	92	typedef struct
AnnaBridge	167:e84263d55307	93	{
AnnaBridge	167:e84263d55307	94	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	167:e84263d55307	95	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	167:e84263d55307	96	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	167:e84263d55307	97	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	167:e84263d55307	98	} LL_RCC_ClocksTypeDef;
AnnaBridge	167:e84263d55307	99
AnnaBridge	167:e84263d55307	100	/**
AnnaBridge	167:e84263d55307	101	* @}
AnnaBridge	167:e84263d55307	102	*/
AnnaBridge	167:e84263d55307	103
AnnaBridge	167:e84263d55307	104	/**
AnnaBridge	167:e84263d55307	105	* @}
AnnaBridge	167:e84263d55307	106	*/
AnnaBridge	167:e84263d55307	107	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	108
AnnaBridge	167:e84263d55307	109	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	110	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	167:e84263d55307	111	* @{
AnnaBridge	167:e84263d55307	112	*/
AnnaBridge	167:e84263d55307	113
AnnaBridge	167:e84263d55307	114	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	167:e84263d55307	115	* @brief Defines used to adapt values of different oscillators
AnnaBridge	167:e84263d55307	116	* @note These values could be modified in the user environment according to
AnnaBridge	167:e84263d55307	117	* HW set-up.
AnnaBridge	167:e84263d55307	118	* @{
AnnaBridge	167:e84263d55307	119	*/
AnnaBridge	167:e84263d55307	120	#if !defined (HSE_VALUE)
AnnaBridge	167:e84263d55307	121	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	167:e84263d55307	122	#endif /* HSE_VALUE */
AnnaBridge	167:e84263d55307	123
AnnaBridge	167:e84263d55307	124	#if !defined (HSI_VALUE)
AnnaBridge	167:e84263d55307	125	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	167:e84263d55307	126	#endif /* HSI_VALUE */
AnnaBridge	167:e84263d55307	127
AnnaBridge	167:e84263d55307	128	#if !defined (LSE_VALUE)
AnnaBridge	167:e84263d55307	129	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	167:e84263d55307	130	#endif /* LSE_VALUE */
AnnaBridge	167:e84263d55307	131
AnnaBridge	167:e84263d55307	132	#if !defined (LSI_VALUE)
AnnaBridge	167:e84263d55307	133	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	167:e84263d55307	134	#endif /* LSI_VALUE */
AnnaBridge	167:e84263d55307	135
AnnaBridge	167:e84263d55307	136	#if !defined (EXTERNAL_CLOCK_VALUE)
AnnaBridge	167:e84263d55307	137	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
AnnaBridge	167:e84263d55307	138	#endif /* EXTERNAL_CLOCK_VALUE */
AnnaBridge	167:e84263d55307	139	/**
AnnaBridge	167:e84263d55307	140	* @}
AnnaBridge	167:e84263d55307	141	*/
AnnaBridge	167:e84263d55307	142
AnnaBridge	167:e84263d55307	143	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	167:e84263d55307	144	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	167:e84263d55307	145	* @{
AnnaBridge	167:e84263d55307	146	*/
AnnaBridge	167:e84263d55307	147	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	167:e84263d55307	148	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	167:e84263d55307	149	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	167:e84263d55307	150	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	167:e84263d55307	151	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	167:e84263d55307	152	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
AnnaBridge	167:e84263d55307	153	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	167:e84263d55307	154	/**
AnnaBridge	167:e84263d55307	155	* @}
AnnaBridge	167:e84263d55307	156	*/
AnnaBridge	167:e84263d55307	157
AnnaBridge	167:e84263d55307	158	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	167:e84263d55307	159	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	167:e84263d55307	160	* @{
AnnaBridge	167:e84263d55307	161	*/
AnnaBridge	167:e84263d55307	162	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	167:e84263d55307	163	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	167:e84263d55307	164	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	167:e84263d55307	165	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	167:e84263d55307	166	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	167:e84263d55307	167	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
AnnaBridge	167:e84263d55307	168	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	167:e84263d55307	169	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	167:e84263d55307	170	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	167:e84263d55307	171	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
AnnaBridge	167:e84263d55307	172	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	167:e84263d55307	173	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	167:e84263d55307	174	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	167:e84263d55307	175	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
AnnaBridge	167:e84263d55307	176	/**
AnnaBridge	167:e84263d55307	177	* @}
AnnaBridge	167:e84263d55307	178	*/
AnnaBridge	167:e84263d55307	179
AnnaBridge	167:e84263d55307	180	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	167:e84263d55307	181	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	167:e84263d55307	182	* @{
AnnaBridge	167:e84263d55307	183	*/
AnnaBridge	167:e84263d55307	184	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	167:e84263d55307	185	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	167:e84263d55307	186	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	167:e84263d55307	187	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	167:e84263d55307	188	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	167:e84263d55307	189	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
AnnaBridge	167:e84263d55307	190	/**
AnnaBridge	167:e84263d55307	191	* @}
AnnaBridge	167:e84263d55307	192	*/
AnnaBridge	167:e84263d55307	193
AnnaBridge	167:e84263d55307	194	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	167:e84263d55307	195	* @{
AnnaBridge	167:e84263d55307	196	*/
AnnaBridge	167:e84263d55307	197	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	167:e84263d55307	198	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	167:e84263d55307	199	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	167:e84263d55307	200	/**
AnnaBridge	167:e84263d55307	201	* @}
AnnaBridge	167:e84263d55307	202	*/
AnnaBridge	167:e84263d55307	203
AnnaBridge	167:e84263d55307	204	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	167:e84263d55307	205	* @{
AnnaBridge	167:e84263d55307	206	*/
AnnaBridge	167:e84263d55307	207	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	167:e84263d55307	208	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	167:e84263d55307	209	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	167:e84263d55307	210	/**
AnnaBridge	167:e84263d55307	211	* @}
AnnaBridge	167:e84263d55307	212	*/
AnnaBridge	167:e84263d55307	213
AnnaBridge	167:e84263d55307	214	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	167:e84263d55307	215	* @{
AnnaBridge	167:e84263d55307	216	*/
AnnaBridge	167:e84263d55307	217	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	167:e84263d55307	218	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	167:e84263d55307	219	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	167:e84263d55307	220	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	167:e84263d55307	221	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	167:e84263d55307	222	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	167:e84263d55307	223	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	167:e84263d55307	224	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	167:e84263d55307	225	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	167:e84263d55307	226	/**
AnnaBridge	167:e84263d55307	227	* @}
AnnaBridge	167:e84263d55307	228	*/
AnnaBridge	167:e84263d55307	229
AnnaBridge	167:e84263d55307	230	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	167:e84263d55307	231	* @{
AnnaBridge	167:e84263d55307	232	*/
AnnaBridge	167:e84263d55307	233	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	167:e84263d55307	234	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	167:e84263d55307	235	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	167:e84263d55307	236	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	167:e84263d55307	237	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	167:e84263d55307	238	/**
AnnaBridge	167:e84263d55307	239	* @}
AnnaBridge	167:e84263d55307	240	*/
AnnaBridge	167:e84263d55307	241
AnnaBridge	167:e84263d55307	242	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	167:e84263d55307	243	* @{
AnnaBridge	167:e84263d55307	244	*/
AnnaBridge	167:e84263d55307	245	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	167:e84263d55307	246	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	167:e84263d55307	247	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	167:e84263d55307	248	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	167:e84263d55307	249	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	167:e84263d55307	250	/**
AnnaBridge	167:e84263d55307	251	* @}
AnnaBridge	167:e84263d55307	252	*/
AnnaBridge	167:e84263d55307	253
AnnaBridge	167:e84263d55307	254	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
AnnaBridge	167:e84263d55307	255	* @{
AnnaBridge	167:e84263d55307	256	*/
AnnaBridge	167:e84263d55307	257	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
AnnaBridge	167:e84263d55307	258	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
AnnaBridge	167:e84263d55307	259	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
AnnaBridge	167:e84263d55307	260	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
AnnaBridge	167:e84263d55307	261	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
AnnaBridge	167:e84263d55307	262	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
AnnaBridge	167:e84263d55307	263	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
AnnaBridge	167:e84263d55307	264	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
AnnaBridge	167:e84263d55307	265	/**
AnnaBridge	167:e84263d55307	266	* @}
AnnaBridge	167:e84263d55307	267	*/
AnnaBridge	167:e84263d55307	268
AnnaBridge	167:e84263d55307	269	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
AnnaBridge	167:e84263d55307	270	* @{
AnnaBridge	167:e84263d55307	271	*/
AnnaBridge	167:e84263d55307	272	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
AnnaBridge	167:e84263d55307	273	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
AnnaBridge	167:e84263d55307	274	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
AnnaBridge	167:e84263d55307	275	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
AnnaBridge	167:e84263d55307	276	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
AnnaBridge	167:e84263d55307	277	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
AnnaBridge	167:e84263d55307	278	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
AnnaBridge	167:e84263d55307	279	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
AnnaBridge	167:e84263d55307	280	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
AnnaBridge	167:e84263d55307	281	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
AnnaBridge	167:e84263d55307	282	/**
AnnaBridge	167:e84263d55307	283	* @}
AnnaBridge	167:e84263d55307	284	*/
AnnaBridge	167:e84263d55307	285
AnnaBridge	167:e84263d55307	286	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
AnnaBridge	167:e84263d55307	287	* @{
AnnaBridge	167:e84263d55307	288	*/
AnnaBridge	167:e84263d55307	289	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
AnnaBridge	167:e84263d55307	290	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
AnnaBridge	167:e84263d55307	291	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
AnnaBridge	167:e84263d55307	292	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
AnnaBridge	167:e84263d55307	293	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
AnnaBridge	167:e84263d55307	294	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
AnnaBridge	167:e84263d55307	295	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
AnnaBridge	167:e84263d55307	296	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
AnnaBridge	167:e84263d55307	297	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
AnnaBridge	167:e84263d55307	298	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
AnnaBridge	167:e84263d55307	299	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
AnnaBridge	167:e84263d55307	300	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
AnnaBridge	167:e84263d55307	301	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
AnnaBridge	167:e84263d55307	302	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
AnnaBridge	167:e84263d55307	303	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
AnnaBridge	167:e84263d55307	304	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
AnnaBridge	167:e84263d55307	305	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
AnnaBridge	167:e84263d55307	306	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
AnnaBridge	167:e84263d55307	307	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
AnnaBridge	167:e84263d55307	308	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
AnnaBridge	167:e84263d55307	309	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
AnnaBridge	167:e84263d55307	310	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
AnnaBridge	167:e84263d55307	311	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
AnnaBridge	167:e84263d55307	312	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
AnnaBridge	167:e84263d55307	313	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
AnnaBridge	167:e84263d55307	314	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
AnnaBridge	167:e84263d55307	315	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
AnnaBridge	167:e84263d55307	316	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
AnnaBridge	167:e84263d55307	317	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
AnnaBridge	167:e84263d55307	318	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
AnnaBridge	167:e84263d55307	319	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
AnnaBridge	167:e84263d55307	320	/**
AnnaBridge	167:e84263d55307	321	* @}
AnnaBridge	167:e84263d55307	322	*/
AnnaBridge	167:e84263d55307	323
AnnaBridge	167:e84263d55307	324	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	325	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	167:e84263d55307	326	* @{
AnnaBridge	167:e84263d55307	327	*/
AnnaBridge	167:e84263d55307	328	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	167:e84263d55307	329	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	167:e84263d55307	330	/**
AnnaBridge	167:e84263d55307	331	* @}
AnnaBridge	167:e84263d55307	332	*/
AnnaBridge	167:e84263d55307	333	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	334
AnnaBridge	167:e84263d55307	335	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
AnnaBridge	167:e84263d55307	336	* @{
AnnaBridge	167:e84263d55307	337	*/
AnnaBridge	167:e84263d55307	338	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
AnnaBridge	167:e84263d55307	339	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
AnnaBridge	167:e84263d55307	340	/**
AnnaBridge	167:e84263d55307	341	* @}
AnnaBridge	167:e84263d55307	342	*/
AnnaBridge	167:e84263d55307	343
AnnaBridge	167:e84263d55307	344	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
AnnaBridge	167:e84263d55307	345	* @{
AnnaBridge	167:e84263d55307	346	*/
AnnaBridge	167:e84263d55307	347	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S1 Clock source selection /
AnnaBridge	167:e84263d55307	348	/**
AnnaBridge	167:e84263d55307	349	* @}
AnnaBridge	167:e84263d55307	350	*/
AnnaBridge	167:e84263d55307	351
AnnaBridge	167:e84263d55307	352	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	167:e84263d55307	353	* @{
AnnaBridge	167:e84263d55307	354	*/
AnnaBridge	167:e84263d55307	355	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	167:e84263d55307	356	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	167:e84263d55307	357	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	167:e84263d55307	358	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
AnnaBridge	167:e84263d55307	359	/**
AnnaBridge	167:e84263d55307	360	* @}
AnnaBridge	167:e84263d55307	361	*/
AnnaBridge	167:e84263d55307	362
AnnaBridge	167:e84263d55307	363	/** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLI2S entry clock source
AnnaBridge	167:e84263d55307	364	* @{
AnnaBridge	167:e84263d55307	365	*/
AnnaBridge	167:e84263d55307	366	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
AnnaBridge	167:e84263d55307	367	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	167:e84263d55307	368	/**
AnnaBridge	167:e84263d55307	369	* @}
AnnaBridge	167:e84263d55307	370	*/
AnnaBridge	167:e84263d55307	371
AnnaBridge	167:e84263d55307	372	/** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLI2S division factor
AnnaBridge	167:e84263d55307	373	* @{
AnnaBridge	167:e84263d55307	374	*/
AnnaBridge	167:e84263d55307	375	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 2 /
AnnaBridge	167:e84263d55307	376	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 3 /
AnnaBridge	167:e84263d55307	377	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 4 /
AnnaBridge	167:e84263d55307	378	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 5 /
AnnaBridge	167:e84263d55307	379	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 6 /
AnnaBridge	167:e84263d55307	380	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 7 /
AnnaBridge	167:e84263d55307	381	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 8 /
AnnaBridge	167:e84263d55307	382	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 9 /
AnnaBridge	167:e84263d55307	383	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 10 /
AnnaBridge	167:e84263d55307	384	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 11 /
AnnaBridge	167:e84263d55307	385	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 12 /
AnnaBridge	167:e84263d55307	386	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 13 /
AnnaBridge	167:e84263d55307	387	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 14 /
AnnaBridge	167:e84263d55307	388	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 15 /
AnnaBridge	167:e84263d55307	389	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL and PLLI2S division factor by 16 /
AnnaBridge	167:e84263d55307	390	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 17 /
AnnaBridge	167:e84263d55307	391	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 18 /
AnnaBridge	167:e84263d55307	392	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 19 /
AnnaBridge	167:e84263d55307	393	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 20 /
AnnaBridge	167:e84263d55307	394	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 21 /
AnnaBridge	167:e84263d55307	395	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 22 /
AnnaBridge	167:e84263d55307	396	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 23 /
AnnaBridge	167:e84263d55307	397	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 24 /
AnnaBridge	167:e84263d55307	398	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 25 /
AnnaBridge	167:e84263d55307	399	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 26 /
AnnaBridge	167:e84263d55307	400	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 27 /
AnnaBridge	167:e84263d55307	401	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 28 /
AnnaBridge	167:e84263d55307	402	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 29 /
AnnaBridge	167:e84263d55307	403	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 30 /
AnnaBridge	167:e84263d55307	404	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 31 /
AnnaBridge	167:e84263d55307	405	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL and PLLI2S division factor by 32 /
AnnaBridge	167:e84263d55307	406	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 33 /
AnnaBridge	167:e84263d55307	407	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 34 /
AnnaBridge	167:e84263d55307	408	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 35 /
AnnaBridge	167:e84263d55307	409	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 36 /
AnnaBridge	167:e84263d55307	410	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 37 /
AnnaBridge	167:e84263d55307	411	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 38 /
AnnaBridge	167:e84263d55307	412	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 39 /
AnnaBridge	167:e84263d55307	413	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 40 /
AnnaBridge	167:e84263d55307	414	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 41 /
AnnaBridge	167:e84263d55307	415	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 42 /
AnnaBridge	167:e84263d55307	416	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 43 /
AnnaBridge	167:e84263d55307	417	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 44 /
AnnaBridge	167:e84263d55307	418	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 45 /
AnnaBridge	167:e84263d55307	419	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 46 /
AnnaBridge	167:e84263d55307	420	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 47 /
AnnaBridge	167:e84263d55307	421	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL and PLLI2S division factor by 48 /
AnnaBridge	167:e84263d55307	422	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 49 /
AnnaBridge	167:e84263d55307	423	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 50 /
AnnaBridge	167:e84263d55307	424	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 51 /
AnnaBridge	167:e84263d55307	425	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 52 /
AnnaBridge	167:e84263d55307	426	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 53 /
AnnaBridge	167:e84263d55307	427	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 54 /
AnnaBridge	167:e84263d55307	428	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 55 /
AnnaBridge	167:e84263d55307	429	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 56 /
AnnaBridge	167:e84263d55307	430	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 57 /
AnnaBridge	167:e84263d55307	431	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 58 /
AnnaBridge	167:e84263d55307	432	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 59 /
AnnaBridge	167:e84263d55307	433	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 60 /
AnnaBridge	167:e84263d55307	434	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 61 /
AnnaBridge	167:e84263d55307	435	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 62 /
AnnaBridge	167:e84263d55307	436	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 63 /
AnnaBridge	167:e84263d55307	437	/**
AnnaBridge	167:e84263d55307	438	* @}
AnnaBridge	167:e84263d55307	439	*/
AnnaBridge	167:e84263d55307	440
AnnaBridge	167:e84263d55307	441	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
AnnaBridge	167:e84263d55307	442	* @{
AnnaBridge	167:e84263d55307	443	*/
AnnaBridge	167:e84263d55307	444	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
AnnaBridge	167:e84263d55307	445	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
AnnaBridge	167:e84263d55307	446	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
AnnaBridge	167:e84263d55307	447	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
AnnaBridge	167:e84263d55307	448	/**
AnnaBridge	167:e84263d55307	449	* @}
AnnaBridge	167:e84263d55307	450	*/
AnnaBridge	167:e84263d55307	451
AnnaBridge	167:e84263d55307	452	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
AnnaBridge	167:e84263d55307	453	* @{
AnnaBridge	167:e84263d55307	454	*/
AnnaBridge	167:e84263d55307	455	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
AnnaBridge	167:e84263d55307	456	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
AnnaBridge	167:e84263d55307	457	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
AnnaBridge	167:e84263d55307	458	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
AnnaBridge	167:e84263d55307	459	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
AnnaBridge	167:e84263d55307	460	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
AnnaBridge	167:e84263d55307	461	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
AnnaBridge	167:e84263d55307	462	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
AnnaBridge	167:e84263d55307	463	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
AnnaBridge	167:e84263d55307	464	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
AnnaBridge	167:e84263d55307	465	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
AnnaBridge	167:e84263d55307	466	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
AnnaBridge	167:e84263d55307	467	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
AnnaBridge	167:e84263d55307	468	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
AnnaBridge	167:e84263d55307	469	/**
AnnaBridge	167:e84263d55307	470	* @}
AnnaBridge	167:e84263d55307	471	*/
AnnaBridge	167:e84263d55307	472
AnnaBridge	167:e84263d55307	473	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
AnnaBridge	167:e84263d55307	474	* @{
AnnaBridge	167:e84263d55307	475	*/
AnnaBridge	167:e84263d55307	476	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
AnnaBridge	167:e84263d55307	477	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
AnnaBridge	167:e84263d55307	478	/**
AnnaBridge	167:e84263d55307	479	* @}
AnnaBridge	167:e84263d55307	480	*/
AnnaBridge	167:e84263d55307	481
AnnaBridge	167:e84263d55307	482	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
AnnaBridge	167:e84263d55307	483	* @{
AnnaBridge	167:e84263d55307	484	*/
AnnaBridge	167:e84263d55307	485	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
AnnaBridge	167:e84263d55307	486	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
AnnaBridge	167:e84263d55307	487	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
AnnaBridge	167:e84263d55307	488	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
AnnaBridge	167:e84263d55307	489	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
AnnaBridge	167:e84263d55307	490	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
AnnaBridge	167:e84263d55307	491	/**
AnnaBridge	167:e84263d55307	492	* @}
AnnaBridge	167:e84263d55307	493	*/
AnnaBridge	167:e84263d55307	494
AnnaBridge	167:e84263d55307	495	/**
AnnaBridge	167:e84263d55307	496	* @}
AnnaBridge	167:e84263d55307	497	*/
AnnaBridge	167:e84263d55307	498
AnnaBridge	167:e84263d55307	499	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	500	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	167:e84263d55307	501	* @{
AnnaBridge	167:e84263d55307	502	*/
AnnaBridge	167:e84263d55307	503
AnnaBridge	167:e84263d55307	504	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	167:e84263d55307	505	* @{
AnnaBridge	167:e84263d55307	506	*/
AnnaBridge	167:e84263d55307	507
AnnaBridge	167:e84263d55307	508	/**
AnnaBridge	167:e84263d55307	509	* @brief Write a value in RCC register
AnnaBridge	167:e84263d55307	510	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	511	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	512	* @retval None
AnnaBridge	167:e84263d55307	513	*/
AnnaBridge	167:e84263d55307	514	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	515
AnnaBridge	167:e84263d55307	516	/**
AnnaBridge	167:e84263d55307	517	* @brief Read a value in RCC register
AnnaBridge	167:e84263d55307	518	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	519	* @retval Register value
AnnaBridge	167:e84263d55307	520	*/
AnnaBridge	167:e84263d55307	521	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	167:e84263d55307	522	/**
AnnaBridge	167:e84263d55307	523	* @}
AnnaBridge	167:e84263d55307	524	*/
AnnaBridge	167:e84263d55307	525
AnnaBridge	167:e84263d55307	526	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	167:e84263d55307	527	* @{
AnnaBridge	167:e84263d55307	528	*/
AnnaBridge	167:e84263d55307	529
AnnaBridge	167:e84263d55307	530	/**
AnnaBridge	167:e84263d55307	531	* @brief Helper macro to calculate the PLLCLK frequency on system domain
AnnaBridge	167:e84263d55307	532	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	167:e84263d55307	533	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	167:e84263d55307	534	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	167:e84263d55307	535	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	536	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	167:e84263d55307	537	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	167:e84263d55307	538	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	167:e84263d55307	539	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	167:e84263d55307	540	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	167:e84263d55307	541	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	167:e84263d55307	542	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	167:e84263d55307	543	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	167:e84263d55307	544	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	167:e84263d55307	545	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	167:e84263d55307	546	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	167:e84263d55307	547	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	167:e84263d55307	548	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	167:e84263d55307	549	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	167:e84263d55307	550	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	167:e84263d55307	551	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	167:e84263d55307	552	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	167:e84263d55307	553	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	167:e84263d55307	554	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	167:e84263d55307	555	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	167:e84263d55307	556	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	167:e84263d55307	557	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	167:e84263d55307	558	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	167:e84263d55307	559	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	167:e84263d55307	560	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	167:e84263d55307	561	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	167:e84263d55307	562	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	167:e84263d55307	563	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	167:e84263d55307	564	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	167:e84263d55307	565	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	167:e84263d55307	566	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	167:e84263d55307	567	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	167:e84263d55307	568	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	167:e84263d55307	569	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	167:e84263d55307	570	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	167:e84263d55307	571	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	167:e84263d55307	572	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	167:e84263d55307	573	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	167:e84263d55307	574	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	167:e84263d55307	575	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	167:e84263d55307	576	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	167:e84263d55307	577	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	167:e84263d55307	578	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	167:e84263d55307	579	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	167:e84263d55307	580	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	167:e84263d55307	581	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	167:e84263d55307	582	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	167:e84263d55307	583	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	167:e84263d55307	584	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	167:e84263d55307	585	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	167:e84263d55307	586	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	167:e84263d55307	587	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	167:e84263d55307	588	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	167:e84263d55307	589	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	167:e84263d55307	590	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	167:e84263d55307	591	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	167:e84263d55307	592	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	167:e84263d55307	593	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	167:e84263d55307	594	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	167:e84263d55307	595	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	167:e84263d55307	596	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	167:e84263d55307	597	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	167:e84263d55307	598	* @param __PLLN__ Between 192 and 432
AnnaBridge	167:e84263d55307	599	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	600	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	167:e84263d55307	601	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	167:e84263d55307	602	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	167:e84263d55307	603	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	167:e84263d55307	604	* @retval PLL clock frequency (in Hz)
AnnaBridge	167:e84263d55307	605	*/
AnnaBridge	167:e84263d55307	606	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	167:e84263d55307	607	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
AnnaBridge	167:e84263d55307	608
AnnaBridge	167:e84263d55307	609	/**
AnnaBridge	167:e84263d55307	610	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
AnnaBridge	167:e84263d55307	611	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	167:e84263d55307	612	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
AnnaBridge	167:e84263d55307	613	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	167:e84263d55307	614	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	615	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	167:e84263d55307	616	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	167:e84263d55307	617	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	167:e84263d55307	618	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	167:e84263d55307	619	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	167:e84263d55307	620	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	167:e84263d55307	621	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	167:e84263d55307	622	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	167:e84263d55307	623	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	167:e84263d55307	624	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	167:e84263d55307	625	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	167:e84263d55307	626	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	167:e84263d55307	627	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	167:e84263d55307	628	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	167:e84263d55307	629	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	167:e84263d55307	630	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	167:e84263d55307	631	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	167:e84263d55307	632	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	167:e84263d55307	633	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	167:e84263d55307	634	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	167:e84263d55307	635	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	167:e84263d55307	636	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	167:e84263d55307	637	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	167:e84263d55307	638	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	167:e84263d55307	639	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	167:e84263d55307	640	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	167:e84263d55307	641	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	167:e84263d55307	642	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	167:e84263d55307	643	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	167:e84263d55307	644	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	167:e84263d55307	645	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	167:e84263d55307	646	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	167:e84263d55307	647	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	167:e84263d55307	648	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	167:e84263d55307	649	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	167:e84263d55307	650	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	167:e84263d55307	651	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	167:e84263d55307	652	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	167:e84263d55307	653	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	167:e84263d55307	654	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	167:e84263d55307	655	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	167:e84263d55307	656	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	167:e84263d55307	657	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	167:e84263d55307	658	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	167:e84263d55307	659	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	167:e84263d55307	660	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	167:e84263d55307	661	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	167:e84263d55307	662	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	167:e84263d55307	663	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	167:e84263d55307	664	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	167:e84263d55307	665	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	167:e84263d55307	666	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	167:e84263d55307	667	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	167:e84263d55307	668	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	167:e84263d55307	669	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	167:e84263d55307	670	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	167:e84263d55307	671	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	167:e84263d55307	672	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	167:e84263d55307	673	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	167:e84263d55307	674	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	167:e84263d55307	675	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	167:e84263d55307	676	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	167:e84263d55307	677	* @param __PLLN__ Between 192 and 432
AnnaBridge	167:e84263d55307	678	* @param __PLLQ__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	679	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	167:e84263d55307	680	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	167:e84263d55307	681	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	167:e84263d55307	682	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	167:e84263d55307	683	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	167:e84263d55307	684	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	167:e84263d55307	685	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	167:e84263d55307	686	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	167:e84263d55307	687	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	167:e84263d55307	688	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	167:e84263d55307	689	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	167:e84263d55307	690	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	167:e84263d55307	691	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	167:e84263d55307	692	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	167:e84263d55307	693	* @retval PLL clock frequency (in Hz)
AnnaBridge	167:e84263d55307	694	*/
AnnaBridge	167:e84263d55307	695	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	167:e84263d55307	696	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
AnnaBridge	167:e84263d55307	697
AnnaBridge	167:e84263d55307	698	/**
AnnaBridge	167:e84263d55307	699	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	167:e84263d55307	700	*/
AnnaBridge	167:e84263d55307	701
AnnaBridge	167:e84263d55307	702	/**
AnnaBridge	167:e84263d55307	703	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
AnnaBridge	167:e84263d55307	704	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	167:e84263d55307	705	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
AnnaBridge	167:e84263d55307	706	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	167:e84263d55307	707	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	708	* @param __PLLI2SN__ Between 192 and 432
AnnaBridge	167:e84263d55307	709	* @param __PLLI2SR__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	710	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	167:e84263d55307	711	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	167:e84263d55307	712	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	167:e84263d55307	713	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	167:e84263d55307	714	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	167:e84263d55307	715	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	167:e84263d55307	716	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	167:e84263d55307	717	*/
AnnaBridge	167:e84263d55307	718	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	167:e84263d55307	719	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
AnnaBridge	167:e84263d55307	720
AnnaBridge	167:e84263d55307	721	/**
AnnaBridge	167:e84263d55307	722	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	167:e84263d55307	723	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
AnnaBridge	167:e84263d55307	724	* @param __AHBPRESCALER__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	725	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	167:e84263d55307	726	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	167:e84263d55307	727	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	167:e84263d55307	728	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	167:e84263d55307	729	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	167:e84263d55307	730	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	167:e84263d55307	731	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	167:e84263d55307	732	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	167:e84263d55307	733	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	167:e84263d55307	734	* @retval HCLK clock frequency (in Hz)
AnnaBridge	167:e84263d55307	735	*/
AnnaBridge	167:e84263d55307	736	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	167:e84263d55307	737
AnnaBridge	167:e84263d55307	738	/**
AnnaBridge	167:e84263d55307	739	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	167:e84263d55307	740	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	167:e84263d55307	741	* @param __APB1PRESCALER__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	742	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	167:e84263d55307	743	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	167:e84263d55307	744	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	167:e84263d55307	745	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	167:e84263d55307	746	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	167:e84263d55307	747	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	167:e84263d55307	748	*/
AnnaBridge	167:e84263d55307	749	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	167:e84263d55307	750
AnnaBridge	167:e84263d55307	751	/**
AnnaBridge	167:e84263d55307	752	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	167:e84263d55307	753	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	167:e84263d55307	754	* @param __APB2PRESCALER__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	755	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	167:e84263d55307	756	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	167:e84263d55307	757	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	167:e84263d55307	758	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	167:e84263d55307	759	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	167:e84263d55307	760	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	167:e84263d55307	761	*/
AnnaBridge	167:e84263d55307	762	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	167:e84263d55307	763
AnnaBridge	167:e84263d55307	764	/**
AnnaBridge	167:e84263d55307	765	* @}
AnnaBridge	167:e84263d55307	766	*/
AnnaBridge	167:e84263d55307	767
AnnaBridge	167:e84263d55307	768	/**
AnnaBridge	167:e84263d55307	769	* @}
AnnaBridge	167:e84263d55307	770	*/
AnnaBridge	167:e84263d55307	771
AnnaBridge	167:e84263d55307	772	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	773	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	167:e84263d55307	774	* @{
AnnaBridge	167:e84263d55307	775	*/
AnnaBridge	167:e84263d55307	776
AnnaBridge	167:e84263d55307	777	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	167:e84263d55307	778	* @{
AnnaBridge	167:e84263d55307	779	*/
AnnaBridge	167:e84263d55307	780
AnnaBridge	167:e84263d55307	781	/**
AnnaBridge	167:e84263d55307	782	* @brief Enable the Clock Security System.
AnnaBridge	167:e84263d55307	783	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	167:e84263d55307	784	* @retval None
AnnaBridge	167:e84263d55307	785	*/
AnnaBridge	167:e84263d55307	786	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	167:e84263d55307	787	{
AnnaBridge	167:e84263d55307	788	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	167:e84263d55307	789	}
AnnaBridge	167:e84263d55307	790
AnnaBridge	167:e84263d55307	791	/**
AnnaBridge	167:e84263d55307	792	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	167:e84263d55307	793	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	167:e84263d55307	794	* @retval None
AnnaBridge	167:e84263d55307	795	*/
AnnaBridge	167:e84263d55307	796	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	167:e84263d55307	797	{
AnnaBridge	167:e84263d55307	798	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	167:e84263d55307	799	}
AnnaBridge	167:e84263d55307	800
AnnaBridge	167:e84263d55307	801	/**
AnnaBridge	167:e84263d55307	802	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	167:e84263d55307	803	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	167:e84263d55307	804	* @retval None
AnnaBridge	167:e84263d55307	805	*/
AnnaBridge	167:e84263d55307	806	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	167:e84263d55307	807	{
AnnaBridge	167:e84263d55307	808	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	167:e84263d55307	809	}
AnnaBridge	167:e84263d55307	810
AnnaBridge	167:e84263d55307	811	/**
AnnaBridge	167:e84263d55307	812	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	167:e84263d55307	813	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	167:e84263d55307	814	* @retval None
AnnaBridge	167:e84263d55307	815	*/
AnnaBridge	167:e84263d55307	816	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	167:e84263d55307	817	{
AnnaBridge	167:e84263d55307	818	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	167:e84263d55307	819	}
AnnaBridge	167:e84263d55307	820
AnnaBridge	167:e84263d55307	821	/**
AnnaBridge	167:e84263d55307	822	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	167:e84263d55307	823	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	167:e84263d55307	824	* @retval None
AnnaBridge	167:e84263d55307	825	*/
AnnaBridge	167:e84263d55307	826	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	167:e84263d55307	827	{
AnnaBridge	167:e84263d55307	828	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	167:e84263d55307	829	}
AnnaBridge	167:e84263d55307	830
AnnaBridge	167:e84263d55307	831	/**
AnnaBridge	167:e84263d55307	832	* @brief Check if HSE oscillator Ready
AnnaBridge	167:e84263d55307	833	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	167:e84263d55307	834	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	835	*/
AnnaBridge	167:e84263d55307	836	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	167:e84263d55307	837	{
AnnaBridge	167:e84263d55307	838	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	167:e84263d55307	839	}
AnnaBridge	167:e84263d55307	840
AnnaBridge	167:e84263d55307	841	/**
AnnaBridge	167:e84263d55307	842	* @}
AnnaBridge	167:e84263d55307	843	*/
AnnaBridge	167:e84263d55307	844
AnnaBridge	167:e84263d55307	845	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	167:e84263d55307	846	* @{
AnnaBridge	167:e84263d55307	847	*/
AnnaBridge	167:e84263d55307	848
AnnaBridge	167:e84263d55307	849	/**
AnnaBridge	167:e84263d55307	850	* @brief Enable HSI oscillator
AnnaBridge	167:e84263d55307	851	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	167:e84263d55307	852	* @retval None
AnnaBridge	167:e84263d55307	853	*/
AnnaBridge	167:e84263d55307	854	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	167:e84263d55307	855	{
AnnaBridge	167:e84263d55307	856	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	167:e84263d55307	857	}
AnnaBridge	167:e84263d55307	858
AnnaBridge	167:e84263d55307	859	/**
AnnaBridge	167:e84263d55307	860	* @brief Disable HSI oscillator
AnnaBridge	167:e84263d55307	861	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	167:e84263d55307	862	* @retval None
AnnaBridge	167:e84263d55307	863	*/
AnnaBridge	167:e84263d55307	864	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	167:e84263d55307	865	{
AnnaBridge	167:e84263d55307	866	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	167:e84263d55307	867	}
AnnaBridge	167:e84263d55307	868
AnnaBridge	167:e84263d55307	869	/**
AnnaBridge	167:e84263d55307	870	* @brief Check if HSI clock is ready
AnnaBridge	167:e84263d55307	871	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	167:e84263d55307	872	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	873	*/
AnnaBridge	167:e84263d55307	874	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	167:e84263d55307	875	{
AnnaBridge	167:e84263d55307	876	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	167:e84263d55307	877	}
AnnaBridge	167:e84263d55307	878
AnnaBridge	167:e84263d55307	879	/**
AnnaBridge	167:e84263d55307	880	* @brief Get HSI Calibration value
AnnaBridge	167:e84263d55307	881	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	167:e84263d55307	882	* HSITRIM and the factory trim value
AnnaBridge	167:e84263d55307	883	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	167:e84263d55307	884	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	167:e84263d55307	885	*/
AnnaBridge	167:e84263d55307	886	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	167:e84263d55307	887	{
AnnaBridge	167:e84263d55307	888	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
AnnaBridge	167:e84263d55307	889	}
AnnaBridge	167:e84263d55307	890
AnnaBridge	167:e84263d55307	891	/**
AnnaBridge	167:e84263d55307	892	* @brief Set HSI Calibration trimming
AnnaBridge	167:e84263d55307	893	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	167:e84263d55307	894	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	167:e84263d55307	895	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	167:e84263d55307	896	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	167:e84263d55307	897	* @param Value Between Min_Data = 0 and Max_Data = 31
AnnaBridge	167:e84263d55307	898	* @retval None
AnnaBridge	167:e84263d55307	899	*/
AnnaBridge	167:e84263d55307	900	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	167:e84263d55307	901	{
AnnaBridge	167:e84263d55307	902	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
AnnaBridge	167:e84263d55307	903	}
AnnaBridge	167:e84263d55307	904
AnnaBridge	167:e84263d55307	905	/**
AnnaBridge	167:e84263d55307	906	* @brief Get HSI Calibration trimming
AnnaBridge	167:e84263d55307	907	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	167:e84263d55307	908	* @retval Between Min_Data = 0 and Max_Data = 31
AnnaBridge	167:e84263d55307	909	*/
AnnaBridge	167:e84263d55307	910	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	167:e84263d55307	911	{
AnnaBridge	167:e84263d55307	912	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
AnnaBridge	167:e84263d55307	913	}
AnnaBridge	167:e84263d55307	914
AnnaBridge	167:e84263d55307	915	/**
AnnaBridge	167:e84263d55307	916	* @}
AnnaBridge	167:e84263d55307	917	*/
AnnaBridge	167:e84263d55307	918
AnnaBridge	167:e84263d55307	919	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	167:e84263d55307	920	* @{
AnnaBridge	167:e84263d55307	921	*/
AnnaBridge	167:e84263d55307	922
AnnaBridge	167:e84263d55307	923	/**
AnnaBridge	167:e84263d55307	924	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	167:e84263d55307	925	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	167:e84263d55307	926	* @retval None
AnnaBridge	167:e84263d55307	927	*/
AnnaBridge	167:e84263d55307	928	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	167:e84263d55307	929	{
AnnaBridge	167:e84263d55307	930	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	167:e84263d55307	931	}
AnnaBridge	167:e84263d55307	932
AnnaBridge	167:e84263d55307	933	/**
AnnaBridge	167:e84263d55307	934	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	167:e84263d55307	935	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	167:e84263d55307	936	* @retval None
AnnaBridge	167:e84263d55307	937	*/
AnnaBridge	167:e84263d55307	938	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	167:e84263d55307	939	{
AnnaBridge	167:e84263d55307	940	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	167:e84263d55307	941	}
AnnaBridge	167:e84263d55307	942
AnnaBridge	167:e84263d55307	943	/**
AnnaBridge	167:e84263d55307	944	* @brief Enable external clock source (LSE bypass).
AnnaBridge	167:e84263d55307	945	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	167:e84263d55307	946	* @retval None
AnnaBridge	167:e84263d55307	947	*/
AnnaBridge	167:e84263d55307	948	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	167:e84263d55307	949	{
AnnaBridge	167:e84263d55307	950	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	167:e84263d55307	951	}
AnnaBridge	167:e84263d55307	952
AnnaBridge	167:e84263d55307	953	/**
AnnaBridge	167:e84263d55307	954	* @brief Disable external clock source (LSE bypass).
AnnaBridge	167:e84263d55307	955	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	167:e84263d55307	956	* @retval None
AnnaBridge	167:e84263d55307	957	*/
AnnaBridge	167:e84263d55307	958	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	167:e84263d55307	959	{
AnnaBridge	167:e84263d55307	960	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	167:e84263d55307	961	}
AnnaBridge	167:e84263d55307	962
AnnaBridge	167:e84263d55307	963	/**
AnnaBridge	167:e84263d55307	964	* @brief Check if LSE oscillator Ready
AnnaBridge	167:e84263d55307	965	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	167:e84263d55307	966	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	967	*/
AnnaBridge	167:e84263d55307	968	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	167:e84263d55307	969	{
AnnaBridge	167:e84263d55307	970	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
AnnaBridge	167:e84263d55307	971	}
AnnaBridge	167:e84263d55307	972
AnnaBridge	167:e84263d55307	973	/**
AnnaBridge	167:e84263d55307	974	* @}
AnnaBridge	167:e84263d55307	975	*/
AnnaBridge	167:e84263d55307	976
AnnaBridge	167:e84263d55307	977	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	167:e84263d55307	978	* @{
AnnaBridge	167:e84263d55307	979	*/
AnnaBridge	167:e84263d55307	980
AnnaBridge	167:e84263d55307	981	/**
AnnaBridge	167:e84263d55307	982	* @brief Enable LSI Oscillator
AnnaBridge	167:e84263d55307	983	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	167:e84263d55307	984	* @retval None
AnnaBridge	167:e84263d55307	985	*/
AnnaBridge	167:e84263d55307	986	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	167:e84263d55307	987	{
AnnaBridge	167:e84263d55307	988	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	167:e84263d55307	989	}
AnnaBridge	167:e84263d55307	990
AnnaBridge	167:e84263d55307	991	/**
AnnaBridge	167:e84263d55307	992	* @brief Disable LSI Oscillator
AnnaBridge	167:e84263d55307	993	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	167:e84263d55307	994	* @retval None
AnnaBridge	167:e84263d55307	995	*/
AnnaBridge	167:e84263d55307	996	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	167:e84263d55307	997	{
AnnaBridge	167:e84263d55307	998	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	167:e84263d55307	999	}
AnnaBridge	167:e84263d55307	1000
AnnaBridge	167:e84263d55307	1001	/**
AnnaBridge	167:e84263d55307	1002	* @brief Check if LSI is Ready
AnnaBridge	167:e84263d55307	1003	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	167:e84263d55307	1004	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1005	*/
AnnaBridge	167:e84263d55307	1006	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	167:e84263d55307	1007	{
AnnaBridge	167:e84263d55307	1008	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	167:e84263d55307	1009	}
AnnaBridge	167:e84263d55307	1010
AnnaBridge	167:e84263d55307	1011	/**
AnnaBridge	167:e84263d55307	1012	* @}
AnnaBridge	167:e84263d55307	1013	*/
AnnaBridge	167:e84263d55307	1014
AnnaBridge	167:e84263d55307	1015	/** @defgroup RCC_LL_EF_System System
AnnaBridge	167:e84263d55307	1016	* @{
AnnaBridge	167:e84263d55307	1017	*/
AnnaBridge	167:e84263d55307	1018
AnnaBridge	167:e84263d55307	1019	/**
AnnaBridge	167:e84263d55307	1020	* @brief Configure the system clock source
AnnaBridge	167:e84263d55307	1021	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	167:e84263d55307	1022	* @param Source This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1023	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	167:e84263d55307	1024	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	167:e84263d55307	1025	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	167:e84263d55307	1026	* @retval None
AnnaBridge	167:e84263d55307	1027	*/
AnnaBridge	167:e84263d55307	1028	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	167:e84263d55307	1029	{
AnnaBridge	167:e84263d55307	1030	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	167:e84263d55307	1031	}
AnnaBridge	167:e84263d55307	1032
AnnaBridge	167:e84263d55307	1033	/**
AnnaBridge	167:e84263d55307	1034	* @brief Get the system clock source
AnnaBridge	167:e84263d55307	1035	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	167:e84263d55307	1036	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1037	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	167:e84263d55307	1038	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	167:e84263d55307	1039	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	167:e84263d55307	1040	*/
AnnaBridge	167:e84263d55307	1041	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	167:e84263d55307	1042	{
AnnaBridge	167:e84263d55307	1043	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	167:e84263d55307	1044	}
AnnaBridge	167:e84263d55307	1045
AnnaBridge	167:e84263d55307	1046	/**
AnnaBridge	167:e84263d55307	1047	* @brief Set AHB prescaler
AnnaBridge	167:e84263d55307	1048	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	167:e84263d55307	1049	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1050	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	167:e84263d55307	1051	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	167:e84263d55307	1052	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	167:e84263d55307	1053	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	167:e84263d55307	1054	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	167:e84263d55307	1055	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	167:e84263d55307	1056	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	167:e84263d55307	1057	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	167:e84263d55307	1058	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	167:e84263d55307	1059	* @retval None
AnnaBridge	167:e84263d55307	1060	*/
AnnaBridge	167:e84263d55307	1061	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	167:e84263d55307	1062	{
AnnaBridge	167:e84263d55307	1063	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	167:e84263d55307	1064	}
AnnaBridge	167:e84263d55307	1065
AnnaBridge	167:e84263d55307	1066	/**
AnnaBridge	167:e84263d55307	1067	* @brief Set APB1 prescaler
AnnaBridge	167:e84263d55307	1068	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	167:e84263d55307	1069	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1070	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	167:e84263d55307	1071	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	167:e84263d55307	1072	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	167:e84263d55307	1073	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	167:e84263d55307	1074	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	167:e84263d55307	1075	* @retval None
AnnaBridge	167:e84263d55307	1076	*/
AnnaBridge	167:e84263d55307	1077	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	167:e84263d55307	1078	{
AnnaBridge	167:e84263d55307	1079	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	167:e84263d55307	1080	}
AnnaBridge	167:e84263d55307	1081
AnnaBridge	167:e84263d55307	1082	/**
AnnaBridge	167:e84263d55307	1083	* @brief Set APB2 prescaler
AnnaBridge	167:e84263d55307	1084	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	167:e84263d55307	1085	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1086	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	167:e84263d55307	1087	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	167:e84263d55307	1088	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	167:e84263d55307	1089	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	167:e84263d55307	1090	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	167:e84263d55307	1091	* @retval None
AnnaBridge	167:e84263d55307	1092	*/
AnnaBridge	167:e84263d55307	1093	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	167:e84263d55307	1094	{
AnnaBridge	167:e84263d55307	1095	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	167:e84263d55307	1096	}
AnnaBridge	167:e84263d55307	1097
AnnaBridge	167:e84263d55307	1098	/**
AnnaBridge	167:e84263d55307	1099	* @brief Get AHB prescaler
AnnaBridge	167:e84263d55307	1100	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	167:e84263d55307	1101	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1102	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	167:e84263d55307	1103	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	167:e84263d55307	1104	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	167:e84263d55307	1105	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	167:e84263d55307	1106	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	167:e84263d55307	1107	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	167:e84263d55307	1108	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	167:e84263d55307	1109	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	167:e84263d55307	1110	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	167:e84263d55307	1111	*/
AnnaBridge	167:e84263d55307	1112	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	167:e84263d55307	1113	{
AnnaBridge	167:e84263d55307	1114	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	167:e84263d55307	1115	}
AnnaBridge	167:e84263d55307	1116
AnnaBridge	167:e84263d55307	1117	/**
AnnaBridge	167:e84263d55307	1118	* @brief Get APB1 prescaler
AnnaBridge	167:e84263d55307	1119	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	167:e84263d55307	1120	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1121	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	167:e84263d55307	1122	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	167:e84263d55307	1123	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	167:e84263d55307	1124	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	167:e84263d55307	1125	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	167:e84263d55307	1126	*/
AnnaBridge	167:e84263d55307	1127	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	167:e84263d55307	1128	{
AnnaBridge	167:e84263d55307	1129	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	167:e84263d55307	1130	}
AnnaBridge	167:e84263d55307	1131
AnnaBridge	167:e84263d55307	1132	/**
AnnaBridge	167:e84263d55307	1133	* @brief Get APB2 prescaler
AnnaBridge	167:e84263d55307	1134	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	167:e84263d55307	1135	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1136	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	167:e84263d55307	1137	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	167:e84263d55307	1138	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	167:e84263d55307	1139	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	167:e84263d55307	1140	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	167:e84263d55307	1141	*/
AnnaBridge	167:e84263d55307	1142	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	167:e84263d55307	1143	{
AnnaBridge	167:e84263d55307	1144	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	167:e84263d55307	1145	}
AnnaBridge	167:e84263d55307	1146
AnnaBridge	167:e84263d55307	1147	/**
AnnaBridge	167:e84263d55307	1148	* @}
AnnaBridge	167:e84263d55307	1149	*/
AnnaBridge	167:e84263d55307	1150
AnnaBridge	167:e84263d55307	1151	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	167:e84263d55307	1152	* @{
AnnaBridge	167:e84263d55307	1153	*/
AnnaBridge	167:e84263d55307	1154
AnnaBridge	167:e84263d55307	1155	/**
AnnaBridge	167:e84263d55307	1156	* @brief Configure MCOx
AnnaBridge	167:e84263d55307	1157	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
AnnaBridge	167:e84263d55307	1158	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
AnnaBridge	167:e84263d55307	1159	* CFGR MCO2 LL_RCC_ConfigMCO\n
AnnaBridge	167:e84263d55307	1160	* CFGR MCO2PRE LL_RCC_ConfigMCO
AnnaBridge	167:e84263d55307	1161	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1162	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	167:e84263d55307	1163	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	167:e84263d55307	1164	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	167:e84263d55307	1165	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	167:e84263d55307	1166	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
AnnaBridge	167:e84263d55307	1167	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
AnnaBridge	167:e84263d55307	1168	* @arg @ref LL_RCC_MCO2SOURCE_HSE
AnnaBridge	167:e84263d55307	1169	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
AnnaBridge	167:e84263d55307	1170	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1171	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	167:e84263d55307	1172	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	167:e84263d55307	1173	* @arg @ref LL_RCC_MCO1_DIV_3
AnnaBridge	167:e84263d55307	1174	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	167:e84263d55307	1175	* @arg @ref LL_RCC_MCO1_DIV_5
AnnaBridge	167:e84263d55307	1176	* @arg @ref LL_RCC_MCO2_DIV_1
AnnaBridge	167:e84263d55307	1177	* @arg @ref LL_RCC_MCO2_DIV_2
AnnaBridge	167:e84263d55307	1178	* @arg @ref LL_RCC_MCO2_DIV_3
AnnaBridge	167:e84263d55307	1179	* @arg @ref LL_RCC_MCO2_DIV_4
AnnaBridge	167:e84263d55307	1180	* @arg @ref LL_RCC_MCO2_DIV_5
AnnaBridge	167:e84263d55307	1181	* @retval None
AnnaBridge	167:e84263d55307	1182	*/
AnnaBridge	167:e84263d55307	1183	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	167:e84263d55307	1184	{
AnnaBridge	167:e84263d55307	1185	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
AnnaBridge	167:e84263d55307	1186	}
AnnaBridge	167:e84263d55307	1187
AnnaBridge	167:e84263d55307	1188	/**
AnnaBridge	167:e84263d55307	1189	* @}
AnnaBridge	167:e84263d55307	1190	*/
AnnaBridge	167:e84263d55307	1191
AnnaBridge	167:e84263d55307	1192	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	167:e84263d55307	1193	* @{
AnnaBridge	167:e84263d55307	1194	*/
AnnaBridge	167:e84263d55307	1195
AnnaBridge	167:e84263d55307	1196	/**
AnnaBridge	167:e84263d55307	1197	* @brief Configure I2S clock source
AnnaBridge	167:e84263d55307	1198	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
AnnaBridge	167:e84263d55307	1199	* @param Source This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1200	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
AnnaBridge	167:e84263d55307	1201	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	167:e84263d55307	1202	* @retval None
AnnaBridge	167:e84263d55307	1203	*/
AnnaBridge	167:e84263d55307	1204	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
AnnaBridge	167:e84263d55307	1205	{
AnnaBridge	167:e84263d55307	1206	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
AnnaBridge	167:e84263d55307	1207	}
AnnaBridge	167:e84263d55307	1208
AnnaBridge	167:e84263d55307	1209	/**
AnnaBridge	167:e84263d55307	1210	* @brief Get I2S Clock Source
AnnaBridge	167:e84263d55307	1211	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
AnnaBridge	167:e84263d55307	1212	* @param I2Sx This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1213	* @arg @ref LL_RCC_I2S1_CLKSOURCE
AnnaBridge	167:e84263d55307	1214	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1215	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
AnnaBridge	167:e84263d55307	1216	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	167:e84263d55307	1217	*/
AnnaBridge	167:e84263d55307	1218	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
AnnaBridge	167:e84263d55307	1219	{
AnnaBridge	167:e84263d55307	1220	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
AnnaBridge	167:e84263d55307	1221	}
AnnaBridge	167:e84263d55307	1222
AnnaBridge	167:e84263d55307	1223	/**
AnnaBridge	167:e84263d55307	1224	* @}
AnnaBridge	167:e84263d55307	1225	*/
AnnaBridge	167:e84263d55307	1226
AnnaBridge	167:e84263d55307	1227	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	167:e84263d55307	1228	* @{
AnnaBridge	167:e84263d55307	1229	*/
AnnaBridge	167:e84263d55307	1230
AnnaBridge	167:e84263d55307	1231	/**
AnnaBridge	167:e84263d55307	1232	* @brief Set RTC Clock Source
AnnaBridge	167:e84263d55307	1233	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
AnnaBridge	167:e84263d55307	1234	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	167:e84263d55307	1235	* set). The BDRST bit can be used to reset them.
AnnaBridge	167:e84263d55307	1236	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	167:e84263d55307	1237	* @param Source This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1238	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	167:e84263d55307	1239	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	167:e84263d55307	1240	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	167:e84263d55307	1241	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	167:e84263d55307	1242	* @retval None
AnnaBridge	167:e84263d55307	1243	*/
AnnaBridge	167:e84263d55307	1244	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	167:e84263d55307	1245	{
AnnaBridge	167:e84263d55307	1246	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	167:e84263d55307	1247	}
AnnaBridge	167:e84263d55307	1248
AnnaBridge	167:e84263d55307	1249	/**
AnnaBridge	167:e84263d55307	1250	* @brief Get RTC Clock Source
AnnaBridge	167:e84263d55307	1251	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	167:e84263d55307	1252	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1253	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	167:e84263d55307	1254	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	167:e84263d55307	1255	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	167:e84263d55307	1256	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	167:e84263d55307	1257	*/
AnnaBridge	167:e84263d55307	1258	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	167:e84263d55307	1259	{
AnnaBridge	167:e84263d55307	1260	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	167:e84263d55307	1261	}
AnnaBridge	167:e84263d55307	1262
AnnaBridge	167:e84263d55307	1263	/**
AnnaBridge	167:e84263d55307	1264	* @brief Enable RTC
AnnaBridge	167:e84263d55307	1265	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	167:e84263d55307	1266	* @retval None
AnnaBridge	167:e84263d55307	1267	*/
AnnaBridge	167:e84263d55307	1268	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	167:e84263d55307	1269	{
AnnaBridge	167:e84263d55307	1270	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	167:e84263d55307	1271	}
AnnaBridge	167:e84263d55307	1272
AnnaBridge	167:e84263d55307	1273	/**
AnnaBridge	167:e84263d55307	1274	* @brief Disable RTC
AnnaBridge	167:e84263d55307	1275	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	167:e84263d55307	1276	* @retval None
AnnaBridge	167:e84263d55307	1277	*/
AnnaBridge	167:e84263d55307	1278	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	167:e84263d55307	1279	{
AnnaBridge	167:e84263d55307	1280	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	167:e84263d55307	1281	}
AnnaBridge	167:e84263d55307	1282
AnnaBridge	167:e84263d55307	1283	/**
AnnaBridge	167:e84263d55307	1284	* @brief Check if RTC has been enabled or not
AnnaBridge	167:e84263d55307	1285	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	167:e84263d55307	1286	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1287	*/
AnnaBridge	167:e84263d55307	1288	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	167:e84263d55307	1289	{
AnnaBridge	167:e84263d55307	1290	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
AnnaBridge	167:e84263d55307	1291	}
AnnaBridge	167:e84263d55307	1292
AnnaBridge	167:e84263d55307	1293	/**
AnnaBridge	167:e84263d55307	1294	* @brief Force the Backup domain reset
AnnaBridge	167:e84263d55307	1295	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	167:e84263d55307	1296	* @retval None
AnnaBridge	167:e84263d55307	1297	*/
AnnaBridge	167:e84263d55307	1298	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	167:e84263d55307	1299	{
AnnaBridge	167:e84263d55307	1300	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	167:e84263d55307	1301	}
AnnaBridge	167:e84263d55307	1302
AnnaBridge	167:e84263d55307	1303	/**
AnnaBridge	167:e84263d55307	1304	* @brief Release the Backup domain reset
AnnaBridge	167:e84263d55307	1305	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	167:e84263d55307	1306	* @retval None
AnnaBridge	167:e84263d55307	1307	*/
AnnaBridge	167:e84263d55307	1308	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	167:e84263d55307	1309	{
AnnaBridge	167:e84263d55307	1310	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	167:e84263d55307	1311	}
AnnaBridge	167:e84263d55307	1312
AnnaBridge	167:e84263d55307	1313	/**
AnnaBridge	167:e84263d55307	1314	* @brief Set HSE Prescalers for RTC Clock
AnnaBridge	167:e84263d55307	1315	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
AnnaBridge	167:e84263d55307	1316	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1317	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	167:e84263d55307	1318	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	167:e84263d55307	1319	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	167:e84263d55307	1320	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	167:e84263d55307	1321	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	167:e84263d55307	1322	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	167:e84263d55307	1323	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	167:e84263d55307	1324	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	167:e84263d55307	1325	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	167:e84263d55307	1326	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	167:e84263d55307	1327	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	167:e84263d55307	1328	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	167:e84263d55307	1329	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	167:e84263d55307	1330	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	167:e84263d55307	1331	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	167:e84263d55307	1332	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	167:e84263d55307	1333	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	167:e84263d55307	1334	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	167:e84263d55307	1335	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	167:e84263d55307	1336	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	167:e84263d55307	1337	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	167:e84263d55307	1338	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	167:e84263d55307	1339	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	167:e84263d55307	1340	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	167:e84263d55307	1341	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	167:e84263d55307	1342	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	167:e84263d55307	1343	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	167:e84263d55307	1344	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	167:e84263d55307	1345	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	167:e84263d55307	1346	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	167:e84263d55307	1347	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	167:e84263d55307	1348	* @retval None
AnnaBridge	167:e84263d55307	1349	*/
AnnaBridge	167:e84263d55307	1350	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
AnnaBridge	167:e84263d55307	1351	{
AnnaBridge	167:e84263d55307	1352	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
AnnaBridge	167:e84263d55307	1353	}
AnnaBridge	167:e84263d55307	1354
AnnaBridge	167:e84263d55307	1355	/**
AnnaBridge	167:e84263d55307	1356	* @brief Get HSE Prescalers for RTC Clock
AnnaBridge	167:e84263d55307	1357	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
AnnaBridge	167:e84263d55307	1358	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1359	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	167:e84263d55307	1360	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	167:e84263d55307	1361	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	167:e84263d55307	1362	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	167:e84263d55307	1363	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	167:e84263d55307	1364	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	167:e84263d55307	1365	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	167:e84263d55307	1366	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	167:e84263d55307	1367	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	167:e84263d55307	1368	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	167:e84263d55307	1369	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	167:e84263d55307	1370	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	167:e84263d55307	1371	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	167:e84263d55307	1372	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	167:e84263d55307	1373	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	167:e84263d55307	1374	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	167:e84263d55307	1375	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	167:e84263d55307	1376	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	167:e84263d55307	1377	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	167:e84263d55307	1378	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	167:e84263d55307	1379	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	167:e84263d55307	1380	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	167:e84263d55307	1381	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	167:e84263d55307	1382	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	167:e84263d55307	1383	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	167:e84263d55307	1384	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	167:e84263d55307	1385	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	167:e84263d55307	1386	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	167:e84263d55307	1387	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	167:e84263d55307	1388	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	167:e84263d55307	1389	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	167:e84263d55307	1390	*/
AnnaBridge	167:e84263d55307	1391	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
AnnaBridge	167:e84263d55307	1392	{
AnnaBridge	167:e84263d55307	1393	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
AnnaBridge	167:e84263d55307	1394	}
AnnaBridge	167:e84263d55307	1395
AnnaBridge	167:e84263d55307	1396	/**
AnnaBridge	167:e84263d55307	1397	* @}
AnnaBridge	167:e84263d55307	1398	*/
AnnaBridge	167:e84263d55307	1399
AnnaBridge	167:e84263d55307	1400	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	167:e84263d55307	1401	* @{
AnnaBridge	167:e84263d55307	1402	*/
AnnaBridge	167:e84263d55307	1403
AnnaBridge	167:e84263d55307	1404	/**
AnnaBridge	167:e84263d55307	1405	* @brief Enable PLL
AnnaBridge	167:e84263d55307	1406	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	167:e84263d55307	1407	* @retval None
AnnaBridge	167:e84263d55307	1408	*/
AnnaBridge	167:e84263d55307	1409	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	167:e84263d55307	1410	{
AnnaBridge	167:e84263d55307	1411	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	167:e84263d55307	1412	}
AnnaBridge	167:e84263d55307	1413
AnnaBridge	167:e84263d55307	1414	/**
AnnaBridge	167:e84263d55307	1415	* @brief Disable PLL
AnnaBridge	167:e84263d55307	1416	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	167:e84263d55307	1417	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	167:e84263d55307	1418	* @retval None
AnnaBridge	167:e84263d55307	1419	*/
AnnaBridge	167:e84263d55307	1420	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	167:e84263d55307	1421	{
AnnaBridge	167:e84263d55307	1422	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	167:e84263d55307	1423	}
AnnaBridge	167:e84263d55307	1424
AnnaBridge	167:e84263d55307	1425	/**
AnnaBridge	167:e84263d55307	1426	* @brief Check if PLL Ready
AnnaBridge	167:e84263d55307	1427	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	167:e84263d55307	1428	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1429	*/
AnnaBridge	167:e84263d55307	1430	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	167:e84263d55307	1431	{
AnnaBridge	167:e84263d55307	1432	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	167:e84263d55307	1433	}
AnnaBridge	167:e84263d55307	1434
AnnaBridge	167:e84263d55307	1435	/**
AnnaBridge	167:e84263d55307	1436	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	167:e84263d55307	1437	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	167:e84263d55307	1438	* PLLI2S are disabled
AnnaBridge	167:e84263d55307	1439	* @note PLLN/PLLP can be written only when PLL is disabled
AnnaBridge	167:e84263d55307	1440	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	167:e84263d55307	1441	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	167:e84263d55307	1442	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	167:e84263d55307	1443	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	167:e84263d55307	1444	* @param Source This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1445	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	167:e84263d55307	1446	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	167:e84263d55307	1447	* @param PLLM This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1448	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	167:e84263d55307	1449	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	167:e84263d55307	1450	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	167:e84263d55307	1451	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	167:e84263d55307	1452	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	167:e84263d55307	1453	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	167:e84263d55307	1454	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	167:e84263d55307	1455	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	167:e84263d55307	1456	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	167:e84263d55307	1457	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	167:e84263d55307	1458	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	167:e84263d55307	1459	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	167:e84263d55307	1460	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	167:e84263d55307	1461	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	167:e84263d55307	1462	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	167:e84263d55307	1463	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	167:e84263d55307	1464	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	167:e84263d55307	1465	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	167:e84263d55307	1466	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	167:e84263d55307	1467	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	167:e84263d55307	1468	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	167:e84263d55307	1469	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	167:e84263d55307	1470	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	167:e84263d55307	1471	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	167:e84263d55307	1472	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	167:e84263d55307	1473	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	167:e84263d55307	1474	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	167:e84263d55307	1475	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	167:e84263d55307	1476	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	167:e84263d55307	1477	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	167:e84263d55307	1478	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	167:e84263d55307	1479	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	167:e84263d55307	1480	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	167:e84263d55307	1481	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	167:e84263d55307	1482	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	167:e84263d55307	1483	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	167:e84263d55307	1484	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	167:e84263d55307	1485	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	167:e84263d55307	1486	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	167:e84263d55307	1487	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	167:e84263d55307	1488	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	167:e84263d55307	1489	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	167:e84263d55307	1490	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	167:e84263d55307	1491	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	167:e84263d55307	1492	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	167:e84263d55307	1493	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	167:e84263d55307	1494	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	167:e84263d55307	1495	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	167:e84263d55307	1496	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	167:e84263d55307	1497	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	167:e84263d55307	1498	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	167:e84263d55307	1499	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	167:e84263d55307	1500	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	167:e84263d55307	1501	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	167:e84263d55307	1502	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	167:e84263d55307	1503	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	167:e84263d55307	1504	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	167:e84263d55307	1505	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	167:e84263d55307	1506	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	167:e84263d55307	1507	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	167:e84263d55307	1508	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	167:e84263d55307	1509	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	167:e84263d55307	1510	* @param PLLN Between 192 and 432
AnnaBridge	167:e84263d55307	1511	* @param PLLP This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1512	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	167:e84263d55307	1513	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	167:e84263d55307	1514	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	167:e84263d55307	1515	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	167:e84263d55307	1516	* @retval None
AnnaBridge	167:e84263d55307	1517	*/
AnnaBridge	167:e84263d55307	1518	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	167:e84263d55307	1519	{
AnnaBridge	167:e84263d55307	1520	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
AnnaBridge	167:e84263d55307	1521	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
AnnaBridge	167:e84263d55307	1522	}
AnnaBridge	167:e84263d55307	1523
AnnaBridge	167:e84263d55307	1524	/**
AnnaBridge	167:e84263d55307	1525	* @brief Configure PLL used for 48Mhz domain clock
AnnaBridge	167:e84263d55307	1526	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	167:e84263d55307	1527	* PLLI2S are disabled
AnnaBridge	167:e84263d55307	1528	* @note PLLN/PLLQ can be written only when PLL is disabled
AnnaBridge	167:e84263d55307	1529	* @note This can be selected for USB, RNG, SDIO
AnnaBridge	167:e84263d55307	1530	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	167:e84263d55307	1531	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	167:e84263d55307	1532	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	167:e84263d55307	1533	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
AnnaBridge	167:e84263d55307	1534	* @param Source This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1535	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	167:e84263d55307	1536	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	167:e84263d55307	1537	* @param PLLM This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1538	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	167:e84263d55307	1539	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	167:e84263d55307	1540	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	167:e84263d55307	1541	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	167:e84263d55307	1542	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	167:e84263d55307	1543	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	167:e84263d55307	1544	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	167:e84263d55307	1545	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	167:e84263d55307	1546	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	167:e84263d55307	1547	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	167:e84263d55307	1548	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	167:e84263d55307	1549	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	167:e84263d55307	1550	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	167:e84263d55307	1551	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	167:e84263d55307	1552	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	167:e84263d55307	1553	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	167:e84263d55307	1554	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	167:e84263d55307	1555	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	167:e84263d55307	1556	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	167:e84263d55307	1557	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	167:e84263d55307	1558	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	167:e84263d55307	1559	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	167:e84263d55307	1560	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	167:e84263d55307	1561	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	167:e84263d55307	1562	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	167:e84263d55307	1563	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	167:e84263d55307	1564	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	167:e84263d55307	1565	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	167:e84263d55307	1566	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	167:e84263d55307	1567	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	167:e84263d55307	1568	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	167:e84263d55307	1569	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	167:e84263d55307	1570	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	167:e84263d55307	1571	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	167:e84263d55307	1572	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	167:e84263d55307	1573	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	167:e84263d55307	1574	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	167:e84263d55307	1575	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	167:e84263d55307	1576	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	167:e84263d55307	1577	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	167:e84263d55307	1578	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	167:e84263d55307	1579	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	167:e84263d55307	1580	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	167:e84263d55307	1581	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	167:e84263d55307	1582	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	167:e84263d55307	1583	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	167:e84263d55307	1584	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	167:e84263d55307	1585	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	167:e84263d55307	1586	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	167:e84263d55307	1587	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	167:e84263d55307	1588	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	167:e84263d55307	1589	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	167:e84263d55307	1590	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	167:e84263d55307	1591	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	167:e84263d55307	1592	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	167:e84263d55307	1593	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	167:e84263d55307	1594	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	167:e84263d55307	1595	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	167:e84263d55307	1596	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	167:e84263d55307	1597	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	167:e84263d55307	1598	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	167:e84263d55307	1599	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	167:e84263d55307	1600	* @param PLLN Between 192 and 432
AnnaBridge	167:e84263d55307	1601	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1602	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	167:e84263d55307	1603	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	167:e84263d55307	1604	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	167:e84263d55307	1605	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	167:e84263d55307	1606	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	167:e84263d55307	1607	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	167:e84263d55307	1608	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	167:e84263d55307	1609	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	167:e84263d55307	1610	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	167:e84263d55307	1611	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	167:e84263d55307	1612	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	167:e84263d55307	1613	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	167:e84263d55307	1614	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	167:e84263d55307	1615	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	167:e84263d55307	1616	* @retval None
AnnaBridge	167:e84263d55307	1617	*/
AnnaBridge	167:e84263d55307	1618	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	167:e84263d55307	1619	{
AnnaBridge	167:e84263d55307	1620	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	167:e84263d55307	1621	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
AnnaBridge	167:e84263d55307	1622	}
AnnaBridge	167:e84263d55307	1623
AnnaBridge	167:e84263d55307	1624	/**
AnnaBridge	167:e84263d55307	1625	* @brief Get Main PLL multiplication factor for VCO
AnnaBridge	167:e84263d55307	1626	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
AnnaBridge	167:e84263d55307	1627	* @retval Between 192 and 432
AnnaBridge	167:e84263d55307	1628	*/
AnnaBridge	167:e84263d55307	1629	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
AnnaBridge	167:e84263d55307	1630	{
AnnaBridge	167:e84263d55307	1631	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
AnnaBridge	167:e84263d55307	1632	}
AnnaBridge	167:e84263d55307	1633
AnnaBridge	167:e84263d55307	1634	/**
AnnaBridge	167:e84263d55307	1635	* @brief Get Main PLL division factor for PLLP
AnnaBridge	167:e84263d55307	1636	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
AnnaBridge	167:e84263d55307	1637	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1638	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	167:e84263d55307	1639	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	167:e84263d55307	1640	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	167:e84263d55307	1641	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	167:e84263d55307	1642	*/
AnnaBridge	167:e84263d55307	1643	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	167:e84263d55307	1644	{
AnnaBridge	167:e84263d55307	1645	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
AnnaBridge	167:e84263d55307	1646	}
AnnaBridge	167:e84263d55307	1647
AnnaBridge	167:e84263d55307	1648	/**
AnnaBridge	167:e84263d55307	1649	* @brief Get Main PLL division factor for PLLQ
AnnaBridge	167:e84263d55307	1650	* @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
AnnaBridge	167:e84263d55307	1651	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
AnnaBridge	167:e84263d55307	1652	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1653	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	167:e84263d55307	1654	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	167:e84263d55307	1655	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	167:e84263d55307	1656	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	167:e84263d55307	1657	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	167:e84263d55307	1658	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	167:e84263d55307	1659	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	167:e84263d55307	1660	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	167:e84263d55307	1661	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	167:e84263d55307	1662	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	167:e84263d55307	1663	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	167:e84263d55307	1664	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	167:e84263d55307	1665	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	167:e84263d55307	1666	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	167:e84263d55307	1667	*/
AnnaBridge	167:e84263d55307	1668	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
AnnaBridge	167:e84263d55307	1669	{
AnnaBridge	167:e84263d55307	1670	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
AnnaBridge	167:e84263d55307	1671	}
AnnaBridge	167:e84263d55307	1672
AnnaBridge	167:e84263d55307	1673	/**
AnnaBridge	167:e84263d55307	1674	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	167:e84263d55307	1675	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	167:e84263d55307	1676	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1677	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	167:e84263d55307	1678	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	167:e84263d55307	1679	*/
AnnaBridge	167:e84263d55307	1680	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	167:e84263d55307	1681	{
AnnaBridge	167:e84263d55307	1682	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	167:e84263d55307	1683	}
AnnaBridge	167:e84263d55307	1684
AnnaBridge	167:e84263d55307	1685	/**
AnnaBridge	167:e84263d55307	1686	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	167:e84263d55307	1687	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
AnnaBridge	167:e84263d55307	1688	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1689	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	167:e84263d55307	1690	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	167:e84263d55307	1691	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	167:e84263d55307	1692	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	167:e84263d55307	1693	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	167:e84263d55307	1694	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	167:e84263d55307	1695	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	167:e84263d55307	1696	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	167:e84263d55307	1697	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	167:e84263d55307	1698	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	167:e84263d55307	1699	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	167:e84263d55307	1700	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	167:e84263d55307	1701	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	167:e84263d55307	1702	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	167:e84263d55307	1703	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	167:e84263d55307	1704	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	167:e84263d55307	1705	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	167:e84263d55307	1706	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	167:e84263d55307	1707	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	167:e84263d55307	1708	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	167:e84263d55307	1709	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	167:e84263d55307	1710	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	167:e84263d55307	1711	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	167:e84263d55307	1712	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	167:e84263d55307	1713	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	167:e84263d55307	1714	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	167:e84263d55307	1715	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	167:e84263d55307	1716	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	167:e84263d55307	1717	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	167:e84263d55307	1718	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	167:e84263d55307	1719	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	167:e84263d55307	1720	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	167:e84263d55307	1721	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	167:e84263d55307	1722	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	167:e84263d55307	1723	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	167:e84263d55307	1724	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	167:e84263d55307	1725	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	167:e84263d55307	1726	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	167:e84263d55307	1727	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	167:e84263d55307	1728	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	167:e84263d55307	1729	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	167:e84263d55307	1730	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	167:e84263d55307	1731	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	167:e84263d55307	1732	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	167:e84263d55307	1733	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	167:e84263d55307	1734	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	167:e84263d55307	1735	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	167:e84263d55307	1736	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	167:e84263d55307	1737	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	167:e84263d55307	1738	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	167:e84263d55307	1739	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	167:e84263d55307	1740	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	167:e84263d55307	1741	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	167:e84263d55307	1742	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	167:e84263d55307	1743	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	167:e84263d55307	1744	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	167:e84263d55307	1745	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	167:e84263d55307	1746	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	167:e84263d55307	1747	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	167:e84263d55307	1748	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	167:e84263d55307	1749	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	167:e84263d55307	1750	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	167:e84263d55307	1751	*/
AnnaBridge	167:e84263d55307	1752	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	167:e84263d55307	1753	{
AnnaBridge	167:e84263d55307	1754	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	167:e84263d55307	1755	}
AnnaBridge	167:e84263d55307	1756
AnnaBridge	167:e84263d55307	1757	/**
AnnaBridge	167:e84263d55307	1758	* @brief Configure Spread Spectrum used for PLL
AnnaBridge	167:e84263d55307	1759	* @note These bits must be written before enabling PLL
AnnaBridge	167:e84263d55307	1760	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	167:e84263d55307	1761	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	167:e84263d55307	1762	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
AnnaBridge	167:e84263d55307	1763	* @param Mod Between Min_Data=0 and Max_Data=8191
AnnaBridge	167:e84263d55307	1764	* @param Inc Between Min_Data=0 and Max_Data=32767
AnnaBridge	167:e84263d55307	1765	* @param Sel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1766	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	167:e84263d55307	1767	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	167:e84263d55307	1768	* @retval None
AnnaBridge	167:e84263d55307	1769	*/
AnnaBridge	167:e84263d55307	1770	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
AnnaBridge	167:e84263d55307	1771	{
AnnaBridge	167:e84263d55307	1772	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
AnnaBridge	167:e84263d55307	1773	}
AnnaBridge	167:e84263d55307	1774
AnnaBridge	167:e84263d55307	1775	/**
AnnaBridge	167:e84263d55307	1776	* @brief Get Spread Spectrum Modulation Period for PLL
AnnaBridge	167:e84263d55307	1777	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
AnnaBridge	167:e84263d55307	1778	* @retval Between Min_Data=0 and Max_Data=8191
AnnaBridge	167:e84263d55307	1779	*/
AnnaBridge	167:e84263d55307	1780	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
AnnaBridge	167:e84263d55307	1781	{
AnnaBridge	167:e84263d55307	1782	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
AnnaBridge	167:e84263d55307	1783	}
AnnaBridge	167:e84263d55307	1784
AnnaBridge	167:e84263d55307	1785	/**
AnnaBridge	167:e84263d55307	1786	* @brief Get Spread Spectrum Incrementation Step for PLL
AnnaBridge	167:e84263d55307	1787	* @note Must be written before enabling PLL
AnnaBridge	167:e84263d55307	1788	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
AnnaBridge	167:e84263d55307	1789	* @retval Between Min_Data=0 and Max_Data=32767
AnnaBridge	167:e84263d55307	1790	*/
AnnaBridge	167:e84263d55307	1791	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
AnnaBridge	167:e84263d55307	1792	{
AnnaBridge	167:e84263d55307	1793	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
AnnaBridge	167:e84263d55307	1794	}
AnnaBridge	167:e84263d55307	1795
AnnaBridge	167:e84263d55307	1796	/**
AnnaBridge	167:e84263d55307	1797	* @brief Get Spread Spectrum Selection for PLL
AnnaBridge	167:e84263d55307	1798	* @note Must be written before enabling PLL
AnnaBridge	167:e84263d55307	1799	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
AnnaBridge	167:e84263d55307	1800	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1801	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	167:e84263d55307	1802	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	167:e84263d55307	1803	*/
AnnaBridge	167:e84263d55307	1804	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
AnnaBridge	167:e84263d55307	1805	{
AnnaBridge	167:e84263d55307	1806	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
AnnaBridge	167:e84263d55307	1807	}
AnnaBridge	167:e84263d55307	1808
AnnaBridge	167:e84263d55307	1809	/**
AnnaBridge	167:e84263d55307	1810	* @brief Enable Spread Spectrum for PLL.
AnnaBridge	167:e84263d55307	1811	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
AnnaBridge	167:e84263d55307	1812	* @retval None
AnnaBridge	167:e84263d55307	1813	*/
AnnaBridge	167:e84263d55307	1814	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
AnnaBridge	167:e84263d55307	1815	{
AnnaBridge	167:e84263d55307	1816	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	167:e84263d55307	1817	}
AnnaBridge	167:e84263d55307	1818
AnnaBridge	167:e84263d55307	1819	/**
AnnaBridge	167:e84263d55307	1820	* @brief Disable Spread Spectrum for PLL.
AnnaBridge	167:e84263d55307	1821	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
AnnaBridge	167:e84263d55307	1822	* @retval None
AnnaBridge	167:e84263d55307	1823	*/
AnnaBridge	167:e84263d55307	1824	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
AnnaBridge	167:e84263d55307	1825	{
AnnaBridge	167:e84263d55307	1826	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	167:e84263d55307	1827	}
AnnaBridge	167:e84263d55307	1828
AnnaBridge	167:e84263d55307	1829	/**
AnnaBridge	167:e84263d55307	1830	* @}
AnnaBridge	167:e84263d55307	1831	*/
AnnaBridge	167:e84263d55307	1832
AnnaBridge	167:e84263d55307	1833	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
AnnaBridge	167:e84263d55307	1834	* @{
AnnaBridge	167:e84263d55307	1835	*/
AnnaBridge	167:e84263d55307	1836
AnnaBridge	167:e84263d55307	1837	/**
AnnaBridge	167:e84263d55307	1838	* @brief Enable PLLI2S
AnnaBridge	167:e84263d55307	1839	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
AnnaBridge	167:e84263d55307	1840	* @retval None
AnnaBridge	167:e84263d55307	1841	*/
AnnaBridge	167:e84263d55307	1842	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
AnnaBridge	167:e84263d55307	1843	{
AnnaBridge	167:e84263d55307	1844	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	167:e84263d55307	1845	}
AnnaBridge	167:e84263d55307	1846
AnnaBridge	167:e84263d55307	1847	/**
AnnaBridge	167:e84263d55307	1848	* @brief Disable PLLI2S
AnnaBridge	167:e84263d55307	1849	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
AnnaBridge	167:e84263d55307	1850	* @retval None
AnnaBridge	167:e84263d55307	1851	*/
AnnaBridge	167:e84263d55307	1852	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
AnnaBridge	167:e84263d55307	1853	{
AnnaBridge	167:e84263d55307	1854	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	167:e84263d55307	1855	}
AnnaBridge	167:e84263d55307	1856
AnnaBridge	167:e84263d55307	1857	/**
AnnaBridge	167:e84263d55307	1858	* @brief Check if PLLI2S Ready
AnnaBridge	167:e84263d55307	1859	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
AnnaBridge	167:e84263d55307	1860	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1861	*/
AnnaBridge	167:e84263d55307	1862	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
AnnaBridge	167:e84263d55307	1863	{
AnnaBridge	167:e84263d55307	1864	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
AnnaBridge	167:e84263d55307	1865	}
AnnaBridge	167:e84263d55307	1866
AnnaBridge	167:e84263d55307	1867	/**
AnnaBridge	167:e84263d55307	1868	* @brief Configure PLLI2S used for I2S1 domain clock
AnnaBridge	167:e84263d55307	1869	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	167:e84263d55307	1870	* PLLI2S are disabled
AnnaBridge	167:e84263d55307	1871	* @note PLLN/PLLR can be written only when PLLI2S is disabled
AnnaBridge	167:e84263d55307	1872	* @note This can be selected for I2S
AnnaBridge	167:e84263d55307	1873	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	167:e84263d55307	1874	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	167:e84263d55307	1875	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	167:e84263d55307	1876	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
AnnaBridge	167:e84263d55307	1877	* @param Source This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1878	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	167:e84263d55307	1879	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	167:e84263d55307	1880	* @param PLLM This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1881	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	167:e84263d55307	1882	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	167:e84263d55307	1883	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	167:e84263d55307	1884	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	167:e84263d55307	1885	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	167:e84263d55307	1886	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	167:e84263d55307	1887	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	167:e84263d55307	1888	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	167:e84263d55307	1889	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	167:e84263d55307	1890	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	167:e84263d55307	1891	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	167:e84263d55307	1892	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	167:e84263d55307	1893	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	167:e84263d55307	1894	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	167:e84263d55307	1895	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	167:e84263d55307	1896	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	167:e84263d55307	1897	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	167:e84263d55307	1898	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	167:e84263d55307	1899	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	167:e84263d55307	1900	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	167:e84263d55307	1901	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	167:e84263d55307	1902	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	167:e84263d55307	1903	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	167:e84263d55307	1904	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	167:e84263d55307	1905	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	167:e84263d55307	1906	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	167:e84263d55307	1907	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	167:e84263d55307	1908	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	167:e84263d55307	1909	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	167:e84263d55307	1910	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	167:e84263d55307	1911	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	167:e84263d55307	1912	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	167:e84263d55307	1913	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	167:e84263d55307	1914	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	167:e84263d55307	1915	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	167:e84263d55307	1916	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	167:e84263d55307	1917	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	167:e84263d55307	1918	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	167:e84263d55307	1919	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	167:e84263d55307	1920	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	167:e84263d55307	1921	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	167:e84263d55307	1922	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	167:e84263d55307	1923	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	167:e84263d55307	1924	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	167:e84263d55307	1925	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	167:e84263d55307	1926	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	167:e84263d55307	1927	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	167:e84263d55307	1928	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	167:e84263d55307	1929	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	167:e84263d55307	1930	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	167:e84263d55307	1931	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	167:e84263d55307	1932	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	167:e84263d55307	1933	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	167:e84263d55307	1934	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	167:e84263d55307	1935	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	167:e84263d55307	1936	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	167:e84263d55307	1937	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	167:e84263d55307	1938	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	167:e84263d55307	1939	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	167:e84263d55307	1940	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	167:e84263d55307	1941	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	167:e84263d55307	1942	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	167:e84263d55307	1943	* @param PLLN Between 192 and 432
AnnaBridge	167:e84263d55307	1944	* @param PLLR This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1945	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	167:e84263d55307	1946	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	167:e84263d55307	1947	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	167:e84263d55307	1948	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	167:e84263d55307	1949	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	167:e84263d55307	1950	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	167:e84263d55307	1951	* @retval None
AnnaBridge	167:e84263d55307	1952	*/
AnnaBridge	167:e84263d55307	1953	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	167:e84263d55307	1954	{
AnnaBridge	167:e84263d55307	1955	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	167:e84263d55307	1956	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
AnnaBridge	167:e84263d55307	1957	}
AnnaBridge	167:e84263d55307	1958
AnnaBridge	167:e84263d55307	1959	/**
AnnaBridge	167:e84263d55307	1960	* @brief Get I2SPLL multiplication factor for VCO
AnnaBridge	167:e84263d55307	1961	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
AnnaBridge	167:e84263d55307	1962	* @retval Between 192 and 432
AnnaBridge	167:e84263d55307	1963	*/
AnnaBridge	167:e84263d55307	1964	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
AnnaBridge	167:e84263d55307	1965	{
AnnaBridge	167:e84263d55307	1966	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
AnnaBridge	167:e84263d55307	1967	}
AnnaBridge	167:e84263d55307	1968
AnnaBridge	167:e84263d55307	1969	/**
AnnaBridge	167:e84263d55307	1970	* @brief Get I2SPLL division factor for PLLI2SR
AnnaBridge	167:e84263d55307	1971	* @note used for PLLI2SCLK (I2S clock)
AnnaBridge	167:e84263d55307	1972	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
AnnaBridge	167:e84263d55307	1973	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1974	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	167:e84263d55307	1975	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	167:e84263d55307	1976	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	167:e84263d55307	1977	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	167:e84263d55307	1978	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	167:e84263d55307	1979	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	167:e84263d55307	1980	*/
AnnaBridge	167:e84263d55307	1981	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
AnnaBridge	167:e84263d55307	1982	{
AnnaBridge	167:e84263d55307	1983	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
AnnaBridge	167:e84263d55307	1984	}
AnnaBridge	167:e84263d55307	1985
AnnaBridge	167:e84263d55307	1986	/**
AnnaBridge	167:e84263d55307	1987	* @}
AnnaBridge	167:e84263d55307	1988	*/
AnnaBridge	167:e84263d55307	1989
AnnaBridge	167:e84263d55307	1990	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	167:e84263d55307	1991	* @{
AnnaBridge	167:e84263d55307	1992	*/
AnnaBridge	167:e84263d55307	1993
AnnaBridge	167:e84263d55307	1994	/**
AnnaBridge	167:e84263d55307	1995	* @brief Clear LSI ready interrupt flag
AnnaBridge	167:e84263d55307	1996	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	167:e84263d55307	1997	* @retval None
AnnaBridge	167:e84263d55307	1998	*/
AnnaBridge	167:e84263d55307	1999	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	167:e84263d55307	2000	{
AnnaBridge	167:e84263d55307	2001	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
AnnaBridge	167:e84263d55307	2002	}
AnnaBridge	167:e84263d55307	2003
AnnaBridge	167:e84263d55307	2004	/**
AnnaBridge	167:e84263d55307	2005	* @brief Clear LSE ready interrupt flag
AnnaBridge	167:e84263d55307	2006	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	167:e84263d55307	2007	* @retval None
AnnaBridge	167:e84263d55307	2008	*/
AnnaBridge	167:e84263d55307	2009	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	167:e84263d55307	2010	{
AnnaBridge	167:e84263d55307	2011	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
AnnaBridge	167:e84263d55307	2012	}
AnnaBridge	167:e84263d55307	2013
AnnaBridge	167:e84263d55307	2014	/**
AnnaBridge	167:e84263d55307	2015	* @brief Clear HSI ready interrupt flag
AnnaBridge	167:e84263d55307	2016	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	167:e84263d55307	2017	* @retval None
AnnaBridge	167:e84263d55307	2018	*/
AnnaBridge	167:e84263d55307	2019	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	167:e84263d55307	2020	{
AnnaBridge	167:e84263d55307	2021	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
AnnaBridge	167:e84263d55307	2022	}
AnnaBridge	167:e84263d55307	2023
AnnaBridge	167:e84263d55307	2024	/**
AnnaBridge	167:e84263d55307	2025	* @brief Clear HSE ready interrupt flag
AnnaBridge	167:e84263d55307	2026	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	167:e84263d55307	2027	* @retval None
AnnaBridge	167:e84263d55307	2028	*/
AnnaBridge	167:e84263d55307	2029	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	167:e84263d55307	2030	{
AnnaBridge	167:e84263d55307	2031	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
AnnaBridge	167:e84263d55307	2032	}
AnnaBridge	167:e84263d55307	2033
AnnaBridge	167:e84263d55307	2034	/**
AnnaBridge	167:e84263d55307	2035	* @brief Clear PLL ready interrupt flag
AnnaBridge	167:e84263d55307	2036	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	167:e84263d55307	2037	* @retval None
AnnaBridge	167:e84263d55307	2038	*/
AnnaBridge	167:e84263d55307	2039	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	167:e84263d55307	2040	{
AnnaBridge	167:e84263d55307	2041	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
AnnaBridge	167:e84263d55307	2042	}
AnnaBridge	167:e84263d55307	2043
AnnaBridge	167:e84263d55307	2044	/**
AnnaBridge	167:e84263d55307	2045	* @brief Clear PLLI2S ready interrupt flag
AnnaBridge	167:e84263d55307	2046	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
AnnaBridge	167:e84263d55307	2047	* @retval None
AnnaBridge	167:e84263d55307	2048	*/
AnnaBridge	167:e84263d55307	2049	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
AnnaBridge	167:e84263d55307	2050	{
AnnaBridge	167:e84263d55307	2051	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
AnnaBridge	167:e84263d55307	2052	}
AnnaBridge	167:e84263d55307	2053
AnnaBridge	167:e84263d55307	2054	/**
AnnaBridge	167:e84263d55307	2055	* @brief Clear Clock security system interrupt flag
AnnaBridge	167:e84263d55307	2056	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	167:e84263d55307	2057	* @retval None
AnnaBridge	167:e84263d55307	2058	*/
AnnaBridge	167:e84263d55307	2059	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	167:e84263d55307	2060	{
AnnaBridge	167:e84263d55307	2061	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
AnnaBridge	167:e84263d55307	2062	}
AnnaBridge	167:e84263d55307	2063
AnnaBridge	167:e84263d55307	2064	/**
AnnaBridge	167:e84263d55307	2065	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	167:e84263d55307	2066	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	167:e84263d55307	2067	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2068	*/
AnnaBridge	167:e84263d55307	2069	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	167:e84263d55307	2070	{
AnnaBridge	167:e84263d55307	2071	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
AnnaBridge	167:e84263d55307	2072	}
AnnaBridge	167:e84263d55307	2073
AnnaBridge	167:e84263d55307	2074	/**
AnnaBridge	167:e84263d55307	2075	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	167:e84263d55307	2076	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	167:e84263d55307	2077	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2078	*/
AnnaBridge	167:e84263d55307	2079	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	167:e84263d55307	2080	{
AnnaBridge	167:e84263d55307	2081	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
AnnaBridge	167:e84263d55307	2082	}
AnnaBridge	167:e84263d55307	2083
AnnaBridge	167:e84263d55307	2084	/**
AnnaBridge	167:e84263d55307	2085	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	167:e84263d55307	2086	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	167:e84263d55307	2087	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2088	*/
AnnaBridge	167:e84263d55307	2089	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	167:e84263d55307	2090	{
AnnaBridge	167:e84263d55307	2091	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
AnnaBridge	167:e84263d55307	2092	}
AnnaBridge	167:e84263d55307	2093
AnnaBridge	167:e84263d55307	2094	/**
AnnaBridge	167:e84263d55307	2095	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	167:e84263d55307	2096	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	167:e84263d55307	2097	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2098	*/
AnnaBridge	167:e84263d55307	2099	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	167:e84263d55307	2100	{
AnnaBridge	167:e84263d55307	2101	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
AnnaBridge	167:e84263d55307	2102	}
AnnaBridge	167:e84263d55307	2103
AnnaBridge	167:e84263d55307	2104	/**
AnnaBridge	167:e84263d55307	2105	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	167:e84263d55307	2106	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	167:e84263d55307	2107	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2108	*/
AnnaBridge	167:e84263d55307	2109	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	167:e84263d55307	2110	{
AnnaBridge	167:e84263d55307	2111	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
AnnaBridge	167:e84263d55307	2112	}
AnnaBridge	167:e84263d55307	2113
AnnaBridge	167:e84263d55307	2114	/**
AnnaBridge	167:e84263d55307	2115	* @brief Check if PLLI2S ready interrupt occurred or not
AnnaBridge	167:e84263d55307	2116	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
AnnaBridge	167:e84263d55307	2117	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2118	*/
AnnaBridge	167:e84263d55307	2119	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
AnnaBridge	167:e84263d55307	2120	{
AnnaBridge	167:e84263d55307	2121	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
AnnaBridge	167:e84263d55307	2122	}
AnnaBridge	167:e84263d55307	2123
AnnaBridge	167:e84263d55307	2124	/**
AnnaBridge	167:e84263d55307	2125	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	167:e84263d55307	2126	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	167:e84263d55307	2127	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2128	*/
AnnaBridge	167:e84263d55307	2129	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	167:e84263d55307	2130	{
AnnaBridge	167:e84263d55307	2131	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
AnnaBridge	167:e84263d55307	2132	}
AnnaBridge	167:e84263d55307	2133
AnnaBridge	167:e84263d55307	2134	/**
AnnaBridge	167:e84263d55307	2135	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	167:e84263d55307	2136	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	167:e84263d55307	2137	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2138	*/
AnnaBridge	167:e84263d55307	2139	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	167:e84263d55307	2140	{
AnnaBridge	167:e84263d55307	2141	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	167:e84263d55307	2142	}
AnnaBridge	167:e84263d55307	2143
AnnaBridge	167:e84263d55307	2144	/**
AnnaBridge	167:e84263d55307	2145	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	167:e84263d55307	2146	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	167:e84263d55307	2147	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2148	*/
AnnaBridge	167:e84263d55307	2149	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	167:e84263d55307	2150	{
AnnaBridge	167:e84263d55307	2151	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	167:e84263d55307	2152	}
AnnaBridge	167:e84263d55307	2153
AnnaBridge	167:e84263d55307	2154	/**
AnnaBridge	167:e84263d55307	2155	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	167:e84263d55307	2156	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	167:e84263d55307	2157	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2158	*/
AnnaBridge	167:e84263d55307	2159	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	167:e84263d55307	2160	{
AnnaBridge	167:e84263d55307	2161	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	167:e84263d55307	2162	}
AnnaBridge	167:e84263d55307	2163
AnnaBridge	167:e84263d55307	2164	/**
AnnaBridge	167:e84263d55307	2165	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	167:e84263d55307	2166	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	167:e84263d55307	2167	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2168	*/
AnnaBridge	167:e84263d55307	2169	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	167:e84263d55307	2170	{
AnnaBridge	167:e84263d55307	2171	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
AnnaBridge	167:e84263d55307	2172	}
AnnaBridge	167:e84263d55307	2173
AnnaBridge	167:e84263d55307	2174	/**
AnnaBridge	167:e84263d55307	2175	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	167:e84263d55307	2176	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	167:e84263d55307	2177	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2178	*/
AnnaBridge	167:e84263d55307	2179	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	167:e84263d55307	2180	{
AnnaBridge	167:e84263d55307	2181	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	167:e84263d55307	2182	}
AnnaBridge	167:e84263d55307	2183
AnnaBridge	167:e84263d55307	2184	/**
AnnaBridge	167:e84263d55307	2185	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	167:e84263d55307	2186	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	167:e84263d55307	2187	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2188	*/
AnnaBridge	167:e84263d55307	2189	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	167:e84263d55307	2190	{
AnnaBridge	167:e84263d55307	2191	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	167:e84263d55307	2192	}
AnnaBridge	167:e84263d55307	2193
AnnaBridge	167:e84263d55307	2194	/**
AnnaBridge	167:e84263d55307	2195	* @brief Check if RCC flag BOR reset is set or not.
AnnaBridge	167:e84263d55307	2196	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
AnnaBridge	167:e84263d55307	2197	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2198	*/
AnnaBridge	167:e84263d55307	2199	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
AnnaBridge	167:e84263d55307	2200	{
AnnaBridge	167:e84263d55307	2201	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
AnnaBridge	167:e84263d55307	2202	}
AnnaBridge	167:e84263d55307	2203
AnnaBridge	167:e84263d55307	2204	/**
AnnaBridge	167:e84263d55307	2205	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	167:e84263d55307	2206	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	167:e84263d55307	2207	* @retval None
AnnaBridge	167:e84263d55307	2208	*/
AnnaBridge	167:e84263d55307	2209	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	167:e84263d55307	2210	{
AnnaBridge	167:e84263d55307	2211	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	167:e84263d55307	2212	}
AnnaBridge	167:e84263d55307	2213
AnnaBridge	167:e84263d55307	2214	/**
AnnaBridge	167:e84263d55307	2215	* @}
AnnaBridge	167:e84263d55307	2216	*/
AnnaBridge	167:e84263d55307	2217
AnnaBridge	167:e84263d55307	2218	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	167:e84263d55307	2219	* @{
AnnaBridge	167:e84263d55307	2220	*/
AnnaBridge	167:e84263d55307	2221
AnnaBridge	167:e84263d55307	2222	/**
AnnaBridge	167:e84263d55307	2223	* @brief Enable LSI ready interrupt
AnnaBridge	167:e84263d55307	2224	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	167:e84263d55307	2225	* @retval None
AnnaBridge	167:e84263d55307	2226	*/
AnnaBridge	167:e84263d55307	2227	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	167:e84263d55307	2228	{
AnnaBridge	167:e84263d55307	2229	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	167:e84263d55307	2230	}
AnnaBridge	167:e84263d55307	2231
AnnaBridge	167:e84263d55307	2232	/**
AnnaBridge	167:e84263d55307	2233	* @brief Enable LSE ready interrupt
AnnaBridge	167:e84263d55307	2234	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	167:e84263d55307	2235	* @retval None
AnnaBridge	167:e84263d55307	2236	*/
AnnaBridge	167:e84263d55307	2237	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	167:e84263d55307	2238	{
AnnaBridge	167:e84263d55307	2239	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	167:e84263d55307	2240	}
AnnaBridge	167:e84263d55307	2241
AnnaBridge	167:e84263d55307	2242	/**
AnnaBridge	167:e84263d55307	2243	* @brief Enable HSI ready interrupt
AnnaBridge	167:e84263d55307	2244	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	167:e84263d55307	2245	* @retval None
AnnaBridge	167:e84263d55307	2246	*/
AnnaBridge	167:e84263d55307	2247	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	167:e84263d55307	2248	{
AnnaBridge	167:e84263d55307	2249	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	167:e84263d55307	2250	}
AnnaBridge	167:e84263d55307	2251
AnnaBridge	167:e84263d55307	2252	/**
AnnaBridge	167:e84263d55307	2253	* @brief Enable HSE ready interrupt
AnnaBridge	167:e84263d55307	2254	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	167:e84263d55307	2255	* @retval None
AnnaBridge	167:e84263d55307	2256	*/
AnnaBridge	167:e84263d55307	2257	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	167:e84263d55307	2258	{
AnnaBridge	167:e84263d55307	2259	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	167:e84263d55307	2260	}
AnnaBridge	167:e84263d55307	2261
AnnaBridge	167:e84263d55307	2262	/**
AnnaBridge	167:e84263d55307	2263	* @brief Enable PLL ready interrupt
AnnaBridge	167:e84263d55307	2264	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	167:e84263d55307	2265	* @retval None
AnnaBridge	167:e84263d55307	2266	*/
AnnaBridge	167:e84263d55307	2267	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	167:e84263d55307	2268	{
AnnaBridge	167:e84263d55307	2269	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	167:e84263d55307	2270	}
AnnaBridge	167:e84263d55307	2271
AnnaBridge	167:e84263d55307	2272	/**
AnnaBridge	167:e84263d55307	2273	* @brief Enable PLLI2S ready interrupt
AnnaBridge	167:e84263d55307	2274	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
AnnaBridge	167:e84263d55307	2275	* @retval None
AnnaBridge	167:e84263d55307	2276	*/
AnnaBridge	167:e84263d55307	2277	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
AnnaBridge	167:e84263d55307	2278	{
AnnaBridge	167:e84263d55307	2279	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	167:e84263d55307	2280	}
AnnaBridge	167:e84263d55307	2281
AnnaBridge	167:e84263d55307	2282	/**
AnnaBridge	167:e84263d55307	2283	* @brief Disable LSI ready interrupt
AnnaBridge	167:e84263d55307	2284	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	167:e84263d55307	2285	* @retval None
AnnaBridge	167:e84263d55307	2286	*/
AnnaBridge	167:e84263d55307	2287	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	167:e84263d55307	2288	{
AnnaBridge	167:e84263d55307	2289	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	167:e84263d55307	2290	}
AnnaBridge	167:e84263d55307	2291
AnnaBridge	167:e84263d55307	2292	/**
AnnaBridge	167:e84263d55307	2293	* @brief Disable LSE ready interrupt
AnnaBridge	167:e84263d55307	2294	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	167:e84263d55307	2295	* @retval None
AnnaBridge	167:e84263d55307	2296	*/
AnnaBridge	167:e84263d55307	2297	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	167:e84263d55307	2298	{
AnnaBridge	167:e84263d55307	2299	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	167:e84263d55307	2300	}
AnnaBridge	167:e84263d55307	2301
AnnaBridge	167:e84263d55307	2302	/**
AnnaBridge	167:e84263d55307	2303	* @brief Disable HSI ready interrupt
AnnaBridge	167:e84263d55307	2304	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	167:e84263d55307	2305	* @retval None
AnnaBridge	167:e84263d55307	2306	*/
AnnaBridge	167:e84263d55307	2307	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	167:e84263d55307	2308	{
AnnaBridge	167:e84263d55307	2309	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	167:e84263d55307	2310	}
AnnaBridge	167:e84263d55307	2311
AnnaBridge	167:e84263d55307	2312	/**
AnnaBridge	167:e84263d55307	2313	* @brief Disable HSE ready interrupt
AnnaBridge	167:e84263d55307	2314	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	167:e84263d55307	2315	* @retval None
AnnaBridge	167:e84263d55307	2316	*/
AnnaBridge	167:e84263d55307	2317	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	167:e84263d55307	2318	{
AnnaBridge	167:e84263d55307	2319	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	167:e84263d55307	2320	}
AnnaBridge	167:e84263d55307	2321
AnnaBridge	167:e84263d55307	2322	/**
AnnaBridge	167:e84263d55307	2323	* @brief Disable PLL ready interrupt
AnnaBridge	167:e84263d55307	2324	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	167:e84263d55307	2325	* @retval None
AnnaBridge	167:e84263d55307	2326	*/
AnnaBridge	167:e84263d55307	2327	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	167:e84263d55307	2328	{
AnnaBridge	167:e84263d55307	2329	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	167:e84263d55307	2330	}
AnnaBridge	167:e84263d55307	2331
AnnaBridge	167:e84263d55307	2332	/**
AnnaBridge	167:e84263d55307	2333	* @brief Disable PLLI2S ready interrupt
AnnaBridge	167:e84263d55307	2334	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
AnnaBridge	167:e84263d55307	2335	* @retval None
AnnaBridge	167:e84263d55307	2336	*/
AnnaBridge	167:e84263d55307	2337	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
AnnaBridge	167:e84263d55307	2338	{
AnnaBridge	167:e84263d55307	2339	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	167:e84263d55307	2340	}
AnnaBridge	167:e84263d55307	2341
AnnaBridge	167:e84263d55307	2342	/**
AnnaBridge	167:e84263d55307	2343	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	167:e84263d55307	2344	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	167:e84263d55307	2345	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2346	*/
AnnaBridge	167:e84263d55307	2347	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	167:e84263d55307	2348	{
AnnaBridge	167:e84263d55307	2349	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
AnnaBridge	167:e84263d55307	2350	}
AnnaBridge	167:e84263d55307	2351
AnnaBridge	167:e84263d55307	2352	/**
AnnaBridge	167:e84263d55307	2353	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	167:e84263d55307	2354	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	167:e84263d55307	2355	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2356	*/
AnnaBridge	167:e84263d55307	2357	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	167:e84263d55307	2358	{
AnnaBridge	167:e84263d55307	2359	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
AnnaBridge	167:e84263d55307	2360	}
AnnaBridge	167:e84263d55307	2361
AnnaBridge	167:e84263d55307	2362	/**
AnnaBridge	167:e84263d55307	2363	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	167:e84263d55307	2364	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	167:e84263d55307	2365	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2366	*/
AnnaBridge	167:e84263d55307	2367	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	167:e84263d55307	2368	{
AnnaBridge	167:e84263d55307	2369	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
AnnaBridge	167:e84263d55307	2370	}
AnnaBridge	167:e84263d55307	2371
AnnaBridge	167:e84263d55307	2372	/**
AnnaBridge	167:e84263d55307	2373	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	167:e84263d55307	2374	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	167:e84263d55307	2375	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2376	*/
AnnaBridge	167:e84263d55307	2377	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	167:e84263d55307	2378	{
AnnaBridge	167:e84263d55307	2379	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
AnnaBridge	167:e84263d55307	2380	}
AnnaBridge	167:e84263d55307	2381
AnnaBridge	167:e84263d55307	2382	/**
AnnaBridge	167:e84263d55307	2383	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	167:e84263d55307	2384	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	167:e84263d55307	2385	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2386	*/
AnnaBridge	167:e84263d55307	2387	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	167:e84263d55307	2388	{
AnnaBridge	167:e84263d55307	2389	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
AnnaBridge	167:e84263d55307	2390	}
AnnaBridge	167:e84263d55307	2391
AnnaBridge	167:e84263d55307	2392	/**
AnnaBridge	167:e84263d55307	2393	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
AnnaBridge	167:e84263d55307	2394	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
AnnaBridge	167:e84263d55307	2395	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2396	*/
AnnaBridge	167:e84263d55307	2397	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
AnnaBridge	167:e84263d55307	2398	{
AnnaBridge	167:e84263d55307	2399	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
AnnaBridge	167:e84263d55307	2400	}
AnnaBridge	167:e84263d55307	2401
AnnaBridge	167:e84263d55307	2402	/**
AnnaBridge	167:e84263d55307	2403	* @}
AnnaBridge	167:e84263d55307	2404	*/
AnnaBridge	167:e84263d55307	2405
AnnaBridge	167:e84263d55307	2406	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	2407	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	167:e84263d55307	2408	* @{
AnnaBridge	167:e84263d55307	2409	*/
AnnaBridge	167:e84263d55307	2410	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	167:e84263d55307	2411	/**
AnnaBridge	167:e84263d55307	2412	* @}
AnnaBridge	167:e84263d55307	2413	*/
AnnaBridge	167:e84263d55307	2414
AnnaBridge	167:e84263d55307	2415	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	167:e84263d55307	2416	* @{
AnnaBridge	167:e84263d55307	2417	*/
AnnaBridge	167:e84263d55307	2418	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	167:e84263d55307	2419	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
AnnaBridge	167:e84263d55307	2420	/**
AnnaBridge	167:e84263d55307	2421	* @}
AnnaBridge	167:e84263d55307	2422	*/
AnnaBridge	167:e84263d55307	2423	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	2424
AnnaBridge	167:e84263d55307	2425	/**
AnnaBridge	167:e84263d55307	2426	* @}
AnnaBridge	167:e84263d55307	2427	*/
AnnaBridge	167:e84263d55307	2428
AnnaBridge	167:e84263d55307	2429	/**
AnnaBridge	167:e84263d55307	2430	* @}
AnnaBridge	167:e84263d55307	2431	*/
AnnaBridge	167:e84263d55307	2432
AnnaBridge	167:e84263d55307	2433	#endif /* defined(RCC) */
AnnaBridge	167:e84263d55307	2434
AnnaBridge	167:e84263d55307	2435	/**
AnnaBridge	167:e84263d55307	2436	* @}
AnnaBridge	167:e84263d55307	2437	*/
AnnaBridge	167:e84263d55307	2438
AnnaBridge	167:e84263d55307	2439	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	2440	}
AnnaBridge	167:e84263d55307	2441	#endif
AnnaBridge	167:e84263d55307	2442
AnnaBridge	167:e84263d55307	2443	#endif /* __STM32F2xx_LL_RCC_H */
AnnaBridge	167:e84263d55307	2444
AnnaBridge	167:e84263d55307	2445	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/