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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/**
AnnaBridge	167:e84263d55307	2	******************************************************************************
AnnaBridge	167:e84263d55307	3	* @file stm32f2xx_ll_dma.h
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
AnnaBridge	167:e84263d55307	7	* @brief Header file of DMA LL module.
AnnaBridge	167:e84263d55307	8	******************************************************************************
AnnaBridge	167:e84263d55307	9	* @attention
AnnaBridge	167:e84263d55307	10	*
AnnaBridge	167:e84263d55307	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	167:e84263d55307	12	*
AnnaBridge	167:e84263d55307	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	167:e84263d55307	14	* are permitted provided that the following conditions are met:
AnnaBridge	167:e84263d55307	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	167:e84263d55307	16	* this list of conditions and the following disclaimer.
AnnaBridge	167:e84263d55307	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	167:e84263d55307	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	167:e84263d55307	19	* and/or other materials provided with the distribution.
AnnaBridge	167:e84263d55307	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	167:e84263d55307	21	* may be used to endorse or promote products derived from this software
AnnaBridge	167:e84263d55307	22	* without specific prior written permission.
AnnaBridge	167:e84263d55307	23	*
AnnaBridge	167:e84263d55307	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	167:e84263d55307	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	167:e84263d55307	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	167:e84263d55307	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	167:e84263d55307	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	167:e84263d55307	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	167:e84263d55307	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	167:e84263d55307	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	167:e84263d55307	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	167:e84263d55307	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	167:e84263d55307	34	*
AnnaBridge	167:e84263d55307	35	******************************************************************************
AnnaBridge	167:e84263d55307	36	*/
AnnaBridge	167:e84263d55307	37
AnnaBridge	167:e84263d55307	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	167:e84263d55307	39	#ifndef __STM32F2xx_LL_DMA_H
AnnaBridge	167:e84263d55307	40	#define __STM32F2xx_LL_DMA_H
AnnaBridge	167:e84263d55307	41
AnnaBridge	167:e84263d55307	42	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	43	extern "C" {
AnnaBridge	167:e84263d55307	44	#endif
AnnaBridge	167:e84263d55307	45
AnnaBridge	167:e84263d55307	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	47	#include "stm32f2xx.h"
AnnaBridge	167:e84263d55307	48
AnnaBridge	167:e84263d55307	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	167:e84263d55307	50	* @{
AnnaBridge	167:e84263d55307	51	*/
AnnaBridge	167:e84263d55307	52
AnnaBridge	167:e84263d55307	53	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/** @defgroup DMA_LL DMA
AnnaBridge	167:e84263d55307	56	* @{
AnnaBridge	167:e84263d55307	57	*/
AnnaBridge	167:e84263d55307	58
AnnaBridge	167:e84263d55307	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	167:e84263d55307	62	* @{
AnnaBridge	167:e84263d55307	63	*/
AnnaBridge	167:e84263d55307	64	/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
AnnaBridge	167:e84263d55307	65	static const uint8_t STREAM_OFFSET_TAB[] =
AnnaBridge	167:e84263d55307	66	{
AnnaBridge	167:e84263d55307	67	(uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	68	(uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	69	(uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	70	(uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	71	(uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	72	(uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	73	(uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	74	(uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
AnnaBridge	167:e84263d55307	75	};
AnnaBridge	167:e84263d55307	76
AnnaBridge	167:e84263d55307	77	/**
AnnaBridge	167:e84263d55307	78	* @}
AnnaBridge	167:e84263d55307	79	*/
AnnaBridge	167:e84263d55307	80
AnnaBridge	167:e84263d55307	81	/* Private constants ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	82	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	167:e84263d55307	83	* @{
AnnaBridge	167:e84263d55307	84	*/
AnnaBridge	167:e84263d55307	85	/**
AnnaBridge	167:e84263d55307	86	* @}
AnnaBridge	167:e84263d55307	87	*/
AnnaBridge	167:e84263d55307	88
AnnaBridge	167:e84263d55307	89
AnnaBridge	167:e84263d55307	90	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	91	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	92	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	93	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	167:e84263d55307	94	* @{
AnnaBridge	167:e84263d55307	95	*/
AnnaBridge	167:e84263d55307	96	typedef struct
AnnaBridge	167:e84263d55307	97	{
AnnaBridge	167:e84263d55307	98	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	167:e84263d55307	99	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	100
AnnaBridge	167:e84263d55307	101	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	167:e84263d55307	102
AnnaBridge	167:e84263d55307	103	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	167:e84263d55307	104	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	105
AnnaBridge	167:e84263d55307	106	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	167:e84263d55307	107
AnnaBridge	167:e84263d55307	108	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	167:e84263d55307	109	from memory to memory or from peripheral to memory.
AnnaBridge	167:e84263d55307	110	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	167:e84263d55307	111
AnnaBridge	167:e84263d55307	112	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	167:e84263d55307	113
AnnaBridge	167:e84263d55307	114	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	167:e84263d55307	115	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	167:e84263d55307	116	@note The circular buffer mode cannot be used if the memory to memory
AnnaBridge	167:e84263d55307	117	data transfer direction is configured on the selected Stream
AnnaBridge	167:e84263d55307	118
AnnaBridge	167:e84263d55307	119	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	167:e84263d55307	120
AnnaBridge	167:e84263d55307	121	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	167:e84263d55307	122	is incremented or not.
AnnaBridge	167:e84263d55307	123	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	167:e84263d55307	124
AnnaBridge	167:e84263d55307	125	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	167:e84263d55307	126
AnnaBridge	167:e84263d55307	127	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	167:e84263d55307	128	is incremented or not.
AnnaBridge	167:e84263d55307	129	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	167:e84263d55307	130
AnnaBridge	167:e84263d55307	131	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	167:e84263d55307	132
AnnaBridge	167:e84263d55307	133	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	167:e84263d55307	134	in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	135	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	167:e84263d55307	136
AnnaBridge	167:e84263d55307	137	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	167:e84263d55307	138
AnnaBridge	167:e84263d55307	139	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	167:e84263d55307	140	in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	141	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	167:e84263d55307	142
AnnaBridge	167:e84263d55307	143	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	167:e84263d55307	144
AnnaBridge	167:e84263d55307	145	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	167:e84263d55307	146	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	167:e84263d55307	147	or MemorySize parameters depending in the transfer direction.
AnnaBridge	167:e84263d55307	148	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	167:e84263d55307	149
AnnaBridge	167:e84263d55307	150	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	167:e84263d55307	151
AnnaBridge	167:e84263d55307	152	uint32_t Channel; /*!< Specifies the peripheral channel.
AnnaBridge	167:e84263d55307	153	This parameter can be a value of @ref DMA_LL_EC_CHANNEL
AnnaBridge	167:e84263d55307	154
AnnaBridge	167:e84263d55307	155	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
AnnaBridge	167:e84263d55307	156
AnnaBridge	167:e84263d55307	157	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	167:e84263d55307	158	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	167:e84263d55307	159
AnnaBridge	167:e84263d55307	160	This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
AnnaBridge	167:e84263d55307	161
AnnaBridge	167:e84263d55307	162	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
AnnaBridge	167:e84263d55307	163	This parameter can be a value of @ref DMA_LL_FIFOMODE
AnnaBridge	167:e84263d55307	164	@note The Direct mode (FIFO mode disabled) cannot be used if the
AnnaBridge	167:e84263d55307	165	memory-to-memory data transfer is configured on the selected stream
AnnaBridge	167:e84263d55307	166
AnnaBridge	167:e84263d55307	167	This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
AnnaBridge	167:e84263d55307	168
AnnaBridge	167:e84263d55307	169	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge	167:e84263d55307	170	This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
AnnaBridge	167:e84263d55307	171
AnnaBridge	167:e84263d55307	172	This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
AnnaBridge	167:e84263d55307	173
AnnaBridge	167:e84263d55307	174	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
AnnaBridge	167:e84263d55307	175	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	167:e84263d55307	176	transaction.
AnnaBridge	167:e84263d55307	177	This parameter can be a value of @ref DMA_LL_EC_MBURST
AnnaBridge	167:e84263d55307	178	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	167:e84263d55307	179
AnnaBridge	167:e84263d55307	180	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
AnnaBridge	167:e84263d55307	181
AnnaBridge	167:e84263d55307	182	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
AnnaBridge	167:e84263d55307	183	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	167:e84263d55307	184	transaction.
AnnaBridge	167:e84263d55307	185	This parameter can be a value of @ref DMA_LL_EC_PBURST
AnnaBridge	167:e84263d55307	186	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	167:e84263d55307	187
AnnaBridge	167:e84263d55307	188	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
AnnaBridge	167:e84263d55307	189
AnnaBridge	167:e84263d55307	190	} LL_DMA_InitTypeDef;
AnnaBridge	167:e84263d55307	191	/**
AnnaBridge	167:e84263d55307	192	* @}
AnnaBridge	167:e84263d55307	193	*/
AnnaBridge	167:e84263d55307	194	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	167:e84263d55307	195	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	196	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	167:e84263d55307	197	* @{
AnnaBridge	167:e84263d55307	198	*/
AnnaBridge	167:e84263d55307	199
AnnaBridge	167:e84263d55307	200	/** @defgroup DMA_LL_EC_STREAM STREAM
AnnaBridge	167:e84263d55307	201	* @{
AnnaBridge	167:e84263d55307	202	*/
AnnaBridge	167:e84263d55307	203	#define LL_DMA_STREAM_0 0x00000000U
AnnaBridge	167:e84263d55307	204	#define LL_DMA_STREAM_1 0x00000001U
AnnaBridge	167:e84263d55307	205	#define LL_DMA_STREAM_2 0x00000002U
AnnaBridge	167:e84263d55307	206	#define LL_DMA_STREAM_3 0x00000003U
AnnaBridge	167:e84263d55307	207	#define LL_DMA_STREAM_4 0x00000004U
AnnaBridge	167:e84263d55307	208	#define LL_DMA_STREAM_5 0x00000005U
AnnaBridge	167:e84263d55307	209	#define LL_DMA_STREAM_6 0x00000006U
AnnaBridge	167:e84263d55307	210	#define LL_DMA_STREAM_7 0x00000007U
AnnaBridge	167:e84263d55307	211	#define LL_DMA_STREAM_ALL 0xFFFF0000U
AnnaBridge	167:e84263d55307	212	/**
AnnaBridge	167:e84263d55307	213	* @}
AnnaBridge	167:e84263d55307	214	*/
AnnaBridge	167:e84263d55307	215
AnnaBridge	167:e84263d55307	216	/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
AnnaBridge	167:e84263d55307	217	* @{
AnnaBridge	167:e84263d55307	218	*/
AnnaBridge	167:e84263d55307	219	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	167:e84263d55307	220	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /!< Memory to peripheral direction /
AnnaBridge	167:e84263d55307	221	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /!< Memory to memory direction /
AnnaBridge	167:e84263d55307	222	/**
AnnaBridge	167:e84263d55307	223	* @}
AnnaBridge	167:e84263d55307	224	*/
AnnaBridge	167:e84263d55307	225
AnnaBridge	167:e84263d55307	226	/** @defgroup DMA_LL_EC_MODE MODE
AnnaBridge	167:e84263d55307	227	* @{
AnnaBridge	167:e84263d55307	228	*/
AnnaBridge	167:e84263d55307	229	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	167:e84263d55307	230	#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /!< Circular Mode /
AnnaBridge	167:e84263d55307	231	#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /!< Peripheral flow control mode /
AnnaBridge	167:e84263d55307	232	/**
AnnaBridge	167:e84263d55307	233	* @}
AnnaBridge	167:e84263d55307	234	*/
AnnaBridge	167:e84263d55307	235
AnnaBridge	167:e84263d55307	236	/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
AnnaBridge	167:e84263d55307	237	* @{
AnnaBridge	167:e84263d55307	238	*/
AnnaBridge	167:e84263d55307	239	#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /!< Disable double buffering mode /
AnnaBridge	167:e84263d55307	240	#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /!< Enable double buffering mode /
AnnaBridge	167:e84263d55307	241	/**
AnnaBridge	167:e84263d55307	242	* @}
AnnaBridge	167:e84263d55307	243	*/
AnnaBridge	167:e84263d55307	244
AnnaBridge	167:e84263d55307	245	/** @defgroup DMA_LL_EC_PERIPH PERIPH
AnnaBridge	167:e84263d55307	246	* @{
AnnaBridge	167:e84263d55307	247	*/
AnnaBridge	167:e84263d55307	248	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	167:e84263d55307	249	#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	167:e84263d55307	250	/**
AnnaBridge	167:e84263d55307	251	* @}
AnnaBridge	167:e84263d55307	252	*/
AnnaBridge	167:e84263d55307	253
AnnaBridge	167:e84263d55307	254	/** @defgroup DMA_LL_EC_MEMORY MEMORY
AnnaBridge	167:e84263d55307	255	* @{
AnnaBridge	167:e84263d55307	256	*/
AnnaBridge	167:e84263d55307	257	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	167:e84263d55307	258	#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /!< Memory increment mode Enable /
AnnaBridge	167:e84263d55307	259	/**
AnnaBridge	167:e84263d55307	260	* @}
AnnaBridge	167:e84263d55307	261	*/
AnnaBridge	167:e84263d55307	262
AnnaBridge	167:e84263d55307	263	/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
AnnaBridge	167:e84263d55307	264	* @{
AnnaBridge	167:e84263d55307	265	*/
AnnaBridge	167:e84263d55307	266	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	167:e84263d55307	267	#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	167:e84263d55307	268	#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	167:e84263d55307	269	/**
AnnaBridge	167:e84263d55307	270	* @}
AnnaBridge	167:e84263d55307	271	*/
AnnaBridge	167:e84263d55307	272
AnnaBridge	167:e84263d55307	273	/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
AnnaBridge	167:e84263d55307	274	* @{
AnnaBridge	167:e84263d55307	275	*/
AnnaBridge	167:e84263d55307	276	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	167:e84263d55307	277	#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	167:e84263d55307	278	#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	167:e84263d55307	279	/**
AnnaBridge	167:e84263d55307	280	* @}
AnnaBridge	167:e84263d55307	281	*/
AnnaBridge	167:e84263d55307	282
AnnaBridge	167:e84263d55307	283	/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
AnnaBridge	167:e84263d55307	284	* @{
AnnaBridge	167:e84263d55307	285	*/
AnnaBridge	167:e84263d55307	286	#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /!< Peripheral increment offset size is linked to the PSIZE /
AnnaBridge	167:e84263d55307	287	#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /!< Peripheral increment offset size is fixed to 4 (32-bit alignment) /
AnnaBridge	167:e84263d55307	288	/**
AnnaBridge	167:e84263d55307	289	* @}
AnnaBridge	167:e84263d55307	290	*/
AnnaBridge	167:e84263d55307	291
AnnaBridge	167:e84263d55307	292	/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
AnnaBridge	167:e84263d55307	293	* @{
AnnaBridge	167:e84263d55307	294	*/
AnnaBridge	167:e84263d55307	295	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	167:e84263d55307	296	#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /!< Priority level : Medium /
AnnaBridge	167:e84263d55307	297	#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /!< Priority level : High /
AnnaBridge	167:e84263d55307	298	#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /!< Priority level : Very_High /
AnnaBridge	167:e84263d55307	299	/**
AnnaBridge	167:e84263d55307	300	* @}
AnnaBridge	167:e84263d55307	301	*/
AnnaBridge	167:e84263d55307	302
AnnaBridge	167:e84263d55307	303	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	167:e84263d55307	304	* @{
AnnaBridge	167:e84263d55307	305	*/
AnnaBridge	167:e84263d55307	306	#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
AnnaBridge	167:e84263d55307	307	#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
AnnaBridge	167:e84263d55307	308	#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
AnnaBridge	167:e84263d55307	309	#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 \| DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
AnnaBridge	167:e84263d55307	310	#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
AnnaBridge	167:e84263d55307	311	#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
AnnaBridge	167:e84263d55307	312	#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
AnnaBridge	167:e84263d55307	313	#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1 \| DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
AnnaBridge	167:e84263d55307	314	/**
AnnaBridge	167:e84263d55307	315	* @}
AnnaBridge	167:e84263d55307	316	*/
AnnaBridge	167:e84263d55307	317
AnnaBridge	167:e84263d55307	318	/** @defgroup DMA_LL_EC_MBURST MBURST
AnnaBridge	167:e84263d55307	319	* @{
AnnaBridge	167:e84263d55307	320	*/
AnnaBridge	167:e84263d55307	321	#define LL_DMA_MBURST_SINGLE 0x00000000U /!< Memory burst single transfer configuration /
AnnaBridge	167:e84263d55307	322	#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /!< Memory burst of 4 beats transfer configuration /
AnnaBridge	167:e84263d55307	323	#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /!< Memory burst of 8 beats transfer configuration /
AnnaBridge	167:e84263d55307	324	#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 \| DMA_SxCR_MBURST_1) /!< Memory burst of 16 beats transfer configuration /
AnnaBridge	167:e84263d55307	325	/**
AnnaBridge	167:e84263d55307	326	* @}
AnnaBridge	167:e84263d55307	327	*/
AnnaBridge	167:e84263d55307	328
AnnaBridge	167:e84263d55307	329	/** @defgroup DMA_LL_EC_PBURST PBURST
AnnaBridge	167:e84263d55307	330	* @{
AnnaBridge	167:e84263d55307	331	*/
AnnaBridge	167:e84263d55307	332	#define LL_DMA_PBURST_SINGLE 0x00000000U /!< Peripheral burst single transfer configuration /
AnnaBridge	167:e84263d55307	333	#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /!< Peripheral burst of 4 beats transfer configuration /
AnnaBridge	167:e84263d55307	334	#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /!< Peripheral burst of 8 beats transfer configuration /
AnnaBridge	167:e84263d55307	335	#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 \| DMA_SxCR_PBURST_1) /!< Peripheral burst of 16 beats transfer configuration /
AnnaBridge	167:e84263d55307	336	/**
AnnaBridge	167:e84263d55307	337	* @}
AnnaBridge	167:e84263d55307	338	*/
AnnaBridge	167:e84263d55307	339
AnnaBridge	167:e84263d55307	340	/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
AnnaBridge	167:e84263d55307	341	* @{
AnnaBridge	167:e84263d55307	342	*/
AnnaBridge	167:e84263d55307	343	#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /!< FIFO mode disable (direct mode is enabled) /
AnnaBridge	167:e84263d55307	344	#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /!< FIFO mode enable /
AnnaBridge	167:e84263d55307	345	/**
AnnaBridge	167:e84263d55307	346	* @}
AnnaBridge	167:e84263d55307	347	*/
AnnaBridge	167:e84263d55307	348
AnnaBridge	167:e84263d55307	349	/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
AnnaBridge	167:e84263d55307	350	* @{
AnnaBridge	167:e84263d55307	351	*/
AnnaBridge	167:e84263d55307	352	#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /!< 0 < fifo_level < 1/4 /
AnnaBridge	167:e84263d55307	353	#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /!< 1/4 < fifo_level < 1/2 /
AnnaBridge	167:e84263d55307	354	#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /!< 1/2 < fifo_level < 3/4 /
AnnaBridge	167:e84263d55307	355	#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 \| DMA_SxFCR_FS_0) /!< 3/4 < fifo_level < full /
AnnaBridge	167:e84263d55307	356	#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /!< FIFO is empty /
AnnaBridge	167:e84263d55307	357	#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 \| DMA_SxFCR_FS_0) /!< FIFO is full /
AnnaBridge	167:e84263d55307	358	/**
AnnaBridge	167:e84263d55307	359	* @}
AnnaBridge	167:e84263d55307	360	*/
AnnaBridge	167:e84263d55307	361
AnnaBridge	167:e84263d55307	362	/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
AnnaBridge	167:e84263d55307	363	* @{
AnnaBridge	167:e84263d55307	364	*/
AnnaBridge	167:e84263d55307	365	#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /!< FIFO threshold 1 quart full configuration /
AnnaBridge	167:e84263d55307	366	#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /!< FIFO threshold half full configuration /
AnnaBridge	167:e84263d55307	367	#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /!< FIFO threshold 3 quarts full configuration /
AnnaBridge	167:e84263d55307	368	#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /!< FIFO threshold full configuration /
AnnaBridge	167:e84263d55307	369	/**
AnnaBridge	167:e84263d55307	370	* @}
AnnaBridge	167:e84263d55307	371	*/
AnnaBridge	167:e84263d55307	372
AnnaBridge	167:e84263d55307	373	/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
AnnaBridge	167:e84263d55307	374	* @{
AnnaBridge	167:e84263d55307	375	*/
AnnaBridge	167:e84263d55307	376	#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /!< Set CurrentTarget Memory to Memory 0 /
AnnaBridge	167:e84263d55307	377	#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /!< Set CurrentTarget Memory to Memory 1 /
AnnaBridge	167:e84263d55307	378	/**
AnnaBridge	167:e84263d55307	379	* @}
AnnaBridge	167:e84263d55307	380	*/
AnnaBridge	167:e84263d55307	381
AnnaBridge	167:e84263d55307	382	/**
AnnaBridge	167:e84263d55307	383	* @}
AnnaBridge	167:e84263d55307	384	*/
AnnaBridge	167:e84263d55307	385
AnnaBridge	167:e84263d55307	386	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	387	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	167:e84263d55307	388	* @{
AnnaBridge	167:e84263d55307	389	*/
AnnaBridge	167:e84263d55307	390
AnnaBridge	167:e84263d55307	391	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	167:e84263d55307	392	* @{
AnnaBridge	167:e84263d55307	393	*/
AnnaBridge	167:e84263d55307	394	/**
AnnaBridge	167:e84263d55307	395	* @brief Write a value in DMA register
AnnaBridge	167:e84263d55307	396	* @param __INSTANCE__ DMA Instance
AnnaBridge	167:e84263d55307	397	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	398	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	399	* @retval None
AnnaBridge	167:e84263d55307	400	*/
AnnaBridge	167:e84263d55307	401	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	402
AnnaBridge	167:e84263d55307	403	/**
AnnaBridge	167:e84263d55307	404	* @brief Read a value in DMA register
AnnaBridge	167:e84263d55307	405	* @param __INSTANCE__ DMA Instance
AnnaBridge	167:e84263d55307	406	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	407	* @retval Register value
AnnaBridge	167:e84263d55307	408	*/
AnnaBridge	167:e84263d55307	409	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	167:e84263d55307	410	/**
AnnaBridge	167:e84263d55307	411	* @}
AnnaBridge	167:e84263d55307	412	*/
AnnaBridge	167:e84263d55307	413
AnnaBridge	167:e84263d55307	414	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
AnnaBridge	167:e84263d55307	415	* @{
AnnaBridge	167:e84263d55307	416	*/
AnnaBridge	167:e84263d55307	417	/**
AnnaBridge	167:e84263d55307	418	* @brief Convert DMAx_Streamy into DMAx
AnnaBridge	167:e84263d55307	419	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	167:e84263d55307	420	* @retval DMAx
AnnaBridge	167:e84263d55307	421	*/
AnnaBridge	167:e84263d55307	422	#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
AnnaBridge	167:e84263d55307	423	(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
AnnaBridge	167:e84263d55307	424
AnnaBridge	167:e84263d55307	425	/**
AnnaBridge	167:e84263d55307	426	* @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
AnnaBridge	167:e84263d55307	427	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	167:e84263d55307	428	* @retval LL_DMA_CHANNEL_y
AnnaBridge	167:e84263d55307	429	*/
AnnaBridge	167:e84263d55307	430	#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
AnnaBridge	167:e84263d55307	431	(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	167:e84263d55307	432	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	167:e84263d55307	433	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	167:e84263d55307	434	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	167:e84263d55307	435	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	167:e84263d55307	436	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	167:e84263d55307	437	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	167:e84263d55307	438	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	167:e84263d55307	439	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	167:e84263d55307	440	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	167:e84263d55307	441	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	167:e84263d55307	442	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	167:e84263d55307	443	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	167:e84263d55307	444	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	167:e84263d55307	445	LL_DMA_STREAM_7)
AnnaBridge	167:e84263d55307	446
AnnaBridge	167:e84263d55307	447	/**
AnnaBridge	167:e84263d55307	448	* @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
AnnaBridge	167:e84263d55307	449	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	167:e84263d55307	450	* @param __STREAM__ LL_DMA_STREAM_y
AnnaBridge	167:e84263d55307	451	* @retval DMAx_Streamy
AnnaBridge	167:e84263d55307	452	*/
AnnaBridge	167:e84263d55307	453	#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
AnnaBridge	167:e84263d55307	454	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
AnnaBridge	167:e84263d55307	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
AnnaBridge	167:e84263d55307	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
AnnaBridge	167:e84263d55307	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
AnnaBridge	167:e84263d55307	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
AnnaBridge	167:e84263d55307	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
AnnaBridge	167:e84263d55307	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
AnnaBridge	167:e84263d55307	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
AnnaBridge	167:e84263d55307	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
AnnaBridge	167:e84263d55307	463	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
AnnaBridge	167:e84263d55307	464	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
AnnaBridge	167:e84263d55307	465	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
AnnaBridge	167:e84263d55307	466	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
AnnaBridge	167:e84263d55307	467	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
AnnaBridge	167:e84263d55307	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
AnnaBridge	167:e84263d55307	469	DMA2_Stream7)
AnnaBridge	167:e84263d55307	470
AnnaBridge	167:e84263d55307	471	/**
AnnaBridge	167:e84263d55307	472	* @}
AnnaBridge	167:e84263d55307	473	*/
AnnaBridge	167:e84263d55307	474
AnnaBridge	167:e84263d55307	475	/**
AnnaBridge	167:e84263d55307	476	* @}
AnnaBridge	167:e84263d55307	477	*/
AnnaBridge	167:e84263d55307	478
AnnaBridge	167:e84263d55307	479
AnnaBridge	167:e84263d55307	480	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	481	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	167:e84263d55307	482	* @{
AnnaBridge	167:e84263d55307	483	*/
AnnaBridge	167:e84263d55307	484
AnnaBridge	167:e84263d55307	485	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	167:e84263d55307	486	* @{
AnnaBridge	167:e84263d55307	487	*/
AnnaBridge	167:e84263d55307	488	/**
AnnaBridge	167:e84263d55307	489	* @brief Enable DMA stream.
AnnaBridge	167:e84263d55307	490	* @rmtoll CR EN LL_DMA_EnableStream
AnnaBridge	167:e84263d55307	491	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	492	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	493	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	494	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	495	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	496	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	497	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	498	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	499	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	500	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	501	* @retval None
AnnaBridge	167:e84263d55307	502	*/
AnnaBridge	167:e84263d55307	503	__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	504	{
AnnaBridge	167:e84263d55307	505	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
AnnaBridge	167:e84263d55307	506	}
AnnaBridge	167:e84263d55307	507
AnnaBridge	167:e84263d55307	508	/**
AnnaBridge	167:e84263d55307	509	* @brief Disable DMA stream.
AnnaBridge	167:e84263d55307	510	* @rmtoll CR EN LL_DMA_DisableStream
AnnaBridge	167:e84263d55307	511	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	512	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	513	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	514	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	515	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	516	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	517	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	518	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	519	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	520	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	521	* @retval None
AnnaBridge	167:e84263d55307	522	*/
AnnaBridge	167:e84263d55307	523	__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	524	{
AnnaBridge	167:e84263d55307	525	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
AnnaBridge	167:e84263d55307	526	}
AnnaBridge	167:e84263d55307	527
AnnaBridge	167:e84263d55307	528	/**
AnnaBridge	167:e84263d55307	529	* @brief Check if DMA stream is enabled or disabled.
AnnaBridge	167:e84263d55307	530	* @rmtoll CR EN LL_DMA_IsEnabledStream
AnnaBridge	167:e84263d55307	531	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	532	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	533	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	534	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	535	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	536	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	537	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	538	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	539	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	540	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	541	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	542	*/
AnnaBridge	167:e84263d55307	543	__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	544	{
AnnaBridge	167:e84263d55307	545	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
AnnaBridge	167:e84263d55307	546	}
AnnaBridge	167:e84263d55307	547
AnnaBridge	167:e84263d55307	548	/**
AnnaBridge	167:e84263d55307	549	* @brief Configure all parameters linked to DMA transfer.
AnnaBridge	167:e84263d55307	550	* @rmtoll CR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	551	* CR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	552	* CR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	553	* CR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	554	* CR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	555	* CR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	556	* CR PL LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	557	* CR PFCTRL LL_DMA_ConfigTransfer
AnnaBridge	167:e84263d55307	558	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	559	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	560	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	561	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	562	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	563	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	564	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	565	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	566	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	567	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	568	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	167:e84263d55307	569	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	570	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
AnnaBridge	167:e84263d55307	571	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	167:e84263d55307	572	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	167:e84263d55307	573	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	167:e84263d55307	574	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	167:e84263d55307	575	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	167:e84263d55307	576	*@retval None
AnnaBridge	167:e84263d55307	577	*/
AnnaBridge	167:e84263d55307	578	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
AnnaBridge	167:e84263d55307	579	{
AnnaBridge	167:e84263d55307	580	MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
AnnaBridge	167:e84263d55307	581	DMA_SxCR_DIR \| DMA_SxCR_CIRC \| DMA_SxCR_PINC \| DMA_SxCR_MINC \| DMA_SxCR_PSIZE \| DMA_SxCR_MSIZE \| DMA_SxCR_PL \| DMA_SxCR_PFCTRL,
AnnaBridge	167:e84263d55307	582	Configuration);
AnnaBridge	167:e84263d55307	583	}
AnnaBridge	167:e84263d55307	584
AnnaBridge	167:e84263d55307	585	/**
AnnaBridge	167:e84263d55307	586	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	167:e84263d55307	587	* @rmtoll CR DIR LL_DMA_SetDataTransferDirection
AnnaBridge	167:e84263d55307	588	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	589	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	590	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	591	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	592	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	593	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	594	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	595	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	596	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	597	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	598	* @param Direction This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	599	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	167:e84263d55307	600	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	167:e84263d55307	601	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	602	* @retval None
AnnaBridge	167:e84263d55307	603	*/
AnnaBridge	167:e84263d55307	604	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
AnnaBridge	167:e84263d55307	605	{
AnnaBridge	167:e84263d55307	606	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
AnnaBridge	167:e84263d55307	607	}
AnnaBridge	167:e84263d55307	608
AnnaBridge	167:e84263d55307	609	/**
AnnaBridge	167:e84263d55307	610	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	167:e84263d55307	611	* @rmtoll CR DIR LL_DMA_GetDataTransferDirection
AnnaBridge	167:e84263d55307	612	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	613	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	614	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	615	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	616	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	617	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	618	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	619	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	620	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	621	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	622	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	623	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	167:e84263d55307	624	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	167:e84263d55307	625	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	626	*/
AnnaBridge	167:e84263d55307	627	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	628	{
AnnaBridge	167:e84263d55307	629	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
AnnaBridge	167:e84263d55307	630	}
AnnaBridge	167:e84263d55307	631
AnnaBridge	167:e84263d55307	632	/**
AnnaBridge	167:e84263d55307	633	* @brief Set DMA mode normal, circular or peripheral flow control.
AnnaBridge	167:e84263d55307	634	* @rmtoll CR CIRC LL_DMA_SetMode\n
AnnaBridge	167:e84263d55307	635	* CR PFCTRL LL_DMA_SetMode
AnnaBridge	167:e84263d55307	636	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	637	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	638	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	639	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	640	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	641	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	642	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	643	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	644	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	645	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	646	* @param Mode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	647	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	167:e84263d55307	648	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	167:e84263d55307	649	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	167:e84263d55307	650	* @retval None
AnnaBridge	167:e84263d55307	651	*/
AnnaBridge	167:e84263d55307	652	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
AnnaBridge	167:e84263d55307	653	{
AnnaBridge	167:e84263d55307	654	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL, Mode);
AnnaBridge	167:e84263d55307	655	}
AnnaBridge	167:e84263d55307	656
AnnaBridge	167:e84263d55307	657	/**
AnnaBridge	167:e84263d55307	658	* @brief Get DMA mode normal, circular or peripheral flow control.
AnnaBridge	167:e84263d55307	659	* @rmtoll CR CIRC LL_DMA_GetMode\n
AnnaBridge	167:e84263d55307	660	* CR PFCTRL LL_DMA_GetMode
AnnaBridge	167:e84263d55307	661	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	662	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	663	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	664	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	665	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	666	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	667	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	668	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	669	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	670	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	671	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	672	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	167:e84263d55307	673	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	167:e84263d55307	674	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	167:e84263d55307	675	*/
AnnaBridge	167:e84263d55307	676	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	677	{
AnnaBridge	167:e84263d55307	678	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL));
AnnaBridge	167:e84263d55307	679	}
AnnaBridge	167:e84263d55307	680
AnnaBridge	167:e84263d55307	681	/**
AnnaBridge	167:e84263d55307	682	* @brief Set Peripheral increment mode.
AnnaBridge	167:e84263d55307	683	* @rmtoll CR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	167:e84263d55307	684	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	685	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	686	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	687	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	688	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	689	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	690	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	691	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	692	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	693	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	694	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	695	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	167:e84263d55307	696	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	167:e84263d55307	697	* @retval None
AnnaBridge	167:e84263d55307	698	*/
AnnaBridge	167:e84263d55307	699	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	167:e84263d55307	700	{
AnnaBridge	167:e84263d55307	701	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
AnnaBridge	167:e84263d55307	702	}
AnnaBridge	167:e84263d55307	703
AnnaBridge	167:e84263d55307	704	/**
AnnaBridge	167:e84263d55307	705	* @brief Get Peripheral increment mode.
AnnaBridge	167:e84263d55307	706	* @rmtoll CR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	167:e84263d55307	707	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	708	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	709	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	710	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	711	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	712	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	713	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	714	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	715	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	716	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	717	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	718	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	167:e84263d55307	719	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	167:e84263d55307	720	*/
AnnaBridge	167:e84263d55307	721	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	722	{
AnnaBridge	167:e84263d55307	723	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
AnnaBridge	167:e84263d55307	724	}
AnnaBridge	167:e84263d55307	725
AnnaBridge	167:e84263d55307	726	/**
AnnaBridge	167:e84263d55307	727	* @brief Set Memory increment mode.
AnnaBridge	167:e84263d55307	728	* @rmtoll CR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	167:e84263d55307	729	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	730	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	731	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	732	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	733	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	734	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	735	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	736	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	737	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	738	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	739	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	740	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	167:e84263d55307	741	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	167:e84263d55307	742	* @retval None
AnnaBridge	167:e84263d55307	743	*/
AnnaBridge	167:e84263d55307	744	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	167:e84263d55307	745	{
AnnaBridge	167:e84263d55307	746	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
AnnaBridge	167:e84263d55307	747	}
AnnaBridge	167:e84263d55307	748
AnnaBridge	167:e84263d55307	749	/**
AnnaBridge	167:e84263d55307	750	* @brief Get Memory increment mode.
AnnaBridge	167:e84263d55307	751	* @rmtoll CR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	167:e84263d55307	752	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	753	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	754	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	755	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	756	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	757	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	758	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	759	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	760	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	761	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	762	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	763	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	167:e84263d55307	764	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	167:e84263d55307	765	*/
AnnaBridge	167:e84263d55307	766	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	767	{
AnnaBridge	167:e84263d55307	768	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
AnnaBridge	167:e84263d55307	769	}
AnnaBridge	167:e84263d55307	770
AnnaBridge	167:e84263d55307	771	/**
AnnaBridge	167:e84263d55307	772	* @brief Set Peripheral size.
AnnaBridge	167:e84263d55307	773	* @rmtoll CR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	167:e84263d55307	774	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	775	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	776	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	777	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	778	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	779	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	780	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	781	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	782	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	783	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	784	* @param Size This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	785	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	786	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	787	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	167:e84263d55307	788	* @retval None
AnnaBridge	167:e84263d55307	789	*/
AnnaBridge	167:e84263d55307	790	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	167:e84263d55307	791	{
AnnaBridge	167:e84263d55307	792	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
AnnaBridge	167:e84263d55307	793	}
AnnaBridge	167:e84263d55307	794
AnnaBridge	167:e84263d55307	795	/**
AnnaBridge	167:e84263d55307	796	* @brief Get Peripheral size.
AnnaBridge	167:e84263d55307	797	* @rmtoll CR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	167:e84263d55307	798	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	799	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	800	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	801	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	802	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	803	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	804	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	805	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	806	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	807	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	808	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	809	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	810	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	811	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	167:e84263d55307	812	*/
AnnaBridge	167:e84263d55307	813	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	814	{
AnnaBridge	167:e84263d55307	815	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
AnnaBridge	167:e84263d55307	816	}
AnnaBridge	167:e84263d55307	817
AnnaBridge	167:e84263d55307	818	/**
AnnaBridge	167:e84263d55307	819	* @brief Set Memory size.
AnnaBridge	167:e84263d55307	820	* @rmtoll CR MSIZE LL_DMA_SetMemorySize
AnnaBridge	167:e84263d55307	821	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	822	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	823	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	824	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	825	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	826	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	827	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	828	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	829	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	830	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	831	* @param Size This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	832	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	833	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	834	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	167:e84263d55307	835	* @retval None
AnnaBridge	167:e84263d55307	836	*/
AnnaBridge	167:e84263d55307	837	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	167:e84263d55307	838	{
AnnaBridge	167:e84263d55307	839	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
AnnaBridge	167:e84263d55307	840	}
AnnaBridge	167:e84263d55307	841
AnnaBridge	167:e84263d55307	842	/**
AnnaBridge	167:e84263d55307	843	* @brief Get Memory size.
AnnaBridge	167:e84263d55307	844	* @rmtoll CR MSIZE LL_DMA_GetMemorySize
AnnaBridge	167:e84263d55307	845	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	846	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	847	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	848	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	849	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	850	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	851	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	852	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	853	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	854	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	855	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	856	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	857	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	858	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	167:e84263d55307	859	*/
AnnaBridge	167:e84263d55307	860	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	861	{
AnnaBridge	167:e84263d55307	862	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
AnnaBridge	167:e84263d55307	863	}
AnnaBridge	167:e84263d55307	864
AnnaBridge	167:e84263d55307	865	/**
AnnaBridge	167:e84263d55307	866	* @brief Set Peripheral increment offset size.
AnnaBridge	167:e84263d55307	867	* @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
AnnaBridge	167:e84263d55307	868	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	869	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	870	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	871	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	872	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	873	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	874	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	875	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	876	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	877	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	878	* @param OffsetSize This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	879	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	167:e84263d55307	880	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	167:e84263d55307	881	* @retval None
AnnaBridge	167:e84263d55307	882	*/
AnnaBridge	167:e84263d55307	883	__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
AnnaBridge	167:e84263d55307	884	{
AnnaBridge	167:e84263d55307	885	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
AnnaBridge	167:e84263d55307	886	}
AnnaBridge	167:e84263d55307	887
AnnaBridge	167:e84263d55307	888	/**
AnnaBridge	167:e84263d55307	889	* @brief Get Peripheral increment offset size.
AnnaBridge	167:e84263d55307	890	* @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
AnnaBridge	167:e84263d55307	891	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	892	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	893	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	894	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	895	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	896	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	897	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	898	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	899	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	900	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	901	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	902	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	167:e84263d55307	903	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	167:e84263d55307	904	*/
AnnaBridge	167:e84263d55307	905	__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	906	{
AnnaBridge	167:e84263d55307	907	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
AnnaBridge	167:e84263d55307	908	}
AnnaBridge	167:e84263d55307	909
AnnaBridge	167:e84263d55307	910	/**
AnnaBridge	167:e84263d55307	911	* @brief Set Stream priority level.
AnnaBridge	167:e84263d55307	912	* @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
AnnaBridge	167:e84263d55307	913	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	914	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	915	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	916	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	917	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	918	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	919	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	920	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	921	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	922	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	923	* @param Priority This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	924	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	167:e84263d55307	925	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	167:e84263d55307	926	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	167:e84263d55307	927	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	167:e84263d55307	928	* @retval None
AnnaBridge	167:e84263d55307	929	*/
AnnaBridge	167:e84263d55307	930	__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
AnnaBridge	167:e84263d55307	931	{
AnnaBridge	167:e84263d55307	932	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
AnnaBridge	167:e84263d55307	933	}
AnnaBridge	167:e84263d55307	934
AnnaBridge	167:e84263d55307	935	/**
AnnaBridge	167:e84263d55307	936	* @brief Get Stream priority level.
AnnaBridge	167:e84263d55307	937	* @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
AnnaBridge	167:e84263d55307	938	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	939	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	940	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	941	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	942	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	943	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	944	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	945	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	946	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	947	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	948	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	949	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	167:e84263d55307	950	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	167:e84263d55307	951	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	167:e84263d55307	952	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	167:e84263d55307	953	*/
AnnaBridge	167:e84263d55307	954	__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	955	{
AnnaBridge	167:e84263d55307	956	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
AnnaBridge	167:e84263d55307	957	}
AnnaBridge	167:e84263d55307	958
AnnaBridge	167:e84263d55307	959	/**
AnnaBridge	167:e84263d55307	960	* @brief Set Number of data to transfer.
AnnaBridge	167:e84263d55307	961	* @rmtoll NDTR NDT LL_DMA_SetDataLength
AnnaBridge	167:e84263d55307	962	* @note This action has no effect if
AnnaBridge	167:e84263d55307	963	* stream is enabled.
AnnaBridge	167:e84263d55307	964	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	965	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	966	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	967	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	968	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	969	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	970	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	971	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	972	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	973	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	974	* @param NbData Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	975	* @retval None
AnnaBridge	167:e84263d55307	976	*/
AnnaBridge	167:e84263d55307	977	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
AnnaBridge	167:e84263d55307	978	{
AnnaBridge	167:e84263d55307	979	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
AnnaBridge	167:e84263d55307	980	}
AnnaBridge	167:e84263d55307	981
AnnaBridge	167:e84263d55307	982	/**
AnnaBridge	167:e84263d55307	983	* @brief Get Number of data to transfer.
AnnaBridge	167:e84263d55307	984	* @rmtoll NDTR NDT LL_DMA_GetDataLength
AnnaBridge	167:e84263d55307	985	* @note Once the stream is enabled, the return value indicate the
AnnaBridge	167:e84263d55307	986	* remaining bytes to be transmitted.
AnnaBridge	167:e84263d55307	987	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	988	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	989	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	990	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	991	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	992	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	993	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	994	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	995	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	996	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	997	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	998	*/
AnnaBridge	167:e84263d55307	999	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1000	{
AnnaBridge	167:e84263d55307	1001	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
AnnaBridge	167:e84263d55307	1002	}
AnnaBridge	167:e84263d55307	1003
AnnaBridge	167:e84263d55307	1004	/**
AnnaBridge	167:e84263d55307	1005	* @brief Select Channel number associated to the Stream.
AnnaBridge	167:e84263d55307	1006	* @rmtoll CR CHSEL LL_DMA_SetChannelSelection
AnnaBridge	167:e84263d55307	1007	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1008	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1009	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1010	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1011	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1012	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1013	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1014	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1015	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1016	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1017	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1018	* @arg @ref LL_DMA_CHANNEL_0
AnnaBridge	167:e84263d55307	1019	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	167:e84263d55307	1020	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	167:e84263d55307	1021	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	167:e84263d55307	1022	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	167:e84263d55307	1023	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	167:e84263d55307	1024	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	167:e84263d55307	1025	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	167:e84263d55307	1026	* @retval None
AnnaBridge	167:e84263d55307	1027	*/
AnnaBridge	167:e84263d55307	1028	__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
AnnaBridge	167:e84263d55307	1029	{
AnnaBridge	167:e84263d55307	1030	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
AnnaBridge	167:e84263d55307	1031	}
AnnaBridge	167:e84263d55307	1032
AnnaBridge	167:e84263d55307	1033	/**
AnnaBridge	167:e84263d55307	1034	* @brief Get the Channel number associated to the Stream.
AnnaBridge	167:e84263d55307	1035	* @rmtoll CR CHSEL LL_DMA_GetChannelSelection
AnnaBridge	167:e84263d55307	1036	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1037	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1038	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1039	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1040	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1041	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1042	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1043	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1044	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1045	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1046	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1047	* @arg @ref LL_DMA_CHANNEL_0
AnnaBridge	167:e84263d55307	1048	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	167:e84263d55307	1049	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	167:e84263d55307	1050	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	167:e84263d55307	1051	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	167:e84263d55307	1052	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	167:e84263d55307	1053	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	167:e84263d55307	1054	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	167:e84263d55307	1055	*/
AnnaBridge	167:e84263d55307	1056	__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1057	{
AnnaBridge	167:e84263d55307	1058	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
AnnaBridge	167:e84263d55307	1059	}
AnnaBridge	167:e84263d55307	1060
AnnaBridge	167:e84263d55307	1061	/**
AnnaBridge	167:e84263d55307	1062	* @brief Set Memory burst transfer configuration.
AnnaBridge	167:e84263d55307	1063	* @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
AnnaBridge	167:e84263d55307	1064	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1065	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1066	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1067	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1068	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1069	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1070	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1071	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1072	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1073	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1074	* @param Mburst This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1075	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	167:e84263d55307	1076	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	167:e84263d55307	1077	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	167:e84263d55307	1078	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	167:e84263d55307	1079	* @retval None
AnnaBridge	167:e84263d55307	1080	*/
AnnaBridge	167:e84263d55307	1081	__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
AnnaBridge	167:e84263d55307	1082	{
AnnaBridge	167:e84263d55307	1083	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
AnnaBridge	167:e84263d55307	1084	}
AnnaBridge	167:e84263d55307	1085
AnnaBridge	167:e84263d55307	1086	/**
AnnaBridge	167:e84263d55307	1087	* @brief Get Memory burst transfer configuration.
AnnaBridge	167:e84263d55307	1088	* @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
AnnaBridge	167:e84263d55307	1089	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1090	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1091	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1092	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1093	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1094	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1095	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1096	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1097	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1098	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1099	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1100	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	167:e84263d55307	1101	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	167:e84263d55307	1102	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	167:e84263d55307	1103	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	167:e84263d55307	1104	*/
AnnaBridge	167:e84263d55307	1105	__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1106	{
AnnaBridge	167:e84263d55307	1107	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
AnnaBridge	167:e84263d55307	1108	}
AnnaBridge	167:e84263d55307	1109
AnnaBridge	167:e84263d55307	1110	/**
AnnaBridge	167:e84263d55307	1111	* @brief Set Peripheral burst transfer configuration.
AnnaBridge	167:e84263d55307	1112	* @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
AnnaBridge	167:e84263d55307	1113	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1114	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1115	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1116	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1117	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1118	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1119	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1120	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1121	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1122	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1123	* @param Pburst This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1124	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	167:e84263d55307	1125	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	167:e84263d55307	1126	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	167:e84263d55307	1127	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	167:e84263d55307	1128	* @retval None
AnnaBridge	167:e84263d55307	1129	*/
AnnaBridge	167:e84263d55307	1130	__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
AnnaBridge	167:e84263d55307	1131	{
AnnaBridge	167:e84263d55307	1132	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
AnnaBridge	167:e84263d55307	1133	}
AnnaBridge	167:e84263d55307	1134
AnnaBridge	167:e84263d55307	1135	/**
AnnaBridge	167:e84263d55307	1136	* @brief Get Peripheral burst transfer configuration.
AnnaBridge	167:e84263d55307	1137	* @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
AnnaBridge	167:e84263d55307	1138	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1139	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1140	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1141	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1142	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1143	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1144	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1145	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1146	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1147	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1148	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1149	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	167:e84263d55307	1150	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	167:e84263d55307	1151	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	167:e84263d55307	1152	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	167:e84263d55307	1153	*/
AnnaBridge	167:e84263d55307	1154	__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1155	{
AnnaBridge	167:e84263d55307	1156	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
AnnaBridge	167:e84263d55307	1157	}
AnnaBridge	167:e84263d55307	1158
AnnaBridge	167:e84263d55307	1159	/**
AnnaBridge	167:e84263d55307	1160	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	167:e84263d55307	1161	* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
AnnaBridge	167:e84263d55307	1162	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1163	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1164	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1165	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1166	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1167	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1168	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1169	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1170	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1171	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1172	* @param CurrentMemory This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1173	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	167:e84263d55307	1174	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	167:e84263d55307	1175	* @retval None
AnnaBridge	167:e84263d55307	1176	*/
AnnaBridge	167:e84263d55307	1177	__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
AnnaBridge	167:e84263d55307	1178	{
AnnaBridge	167:e84263d55307	1179	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
AnnaBridge	167:e84263d55307	1180	}
AnnaBridge	167:e84263d55307	1181
AnnaBridge	167:e84263d55307	1182	/**
AnnaBridge	167:e84263d55307	1183	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	167:e84263d55307	1184	* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
AnnaBridge	167:e84263d55307	1185	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1186	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1187	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1188	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1189	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1190	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1191	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1192	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1193	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1194	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1195	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1196	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	167:e84263d55307	1197	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	167:e84263d55307	1198	*/
AnnaBridge	167:e84263d55307	1199	__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1200	{
AnnaBridge	167:e84263d55307	1201	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
AnnaBridge	167:e84263d55307	1202	}
AnnaBridge	167:e84263d55307	1203
AnnaBridge	167:e84263d55307	1204	/**
AnnaBridge	167:e84263d55307	1205	* @brief Enable the double buffer mode.
AnnaBridge	167:e84263d55307	1206	* @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
AnnaBridge	167:e84263d55307	1207	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1208	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1209	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1210	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1211	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1212	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1213	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1214	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1215	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1216	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1217	* @retval None
AnnaBridge	167:e84263d55307	1218	*/
AnnaBridge	167:e84263d55307	1219	__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1220	{
AnnaBridge	167:e84263d55307	1221	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
AnnaBridge	167:e84263d55307	1222	}
AnnaBridge	167:e84263d55307	1223
AnnaBridge	167:e84263d55307	1224	/**
AnnaBridge	167:e84263d55307	1225	* @brief Disable the double buffer mode.
AnnaBridge	167:e84263d55307	1226	* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
AnnaBridge	167:e84263d55307	1227	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1228	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1229	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1230	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1231	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1232	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1233	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1234	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1235	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1236	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1237	* @retval None
AnnaBridge	167:e84263d55307	1238	*/
AnnaBridge	167:e84263d55307	1239	__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1240	{
AnnaBridge	167:e84263d55307	1241	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
AnnaBridge	167:e84263d55307	1242	}
AnnaBridge	167:e84263d55307	1243
AnnaBridge	167:e84263d55307	1244	/**
AnnaBridge	167:e84263d55307	1245	* @brief Get FIFO status.
AnnaBridge	167:e84263d55307	1246	* @rmtoll FCR FS LL_DMA_GetFIFOStatus
AnnaBridge	167:e84263d55307	1247	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1248	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1249	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1250	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1251	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1252	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1253	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1254	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1255	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1256	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1257	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1258	* @arg @ref LL_DMA_FIFOSTATUS_0_25
AnnaBridge	167:e84263d55307	1259	* @arg @ref LL_DMA_FIFOSTATUS_25_50
AnnaBridge	167:e84263d55307	1260	* @arg @ref LL_DMA_FIFOSTATUS_50_75
AnnaBridge	167:e84263d55307	1261	* @arg @ref LL_DMA_FIFOSTATUS_75_100
AnnaBridge	167:e84263d55307	1262	* @arg @ref LL_DMA_FIFOSTATUS_EMPTY
AnnaBridge	167:e84263d55307	1263	* @arg @ref LL_DMA_FIFOSTATUS_FULL
AnnaBridge	167:e84263d55307	1264	*/
AnnaBridge	167:e84263d55307	1265	__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1266	{
AnnaBridge	167:e84263d55307	1267	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
AnnaBridge	167:e84263d55307	1268	}
AnnaBridge	167:e84263d55307	1269
AnnaBridge	167:e84263d55307	1270	/**
AnnaBridge	167:e84263d55307	1271	* @brief Disable Fifo mode.
AnnaBridge	167:e84263d55307	1272	* @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
AnnaBridge	167:e84263d55307	1273	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1274	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1275	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1276	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1277	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1278	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1279	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1280	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1281	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1282	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1283	* @retval None
AnnaBridge	167:e84263d55307	1284	*/
AnnaBridge	167:e84263d55307	1285	__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1286	{
AnnaBridge	167:e84263d55307	1287	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	167:e84263d55307	1288	}
AnnaBridge	167:e84263d55307	1289
AnnaBridge	167:e84263d55307	1290	/**
AnnaBridge	167:e84263d55307	1291	* @brief Enable Fifo mode.
AnnaBridge	167:e84263d55307	1292	* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
AnnaBridge	167:e84263d55307	1293	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1294	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1295	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1296	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1297	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1298	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1299	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1300	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1301	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1302	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1303	* @retval None
AnnaBridge	167:e84263d55307	1304	*/
AnnaBridge	167:e84263d55307	1305	__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1306	{
AnnaBridge	167:e84263d55307	1307	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	167:e84263d55307	1308	}
AnnaBridge	167:e84263d55307	1309
AnnaBridge	167:e84263d55307	1310	/**
AnnaBridge	167:e84263d55307	1311	* @brief Select FIFO threshold.
AnnaBridge	167:e84263d55307	1312	* @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
AnnaBridge	167:e84263d55307	1313	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1314	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1315	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1316	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1317	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1318	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1319	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1320	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1321	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1322	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1323	* @param Threshold This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1324	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	167:e84263d55307	1325	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	167:e84263d55307	1326	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	167:e84263d55307	1327	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	167:e84263d55307	1328	* @retval None
AnnaBridge	167:e84263d55307	1329	*/
AnnaBridge	167:e84263d55307	1330	__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
AnnaBridge	167:e84263d55307	1331	{
AnnaBridge	167:e84263d55307	1332	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
AnnaBridge	167:e84263d55307	1333	}
AnnaBridge	167:e84263d55307	1334
AnnaBridge	167:e84263d55307	1335	/**
AnnaBridge	167:e84263d55307	1336	* @brief Get FIFO threshold.
AnnaBridge	167:e84263d55307	1337	* @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
AnnaBridge	167:e84263d55307	1338	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1339	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1340	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1341	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1342	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1343	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1344	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1345	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1346	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1347	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1348	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1349	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	167:e84263d55307	1350	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	167:e84263d55307	1351	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	167:e84263d55307	1352	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	167:e84263d55307	1353	*/
AnnaBridge	167:e84263d55307	1354	__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1355	{
AnnaBridge	167:e84263d55307	1356	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
AnnaBridge	167:e84263d55307	1357	}
AnnaBridge	167:e84263d55307	1358
AnnaBridge	167:e84263d55307	1359	/**
AnnaBridge	167:e84263d55307	1360	* @brief Configure the FIFO .
AnnaBridge	167:e84263d55307	1361	* @rmtoll FCR FTH LL_DMA_ConfigFifo\n
AnnaBridge	167:e84263d55307	1362	* FCR DMDIS LL_DMA_ConfigFifo
AnnaBridge	167:e84263d55307	1363	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1364	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1365	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1366	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1367	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1368	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1369	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1370	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1371	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1372	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1373	* @param FifoMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1374	* @arg @ref LL_DMA_FIFOMODE_ENABLE
AnnaBridge	167:e84263d55307	1375	* @arg @ref LL_DMA_FIFOMODE_DISABLE
AnnaBridge	167:e84263d55307	1376	* @param FifoThreshold This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1377	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	167:e84263d55307	1378	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	167:e84263d55307	1379	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	167:e84263d55307	1380	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	167:e84263d55307	1381	* @retval None
AnnaBridge	167:e84263d55307	1382	*/
AnnaBridge	167:e84263d55307	1383	__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
AnnaBridge	167:e84263d55307	1384	{
AnnaBridge	167:e84263d55307	1385	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH\|DMA_SxFCR_DMDIS, FifoMode\|FifoThreshold);
AnnaBridge	167:e84263d55307	1386	}
AnnaBridge	167:e84263d55307	1387
AnnaBridge	167:e84263d55307	1388	/**
AnnaBridge	167:e84263d55307	1389	* @brief Configure the Source and Destination addresses.
AnnaBridge	167:e84263d55307	1390	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	167:e84263d55307	1391	* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
AnnaBridge	167:e84263d55307	1392	* PAR PA LL_DMA_ConfigAddresses
AnnaBridge	167:e84263d55307	1393	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1394	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1395	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1396	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1397	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1398	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1399	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1400	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1401	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1402	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1403	* @param SrcAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1404	* @param DstAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1405	* @param Direction This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1406	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	167:e84263d55307	1407	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	167:e84263d55307	1408	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	1409	* @retval None
AnnaBridge	167:e84263d55307	1410	*/
AnnaBridge	167:e84263d55307	1411	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
AnnaBridge	167:e84263d55307	1412	{
AnnaBridge	167:e84263d55307	1413	/* Direction Memory to Periph */
AnnaBridge	167:e84263d55307	1414	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	167:e84263d55307	1415	{
AnnaBridge	167:e84263d55307	1416	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
AnnaBridge	167:e84263d55307	1417	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
AnnaBridge	167:e84263d55307	1418	}
AnnaBridge	167:e84263d55307	1419	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	167:e84263d55307	1420	else
AnnaBridge	167:e84263d55307	1421	{
AnnaBridge	167:e84263d55307	1422	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
AnnaBridge	167:e84263d55307	1423	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
AnnaBridge	167:e84263d55307	1424	}
AnnaBridge	167:e84263d55307	1425	}
AnnaBridge	167:e84263d55307	1426
AnnaBridge	167:e84263d55307	1427	/**
AnnaBridge	167:e84263d55307	1428	* @brief Set the Memory address.
AnnaBridge	167:e84263d55307	1429	* @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
AnnaBridge	167:e84263d55307	1430	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1431	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1432	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1433	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1434	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1435	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1436	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1437	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1438	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1439	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1440	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1441	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1442	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1443	* @retval None
AnnaBridge	167:e84263d55307	1444	*/
AnnaBridge	167:e84263d55307	1445	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	167:e84263d55307	1446	{
AnnaBridge	167:e84263d55307	1447	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
AnnaBridge	167:e84263d55307	1448	}
AnnaBridge	167:e84263d55307	1449
AnnaBridge	167:e84263d55307	1450	/**
AnnaBridge	167:e84263d55307	1451	* @brief Set the Peripheral address.
AnnaBridge	167:e84263d55307	1452	* @rmtoll PAR PA LL_DMA_SetPeriphAddress
AnnaBridge	167:e84263d55307	1453	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1454	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1455	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1456	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1457	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1458	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1459	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1460	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1461	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1462	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1463	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1464	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1465	* @param PeriphAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1466	* @retval None
AnnaBridge	167:e84263d55307	1467	*/
AnnaBridge	167:e84263d55307	1468	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
AnnaBridge	167:e84263d55307	1469	{
AnnaBridge	167:e84263d55307	1470	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
AnnaBridge	167:e84263d55307	1471	}
AnnaBridge	167:e84263d55307	1472
AnnaBridge	167:e84263d55307	1473	/**
AnnaBridge	167:e84263d55307	1474	* @brief Get the Memory address.
AnnaBridge	167:e84263d55307	1475	* @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
AnnaBridge	167:e84263d55307	1476	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1477	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1478	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1479	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1480	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1481	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1482	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1483	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1484	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1485	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1486	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1487	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1488	*/
AnnaBridge	167:e84263d55307	1489	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1490	{
AnnaBridge	167:e84263d55307	1491	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
AnnaBridge	167:e84263d55307	1492	}
AnnaBridge	167:e84263d55307	1493
AnnaBridge	167:e84263d55307	1494	/**
AnnaBridge	167:e84263d55307	1495	* @brief Get the Peripheral address.
AnnaBridge	167:e84263d55307	1496	* @rmtoll PAR PA LL_DMA_GetPeriphAddress
AnnaBridge	167:e84263d55307	1497	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1498	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1499	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1500	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1501	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1502	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1503	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1504	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1505	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1506	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1507	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1508	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1509	*/
AnnaBridge	167:e84263d55307	1510	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1511	{
AnnaBridge	167:e84263d55307	1512	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
AnnaBridge	167:e84263d55307	1513	}
AnnaBridge	167:e84263d55307	1514
AnnaBridge	167:e84263d55307	1515	/**
AnnaBridge	167:e84263d55307	1516	* @brief Set the Memory to Memory Source address.
AnnaBridge	167:e84263d55307	1517	* @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	167:e84263d55307	1518	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1519	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1520	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1521	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1522	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1523	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1524	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1525	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1526	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1527	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1528	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1529	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1530	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1531	* @retval None
AnnaBridge	167:e84263d55307	1532	*/
AnnaBridge	167:e84263d55307	1533	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	167:e84263d55307	1534	{
AnnaBridge	167:e84263d55307	1535	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
AnnaBridge	167:e84263d55307	1536	}
AnnaBridge	167:e84263d55307	1537
AnnaBridge	167:e84263d55307	1538	/**
AnnaBridge	167:e84263d55307	1539	* @brief Set the Memory to Memory Destination address.
AnnaBridge	167:e84263d55307	1540	* @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
AnnaBridge	167:e84263d55307	1541	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1542	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1543	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1544	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1545	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1546	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1547	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1548	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1549	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1550	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1551	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1552	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1553	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1554	* @retval None
AnnaBridge	167:e84263d55307	1555	*/
AnnaBridge	167:e84263d55307	1556	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	167:e84263d55307	1557	{
AnnaBridge	167:e84263d55307	1558	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
AnnaBridge	167:e84263d55307	1559	}
AnnaBridge	167:e84263d55307	1560
AnnaBridge	167:e84263d55307	1561	/**
AnnaBridge	167:e84263d55307	1562	* @brief Get the Memory to Memory Source address.
AnnaBridge	167:e84263d55307	1563	* @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	167:e84263d55307	1564	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1565	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1566	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1567	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1568	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1569	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1570	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1571	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1572	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1573	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1574	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1575	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1576	*/
AnnaBridge	167:e84263d55307	1577	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1578	{
AnnaBridge	167:e84263d55307	1579	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
AnnaBridge	167:e84263d55307	1580	}
AnnaBridge	167:e84263d55307	1581
AnnaBridge	167:e84263d55307	1582	/**
AnnaBridge	167:e84263d55307	1583	* @brief Get the Memory to Memory Destination address.
AnnaBridge	167:e84263d55307	1584	* @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
AnnaBridge	167:e84263d55307	1585	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1586	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1587	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1588	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1589	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1590	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1591	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1592	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1593	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1594	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1595	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1596	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1597	*/
AnnaBridge	167:e84263d55307	1598	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1599	{
AnnaBridge	167:e84263d55307	1600	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
AnnaBridge	167:e84263d55307	1601	}
AnnaBridge	167:e84263d55307	1602
AnnaBridge	167:e84263d55307	1603	/**
AnnaBridge	167:e84263d55307	1604	* @brief Set Memory 1 address (used in case of Double buffer mode).
AnnaBridge	167:e84263d55307	1605	* @rmtoll M1AR M1A LL_DMA_SetMemory1Address
AnnaBridge	167:e84263d55307	1606	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1607	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1608	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1609	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1610	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1611	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1612	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1613	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1614	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1615	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1616	* @param Address Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1617	* @retval None
AnnaBridge	167:e84263d55307	1618	*/
AnnaBridge	167:e84263d55307	1619	__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
AnnaBridge	167:e84263d55307	1620	{
AnnaBridge	167:e84263d55307	1621	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
AnnaBridge	167:e84263d55307	1622	}
AnnaBridge	167:e84263d55307	1623
AnnaBridge	167:e84263d55307	1624	/**
AnnaBridge	167:e84263d55307	1625	* @brief Get Memory 1 address (used in case of Double buffer mode).
AnnaBridge	167:e84263d55307	1626	* @rmtoll M1AR M1A LL_DMA_GetMemory1Address
AnnaBridge	167:e84263d55307	1627	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1628	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1629	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1630	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1631	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1632	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1633	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1634	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1635	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1636	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1637	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1638	*/
AnnaBridge	167:e84263d55307	1639	__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1640	{
AnnaBridge	167:e84263d55307	1641	return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
AnnaBridge	167:e84263d55307	1642	}
AnnaBridge	167:e84263d55307	1643
AnnaBridge	167:e84263d55307	1644	/**
AnnaBridge	167:e84263d55307	1645	* @}
AnnaBridge	167:e84263d55307	1646	*/
AnnaBridge	167:e84263d55307	1647
AnnaBridge	167:e84263d55307	1648	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	167:e84263d55307	1649	* @{
AnnaBridge	167:e84263d55307	1650	*/
AnnaBridge	167:e84263d55307	1651
AnnaBridge	167:e84263d55307	1652	/**
AnnaBridge	167:e84263d55307	1653	* @brief Get Stream 0 half transfer flag.
AnnaBridge	167:e84263d55307	1654	* @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
AnnaBridge	167:e84263d55307	1655	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1656	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1657	*/
AnnaBridge	167:e84263d55307	1658	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1659	{
AnnaBridge	167:e84263d55307	1660	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
AnnaBridge	167:e84263d55307	1661	}
AnnaBridge	167:e84263d55307	1662
AnnaBridge	167:e84263d55307	1663	/**
AnnaBridge	167:e84263d55307	1664	* @brief Get Stream 1 half transfer flag.
AnnaBridge	167:e84263d55307	1665	* @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	167:e84263d55307	1666	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1667	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1668	*/
AnnaBridge	167:e84263d55307	1669	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1670	{
AnnaBridge	167:e84263d55307	1671	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
AnnaBridge	167:e84263d55307	1672	}
AnnaBridge	167:e84263d55307	1673
AnnaBridge	167:e84263d55307	1674	/**
AnnaBridge	167:e84263d55307	1675	* @brief Get Stream 2 half transfer flag.
AnnaBridge	167:e84263d55307	1676	* @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	167:e84263d55307	1677	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1678	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1679	*/
AnnaBridge	167:e84263d55307	1680	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1681	{
AnnaBridge	167:e84263d55307	1682	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
AnnaBridge	167:e84263d55307	1683	}
AnnaBridge	167:e84263d55307	1684
AnnaBridge	167:e84263d55307	1685	/**
AnnaBridge	167:e84263d55307	1686	* @brief Get Stream 3 half transfer flag.
AnnaBridge	167:e84263d55307	1687	* @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	167:e84263d55307	1688	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1689	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1690	*/
AnnaBridge	167:e84263d55307	1691	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1692	{
AnnaBridge	167:e84263d55307	1693	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
AnnaBridge	167:e84263d55307	1694	}
AnnaBridge	167:e84263d55307	1695
AnnaBridge	167:e84263d55307	1696	/**
AnnaBridge	167:e84263d55307	1697	* @brief Get Stream 4 half transfer flag.
AnnaBridge	167:e84263d55307	1698	* @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	167:e84263d55307	1699	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1700	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1701	*/
AnnaBridge	167:e84263d55307	1702	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1703	{
AnnaBridge	167:e84263d55307	1704	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
AnnaBridge	167:e84263d55307	1705	}
AnnaBridge	167:e84263d55307	1706
AnnaBridge	167:e84263d55307	1707	/**
AnnaBridge	167:e84263d55307	1708	* @brief Get Stream 5 half transfer flag.
AnnaBridge	167:e84263d55307	1709	* @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
AnnaBridge	167:e84263d55307	1710	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1711	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1712	*/
AnnaBridge	167:e84263d55307	1713	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1714	{
AnnaBridge	167:e84263d55307	1715	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
AnnaBridge	167:e84263d55307	1716	}
AnnaBridge	167:e84263d55307	1717
AnnaBridge	167:e84263d55307	1718	/**
AnnaBridge	167:e84263d55307	1719	* @brief Get Stream 6 half transfer flag.
AnnaBridge	167:e84263d55307	1720	* @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	167:e84263d55307	1721	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1722	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1723	*/
AnnaBridge	167:e84263d55307	1724	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1725	{
AnnaBridge	167:e84263d55307	1726	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
AnnaBridge	167:e84263d55307	1727	}
AnnaBridge	167:e84263d55307	1728
AnnaBridge	167:e84263d55307	1729	/**
AnnaBridge	167:e84263d55307	1730	* @brief Get Stream 7 half transfer flag.
AnnaBridge	167:e84263d55307	1731	* @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	167:e84263d55307	1732	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1733	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1734	*/
AnnaBridge	167:e84263d55307	1735	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1736	{
AnnaBridge	167:e84263d55307	1737	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
AnnaBridge	167:e84263d55307	1738	}
AnnaBridge	167:e84263d55307	1739
AnnaBridge	167:e84263d55307	1740	/**
AnnaBridge	167:e84263d55307	1741	* @brief Get Stream 0 transfer complete flag.
AnnaBridge	167:e84263d55307	1742	* @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
AnnaBridge	167:e84263d55307	1743	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1744	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1745	*/
AnnaBridge	167:e84263d55307	1746	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1747	{
AnnaBridge	167:e84263d55307	1748	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
AnnaBridge	167:e84263d55307	1749	}
AnnaBridge	167:e84263d55307	1750
AnnaBridge	167:e84263d55307	1751	/**
AnnaBridge	167:e84263d55307	1752	* @brief Get Stream 1 transfer complete flag.
AnnaBridge	167:e84263d55307	1753	* @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	167:e84263d55307	1754	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1755	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1756	*/
AnnaBridge	167:e84263d55307	1757	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1758	{
AnnaBridge	167:e84263d55307	1759	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
AnnaBridge	167:e84263d55307	1760	}
AnnaBridge	167:e84263d55307	1761
AnnaBridge	167:e84263d55307	1762	/**
AnnaBridge	167:e84263d55307	1763	* @brief Get Stream 2 transfer complete flag.
AnnaBridge	167:e84263d55307	1764	* @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	167:e84263d55307	1765	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1766	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1767	*/
AnnaBridge	167:e84263d55307	1768	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1769	{
AnnaBridge	167:e84263d55307	1770	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
AnnaBridge	167:e84263d55307	1771	}
AnnaBridge	167:e84263d55307	1772
AnnaBridge	167:e84263d55307	1773	/**
AnnaBridge	167:e84263d55307	1774	* @brief Get Stream 3 transfer complete flag.
AnnaBridge	167:e84263d55307	1775	* @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	167:e84263d55307	1776	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1777	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1778	*/
AnnaBridge	167:e84263d55307	1779	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1780	{
AnnaBridge	167:e84263d55307	1781	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
AnnaBridge	167:e84263d55307	1782	}
AnnaBridge	167:e84263d55307	1783
AnnaBridge	167:e84263d55307	1784	/**
AnnaBridge	167:e84263d55307	1785	* @brief Get Stream 4 transfer complete flag.
AnnaBridge	167:e84263d55307	1786	* @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	167:e84263d55307	1787	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1788	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1789	*/
AnnaBridge	167:e84263d55307	1790	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1791	{
AnnaBridge	167:e84263d55307	1792	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
AnnaBridge	167:e84263d55307	1793	}
AnnaBridge	167:e84263d55307	1794
AnnaBridge	167:e84263d55307	1795	/**
AnnaBridge	167:e84263d55307	1796	* @brief Get Stream 5 transfer complete flag.
AnnaBridge	167:e84263d55307	1797	* @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
AnnaBridge	167:e84263d55307	1798	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1799	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1800	*/
AnnaBridge	167:e84263d55307	1801	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1802	{
AnnaBridge	167:e84263d55307	1803	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
AnnaBridge	167:e84263d55307	1804	}
AnnaBridge	167:e84263d55307	1805
AnnaBridge	167:e84263d55307	1806	/**
AnnaBridge	167:e84263d55307	1807	* @brief Get Stream 6 transfer complete flag.
AnnaBridge	167:e84263d55307	1808	* @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	167:e84263d55307	1809	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1810	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1811	*/
AnnaBridge	167:e84263d55307	1812	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1813	{
AnnaBridge	167:e84263d55307	1814	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
AnnaBridge	167:e84263d55307	1815	}
AnnaBridge	167:e84263d55307	1816
AnnaBridge	167:e84263d55307	1817	/**
AnnaBridge	167:e84263d55307	1818	* @brief Get Stream 7 transfer complete flag.
AnnaBridge	167:e84263d55307	1819	* @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	167:e84263d55307	1820	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1821	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1822	*/
AnnaBridge	167:e84263d55307	1823	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1824	{
AnnaBridge	167:e84263d55307	1825	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
AnnaBridge	167:e84263d55307	1826	}
AnnaBridge	167:e84263d55307	1827
AnnaBridge	167:e84263d55307	1828	/**
AnnaBridge	167:e84263d55307	1829	* @brief Get Stream 0 transfer error flag.
AnnaBridge	167:e84263d55307	1830	* @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
AnnaBridge	167:e84263d55307	1831	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1832	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1833	*/
AnnaBridge	167:e84263d55307	1834	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1835	{
AnnaBridge	167:e84263d55307	1836	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
AnnaBridge	167:e84263d55307	1837	}
AnnaBridge	167:e84263d55307	1838
AnnaBridge	167:e84263d55307	1839	/**
AnnaBridge	167:e84263d55307	1840	* @brief Get Stream 1 transfer error flag.
AnnaBridge	167:e84263d55307	1841	* @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	167:e84263d55307	1842	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1843	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1844	*/
AnnaBridge	167:e84263d55307	1845	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1846	{
AnnaBridge	167:e84263d55307	1847	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
AnnaBridge	167:e84263d55307	1848	}
AnnaBridge	167:e84263d55307	1849
AnnaBridge	167:e84263d55307	1850	/**
AnnaBridge	167:e84263d55307	1851	* @brief Get Stream 2 transfer error flag.
AnnaBridge	167:e84263d55307	1852	* @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	167:e84263d55307	1853	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1854	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1855	*/
AnnaBridge	167:e84263d55307	1856	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1857	{
AnnaBridge	167:e84263d55307	1858	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
AnnaBridge	167:e84263d55307	1859	}
AnnaBridge	167:e84263d55307	1860
AnnaBridge	167:e84263d55307	1861	/**
AnnaBridge	167:e84263d55307	1862	* @brief Get Stream 3 transfer error flag.
AnnaBridge	167:e84263d55307	1863	* @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	167:e84263d55307	1864	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1865	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1866	*/
AnnaBridge	167:e84263d55307	1867	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1868	{
AnnaBridge	167:e84263d55307	1869	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
AnnaBridge	167:e84263d55307	1870	}
AnnaBridge	167:e84263d55307	1871
AnnaBridge	167:e84263d55307	1872	/**
AnnaBridge	167:e84263d55307	1873	* @brief Get Stream 4 transfer error flag.
AnnaBridge	167:e84263d55307	1874	* @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	167:e84263d55307	1875	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1876	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1877	*/
AnnaBridge	167:e84263d55307	1878	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1879	{
AnnaBridge	167:e84263d55307	1880	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
AnnaBridge	167:e84263d55307	1881	}
AnnaBridge	167:e84263d55307	1882
AnnaBridge	167:e84263d55307	1883	/**
AnnaBridge	167:e84263d55307	1884	* @brief Get Stream 5 transfer error flag.
AnnaBridge	167:e84263d55307	1885	* @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
AnnaBridge	167:e84263d55307	1886	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1887	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1888	*/
AnnaBridge	167:e84263d55307	1889	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1890	{
AnnaBridge	167:e84263d55307	1891	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
AnnaBridge	167:e84263d55307	1892	}
AnnaBridge	167:e84263d55307	1893
AnnaBridge	167:e84263d55307	1894	/**
AnnaBridge	167:e84263d55307	1895	* @brief Get Stream 6 transfer error flag.
AnnaBridge	167:e84263d55307	1896	* @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	167:e84263d55307	1897	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1898	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1899	*/
AnnaBridge	167:e84263d55307	1900	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1901	{
AnnaBridge	167:e84263d55307	1902	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
AnnaBridge	167:e84263d55307	1903	}
AnnaBridge	167:e84263d55307	1904
AnnaBridge	167:e84263d55307	1905	/**
AnnaBridge	167:e84263d55307	1906	* @brief Get Stream 7 transfer error flag.
AnnaBridge	167:e84263d55307	1907	* @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	167:e84263d55307	1908	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1909	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1910	*/
AnnaBridge	167:e84263d55307	1911	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1912	{
AnnaBridge	167:e84263d55307	1913	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
AnnaBridge	167:e84263d55307	1914	}
AnnaBridge	167:e84263d55307	1915
AnnaBridge	167:e84263d55307	1916	/**
AnnaBridge	167:e84263d55307	1917	* @brief Get Stream 0 direct mode error flag.
AnnaBridge	167:e84263d55307	1918	* @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
AnnaBridge	167:e84263d55307	1919	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1920	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1921	*/
AnnaBridge	167:e84263d55307	1922	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1923	{
AnnaBridge	167:e84263d55307	1924	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
AnnaBridge	167:e84263d55307	1925	}
AnnaBridge	167:e84263d55307	1926
AnnaBridge	167:e84263d55307	1927	/**
AnnaBridge	167:e84263d55307	1928	* @brief Get Stream 1 direct mode error flag.
AnnaBridge	167:e84263d55307	1929	* @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
AnnaBridge	167:e84263d55307	1930	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1931	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1932	*/
AnnaBridge	167:e84263d55307	1933	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1934	{
AnnaBridge	167:e84263d55307	1935	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
AnnaBridge	167:e84263d55307	1936	}
AnnaBridge	167:e84263d55307	1937
AnnaBridge	167:e84263d55307	1938	/**
AnnaBridge	167:e84263d55307	1939	* @brief Get Stream 2 direct mode error flag.
AnnaBridge	167:e84263d55307	1940	* @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
AnnaBridge	167:e84263d55307	1941	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1942	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1943	*/
AnnaBridge	167:e84263d55307	1944	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1945	{
AnnaBridge	167:e84263d55307	1946	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
AnnaBridge	167:e84263d55307	1947	}
AnnaBridge	167:e84263d55307	1948
AnnaBridge	167:e84263d55307	1949	/**
AnnaBridge	167:e84263d55307	1950	* @brief Get Stream 3 direct mode error flag.
AnnaBridge	167:e84263d55307	1951	* @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
AnnaBridge	167:e84263d55307	1952	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1953	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1954	*/
AnnaBridge	167:e84263d55307	1955	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1956	{
AnnaBridge	167:e84263d55307	1957	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
AnnaBridge	167:e84263d55307	1958	}
AnnaBridge	167:e84263d55307	1959
AnnaBridge	167:e84263d55307	1960	/**
AnnaBridge	167:e84263d55307	1961	* @brief Get Stream 4 direct mode error flag.
AnnaBridge	167:e84263d55307	1962	* @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
AnnaBridge	167:e84263d55307	1963	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1964	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1965	*/
AnnaBridge	167:e84263d55307	1966	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1967	{
AnnaBridge	167:e84263d55307	1968	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
AnnaBridge	167:e84263d55307	1969	}
AnnaBridge	167:e84263d55307	1970
AnnaBridge	167:e84263d55307	1971	/**
AnnaBridge	167:e84263d55307	1972	* @brief Get Stream 5 direct mode error flag.
AnnaBridge	167:e84263d55307	1973	* @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
AnnaBridge	167:e84263d55307	1974	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1975	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1976	*/
AnnaBridge	167:e84263d55307	1977	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1978	{
AnnaBridge	167:e84263d55307	1979	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
AnnaBridge	167:e84263d55307	1980	}
AnnaBridge	167:e84263d55307	1981
AnnaBridge	167:e84263d55307	1982	/**
AnnaBridge	167:e84263d55307	1983	* @brief Get Stream 6 direct mode error flag.
AnnaBridge	167:e84263d55307	1984	* @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
AnnaBridge	167:e84263d55307	1985	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1986	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1987	*/
AnnaBridge	167:e84263d55307	1988	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1989	{
AnnaBridge	167:e84263d55307	1990	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
AnnaBridge	167:e84263d55307	1991	}
AnnaBridge	167:e84263d55307	1992
AnnaBridge	167:e84263d55307	1993	/**
AnnaBridge	167:e84263d55307	1994	* @brief Get Stream 7 direct mode error flag.
AnnaBridge	167:e84263d55307	1995	* @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
AnnaBridge	167:e84263d55307	1996	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1997	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1998	*/
AnnaBridge	167:e84263d55307	1999	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2000	{
AnnaBridge	167:e84263d55307	2001	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
AnnaBridge	167:e84263d55307	2002	}
AnnaBridge	167:e84263d55307	2003
AnnaBridge	167:e84263d55307	2004	/**
AnnaBridge	167:e84263d55307	2005	* @brief Get Stream 0 FIFO error flag.
AnnaBridge	167:e84263d55307	2006	* @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
AnnaBridge	167:e84263d55307	2007	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2008	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2009	*/
AnnaBridge	167:e84263d55307	2010	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2011	{
AnnaBridge	167:e84263d55307	2012	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
AnnaBridge	167:e84263d55307	2013	}
AnnaBridge	167:e84263d55307	2014
AnnaBridge	167:e84263d55307	2015	/**
AnnaBridge	167:e84263d55307	2016	* @brief Get Stream 1 FIFO error flag.
AnnaBridge	167:e84263d55307	2017	* @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
AnnaBridge	167:e84263d55307	2018	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2019	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2020	*/
AnnaBridge	167:e84263d55307	2021	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2022	{
AnnaBridge	167:e84263d55307	2023	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
AnnaBridge	167:e84263d55307	2024	}
AnnaBridge	167:e84263d55307	2025
AnnaBridge	167:e84263d55307	2026	/**
AnnaBridge	167:e84263d55307	2027	* @brief Get Stream 2 FIFO error flag.
AnnaBridge	167:e84263d55307	2028	* @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
AnnaBridge	167:e84263d55307	2029	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2030	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2031	*/
AnnaBridge	167:e84263d55307	2032	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2033	{
AnnaBridge	167:e84263d55307	2034	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
AnnaBridge	167:e84263d55307	2035	}
AnnaBridge	167:e84263d55307	2036
AnnaBridge	167:e84263d55307	2037	/**
AnnaBridge	167:e84263d55307	2038	* @brief Get Stream 3 FIFO error flag.
AnnaBridge	167:e84263d55307	2039	* @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
AnnaBridge	167:e84263d55307	2040	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2041	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2042	*/
AnnaBridge	167:e84263d55307	2043	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2044	{
AnnaBridge	167:e84263d55307	2045	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
AnnaBridge	167:e84263d55307	2046	}
AnnaBridge	167:e84263d55307	2047
AnnaBridge	167:e84263d55307	2048	/**
AnnaBridge	167:e84263d55307	2049	* @brief Get Stream 4 FIFO error flag.
AnnaBridge	167:e84263d55307	2050	* @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
AnnaBridge	167:e84263d55307	2051	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2052	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2053	*/
AnnaBridge	167:e84263d55307	2054	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2055	{
AnnaBridge	167:e84263d55307	2056	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
AnnaBridge	167:e84263d55307	2057	}
AnnaBridge	167:e84263d55307	2058
AnnaBridge	167:e84263d55307	2059	/**
AnnaBridge	167:e84263d55307	2060	* @brief Get Stream 5 FIFO error flag.
AnnaBridge	167:e84263d55307	2061	* @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
AnnaBridge	167:e84263d55307	2062	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2063	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2064	*/
AnnaBridge	167:e84263d55307	2065	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2066	{
AnnaBridge	167:e84263d55307	2067	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
AnnaBridge	167:e84263d55307	2068	}
AnnaBridge	167:e84263d55307	2069
AnnaBridge	167:e84263d55307	2070	/**
AnnaBridge	167:e84263d55307	2071	* @brief Get Stream 6 FIFO error flag.
AnnaBridge	167:e84263d55307	2072	* @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
AnnaBridge	167:e84263d55307	2073	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2074	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2075	*/
AnnaBridge	167:e84263d55307	2076	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2077	{
AnnaBridge	167:e84263d55307	2078	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
AnnaBridge	167:e84263d55307	2079	}
AnnaBridge	167:e84263d55307	2080
AnnaBridge	167:e84263d55307	2081	/**
AnnaBridge	167:e84263d55307	2082	* @brief Get Stream 7 FIFO error flag.
AnnaBridge	167:e84263d55307	2083	* @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
AnnaBridge	167:e84263d55307	2084	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2085	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2086	*/
AnnaBridge	167:e84263d55307	2087	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2088	{
AnnaBridge	167:e84263d55307	2089	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
AnnaBridge	167:e84263d55307	2090	}
AnnaBridge	167:e84263d55307	2091
AnnaBridge	167:e84263d55307	2092	/**
AnnaBridge	167:e84263d55307	2093	* @brief Clear Stream 0 half transfer flag.
AnnaBridge	167:e84263d55307	2094	* @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
AnnaBridge	167:e84263d55307	2095	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2096	* @retval None
AnnaBridge	167:e84263d55307	2097	*/
AnnaBridge	167:e84263d55307	2098	__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2099	{
AnnaBridge	167:e84263d55307	2100	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
AnnaBridge	167:e84263d55307	2101	}
AnnaBridge	167:e84263d55307	2102
AnnaBridge	167:e84263d55307	2103	/**
AnnaBridge	167:e84263d55307	2104	* @brief Clear Stream 1 half transfer flag.
AnnaBridge	167:e84263d55307	2105	* @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	167:e84263d55307	2106	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2107	* @retval None
AnnaBridge	167:e84263d55307	2108	*/
AnnaBridge	167:e84263d55307	2109	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2110	{
AnnaBridge	167:e84263d55307	2111	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
AnnaBridge	167:e84263d55307	2112	}
AnnaBridge	167:e84263d55307	2113
AnnaBridge	167:e84263d55307	2114	/**
AnnaBridge	167:e84263d55307	2115	* @brief Clear Stream 2 half transfer flag.
AnnaBridge	167:e84263d55307	2116	* @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	167:e84263d55307	2117	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2118	* @retval None
AnnaBridge	167:e84263d55307	2119	*/
AnnaBridge	167:e84263d55307	2120	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2121	{
AnnaBridge	167:e84263d55307	2122	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
AnnaBridge	167:e84263d55307	2123	}
AnnaBridge	167:e84263d55307	2124
AnnaBridge	167:e84263d55307	2125	/**
AnnaBridge	167:e84263d55307	2126	* @brief Clear Stream 3 half transfer flag.
AnnaBridge	167:e84263d55307	2127	* @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	167:e84263d55307	2128	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2129	* @retval None
AnnaBridge	167:e84263d55307	2130	*/
AnnaBridge	167:e84263d55307	2131	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2132	{
AnnaBridge	167:e84263d55307	2133	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
AnnaBridge	167:e84263d55307	2134	}
AnnaBridge	167:e84263d55307	2135
AnnaBridge	167:e84263d55307	2136	/**
AnnaBridge	167:e84263d55307	2137	* @brief Clear Stream 4 half transfer flag.
AnnaBridge	167:e84263d55307	2138	* @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	167:e84263d55307	2139	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2140	* @retval None
AnnaBridge	167:e84263d55307	2141	*/
AnnaBridge	167:e84263d55307	2142	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2143	{
AnnaBridge	167:e84263d55307	2144	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
AnnaBridge	167:e84263d55307	2145	}
AnnaBridge	167:e84263d55307	2146
AnnaBridge	167:e84263d55307	2147	/**
AnnaBridge	167:e84263d55307	2148	* @brief Clear Stream 5 half transfer flag.
AnnaBridge	167:e84263d55307	2149	* @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	167:e84263d55307	2150	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2151	* @retval None
AnnaBridge	167:e84263d55307	2152	*/
AnnaBridge	167:e84263d55307	2153	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2154	{
AnnaBridge	167:e84263d55307	2155	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
AnnaBridge	167:e84263d55307	2156	}
AnnaBridge	167:e84263d55307	2157
AnnaBridge	167:e84263d55307	2158	/**
AnnaBridge	167:e84263d55307	2159	* @brief Clear Stream 6 half transfer flag.
AnnaBridge	167:e84263d55307	2160	* @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	167:e84263d55307	2161	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2162	* @retval None
AnnaBridge	167:e84263d55307	2163	*/
AnnaBridge	167:e84263d55307	2164	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2165	{
AnnaBridge	167:e84263d55307	2166	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
AnnaBridge	167:e84263d55307	2167	}
AnnaBridge	167:e84263d55307	2168
AnnaBridge	167:e84263d55307	2169	/**
AnnaBridge	167:e84263d55307	2170	* @brief Clear Stream 7 half transfer flag.
AnnaBridge	167:e84263d55307	2171	* @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	167:e84263d55307	2172	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2173	* @retval None
AnnaBridge	167:e84263d55307	2174	*/
AnnaBridge	167:e84263d55307	2175	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2176	{
AnnaBridge	167:e84263d55307	2177	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
AnnaBridge	167:e84263d55307	2178	}
AnnaBridge	167:e84263d55307	2179
AnnaBridge	167:e84263d55307	2180	/**
AnnaBridge	167:e84263d55307	2181	* @brief Clear Stream 0 transfer complete flag.
AnnaBridge	167:e84263d55307	2182	* @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
AnnaBridge	167:e84263d55307	2183	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2184	* @retval None
AnnaBridge	167:e84263d55307	2185	*/
AnnaBridge	167:e84263d55307	2186	__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2187	{
AnnaBridge	167:e84263d55307	2188	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
AnnaBridge	167:e84263d55307	2189	}
AnnaBridge	167:e84263d55307	2190
AnnaBridge	167:e84263d55307	2191	/**
AnnaBridge	167:e84263d55307	2192	* @brief Clear Stream 1 transfer complete flag.
AnnaBridge	167:e84263d55307	2193	* @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	167:e84263d55307	2194	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2195	* @retval None
AnnaBridge	167:e84263d55307	2196	*/
AnnaBridge	167:e84263d55307	2197	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2198	{
AnnaBridge	167:e84263d55307	2199	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
AnnaBridge	167:e84263d55307	2200	}
AnnaBridge	167:e84263d55307	2201
AnnaBridge	167:e84263d55307	2202	/**
AnnaBridge	167:e84263d55307	2203	* @brief Clear Stream 2 transfer complete flag.
AnnaBridge	167:e84263d55307	2204	* @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	167:e84263d55307	2205	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2206	* @retval None
AnnaBridge	167:e84263d55307	2207	*/
AnnaBridge	167:e84263d55307	2208	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2209	{
AnnaBridge	167:e84263d55307	2210	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
AnnaBridge	167:e84263d55307	2211	}
AnnaBridge	167:e84263d55307	2212
AnnaBridge	167:e84263d55307	2213	/**
AnnaBridge	167:e84263d55307	2214	* @brief Clear Stream 3 transfer complete flag.
AnnaBridge	167:e84263d55307	2215	* @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	167:e84263d55307	2216	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2217	* @retval None
AnnaBridge	167:e84263d55307	2218	*/
AnnaBridge	167:e84263d55307	2219	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2220	{
AnnaBridge	167:e84263d55307	2221	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
AnnaBridge	167:e84263d55307	2222	}
AnnaBridge	167:e84263d55307	2223
AnnaBridge	167:e84263d55307	2224	/**
AnnaBridge	167:e84263d55307	2225	* @brief Clear Stream 4 transfer complete flag.
AnnaBridge	167:e84263d55307	2226	* @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	167:e84263d55307	2227	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2228	* @retval None
AnnaBridge	167:e84263d55307	2229	*/
AnnaBridge	167:e84263d55307	2230	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2231	{
AnnaBridge	167:e84263d55307	2232	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
AnnaBridge	167:e84263d55307	2233	}
AnnaBridge	167:e84263d55307	2234
AnnaBridge	167:e84263d55307	2235	/**
AnnaBridge	167:e84263d55307	2236	* @brief Clear Stream 5 transfer complete flag.
AnnaBridge	167:e84263d55307	2237	* @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	167:e84263d55307	2238	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2239	* @retval None
AnnaBridge	167:e84263d55307	2240	*/
AnnaBridge	167:e84263d55307	2241	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2242	{
AnnaBridge	167:e84263d55307	2243	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
AnnaBridge	167:e84263d55307	2244	}
AnnaBridge	167:e84263d55307	2245
AnnaBridge	167:e84263d55307	2246	/**
AnnaBridge	167:e84263d55307	2247	* @brief Clear Stream 6 transfer complete flag.
AnnaBridge	167:e84263d55307	2248	* @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	167:e84263d55307	2249	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2250	* @retval None
AnnaBridge	167:e84263d55307	2251	*/
AnnaBridge	167:e84263d55307	2252	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2253	{
AnnaBridge	167:e84263d55307	2254	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
AnnaBridge	167:e84263d55307	2255	}
AnnaBridge	167:e84263d55307	2256
AnnaBridge	167:e84263d55307	2257	/**
AnnaBridge	167:e84263d55307	2258	* @brief Clear Stream 7 transfer complete flag.
AnnaBridge	167:e84263d55307	2259	* @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	167:e84263d55307	2260	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2261	* @retval None
AnnaBridge	167:e84263d55307	2262	*/
AnnaBridge	167:e84263d55307	2263	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2264	{
AnnaBridge	167:e84263d55307	2265	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
AnnaBridge	167:e84263d55307	2266	}
AnnaBridge	167:e84263d55307	2267
AnnaBridge	167:e84263d55307	2268	/**
AnnaBridge	167:e84263d55307	2269	* @brief Clear Stream 0 transfer error flag.
AnnaBridge	167:e84263d55307	2270	* @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
AnnaBridge	167:e84263d55307	2271	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2272	* @retval None
AnnaBridge	167:e84263d55307	2273	*/
AnnaBridge	167:e84263d55307	2274	__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2275	{
AnnaBridge	167:e84263d55307	2276	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
AnnaBridge	167:e84263d55307	2277	}
AnnaBridge	167:e84263d55307	2278
AnnaBridge	167:e84263d55307	2279	/**
AnnaBridge	167:e84263d55307	2280	* @brief Clear Stream 1 transfer error flag.
AnnaBridge	167:e84263d55307	2281	* @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	167:e84263d55307	2282	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2283	* @retval None
AnnaBridge	167:e84263d55307	2284	*/
AnnaBridge	167:e84263d55307	2285	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2286	{
AnnaBridge	167:e84263d55307	2287	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
AnnaBridge	167:e84263d55307	2288	}
AnnaBridge	167:e84263d55307	2289
AnnaBridge	167:e84263d55307	2290	/**
AnnaBridge	167:e84263d55307	2291	* @brief Clear Stream 2 transfer error flag.
AnnaBridge	167:e84263d55307	2292	* @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	167:e84263d55307	2293	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2294	* @retval None
AnnaBridge	167:e84263d55307	2295	*/
AnnaBridge	167:e84263d55307	2296	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2297	{
AnnaBridge	167:e84263d55307	2298	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
AnnaBridge	167:e84263d55307	2299	}
AnnaBridge	167:e84263d55307	2300
AnnaBridge	167:e84263d55307	2301	/**
AnnaBridge	167:e84263d55307	2302	* @brief Clear Stream 3 transfer error flag.
AnnaBridge	167:e84263d55307	2303	* @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	167:e84263d55307	2304	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2305	* @retval None
AnnaBridge	167:e84263d55307	2306	*/
AnnaBridge	167:e84263d55307	2307	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2308	{
AnnaBridge	167:e84263d55307	2309	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
AnnaBridge	167:e84263d55307	2310	}
AnnaBridge	167:e84263d55307	2311
AnnaBridge	167:e84263d55307	2312	/**
AnnaBridge	167:e84263d55307	2313	* @brief Clear Stream 4 transfer error flag.
AnnaBridge	167:e84263d55307	2314	* @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	167:e84263d55307	2315	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2316	* @retval None
AnnaBridge	167:e84263d55307	2317	*/
AnnaBridge	167:e84263d55307	2318	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2319	{
AnnaBridge	167:e84263d55307	2320	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
AnnaBridge	167:e84263d55307	2321	}
AnnaBridge	167:e84263d55307	2322
AnnaBridge	167:e84263d55307	2323	/**
AnnaBridge	167:e84263d55307	2324	* @brief Clear Stream 5 transfer error flag.
AnnaBridge	167:e84263d55307	2325	* @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	167:e84263d55307	2326	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2327	* @retval None
AnnaBridge	167:e84263d55307	2328	*/
AnnaBridge	167:e84263d55307	2329	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2330	{
AnnaBridge	167:e84263d55307	2331	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
AnnaBridge	167:e84263d55307	2332	}
AnnaBridge	167:e84263d55307	2333
AnnaBridge	167:e84263d55307	2334	/**
AnnaBridge	167:e84263d55307	2335	* @brief Clear Stream 6 transfer error flag.
AnnaBridge	167:e84263d55307	2336	* @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	167:e84263d55307	2337	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2338	* @retval None
AnnaBridge	167:e84263d55307	2339	*/
AnnaBridge	167:e84263d55307	2340	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2341	{
AnnaBridge	167:e84263d55307	2342	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
AnnaBridge	167:e84263d55307	2343	}
AnnaBridge	167:e84263d55307	2344
AnnaBridge	167:e84263d55307	2345	/**
AnnaBridge	167:e84263d55307	2346	* @brief Clear Stream 7 transfer error flag.
AnnaBridge	167:e84263d55307	2347	* @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	167:e84263d55307	2348	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2349	* @retval None
AnnaBridge	167:e84263d55307	2350	*/
AnnaBridge	167:e84263d55307	2351	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2352	{
AnnaBridge	167:e84263d55307	2353	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
AnnaBridge	167:e84263d55307	2354	}
AnnaBridge	167:e84263d55307	2355
AnnaBridge	167:e84263d55307	2356	/**
AnnaBridge	167:e84263d55307	2357	* @brief Clear Stream 0 direct mode error flag.
AnnaBridge	167:e84263d55307	2358	* @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
AnnaBridge	167:e84263d55307	2359	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2360	* @retval None
AnnaBridge	167:e84263d55307	2361	*/
AnnaBridge	167:e84263d55307	2362	__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2363	{
AnnaBridge	167:e84263d55307	2364	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
AnnaBridge	167:e84263d55307	2365	}
AnnaBridge	167:e84263d55307	2366
AnnaBridge	167:e84263d55307	2367	/**
AnnaBridge	167:e84263d55307	2368	* @brief Clear Stream 1 direct mode error flag.
AnnaBridge	167:e84263d55307	2369	* @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
AnnaBridge	167:e84263d55307	2370	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2371	* @retval None
AnnaBridge	167:e84263d55307	2372	*/
AnnaBridge	167:e84263d55307	2373	__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2374	{
AnnaBridge	167:e84263d55307	2375	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
AnnaBridge	167:e84263d55307	2376	}
AnnaBridge	167:e84263d55307	2377
AnnaBridge	167:e84263d55307	2378	/**
AnnaBridge	167:e84263d55307	2379	* @brief Clear Stream 2 direct mode error flag.
AnnaBridge	167:e84263d55307	2380	* @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
AnnaBridge	167:e84263d55307	2381	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2382	* @retval None
AnnaBridge	167:e84263d55307	2383	*/
AnnaBridge	167:e84263d55307	2384	__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2385	{
AnnaBridge	167:e84263d55307	2386	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
AnnaBridge	167:e84263d55307	2387	}
AnnaBridge	167:e84263d55307	2388
AnnaBridge	167:e84263d55307	2389	/**
AnnaBridge	167:e84263d55307	2390	* @brief Clear Stream 3 direct mode error flag.
AnnaBridge	167:e84263d55307	2391	* @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
AnnaBridge	167:e84263d55307	2392	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2393	* @retval None
AnnaBridge	167:e84263d55307	2394	*/
AnnaBridge	167:e84263d55307	2395	__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2396	{
AnnaBridge	167:e84263d55307	2397	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
AnnaBridge	167:e84263d55307	2398	}
AnnaBridge	167:e84263d55307	2399
AnnaBridge	167:e84263d55307	2400	/**
AnnaBridge	167:e84263d55307	2401	* @brief Clear Stream 4 direct mode error flag.
AnnaBridge	167:e84263d55307	2402	* @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
AnnaBridge	167:e84263d55307	2403	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2404	* @retval None
AnnaBridge	167:e84263d55307	2405	*/
AnnaBridge	167:e84263d55307	2406	__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2407	{
AnnaBridge	167:e84263d55307	2408	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
AnnaBridge	167:e84263d55307	2409	}
AnnaBridge	167:e84263d55307	2410
AnnaBridge	167:e84263d55307	2411	/**
AnnaBridge	167:e84263d55307	2412	* @brief Clear Stream 5 direct mode error flag.
AnnaBridge	167:e84263d55307	2413	* @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
AnnaBridge	167:e84263d55307	2414	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2415	* @retval None
AnnaBridge	167:e84263d55307	2416	*/
AnnaBridge	167:e84263d55307	2417	__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2418	{
AnnaBridge	167:e84263d55307	2419	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
AnnaBridge	167:e84263d55307	2420	}
AnnaBridge	167:e84263d55307	2421
AnnaBridge	167:e84263d55307	2422	/**
AnnaBridge	167:e84263d55307	2423	* @brief Clear Stream 6 direct mode error flag.
AnnaBridge	167:e84263d55307	2424	* @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
AnnaBridge	167:e84263d55307	2425	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2426	* @retval None
AnnaBridge	167:e84263d55307	2427	*/
AnnaBridge	167:e84263d55307	2428	__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2429	{
AnnaBridge	167:e84263d55307	2430	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
AnnaBridge	167:e84263d55307	2431	}
AnnaBridge	167:e84263d55307	2432
AnnaBridge	167:e84263d55307	2433	/**
AnnaBridge	167:e84263d55307	2434	* @brief Clear Stream 7 direct mode error flag.
AnnaBridge	167:e84263d55307	2435	* @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
AnnaBridge	167:e84263d55307	2436	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2437	* @retval None
AnnaBridge	167:e84263d55307	2438	*/
AnnaBridge	167:e84263d55307	2439	__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2440	{
AnnaBridge	167:e84263d55307	2441	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
AnnaBridge	167:e84263d55307	2442	}
AnnaBridge	167:e84263d55307	2443
AnnaBridge	167:e84263d55307	2444	/**
AnnaBridge	167:e84263d55307	2445	* @brief Clear Stream 0 FIFO error flag.
AnnaBridge	167:e84263d55307	2446	* @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
AnnaBridge	167:e84263d55307	2447	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2448	* @retval None
AnnaBridge	167:e84263d55307	2449	*/
AnnaBridge	167:e84263d55307	2450	__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2451	{
AnnaBridge	167:e84263d55307	2452	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
AnnaBridge	167:e84263d55307	2453	}
AnnaBridge	167:e84263d55307	2454
AnnaBridge	167:e84263d55307	2455	/**
AnnaBridge	167:e84263d55307	2456	* @brief Clear Stream 1 FIFO error flag.
AnnaBridge	167:e84263d55307	2457	* @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
AnnaBridge	167:e84263d55307	2458	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2459	* @retval None
AnnaBridge	167:e84263d55307	2460	*/
AnnaBridge	167:e84263d55307	2461	__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2462	{
AnnaBridge	167:e84263d55307	2463	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
AnnaBridge	167:e84263d55307	2464	}
AnnaBridge	167:e84263d55307	2465
AnnaBridge	167:e84263d55307	2466	/**
AnnaBridge	167:e84263d55307	2467	* @brief Clear Stream 2 FIFO error flag.
AnnaBridge	167:e84263d55307	2468	* @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
AnnaBridge	167:e84263d55307	2469	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2470	* @retval None
AnnaBridge	167:e84263d55307	2471	*/
AnnaBridge	167:e84263d55307	2472	__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2473	{
AnnaBridge	167:e84263d55307	2474	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
AnnaBridge	167:e84263d55307	2475	}
AnnaBridge	167:e84263d55307	2476
AnnaBridge	167:e84263d55307	2477	/**
AnnaBridge	167:e84263d55307	2478	* @brief Clear Stream 3 FIFO error flag.
AnnaBridge	167:e84263d55307	2479	* @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
AnnaBridge	167:e84263d55307	2480	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2481	* @retval None
AnnaBridge	167:e84263d55307	2482	*/
AnnaBridge	167:e84263d55307	2483	__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2484	{
AnnaBridge	167:e84263d55307	2485	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
AnnaBridge	167:e84263d55307	2486	}
AnnaBridge	167:e84263d55307	2487
AnnaBridge	167:e84263d55307	2488	/**
AnnaBridge	167:e84263d55307	2489	* @brief Clear Stream 4 FIFO error flag.
AnnaBridge	167:e84263d55307	2490	* @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
AnnaBridge	167:e84263d55307	2491	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2492	* @retval None
AnnaBridge	167:e84263d55307	2493	*/
AnnaBridge	167:e84263d55307	2494	__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2495	{
AnnaBridge	167:e84263d55307	2496	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
AnnaBridge	167:e84263d55307	2497	}
AnnaBridge	167:e84263d55307	2498
AnnaBridge	167:e84263d55307	2499	/**
AnnaBridge	167:e84263d55307	2500	* @brief Clear Stream 5 FIFO error flag.
AnnaBridge	167:e84263d55307	2501	* @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
AnnaBridge	167:e84263d55307	2502	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2503	* @retval None
AnnaBridge	167:e84263d55307	2504	*/
AnnaBridge	167:e84263d55307	2505	__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2506	{
AnnaBridge	167:e84263d55307	2507	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
AnnaBridge	167:e84263d55307	2508	}
AnnaBridge	167:e84263d55307	2509
AnnaBridge	167:e84263d55307	2510	/**
AnnaBridge	167:e84263d55307	2511	* @brief Clear Stream 6 FIFO error flag.
AnnaBridge	167:e84263d55307	2512	* @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
AnnaBridge	167:e84263d55307	2513	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2514	* @retval None
AnnaBridge	167:e84263d55307	2515	*/
AnnaBridge	167:e84263d55307	2516	__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2517	{
AnnaBridge	167:e84263d55307	2518	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
AnnaBridge	167:e84263d55307	2519	}
AnnaBridge	167:e84263d55307	2520
AnnaBridge	167:e84263d55307	2521	/**
AnnaBridge	167:e84263d55307	2522	* @brief Clear Stream 7 FIFO error flag.
AnnaBridge	167:e84263d55307	2523	* @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
AnnaBridge	167:e84263d55307	2524	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2525	* @retval None
AnnaBridge	167:e84263d55307	2526	*/
AnnaBridge	167:e84263d55307	2527	__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2528	{
AnnaBridge	167:e84263d55307	2529	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
AnnaBridge	167:e84263d55307	2530	}
AnnaBridge	167:e84263d55307	2531
AnnaBridge	167:e84263d55307	2532	/**
AnnaBridge	167:e84263d55307	2533	* @}
AnnaBridge	167:e84263d55307	2534	*/
AnnaBridge	167:e84263d55307	2535
AnnaBridge	167:e84263d55307	2536	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	167:e84263d55307	2537	* @{
AnnaBridge	167:e84263d55307	2538	*/
AnnaBridge	167:e84263d55307	2539
AnnaBridge	167:e84263d55307	2540	/**
AnnaBridge	167:e84263d55307	2541	* @brief Enable Half transfer interrupt.
AnnaBridge	167:e84263d55307	2542	* @rmtoll CR HTIE LL_DMA_EnableIT_HT
AnnaBridge	167:e84263d55307	2543	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2544	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2545	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2546	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2547	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2548	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2549	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2550	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2551	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2552	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2553	* @retval None
AnnaBridge	167:e84263d55307	2554	*/
AnnaBridge	167:e84263d55307	2555	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2556	{
AnnaBridge	167:e84263d55307	2557	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
AnnaBridge	167:e84263d55307	2558	}
AnnaBridge	167:e84263d55307	2559
AnnaBridge	167:e84263d55307	2560	/**
AnnaBridge	167:e84263d55307	2561	* @brief Enable Transfer error interrupt.
AnnaBridge	167:e84263d55307	2562	* @rmtoll CR TEIE LL_DMA_EnableIT_TE
AnnaBridge	167:e84263d55307	2563	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2564	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2565	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2566	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2567	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2568	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2569	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2570	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2571	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2572	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2573	* @retval None
AnnaBridge	167:e84263d55307	2574	*/
AnnaBridge	167:e84263d55307	2575	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2576	{
AnnaBridge	167:e84263d55307	2577	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
AnnaBridge	167:e84263d55307	2578	}
AnnaBridge	167:e84263d55307	2579
AnnaBridge	167:e84263d55307	2580	/**
AnnaBridge	167:e84263d55307	2581	* @brief Enable Transfer complete interrupt.
AnnaBridge	167:e84263d55307	2582	* @rmtoll CR TCIE LL_DMA_EnableIT_TC
AnnaBridge	167:e84263d55307	2583	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2584	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2585	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2586	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2587	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2588	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2589	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2590	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2591	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2592	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2593	* @retval None
AnnaBridge	167:e84263d55307	2594	*/
AnnaBridge	167:e84263d55307	2595	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2596	{
AnnaBridge	167:e84263d55307	2597	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
AnnaBridge	167:e84263d55307	2598	}
AnnaBridge	167:e84263d55307	2599
AnnaBridge	167:e84263d55307	2600	/**
AnnaBridge	167:e84263d55307	2601	* @brief Enable Direct mode error interrupt.
AnnaBridge	167:e84263d55307	2602	* @rmtoll CR DMEIE LL_DMA_EnableIT_DME
AnnaBridge	167:e84263d55307	2603	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2604	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2605	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2606	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2607	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2608	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2609	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2610	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2611	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2612	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2613	* @retval None
AnnaBridge	167:e84263d55307	2614	*/
AnnaBridge	167:e84263d55307	2615	__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2616	{
AnnaBridge	167:e84263d55307	2617	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
AnnaBridge	167:e84263d55307	2618	}
AnnaBridge	167:e84263d55307	2619
AnnaBridge	167:e84263d55307	2620	/**
AnnaBridge	167:e84263d55307	2621	* @brief Enable FIFO error interrupt.
AnnaBridge	167:e84263d55307	2622	* @rmtoll FCR FEIE LL_DMA_EnableIT_FE
AnnaBridge	167:e84263d55307	2623	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2624	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2625	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2626	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2627	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2628	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2629	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2630	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2631	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2632	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2633	* @retval None
AnnaBridge	167:e84263d55307	2634	*/
AnnaBridge	167:e84263d55307	2635	__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2636	{
AnnaBridge	167:e84263d55307	2637	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	167:e84263d55307	2638	}
AnnaBridge	167:e84263d55307	2639
AnnaBridge	167:e84263d55307	2640	/**
AnnaBridge	167:e84263d55307	2641	* @brief Disable Half transfer interrupt.
AnnaBridge	167:e84263d55307	2642	* @rmtoll CR HTIE LL_DMA_DisableIT_HT
AnnaBridge	167:e84263d55307	2643	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2644	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2645	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2646	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2647	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2648	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2649	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2650	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2651	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2652	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2653	* @retval None
AnnaBridge	167:e84263d55307	2654	*/
AnnaBridge	167:e84263d55307	2655	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2656	{
AnnaBridge	167:e84263d55307	2657	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
AnnaBridge	167:e84263d55307	2658	}
AnnaBridge	167:e84263d55307	2659
AnnaBridge	167:e84263d55307	2660	/**
AnnaBridge	167:e84263d55307	2661	* @brief Disable Transfer error interrupt.
AnnaBridge	167:e84263d55307	2662	* @rmtoll CR TEIE LL_DMA_DisableIT_TE
AnnaBridge	167:e84263d55307	2663	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2664	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2665	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2666	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2667	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2668	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2669	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2670	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2671	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2672	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2673	* @retval None
AnnaBridge	167:e84263d55307	2674	*/
AnnaBridge	167:e84263d55307	2675	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2676	{
AnnaBridge	167:e84263d55307	2677	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
AnnaBridge	167:e84263d55307	2678	}
AnnaBridge	167:e84263d55307	2679
AnnaBridge	167:e84263d55307	2680	/**
AnnaBridge	167:e84263d55307	2681	* @brief Disable Transfer complete interrupt.
AnnaBridge	167:e84263d55307	2682	* @rmtoll CR TCIE LL_DMA_DisableIT_TC
AnnaBridge	167:e84263d55307	2683	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2684	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2685	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2686	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2687	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2688	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2689	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2690	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2691	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2692	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2693	* @retval None
AnnaBridge	167:e84263d55307	2694	*/
AnnaBridge	167:e84263d55307	2695	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2696	{
AnnaBridge	167:e84263d55307	2697	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
AnnaBridge	167:e84263d55307	2698	}
AnnaBridge	167:e84263d55307	2699
AnnaBridge	167:e84263d55307	2700	/**
AnnaBridge	167:e84263d55307	2701	* @brief Disable Direct mode error interrupt.
AnnaBridge	167:e84263d55307	2702	* @rmtoll CR DMEIE LL_DMA_DisableIT_DME
AnnaBridge	167:e84263d55307	2703	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2704	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2705	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2706	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2707	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2708	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2709	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2710	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2711	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2712	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2713	* @retval None
AnnaBridge	167:e84263d55307	2714	*/
AnnaBridge	167:e84263d55307	2715	__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2716	{
AnnaBridge	167:e84263d55307	2717	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
AnnaBridge	167:e84263d55307	2718	}
AnnaBridge	167:e84263d55307	2719
AnnaBridge	167:e84263d55307	2720	/**
AnnaBridge	167:e84263d55307	2721	* @brief Disable FIFO error interrupt.
AnnaBridge	167:e84263d55307	2722	* @rmtoll FCR FEIE LL_DMA_DisableIT_FE
AnnaBridge	167:e84263d55307	2723	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2724	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2725	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2726	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2727	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2728	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2729	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2730	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2731	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2732	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2733	* @retval None
AnnaBridge	167:e84263d55307	2734	*/
AnnaBridge	167:e84263d55307	2735	__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2736	{
AnnaBridge	167:e84263d55307	2737	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	167:e84263d55307	2738	}
AnnaBridge	167:e84263d55307	2739
AnnaBridge	167:e84263d55307	2740	/**
AnnaBridge	167:e84263d55307	2741	* @brief Check if Half transfer interrup is enabled.
AnnaBridge	167:e84263d55307	2742	* @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	167:e84263d55307	2743	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2744	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2745	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2746	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2747	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2748	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2749	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2750	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2751	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2752	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2753	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2754	*/
AnnaBridge	167:e84263d55307	2755	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2756	{
AnnaBridge	167:e84263d55307	2757	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
AnnaBridge	167:e84263d55307	2758	}
AnnaBridge	167:e84263d55307	2759
AnnaBridge	167:e84263d55307	2760	/**
AnnaBridge	167:e84263d55307	2761	* @brief Check if Transfer error nterrup is enabled.
AnnaBridge	167:e84263d55307	2762	* @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	167:e84263d55307	2763	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2764	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2765	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2766	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2767	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2768	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2769	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2770	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2771	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2772	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2773	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2774	*/
AnnaBridge	167:e84263d55307	2775	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2776	{
AnnaBridge	167:e84263d55307	2777	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
AnnaBridge	167:e84263d55307	2778	}
AnnaBridge	167:e84263d55307	2779
AnnaBridge	167:e84263d55307	2780	/**
AnnaBridge	167:e84263d55307	2781	* @brief Check if Transfer complete interrup is enabled.
AnnaBridge	167:e84263d55307	2782	* @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	167:e84263d55307	2783	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2784	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2785	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2786	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2787	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2788	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2789	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2790	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2791	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2792	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2793	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2794	*/
AnnaBridge	167:e84263d55307	2795	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2796	{
AnnaBridge	167:e84263d55307	2797	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
AnnaBridge	167:e84263d55307	2798	}
AnnaBridge	167:e84263d55307	2799
AnnaBridge	167:e84263d55307	2800	/**
AnnaBridge	167:e84263d55307	2801	* @brief Check if Direct mode error interrupt is enabled.
AnnaBridge	167:e84263d55307	2802	* @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
AnnaBridge	167:e84263d55307	2803	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2804	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2805	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2806	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2807	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2808	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2809	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2810	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2811	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2812	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2813	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2814	*/
AnnaBridge	167:e84263d55307	2815	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2816	{
AnnaBridge	167:e84263d55307	2817	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
AnnaBridge	167:e84263d55307	2818	}
AnnaBridge	167:e84263d55307	2819
AnnaBridge	167:e84263d55307	2820	/**
AnnaBridge	167:e84263d55307	2821	* @brief Check if FIFO error interrup is enabled.
AnnaBridge	167:e84263d55307	2822	* @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
AnnaBridge	167:e84263d55307	2823	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2824	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2825	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2826	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2827	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2828	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2829	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2830	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2831	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2832	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2833	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2834	*/
AnnaBridge	167:e84263d55307	2835	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2836	{
AnnaBridge	167:e84263d55307	2837	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
AnnaBridge	167:e84263d55307	2838	}
AnnaBridge	167:e84263d55307	2839
AnnaBridge	167:e84263d55307	2840	/**
AnnaBridge	167:e84263d55307	2841	* @}
AnnaBridge	167:e84263d55307	2842	*/
AnnaBridge	167:e84263d55307	2843
AnnaBridge	167:e84263d55307	2844	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	2845	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	2846	* @{
AnnaBridge	167:e84263d55307	2847	*/
AnnaBridge	167:e84263d55307	2848
AnnaBridge	167:e84263d55307	2849	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Stream, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	167:e84263d55307	2850	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
AnnaBridge	167:e84263d55307	2851	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	167:e84263d55307	2852
AnnaBridge	167:e84263d55307	2853	/**
AnnaBridge	167:e84263d55307	2854	* @}
AnnaBridge	167:e84263d55307	2855	*/
AnnaBridge	167:e84263d55307	2856	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	2857
AnnaBridge	167:e84263d55307	2858	/**
AnnaBridge	167:e84263d55307	2859	* @}
AnnaBridge	167:e84263d55307	2860	*/
AnnaBridge	167:e84263d55307	2861
AnnaBridge	167:e84263d55307	2862	/**
AnnaBridge	167:e84263d55307	2863	* @}
AnnaBridge	167:e84263d55307	2864	*/
AnnaBridge	167:e84263d55307	2865
AnnaBridge	167:e84263d55307	2866	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	167:e84263d55307	2867
AnnaBridge	167:e84263d55307	2868	/**
AnnaBridge	167:e84263d55307	2869	* @}
AnnaBridge	167:e84263d55307	2870	*/
AnnaBridge	167:e84263d55307	2871
AnnaBridge	167:e84263d55307	2872	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	2873	}
AnnaBridge	167:e84263d55307	2874	#endif
AnnaBridge	167:e84263d55307	2875
AnnaBridge	167:e84263d55307	2876	#endif /* __STM32F2xx_LL_DMA_H */
AnnaBridge	167:e84263d55307	2877
AnnaBridge	167:e84263d55307	2878	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/