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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_bus.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 167:e84263d55307
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 167:e84263d55307 | 1 | /** |
| AnnaBridge | 167:e84263d55307 | 2 | ****************************************************************************** |
| AnnaBridge | 167:e84263d55307 | 3 | * @file stm32f2xx_ll_bus.h |
| AnnaBridge | 167:e84263d55307 | 4 | * @author MCD Application Team |
| AnnaBridge | 167:e84263d55307 | 5 | * @version V1.2.1 |
| AnnaBridge | 167:e84263d55307 | 6 | * @date 14-April-2017 |
| AnnaBridge | 167:e84263d55307 | 7 | * @brief Header file of BUS LL module. |
| AnnaBridge | 167:e84263d55307 | 8 | |
| AnnaBridge | 167:e84263d55307 | 9 | @verbatim |
| AnnaBridge | 167:e84263d55307 | 10 | ##### RCC Limitations ##### |
| AnnaBridge | 167:e84263d55307 | 11 | ============================================================================== |
| AnnaBridge | 167:e84263d55307 | 12 | [..] |
| AnnaBridge | 167:e84263d55307 | 13 | A delay between an RCC peripheral clock enable and the effective peripheral |
| AnnaBridge | 167:e84263d55307 | 14 | enabling should be taken into account in order to manage the peripheral read/write |
| AnnaBridge | 167:e84263d55307 | 15 | from/to registers. |
| AnnaBridge | 167:e84263d55307 | 16 | (+) This delay depends on the peripheral mapping. |
| AnnaBridge | 167:e84263d55307 | 17 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| AnnaBridge | 167:e84263d55307 | 18 | |
| AnnaBridge | 167:e84263d55307 | 19 | [..] |
| AnnaBridge | 167:e84263d55307 | 20 | Workarounds: |
| AnnaBridge | 167:e84263d55307 | 21 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| AnnaBridge | 167:e84263d55307 | 22 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| AnnaBridge | 167:e84263d55307 | 23 | |
| AnnaBridge | 167:e84263d55307 | 24 | @endverbatim |
| AnnaBridge | 167:e84263d55307 | 25 | ****************************************************************************** |
| AnnaBridge | 167:e84263d55307 | 26 | * @attention |
| AnnaBridge | 167:e84263d55307 | 27 | * |
| AnnaBridge | 167:e84263d55307 | 28 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 167:e84263d55307 | 29 | * |
| AnnaBridge | 167:e84263d55307 | 30 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 167:e84263d55307 | 31 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 167:e84263d55307 | 32 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 167:e84263d55307 | 33 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 167:e84263d55307 | 34 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 167:e84263d55307 | 35 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 167:e84263d55307 | 36 | * and/or other materials provided with the distribution. |
| AnnaBridge | 167:e84263d55307 | 37 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 167:e84263d55307 | 38 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 167:e84263d55307 | 39 | * without specific prior written permission. |
| AnnaBridge | 167:e84263d55307 | 40 | * |
| AnnaBridge | 167:e84263d55307 | 41 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 167:e84263d55307 | 42 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 167:e84263d55307 | 43 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 167:e84263d55307 | 44 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 167:e84263d55307 | 45 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 167:e84263d55307 | 46 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 167:e84263d55307 | 47 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 167:e84263d55307 | 48 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 167:e84263d55307 | 49 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 167:e84263d55307 | 50 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 167:e84263d55307 | 51 | * |
| AnnaBridge | 167:e84263d55307 | 52 | ****************************************************************************** |
| AnnaBridge | 167:e84263d55307 | 53 | */ |
| AnnaBridge | 167:e84263d55307 | 54 | |
| AnnaBridge | 167:e84263d55307 | 55 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 56 | #ifndef __STM32F2xx_LL_BUS_H |
| AnnaBridge | 167:e84263d55307 | 57 | #define __STM32F2xx_LL_BUS_H |
| AnnaBridge | 167:e84263d55307 | 58 | |
| AnnaBridge | 167:e84263d55307 | 59 | #ifdef __cplusplus |
| AnnaBridge | 167:e84263d55307 | 60 | extern "C" { |
| AnnaBridge | 167:e84263d55307 | 61 | #endif |
| AnnaBridge | 167:e84263d55307 | 62 | |
| AnnaBridge | 167:e84263d55307 | 63 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 64 | #include "stm32f2xx.h" |
| AnnaBridge | 167:e84263d55307 | 65 | |
| AnnaBridge | 167:e84263d55307 | 66 | /** @addtogroup STM32F2xx_LL_Driver |
| AnnaBridge | 167:e84263d55307 | 67 | * @{ |
| AnnaBridge | 167:e84263d55307 | 68 | */ |
| AnnaBridge | 167:e84263d55307 | 69 | |
| AnnaBridge | 167:e84263d55307 | 70 | #if defined(RCC) |
| AnnaBridge | 167:e84263d55307 | 71 | |
| AnnaBridge | 167:e84263d55307 | 72 | /** @defgroup BUS_LL BUS |
| AnnaBridge | 167:e84263d55307 | 73 | * @{ |
| AnnaBridge | 167:e84263d55307 | 74 | */ |
| AnnaBridge | 167:e84263d55307 | 75 | |
| AnnaBridge | 167:e84263d55307 | 76 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 77 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 78 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 79 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 80 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 81 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 82 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| AnnaBridge | 167:e84263d55307 | 83 | * @{ |
| AnnaBridge | 167:e84263d55307 | 84 | */ |
| AnnaBridge | 167:e84263d55307 | 85 | |
| AnnaBridge | 167:e84263d55307 | 86 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| AnnaBridge | 167:e84263d55307 | 87 | * @{ |
| AnnaBridge | 167:e84263d55307 | 88 | */ |
| AnnaBridge | 167:e84263d55307 | 89 | #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 167:e84263d55307 | 90 | #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN |
| AnnaBridge | 167:e84263d55307 | 91 | #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN |
| AnnaBridge | 167:e84263d55307 | 92 | #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN |
| AnnaBridge | 167:e84263d55307 | 93 | #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN |
| AnnaBridge | 167:e84263d55307 | 94 | #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN |
| AnnaBridge | 167:e84263d55307 | 95 | #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN |
| AnnaBridge | 167:e84263d55307 | 96 | #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN |
| AnnaBridge | 167:e84263d55307 | 97 | #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN |
| AnnaBridge | 167:e84263d55307 | 98 | #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN |
| AnnaBridge | 167:e84263d55307 | 99 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN |
| AnnaBridge | 167:e84263d55307 | 100 | #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN |
| AnnaBridge | 167:e84263d55307 | 101 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN |
| AnnaBridge | 167:e84263d55307 | 102 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN |
| AnnaBridge | 167:e84263d55307 | 103 | #if defined(ETH) |
| AnnaBridge | 167:e84263d55307 | 104 | #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN |
| AnnaBridge | 167:e84263d55307 | 105 | #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN |
| AnnaBridge | 167:e84263d55307 | 106 | #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN |
| AnnaBridge | 167:e84263d55307 | 107 | #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN |
| AnnaBridge | 167:e84263d55307 | 108 | #endif /* ETH */ |
| AnnaBridge | 167:e84263d55307 | 109 | #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN |
| AnnaBridge | 167:e84263d55307 | 110 | #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN |
| AnnaBridge | 167:e84263d55307 | 111 | #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN |
| AnnaBridge | 167:e84263d55307 | 112 | #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN |
| AnnaBridge | 167:e84263d55307 | 113 | #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN |
| AnnaBridge | 167:e84263d55307 | 114 | /** |
| AnnaBridge | 167:e84263d55307 | 115 | * @} |
| AnnaBridge | 167:e84263d55307 | 116 | */ |
| AnnaBridge | 167:e84263d55307 | 117 | |
| AnnaBridge | 167:e84263d55307 | 118 | /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH |
| AnnaBridge | 167:e84263d55307 | 119 | * @{ |
| AnnaBridge | 167:e84263d55307 | 120 | */ |
| AnnaBridge | 167:e84263d55307 | 121 | #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 167:e84263d55307 | 122 | #if defined(DCMI) |
| AnnaBridge | 167:e84263d55307 | 123 | #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN |
| AnnaBridge | 167:e84263d55307 | 124 | #endif /* DCMI */ |
| AnnaBridge | 167:e84263d55307 | 125 | #if defined(CRYP) |
| AnnaBridge | 167:e84263d55307 | 126 | #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN |
| AnnaBridge | 167:e84263d55307 | 127 | #endif /* CRYP */ |
| AnnaBridge | 167:e84263d55307 | 128 | #if defined(HASH) |
| AnnaBridge | 167:e84263d55307 | 129 | #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN |
| AnnaBridge | 167:e84263d55307 | 130 | #endif /* HASH */ |
| AnnaBridge | 167:e84263d55307 | 131 | #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN |
| AnnaBridge | 167:e84263d55307 | 132 | #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN |
| AnnaBridge | 167:e84263d55307 | 133 | /** |
| AnnaBridge | 167:e84263d55307 | 134 | * @} |
| AnnaBridge | 167:e84263d55307 | 135 | */ |
| AnnaBridge | 167:e84263d55307 | 136 | |
| AnnaBridge | 167:e84263d55307 | 137 | /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH |
| AnnaBridge | 167:e84263d55307 | 138 | * @{ |
| AnnaBridge | 167:e84263d55307 | 139 | */ |
| AnnaBridge | 167:e84263d55307 | 140 | #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 167:e84263d55307 | 141 | #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN |
| AnnaBridge | 167:e84263d55307 | 142 | /** |
| AnnaBridge | 167:e84263d55307 | 143 | * @} |
| AnnaBridge | 167:e84263d55307 | 144 | */ |
| AnnaBridge | 167:e84263d55307 | 145 | |
| AnnaBridge | 167:e84263d55307 | 146 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| AnnaBridge | 167:e84263d55307 | 147 | * @{ |
| AnnaBridge | 167:e84263d55307 | 148 | */ |
| AnnaBridge | 167:e84263d55307 | 149 | #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 167:e84263d55307 | 150 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
| AnnaBridge | 167:e84263d55307 | 151 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
| AnnaBridge | 167:e84263d55307 | 152 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN |
| AnnaBridge | 167:e84263d55307 | 153 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN |
| AnnaBridge | 167:e84263d55307 | 154 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
| AnnaBridge | 167:e84263d55307 | 155 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
| AnnaBridge | 167:e84263d55307 | 156 | #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN |
| AnnaBridge | 167:e84263d55307 | 157 | #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN |
| AnnaBridge | 167:e84263d55307 | 158 | #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN |
| AnnaBridge | 167:e84263d55307 | 159 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
| AnnaBridge | 167:e84263d55307 | 160 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
| AnnaBridge | 167:e84263d55307 | 161 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN |
| AnnaBridge | 167:e84263d55307 | 162 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
| AnnaBridge | 167:e84263d55307 | 163 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
| AnnaBridge | 167:e84263d55307 | 164 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN |
| AnnaBridge | 167:e84263d55307 | 165 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN |
| AnnaBridge | 167:e84263d55307 | 166 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
| AnnaBridge | 167:e84263d55307 | 167 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
| AnnaBridge | 167:e84263d55307 | 168 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN |
| AnnaBridge | 167:e84263d55307 | 169 | #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN |
| AnnaBridge | 167:e84263d55307 | 170 | #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN |
| AnnaBridge | 167:e84263d55307 | 171 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
| AnnaBridge | 167:e84263d55307 | 172 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN |
| AnnaBridge | 167:e84263d55307 | 173 | /** |
| AnnaBridge | 167:e84263d55307 | 174 | * @} |
| AnnaBridge | 167:e84263d55307 | 175 | */ |
| AnnaBridge | 167:e84263d55307 | 176 | |
| AnnaBridge | 167:e84263d55307 | 177 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| AnnaBridge | 167:e84263d55307 | 178 | * @{ |
| AnnaBridge | 167:e84263d55307 | 179 | */ |
| AnnaBridge | 167:e84263d55307 | 180 | #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 167:e84263d55307 | 181 | #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
| AnnaBridge | 167:e84263d55307 | 182 | #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN |
| AnnaBridge | 167:e84263d55307 | 183 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
| AnnaBridge | 167:e84263d55307 | 184 | #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN |
| AnnaBridge | 167:e84263d55307 | 185 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
| AnnaBridge | 167:e84263d55307 | 186 | #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN |
| AnnaBridge | 167:e84263d55307 | 187 | #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN |
| AnnaBridge | 167:e84263d55307 | 188 | #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN |
| AnnaBridge | 167:e84263d55307 | 189 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
| AnnaBridge | 167:e84263d55307 | 190 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
| AnnaBridge | 167:e84263d55307 | 191 | #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN |
| AnnaBridge | 167:e84263d55307 | 192 | #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN |
| AnnaBridge | 167:e84263d55307 | 193 | #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN |
| AnnaBridge | 167:e84263d55307 | 194 | #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST |
| AnnaBridge | 167:e84263d55307 | 195 | /** |
| AnnaBridge | 167:e84263d55307 | 196 | * @} |
| AnnaBridge | 167:e84263d55307 | 197 | */ |
| AnnaBridge | 167:e84263d55307 | 198 | |
| AnnaBridge | 167:e84263d55307 | 199 | /** |
| AnnaBridge | 167:e84263d55307 | 200 | * @} |
| AnnaBridge | 167:e84263d55307 | 201 | */ |
| AnnaBridge | 167:e84263d55307 | 202 | |
| AnnaBridge | 167:e84263d55307 | 203 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 204 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 205 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| AnnaBridge | 167:e84263d55307 | 206 | * @{ |
| AnnaBridge | 167:e84263d55307 | 207 | */ |
| AnnaBridge | 167:e84263d55307 | 208 | |
| AnnaBridge | 167:e84263d55307 | 209 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| AnnaBridge | 167:e84263d55307 | 210 | * @{ |
| AnnaBridge | 167:e84263d55307 | 211 | */ |
| AnnaBridge | 167:e84263d55307 | 212 | |
| AnnaBridge | 167:e84263d55307 | 213 | /** |
| AnnaBridge | 167:e84263d55307 | 214 | * @brief Enable AHB1 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 215 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 216 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 217 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 218 | * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 219 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 220 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 221 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 222 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 223 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 224 | * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 225 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 226 | * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 227 | * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 228 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 229 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 230 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 231 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 232 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 233 | * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock |
| AnnaBridge | 167:e84263d55307 | 234 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 235 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 167:e84263d55307 | 236 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 167:e84263d55307 | 237 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 167:e84263d55307 | 238 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 167:e84263d55307 | 239 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 167:e84263d55307 | 240 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 167:e84263d55307 | 241 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 167:e84263d55307 | 242 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 167:e84263d55307 | 243 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 167:e84263d55307 | 244 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 167:e84263d55307 | 245 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 167:e84263d55307 | 246 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 167:e84263d55307 | 247 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 167:e84263d55307 | 248 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 167:e84263d55307 | 249 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 167:e84263d55307 | 250 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 167:e84263d55307 | 251 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 167:e84263d55307 | 252 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 167:e84263d55307 | 253 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 167:e84263d55307 | 254 | * |
| AnnaBridge | 167:e84263d55307 | 255 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 256 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 257 | */ |
| AnnaBridge | 167:e84263d55307 | 258 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 259 | { |
| AnnaBridge | 167:e84263d55307 | 260 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 261 | SET_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 262 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 263 | tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 264 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 265 | } |
| AnnaBridge | 167:e84263d55307 | 266 | |
| AnnaBridge | 167:e84263d55307 | 267 | /** |
| AnnaBridge | 167:e84263d55307 | 268 | * @brief Check if AHB1 peripheral clock is enabled or not |
| AnnaBridge | 167:e84263d55307 | 269 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 270 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 271 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 272 | * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 273 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 274 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 275 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 276 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 277 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 278 | * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 279 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 280 | * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 281 | * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 282 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 283 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 284 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 285 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 286 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 287 | * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock |
| AnnaBridge | 167:e84263d55307 | 288 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 289 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 167:e84263d55307 | 290 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 167:e84263d55307 | 291 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 167:e84263d55307 | 292 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 167:e84263d55307 | 293 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 167:e84263d55307 | 294 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 167:e84263d55307 | 295 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 167:e84263d55307 | 296 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 167:e84263d55307 | 297 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 167:e84263d55307 | 298 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 167:e84263d55307 | 299 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 167:e84263d55307 | 300 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 167:e84263d55307 | 301 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 167:e84263d55307 | 302 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 167:e84263d55307 | 303 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 167:e84263d55307 | 304 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 167:e84263d55307 | 305 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 167:e84263d55307 | 306 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 167:e84263d55307 | 307 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 167:e84263d55307 | 308 | * |
| AnnaBridge | 167:e84263d55307 | 309 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 310 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 167:e84263d55307 | 311 | */ |
| AnnaBridge | 167:e84263d55307 | 312 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 313 | { |
| AnnaBridge | 167:e84263d55307 | 314 | return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); |
| AnnaBridge | 167:e84263d55307 | 315 | } |
| AnnaBridge | 167:e84263d55307 | 316 | |
| AnnaBridge | 167:e84263d55307 | 317 | /** |
| AnnaBridge | 167:e84263d55307 | 318 | * @brief Disable AHB1 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 319 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 320 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 321 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 322 | * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 323 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 324 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 325 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 326 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 327 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 328 | * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 329 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 330 | * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 331 | * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 332 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 333 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 334 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 335 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 336 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 337 | * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock |
| AnnaBridge | 167:e84263d55307 | 338 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 339 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 167:e84263d55307 | 340 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 167:e84263d55307 | 341 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 167:e84263d55307 | 342 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 167:e84263d55307 | 343 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 167:e84263d55307 | 344 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 167:e84263d55307 | 345 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 167:e84263d55307 | 346 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 167:e84263d55307 | 347 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 167:e84263d55307 | 348 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 167:e84263d55307 | 349 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 167:e84263d55307 | 350 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 167:e84263d55307 | 351 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 167:e84263d55307 | 352 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 167:e84263d55307 | 353 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 167:e84263d55307 | 354 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 167:e84263d55307 | 355 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 167:e84263d55307 | 356 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 167:e84263d55307 | 357 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 167:e84263d55307 | 358 | * |
| AnnaBridge | 167:e84263d55307 | 359 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 360 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 361 | */ |
| AnnaBridge | 167:e84263d55307 | 362 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 363 | { |
| AnnaBridge | 167:e84263d55307 | 364 | CLEAR_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 365 | } |
| AnnaBridge | 167:e84263d55307 | 366 | |
| AnnaBridge | 167:e84263d55307 | 367 | /** |
| AnnaBridge | 167:e84263d55307 | 368 | * @brief Force AHB1 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 369 | * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 370 | * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 371 | * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 372 | * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 373 | * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 374 | * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 375 | * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 376 | * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 377 | * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 378 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 379 | * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 380 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 381 | * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 382 | * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset |
| AnnaBridge | 167:e84263d55307 | 383 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 384 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 385 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 167:e84263d55307 | 386 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 167:e84263d55307 | 387 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 167:e84263d55307 | 388 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 167:e84263d55307 | 389 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 167:e84263d55307 | 390 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 167:e84263d55307 | 391 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 167:e84263d55307 | 392 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 167:e84263d55307 | 393 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 167:e84263d55307 | 394 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 167:e84263d55307 | 395 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 167:e84263d55307 | 396 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 167:e84263d55307 | 397 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 167:e84263d55307 | 398 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 167:e84263d55307 | 399 | * |
| AnnaBridge | 167:e84263d55307 | 400 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 401 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 402 | */ |
| AnnaBridge | 167:e84263d55307 | 403 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 404 | { |
| AnnaBridge | 167:e84263d55307 | 405 | SET_BIT(RCC->AHB1RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 406 | } |
| AnnaBridge | 167:e84263d55307 | 407 | |
| AnnaBridge | 167:e84263d55307 | 408 | /** |
| AnnaBridge | 167:e84263d55307 | 409 | * @brief Release AHB1 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 410 | * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 411 | * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 412 | * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 413 | * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 414 | * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 415 | * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 416 | * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 417 | * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 418 | * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 419 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 420 | * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 421 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 422 | * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 423 | * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset |
| AnnaBridge | 167:e84263d55307 | 424 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 425 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 426 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 167:e84263d55307 | 427 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 167:e84263d55307 | 428 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 167:e84263d55307 | 429 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 167:e84263d55307 | 430 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 167:e84263d55307 | 431 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 167:e84263d55307 | 432 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 167:e84263d55307 | 433 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 167:e84263d55307 | 434 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 167:e84263d55307 | 435 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 167:e84263d55307 | 436 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 167:e84263d55307 | 437 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 167:e84263d55307 | 438 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 167:e84263d55307 | 439 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 167:e84263d55307 | 440 | * |
| AnnaBridge | 167:e84263d55307 | 441 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 442 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 443 | */ |
| AnnaBridge | 167:e84263d55307 | 444 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 445 | { |
| AnnaBridge | 167:e84263d55307 | 446 | CLEAR_BIT(RCC->AHB1RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 447 | } |
| AnnaBridge | 167:e84263d55307 | 448 | |
| AnnaBridge | 167:e84263d55307 | 449 | /** |
| AnnaBridge | 167:e84263d55307 | 450 | * @brief Enable AHB1 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 451 | * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 452 | * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 453 | * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 454 | * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 455 | * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 456 | * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 457 | * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 458 | * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 459 | * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 460 | * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 461 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 462 | * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 463 | * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 464 | * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 465 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 466 | * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 467 | * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 468 | * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 469 | * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 470 | * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 471 | * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 472 | * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 473 | * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 474 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 475 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 167:e84263d55307 | 476 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 167:e84263d55307 | 477 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 167:e84263d55307 | 478 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 167:e84263d55307 | 479 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 167:e84263d55307 | 480 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 167:e84263d55307 | 481 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 167:e84263d55307 | 482 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 167:e84263d55307 | 483 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 167:e84263d55307 | 484 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 167:e84263d55307 | 485 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 167:e84263d55307 | 486 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF |
| AnnaBridge | 167:e84263d55307 | 487 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| AnnaBridge | 167:e84263d55307 | 488 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 |
| AnnaBridge | 167:e84263d55307 | 489 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 167:e84263d55307 | 490 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 167:e84263d55307 | 491 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 167:e84263d55307 | 492 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 167:e84263d55307 | 493 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 167:e84263d55307 | 494 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 167:e84263d55307 | 495 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 167:e84263d55307 | 496 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 167:e84263d55307 | 497 | * |
| AnnaBridge | 167:e84263d55307 | 498 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 499 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 500 | */ |
| AnnaBridge | 167:e84263d55307 | 501 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 502 | { |
| AnnaBridge | 167:e84263d55307 | 503 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 504 | SET_BIT(RCC->AHB1LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 505 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 506 | tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 507 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 508 | } |
| AnnaBridge | 167:e84263d55307 | 509 | |
| AnnaBridge | 167:e84263d55307 | 510 | /** |
| AnnaBridge | 167:e84263d55307 | 511 | * @brief Disable AHB1 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 512 | * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 513 | * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 514 | * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 515 | * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 516 | * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 517 | * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 518 | * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 519 | * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 520 | * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 521 | * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 522 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 523 | * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 524 | * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 525 | * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 526 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 527 | * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 528 | * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 529 | * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 530 | * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 531 | * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 532 | * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 533 | * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 534 | * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 535 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 536 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 167:e84263d55307 | 537 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 167:e84263d55307 | 538 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 167:e84263d55307 | 539 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 167:e84263d55307 | 540 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 167:e84263d55307 | 541 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 167:e84263d55307 | 542 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 167:e84263d55307 | 543 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 167:e84263d55307 | 544 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 167:e84263d55307 | 545 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 167:e84263d55307 | 546 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 167:e84263d55307 | 547 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF |
| AnnaBridge | 167:e84263d55307 | 548 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| AnnaBridge | 167:e84263d55307 | 549 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 |
| AnnaBridge | 167:e84263d55307 | 550 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 167:e84263d55307 | 551 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 167:e84263d55307 | 552 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 167:e84263d55307 | 553 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 167:e84263d55307 | 554 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 167:e84263d55307 | 555 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 167:e84263d55307 | 556 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 167:e84263d55307 | 557 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 167:e84263d55307 | 558 | * |
| AnnaBridge | 167:e84263d55307 | 559 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 560 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 561 | */ |
| AnnaBridge | 167:e84263d55307 | 562 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 563 | { |
| AnnaBridge | 167:e84263d55307 | 564 | CLEAR_BIT(RCC->AHB1LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 565 | } |
| AnnaBridge | 167:e84263d55307 | 566 | |
| AnnaBridge | 167:e84263d55307 | 567 | /** |
| AnnaBridge | 167:e84263d55307 | 568 | * @} |
| AnnaBridge | 167:e84263d55307 | 569 | */ |
| AnnaBridge | 167:e84263d55307 | 570 | |
| AnnaBridge | 167:e84263d55307 | 571 | /** @defgroup BUS_LL_EF_AHB2 AHB2 |
| AnnaBridge | 167:e84263d55307 | 572 | * @{ |
| AnnaBridge | 167:e84263d55307 | 573 | */ |
| AnnaBridge | 167:e84263d55307 | 574 | |
| AnnaBridge | 167:e84263d55307 | 575 | /** |
| AnnaBridge | 167:e84263d55307 | 576 | * @brief Enable AHB2 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 577 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 578 | * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 579 | * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 580 | * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 581 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock |
| AnnaBridge | 167:e84263d55307 | 582 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 583 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 167:e84263d55307 | 584 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 167:e84263d55307 | 585 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 167:e84263d55307 | 586 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 167:e84263d55307 | 587 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 167:e84263d55307 | 588 | * |
| AnnaBridge | 167:e84263d55307 | 589 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 590 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 591 | */ |
| AnnaBridge | 167:e84263d55307 | 592 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 593 | { |
| AnnaBridge | 167:e84263d55307 | 594 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 595 | SET_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 596 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 597 | tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 598 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 599 | } |
| AnnaBridge | 167:e84263d55307 | 600 | |
| AnnaBridge | 167:e84263d55307 | 601 | /** |
| AnnaBridge | 167:e84263d55307 | 602 | * @brief Check if AHB2 peripheral clock is enabled or not |
| AnnaBridge | 167:e84263d55307 | 603 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 604 | * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 605 | * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 606 | * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 607 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock |
| AnnaBridge | 167:e84263d55307 | 608 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 609 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 167:e84263d55307 | 610 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 167:e84263d55307 | 611 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 167:e84263d55307 | 612 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 167:e84263d55307 | 613 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 167:e84263d55307 | 614 | * |
| AnnaBridge | 167:e84263d55307 | 615 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 616 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 167:e84263d55307 | 617 | */ |
| AnnaBridge | 167:e84263d55307 | 618 | __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 619 | { |
| AnnaBridge | 167:e84263d55307 | 620 | return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); |
| AnnaBridge | 167:e84263d55307 | 621 | } |
| AnnaBridge | 167:e84263d55307 | 622 | |
| AnnaBridge | 167:e84263d55307 | 623 | /** |
| AnnaBridge | 167:e84263d55307 | 624 | * @brief Disable AHB2 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 625 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 626 | * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 627 | * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 628 | * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 629 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock |
| AnnaBridge | 167:e84263d55307 | 630 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 631 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 167:e84263d55307 | 632 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 167:e84263d55307 | 633 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 167:e84263d55307 | 634 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 167:e84263d55307 | 635 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 167:e84263d55307 | 636 | * |
| AnnaBridge | 167:e84263d55307 | 637 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 638 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 639 | */ |
| AnnaBridge | 167:e84263d55307 | 640 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 641 | { |
| AnnaBridge | 167:e84263d55307 | 642 | CLEAR_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 643 | } |
| AnnaBridge | 167:e84263d55307 | 644 | |
| AnnaBridge | 167:e84263d55307 | 645 | /** |
| AnnaBridge | 167:e84263d55307 | 646 | * @brief Force AHB2 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 647 | * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 648 | * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 649 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 650 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 651 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset |
| AnnaBridge | 167:e84263d55307 | 652 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 653 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 654 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 167:e84263d55307 | 655 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 167:e84263d55307 | 656 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 167:e84263d55307 | 657 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 167:e84263d55307 | 658 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 167:e84263d55307 | 659 | * |
| AnnaBridge | 167:e84263d55307 | 660 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 661 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 662 | */ |
| AnnaBridge | 167:e84263d55307 | 663 | __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 664 | { |
| AnnaBridge | 167:e84263d55307 | 665 | SET_BIT(RCC->AHB2RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 666 | } |
| AnnaBridge | 167:e84263d55307 | 667 | |
| AnnaBridge | 167:e84263d55307 | 668 | /** |
| AnnaBridge | 167:e84263d55307 | 669 | * @brief Release AHB2 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 670 | * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 671 | * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 672 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 673 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 674 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset |
| AnnaBridge | 167:e84263d55307 | 675 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 676 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 677 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 167:e84263d55307 | 678 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 167:e84263d55307 | 679 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 167:e84263d55307 | 680 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 167:e84263d55307 | 681 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 167:e84263d55307 | 682 | * |
| AnnaBridge | 167:e84263d55307 | 683 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 684 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 685 | */ |
| AnnaBridge | 167:e84263d55307 | 686 | __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 687 | { |
| AnnaBridge | 167:e84263d55307 | 688 | CLEAR_BIT(RCC->AHB2RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 689 | } |
| AnnaBridge | 167:e84263d55307 | 690 | |
| AnnaBridge | 167:e84263d55307 | 691 | /** |
| AnnaBridge | 167:e84263d55307 | 692 | * @brief Enable AHB2 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 693 | * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 694 | * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 695 | * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 696 | * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 697 | * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 698 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 699 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 167:e84263d55307 | 700 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 167:e84263d55307 | 701 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 167:e84263d55307 | 702 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 167:e84263d55307 | 703 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 167:e84263d55307 | 704 | * |
| AnnaBridge | 167:e84263d55307 | 705 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 706 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 707 | */ |
| AnnaBridge | 167:e84263d55307 | 708 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 709 | { |
| AnnaBridge | 167:e84263d55307 | 710 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 711 | SET_BIT(RCC->AHB2LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 712 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 713 | tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 714 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 715 | } |
| AnnaBridge | 167:e84263d55307 | 716 | |
| AnnaBridge | 167:e84263d55307 | 717 | /** |
| AnnaBridge | 167:e84263d55307 | 718 | * @brief Disable AHB2 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 719 | * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 720 | * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 721 | * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 722 | * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 723 | * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 724 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 725 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 167:e84263d55307 | 726 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 167:e84263d55307 | 727 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 167:e84263d55307 | 728 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 167:e84263d55307 | 729 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 167:e84263d55307 | 730 | * |
| AnnaBridge | 167:e84263d55307 | 731 | * (*) value not defined in all devices. |
| AnnaBridge | 167:e84263d55307 | 732 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 733 | */ |
| AnnaBridge | 167:e84263d55307 | 734 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 735 | { |
| AnnaBridge | 167:e84263d55307 | 736 | CLEAR_BIT(RCC->AHB2LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 737 | } |
| AnnaBridge | 167:e84263d55307 | 738 | |
| AnnaBridge | 167:e84263d55307 | 739 | /** |
| AnnaBridge | 167:e84263d55307 | 740 | * @} |
| AnnaBridge | 167:e84263d55307 | 741 | */ |
| AnnaBridge | 167:e84263d55307 | 742 | |
| AnnaBridge | 167:e84263d55307 | 743 | /** @defgroup BUS_LL_EF_AHB3 AHB3 |
| AnnaBridge | 167:e84263d55307 | 744 | * @{ |
| AnnaBridge | 167:e84263d55307 | 745 | */ |
| AnnaBridge | 167:e84263d55307 | 746 | |
| AnnaBridge | 167:e84263d55307 | 747 | /** |
| AnnaBridge | 167:e84263d55307 | 748 | * @brief Enable AHB3 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 749 | * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock |
| AnnaBridge | 167:e84263d55307 | 750 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 751 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC |
| AnnaBridge | 167:e84263d55307 | 752 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 753 | */ |
| AnnaBridge | 167:e84263d55307 | 754 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 755 | { |
| AnnaBridge | 167:e84263d55307 | 756 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 757 | SET_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 758 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 759 | tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 760 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 761 | } |
| AnnaBridge | 167:e84263d55307 | 762 | |
| AnnaBridge | 167:e84263d55307 | 763 | /** |
| AnnaBridge | 167:e84263d55307 | 764 | * @brief Check if AHB3 peripheral clock is enabled or not |
| AnnaBridge | 167:e84263d55307 | 765 | * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock |
| AnnaBridge | 167:e84263d55307 | 766 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 767 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC |
| AnnaBridge | 167:e84263d55307 | 768 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 167:e84263d55307 | 769 | */ |
| AnnaBridge | 167:e84263d55307 | 770 | __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 771 | { |
| AnnaBridge | 167:e84263d55307 | 772 | return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); |
| AnnaBridge | 167:e84263d55307 | 773 | } |
| AnnaBridge | 167:e84263d55307 | 774 | |
| AnnaBridge | 167:e84263d55307 | 775 | /** |
| AnnaBridge | 167:e84263d55307 | 776 | * @brief Disable AHB3 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 777 | * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock |
| AnnaBridge | 167:e84263d55307 | 778 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 779 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC |
| AnnaBridge | 167:e84263d55307 | 780 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 781 | */ |
| AnnaBridge | 167:e84263d55307 | 782 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 783 | { |
| AnnaBridge | 167:e84263d55307 | 784 | CLEAR_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 785 | } |
| AnnaBridge | 167:e84263d55307 | 786 | |
| AnnaBridge | 167:e84263d55307 | 787 | /** |
| AnnaBridge | 167:e84263d55307 | 788 | * @brief Force AHB3 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 789 | * @rmtoll AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset |
| AnnaBridge | 167:e84263d55307 | 790 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 791 | * @arg @ref LL_AHB3_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 792 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC |
| AnnaBridge | 167:e84263d55307 | 793 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 794 | */ |
| AnnaBridge | 167:e84263d55307 | 795 | __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 796 | { |
| AnnaBridge | 167:e84263d55307 | 797 | SET_BIT(RCC->AHB3RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 798 | } |
| AnnaBridge | 167:e84263d55307 | 799 | |
| AnnaBridge | 167:e84263d55307 | 800 | /** |
| AnnaBridge | 167:e84263d55307 | 801 | * @brief Release AHB3 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 802 | * @rmtoll AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset |
| AnnaBridge | 167:e84263d55307 | 803 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 804 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 805 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC |
| AnnaBridge | 167:e84263d55307 | 806 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 807 | */ |
| AnnaBridge | 167:e84263d55307 | 808 | __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 809 | { |
| AnnaBridge | 167:e84263d55307 | 810 | CLEAR_BIT(RCC->AHB3RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 811 | } |
| AnnaBridge | 167:e84263d55307 | 812 | |
| AnnaBridge | 167:e84263d55307 | 813 | /** |
| AnnaBridge | 167:e84263d55307 | 814 | * @brief Enable AHB3 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 815 | * @rmtoll AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 816 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 817 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC |
| AnnaBridge | 167:e84263d55307 | 818 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 819 | */ |
| AnnaBridge | 167:e84263d55307 | 820 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 821 | { |
| AnnaBridge | 167:e84263d55307 | 822 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 823 | SET_BIT(RCC->AHB3LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 824 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 825 | tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 826 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 827 | } |
| AnnaBridge | 167:e84263d55307 | 828 | |
| AnnaBridge | 167:e84263d55307 | 829 | /** |
| AnnaBridge | 167:e84263d55307 | 830 | * @brief Disable AHB3 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 831 | * @rmtoll AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 832 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 833 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC |
| AnnaBridge | 167:e84263d55307 | 834 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 835 | */ |
| AnnaBridge | 167:e84263d55307 | 836 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 837 | { |
| AnnaBridge | 167:e84263d55307 | 838 | CLEAR_BIT(RCC->AHB3LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 839 | } |
| AnnaBridge | 167:e84263d55307 | 840 | |
| AnnaBridge | 167:e84263d55307 | 841 | /** |
| AnnaBridge | 167:e84263d55307 | 842 | * @} |
| AnnaBridge | 167:e84263d55307 | 843 | */ |
| AnnaBridge | 167:e84263d55307 | 844 | |
| AnnaBridge | 167:e84263d55307 | 845 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| AnnaBridge | 167:e84263d55307 | 846 | * @{ |
| AnnaBridge | 167:e84263d55307 | 847 | */ |
| AnnaBridge | 167:e84263d55307 | 848 | |
| AnnaBridge | 167:e84263d55307 | 849 | /** |
| AnnaBridge | 167:e84263d55307 | 850 | * @brief Enable APB1 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 851 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 852 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 853 | * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 854 | * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 855 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 856 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 857 | * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 858 | * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 859 | * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 860 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 861 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 862 | * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 863 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 864 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 865 | * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 866 | * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 867 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 868 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 869 | * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 870 | * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 871 | * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 872 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 873 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock |
| AnnaBridge | 167:e84263d55307 | 874 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 875 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 167:e84263d55307 | 876 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 167:e84263d55307 | 877 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 167:e84263d55307 | 878 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 167:e84263d55307 | 879 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 167:e84263d55307 | 880 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 167:e84263d55307 | 881 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 167:e84263d55307 | 882 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 167:e84263d55307 | 883 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 167:e84263d55307 | 884 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 167:e84263d55307 | 885 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 167:e84263d55307 | 886 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 167:e84263d55307 | 887 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 167:e84263d55307 | 888 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 167:e84263d55307 | 889 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 167:e84263d55307 | 890 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 167:e84263d55307 | 891 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 167:e84263d55307 | 892 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 167:e84263d55307 | 893 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 167:e84263d55307 | 894 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 167:e84263d55307 | 895 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 |
| AnnaBridge | 167:e84263d55307 | 896 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 167:e84263d55307 | 897 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 167:e84263d55307 | 898 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 899 | */ |
| AnnaBridge | 167:e84263d55307 | 900 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 901 | { |
| AnnaBridge | 167:e84263d55307 | 902 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 903 | SET_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 904 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 905 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 906 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 907 | } |
| AnnaBridge | 167:e84263d55307 | 908 | |
| AnnaBridge | 167:e84263d55307 | 909 | /** |
| AnnaBridge | 167:e84263d55307 | 910 | * @brief Check if APB1 peripheral clock is enabled or not |
| AnnaBridge | 167:e84263d55307 | 911 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 912 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 913 | * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 914 | * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 915 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 916 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 917 | * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 918 | * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 919 | * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 920 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 921 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 922 | * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 923 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 924 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 925 | * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 926 | * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 927 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 928 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 929 | * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 930 | * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 931 | * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 932 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 933 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock |
| AnnaBridge | 167:e84263d55307 | 934 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 935 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 167:e84263d55307 | 936 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 167:e84263d55307 | 937 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 167:e84263d55307 | 938 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 167:e84263d55307 | 939 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 167:e84263d55307 | 940 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 167:e84263d55307 | 941 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 167:e84263d55307 | 942 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 167:e84263d55307 | 943 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 167:e84263d55307 | 944 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 167:e84263d55307 | 945 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 167:e84263d55307 | 946 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 167:e84263d55307 | 947 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 167:e84263d55307 | 948 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 167:e84263d55307 | 949 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 167:e84263d55307 | 950 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 167:e84263d55307 | 951 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 167:e84263d55307 | 952 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 167:e84263d55307 | 953 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 167:e84263d55307 | 954 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 167:e84263d55307 | 955 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 |
| AnnaBridge | 167:e84263d55307 | 956 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 167:e84263d55307 | 957 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 167:e84263d55307 | 958 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 167:e84263d55307 | 959 | */ |
| AnnaBridge | 167:e84263d55307 | 960 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 961 | { |
| AnnaBridge | 167:e84263d55307 | 962 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| AnnaBridge | 167:e84263d55307 | 963 | } |
| AnnaBridge | 167:e84263d55307 | 964 | |
| AnnaBridge | 167:e84263d55307 | 965 | /** |
| AnnaBridge | 167:e84263d55307 | 966 | * @brief Disable APB1 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 967 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 968 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 969 | * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 970 | * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 971 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 972 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 973 | * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 974 | * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 975 | * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 976 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 977 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 978 | * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 979 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 980 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 981 | * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 982 | * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 983 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 984 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 985 | * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 986 | * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 987 | * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 988 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 989 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock |
| AnnaBridge | 167:e84263d55307 | 990 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 991 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 167:e84263d55307 | 992 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 167:e84263d55307 | 993 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 167:e84263d55307 | 994 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 167:e84263d55307 | 995 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 167:e84263d55307 | 996 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 167:e84263d55307 | 997 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 167:e84263d55307 | 998 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 167:e84263d55307 | 999 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 167:e84263d55307 | 1000 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 167:e84263d55307 | 1001 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 167:e84263d55307 | 1002 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 167:e84263d55307 | 1003 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 167:e84263d55307 | 1004 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 167:e84263d55307 | 1005 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 167:e84263d55307 | 1006 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 167:e84263d55307 | 1007 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 167:e84263d55307 | 1008 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 167:e84263d55307 | 1009 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 167:e84263d55307 | 1010 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 167:e84263d55307 | 1011 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 |
| AnnaBridge | 167:e84263d55307 | 1012 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 167:e84263d55307 | 1013 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 167:e84263d55307 | 1014 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1015 | */ |
| AnnaBridge | 167:e84263d55307 | 1016 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1017 | { |
| AnnaBridge | 167:e84263d55307 | 1018 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1019 | } |
| AnnaBridge | 167:e84263d55307 | 1020 | |
| AnnaBridge | 167:e84263d55307 | 1021 | /** |
| AnnaBridge | 167:e84263d55307 | 1022 | * @brief Force APB1 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 1023 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1024 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1025 | * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1026 | * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1027 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1028 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1029 | * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1030 | * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1031 | * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1032 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1033 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1034 | * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1035 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1036 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1037 | * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1038 | * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1039 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1040 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1041 | * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1042 | * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1043 | * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1044 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1045 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset |
| AnnaBridge | 167:e84263d55307 | 1046 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1047 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 1048 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 167:e84263d55307 | 1049 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 167:e84263d55307 | 1050 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 167:e84263d55307 | 1051 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 167:e84263d55307 | 1052 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 167:e84263d55307 | 1053 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 167:e84263d55307 | 1054 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 167:e84263d55307 | 1055 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 167:e84263d55307 | 1056 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 167:e84263d55307 | 1057 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 167:e84263d55307 | 1058 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 167:e84263d55307 | 1059 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 167:e84263d55307 | 1060 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 167:e84263d55307 | 1061 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 167:e84263d55307 | 1062 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 167:e84263d55307 | 1063 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 167:e84263d55307 | 1064 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 167:e84263d55307 | 1065 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 167:e84263d55307 | 1066 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 167:e84263d55307 | 1067 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 167:e84263d55307 | 1068 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 |
| AnnaBridge | 167:e84263d55307 | 1069 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 167:e84263d55307 | 1070 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 167:e84263d55307 | 1071 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1072 | */ |
| AnnaBridge | 167:e84263d55307 | 1073 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1074 | { |
| AnnaBridge | 167:e84263d55307 | 1075 | SET_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1076 | } |
| AnnaBridge | 167:e84263d55307 | 1077 | |
| AnnaBridge | 167:e84263d55307 | 1078 | /** |
| AnnaBridge | 167:e84263d55307 | 1079 | * @brief Release APB1 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 1080 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1081 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1082 | * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1083 | * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1084 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1085 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1086 | * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1087 | * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1088 | * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1089 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1090 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1091 | * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1092 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1093 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1094 | * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1095 | * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1096 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1097 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1098 | * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1099 | * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1100 | * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1101 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1102 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset |
| AnnaBridge | 167:e84263d55307 | 1103 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1104 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 1105 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 167:e84263d55307 | 1106 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 167:e84263d55307 | 1107 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 167:e84263d55307 | 1108 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 167:e84263d55307 | 1109 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 167:e84263d55307 | 1110 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 167:e84263d55307 | 1111 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 167:e84263d55307 | 1112 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 167:e84263d55307 | 1113 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 167:e84263d55307 | 1114 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 167:e84263d55307 | 1115 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 167:e84263d55307 | 1116 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 167:e84263d55307 | 1117 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 167:e84263d55307 | 1118 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 167:e84263d55307 | 1119 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 167:e84263d55307 | 1120 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 167:e84263d55307 | 1121 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 167:e84263d55307 | 1122 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 167:e84263d55307 | 1123 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 167:e84263d55307 | 1124 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 167:e84263d55307 | 1125 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 |
| AnnaBridge | 167:e84263d55307 | 1126 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 167:e84263d55307 | 1127 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 167:e84263d55307 | 1128 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1129 | */ |
| AnnaBridge | 167:e84263d55307 | 1130 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1131 | { |
| AnnaBridge | 167:e84263d55307 | 1132 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1133 | } |
| AnnaBridge | 167:e84263d55307 | 1134 | |
| AnnaBridge | 167:e84263d55307 | 1135 | /** |
| AnnaBridge | 167:e84263d55307 | 1136 | * @brief Enable APB1 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 1137 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1138 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1139 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1140 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1141 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1142 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1143 | * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1144 | * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1145 | * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1146 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1147 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1148 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1149 | * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1150 | * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1151 | * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1152 | * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1153 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1154 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1155 | * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1156 | * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1157 | * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1158 | * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1159 | * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 1160 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1161 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 167:e84263d55307 | 1162 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 167:e84263d55307 | 1163 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 167:e84263d55307 | 1164 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 167:e84263d55307 | 1165 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 167:e84263d55307 | 1166 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 167:e84263d55307 | 1167 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 167:e84263d55307 | 1168 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 167:e84263d55307 | 1169 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 167:e84263d55307 | 1170 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 167:e84263d55307 | 1171 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 167:e84263d55307 | 1172 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 167:e84263d55307 | 1173 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 167:e84263d55307 | 1174 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 167:e84263d55307 | 1175 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 167:e84263d55307 | 1176 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 167:e84263d55307 | 1177 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 167:e84263d55307 | 1178 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 167:e84263d55307 | 1179 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 167:e84263d55307 | 1180 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 167:e84263d55307 | 1181 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 |
| AnnaBridge | 167:e84263d55307 | 1182 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 167:e84263d55307 | 1183 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 167:e84263d55307 | 1184 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1185 | */ |
| AnnaBridge | 167:e84263d55307 | 1186 | __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1187 | { |
| AnnaBridge | 167:e84263d55307 | 1188 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 1189 | SET_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1190 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 1191 | tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1192 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 1193 | } |
| AnnaBridge | 167:e84263d55307 | 1194 | |
| AnnaBridge | 167:e84263d55307 | 1195 | /** |
| AnnaBridge | 167:e84263d55307 | 1196 | * @brief Disable APB1 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 1197 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1198 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1199 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1200 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1201 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1202 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1203 | * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1204 | * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1205 | * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1206 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1207 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1208 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1209 | * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1210 | * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1211 | * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1212 | * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1213 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1214 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1215 | * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1216 | * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1217 | * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1218 | * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1219 | * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 1220 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1221 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 167:e84263d55307 | 1222 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 167:e84263d55307 | 1223 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 167:e84263d55307 | 1224 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 167:e84263d55307 | 1225 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 167:e84263d55307 | 1226 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 167:e84263d55307 | 1227 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 167:e84263d55307 | 1228 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 167:e84263d55307 | 1229 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 167:e84263d55307 | 1230 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 167:e84263d55307 | 1231 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 167:e84263d55307 | 1232 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 167:e84263d55307 | 1233 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 167:e84263d55307 | 1234 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 167:e84263d55307 | 1235 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 167:e84263d55307 | 1236 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 167:e84263d55307 | 1237 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 167:e84263d55307 | 1238 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 167:e84263d55307 | 1239 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 167:e84263d55307 | 1240 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 167:e84263d55307 | 1241 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 |
| AnnaBridge | 167:e84263d55307 | 1242 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 167:e84263d55307 | 1243 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 167:e84263d55307 | 1244 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1245 | */ |
| AnnaBridge | 167:e84263d55307 | 1246 | __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1247 | { |
| AnnaBridge | 167:e84263d55307 | 1248 | CLEAR_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1249 | } |
| AnnaBridge | 167:e84263d55307 | 1250 | |
| AnnaBridge | 167:e84263d55307 | 1251 | /** |
| AnnaBridge | 167:e84263d55307 | 1252 | * @} |
| AnnaBridge | 167:e84263d55307 | 1253 | */ |
| AnnaBridge | 167:e84263d55307 | 1254 | |
| AnnaBridge | 167:e84263d55307 | 1255 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| AnnaBridge | 167:e84263d55307 | 1256 | * @{ |
| AnnaBridge | 167:e84263d55307 | 1257 | */ |
| AnnaBridge | 167:e84263d55307 | 1258 | |
| AnnaBridge | 167:e84263d55307 | 1259 | /** |
| AnnaBridge | 167:e84263d55307 | 1260 | * @brief Enable APB2 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 1261 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1262 | * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1263 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1264 | * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1265 | * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1266 | * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1267 | * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1268 | * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1269 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1270 | * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1271 | * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1272 | * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 167:e84263d55307 | 1273 | * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock |
| AnnaBridge | 167:e84263d55307 | 1274 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1275 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1276 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 167:e84263d55307 | 1277 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 167:e84263d55307 | 1278 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 167:e84263d55307 | 1279 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 167:e84263d55307 | 1280 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 167:e84263d55307 | 1281 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 167:e84263d55307 | 1282 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO |
| AnnaBridge | 167:e84263d55307 | 1283 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 167:e84263d55307 | 1284 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 167:e84263d55307 | 1285 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 167:e84263d55307 | 1286 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 167:e84263d55307 | 1287 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 167:e84263d55307 | 1288 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1289 | */ |
| AnnaBridge | 167:e84263d55307 | 1290 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1291 | { |
| AnnaBridge | 167:e84263d55307 | 1292 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 1293 | SET_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1294 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 1295 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1296 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 1297 | } |
| AnnaBridge | 167:e84263d55307 | 1298 | |
| AnnaBridge | 167:e84263d55307 | 1299 | /** |
| AnnaBridge | 167:e84263d55307 | 1300 | * @brief Check if APB2 peripheral clock is enabled or not |
| AnnaBridge | 167:e84263d55307 | 1301 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1302 | * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1303 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1304 | * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1305 | * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1306 | * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1307 | * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1308 | * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1309 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1310 | * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1311 | * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1312 | * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 167:e84263d55307 | 1313 | * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock |
| AnnaBridge | 167:e84263d55307 | 1314 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1315 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1316 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 167:e84263d55307 | 1317 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 167:e84263d55307 | 1318 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 167:e84263d55307 | 1319 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 167:e84263d55307 | 1320 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 167:e84263d55307 | 1321 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 167:e84263d55307 | 1322 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO |
| AnnaBridge | 167:e84263d55307 | 1323 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 167:e84263d55307 | 1324 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 167:e84263d55307 | 1325 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 167:e84263d55307 | 1326 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 167:e84263d55307 | 1327 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 167:e84263d55307 | 1328 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 167:e84263d55307 | 1329 | */ |
| AnnaBridge | 167:e84263d55307 | 1330 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1331 | { |
| AnnaBridge | 167:e84263d55307 | 1332 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| AnnaBridge | 167:e84263d55307 | 1333 | } |
| AnnaBridge | 167:e84263d55307 | 1334 | |
| AnnaBridge | 167:e84263d55307 | 1335 | /** |
| AnnaBridge | 167:e84263d55307 | 1336 | * @brief Disable APB2 peripherals clock. |
| AnnaBridge | 167:e84263d55307 | 1337 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1338 | * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1339 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1340 | * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1341 | * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1342 | * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1343 | * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1344 | * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1345 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1346 | * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1347 | * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1348 | * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 167:e84263d55307 | 1349 | * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock |
| AnnaBridge | 167:e84263d55307 | 1350 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1351 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1352 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 167:e84263d55307 | 1353 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 167:e84263d55307 | 1354 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 167:e84263d55307 | 1355 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 167:e84263d55307 | 1356 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 167:e84263d55307 | 1357 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 167:e84263d55307 | 1358 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO |
| AnnaBridge | 167:e84263d55307 | 1359 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 167:e84263d55307 | 1360 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 167:e84263d55307 | 1361 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 167:e84263d55307 | 1362 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 167:e84263d55307 | 1363 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 167:e84263d55307 | 1364 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1365 | */ |
| AnnaBridge | 167:e84263d55307 | 1366 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1367 | { |
| AnnaBridge | 167:e84263d55307 | 1368 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1369 | } |
| AnnaBridge | 167:e84263d55307 | 1370 | |
| AnnaBridge | 167:e84263d55307 | 1371 | /** |
| AnnaBridge | 167:e84263d55307 | 1372 | * @brief Force APB2 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 1373 | * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1374 | * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1375 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1376 | * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1377 | * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1378 | * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1379 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1380 | * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1381 | * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1382 | * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 167:e84263d55307 | 1383 | * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset |
| AnnaBridge | 167:e84263d55307 | 1384 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1385 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 1386 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1387 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 167:e84263d55307 | 1388 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 167:e84263d55307 | 1389 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 167:e84263d55307 | 1390 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC |
| AnnaBridge | 167:e84263d55307 | 1391 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO |
| AnnaBridge | 167:e84263d55307 | 1392 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 167:e84263d55307 | 1393 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 167:e84263d55307 | 1394 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 167:e84263d55307 | 1395 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 167:e84263d55307 | 1396 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 167:e84263d55307 | 1397 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1398 | */ |
| AnnaBridge | 167:e84263d55307 | 1399 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1400 | { |
| AnnaBridge | 167:e84263d55307 | 1401 | SET_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1402 | } |
| AnnaBridge | 167:e84263d55307 | 1403 | |
| AnnaBridge | 167:e84263d55307 | 1404 | /** |
| AnnaBridge | 167:e84263d55307 | 1405 | * @brief Release APB2 peripherals reset. |
| AnnaBridge | 167:e84263d55307 | 1406 | * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1407 | * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1408 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1409 | * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1410 | * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1411 | * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1412 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1413 | * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1414 | * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1415 | * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 167:e84263d55307 | 1416 | * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset |
| AnnaBridge | 167:e84263d55307 | 1417 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1418 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 167:e84263d55307 | 1419 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1420 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 167:e84263d55307 | 1421 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 167:e84263d55307 | 1422 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 167:e84263d55307 | 1423 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC |
| AnnaBridge | 167:e84263d55307 | 1424 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO |
| AnnaBridge | 167:e84263d55307 | 1425 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 167:e84263d55307 | 1426 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 167:e84263d55307 | 1427 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 167:e84263d55307 | 1428 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 167:e84263d55307 | 1429 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 167:e84263d55307 | 1430 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1431 | */ |
| AnnaBridge | 167:e84263d55307 | 1432 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1433 | { |
| AnnaBridge | 167:e84263d55307 | 1434 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1435 | } |
| AnnaBridge | 167:e84263d55307 | 1436 | |
| AnnaBridge | 167:e84263d55307 | 1437 | /** |
| AnnaBridge | 167:e84263d55307 | 1438 | * @brief Enable APB2 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 1439 | * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1440 | * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1441 | * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1442 | * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1443 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1444 | * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1445 | * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1446 | * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1447 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1448 | * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1449 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1450 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1451 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 1452 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1453 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1454 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1455 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 167:e84263d55307 | 1456 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 167:e84263d55307 | 1457 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 167:e84263d55307 | 1458 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 167:e84263d55307 | 1459 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 167:e84263d55307 | 1460 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 167:e84263d55307 | 1461 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO |
| AnnaBridge | 167:e84263d55307 | 1462 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 167:e84263d55307 | 1463 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 167:e84263d55307 | 1464 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 167:e84263d55307 | 1465 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 167:e84263d55307 | 1466 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 167:e84263d55307 | 1467 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1468 | */ |
| AnnaBridge | 167:e84263d55307 | 1469 | __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1470 | { |
| AnnaBridge | 167:e84263d55307 | 1471 | __IO uint32_t tmpreg; |
| AnnaBridge | 167:e84263d55307 | 1472 | SET_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1473 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 167:e84263d55307 | 1474 | tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1475 | (void)tmpreg; |
| AnnaBridge | 167:e84263d55307 | 1476 | } |
| AnnaBridge | 167:e84263d55307 | 1477 | |
| AnnaBridge | 167:e84263d55307 | 1478 | /** |
| AnnaBridge | 167:e84263d55307 | 1479 | * @brief Disable APB2 peripheral clocks in low-power mode |
| AnnaBridge | 167:e84263d55307 | 1480 | * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1481 | * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1482 | * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1483 | * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1484 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1485 | * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1486 | * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1487 | * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1488 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1489 | * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1490 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1491 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 167:e84263d55307 | 1492 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower |
| AnnaBridge | 167:e84263d55307 | 1493 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 167:e84263d55307 | 1494 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 167:e84263d55307 | 1495 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 167:e84263d55307 | 1496 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 167:e84263d55307 | 1497 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 167:e84263d55307 | 1498 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 167:e84263d55307 | 1499 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 167:e84263d55307 | 1500 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 167:e84263d55307 | 1501 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO |
| AnnaBridge | 167:e84263d55307 | 1502 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 167:e84263d55307 | 1503 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 167:e84263d55307 | 1504 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 167:e84263d55307 | 1505 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 167:e84263d55307 | 1506 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 167:e84263d55307 | 1507 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 1508 | */ |
| AnnaBridge | 167:e84263d55307 | 1509 | __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 167:e84263d55307 | 1510 | { |
| AnnaBridge | 167:e84263d55307 | 1511 | CLEAR_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 167:e84263d55307 | 1512 | } |
| AnnaBridge | 167:e84263d55307 | 1513 | |
| AnnaBridge | 167:e84263d55307 | 1514 | /** |
| AnnaBridge | 167:e84263d55307 | 1515 | * @} |
| AnnaBridge | 167:e84263d55307 | 1516 | */ |
| AnnaBridge | 167:e84263d55307 | 1517 | |
| AnnaBridge | 167:e84263d55307 | 1518 | /** |
| AnnaBridge | 167:e84263d55307 | 1519 | * @} |
| AnnaBridge | 167:e84263d55307 | 1520 | */ |
| AnnaBridge | 167:e84263d55307 | 1521 | |
| AnnaBridge | 167:e84263d55307 | 1522 | /** |
| AnnaBridge | 167:e84263d55307 | 1523 | * @} |
| AnnaBridge | 167:e84263d55307 | 1524 | */ |
| AnnaBridge | 167:e84263d55307 | 1525 | |
| AnnaBridge | 167:e84263d55307 | 1526 | #endif /* defined(RCC) */ |
| AnnaBridge | 167:e84263d55307 | 1527 | |
| AnnaBridge | 167:e84263d55307 | 1528 | /** |
| AnnaBridge | 167:e84263d55307 | 1529 | * @} |
| AnnaBridge | 167:e84263d55307 | 1530 | */ |
| AnnaBridge | 167:e84263d55307 | 1531 | |
| AnnaBridge | 167:e84263d55307 | 1532 | #ifdef __cplusplus |
| AnnaBridge | 167:e84263d55307 | 1533 | } |
| AnnaBridge | 167:e84263d55307 | 1534 | #endif |
| AnnaBridge | 167:e84263d55307 | 1535 | |
| AnnaBridge | 167:e84263d55307 | 1536 | #endif /* __STM32F2xx_LL_BUS_H */ |
| AnnaBridge | 167:e84263d55307 | 1537 | |
| AnnaBridge | 167:e84263d55307 | 1538 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
