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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_usart.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_usart.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief USART HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	13	@verbatim
<>	144:ef7eb2e8f9f7	14	==============================================================================
<>	144:ef7eb2e8f9f7	15	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	[..]
<>	144:ef7eb2e8f9f7	18	The USART HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	19
<>	144:ef7eb2e8f9f7	20	(#) Declare a USART_HandleTypeDef handle structure.
<>	144:ef7eb2e8f9f7	21	(#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
<>	144:ef7eb2e8f9f7	22	(##) Enable the USARTx interface clock.
<>	144:ef7eb2e8f9f7	23	(##) USART pins configuration:
<>	144:ef7eb2e8f9f7	24	(+++) Enable the clock for the USART GPIOs.
<>	144:ef7eb2e8f9f7	25	(+++) Configure these USART pins as alternate function pull-up.
<>	144:ef7eb2e8f9f7	26	(##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
<>	144:ef7eb2e8f9f7	27	HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
<>	144:ef7eb2e8f9f7	28	(+++) Configure the USARTx interrupt priority.
<>	144:ef7eb2e8f9f7	29	(+++) Enable the NVIC USART IRQ handle.
<>	144:ef7eb2e8f9f7	30	(##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	31	HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
<>	144:ef7eb2e8f9f7	32	(+++) Declare a DMA handle structure for the Tx/Rx stream.
<>	144:ef7eb2e8f9f7	33	(+++) Enable the DMAx interface clock.
<>	144:ef7eb2e8f9f7	34	(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<>	144:ef7eb2e8f9f7	35	(+++) Configure the DMA Tx/Rx Stream.
<>	144:ef7eb2e8f9f7	36	(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
<>	144:ef7eb2e8f9f7	37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
<>	144:ef7eb2e8f9f7	40	flow control and Mode(Receiver/Transmitter) in the husart Init structure.
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	(#) Initialize the USART registers by calling the HAL_USART_Init() API:
<>	144:ef7eb2e8f9f7	43	(++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<>	144:ef7eb2e8f9f7	44	by calling the customized HAL_USART_MspInit(&husart) API.
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	-@@- The specific USART interrupts (Transmission complete interrupt,
<>	144:ef7eb2e8f9f7	47	RXNE interrupt and Error Interrupts) will be managed using the macros
<>	144:ef7eb2e8f9f7	48	__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(#) Three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	53	=================================
<>	144:ef7eb2e8f9f7	54	[..]
<>	144:ef7eb2e8f9f7	55	(+) Send an amount of data in blocking mode using HAL_USART_Transmit()
<>	144:ef7eb2e8f9f7	56	(+) Receive an amount of data in blocking mode using HAL_USART_Receive()
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	59	===================================
<>	144:ef7eb2e8f9f7	60	[..]
<>	144:ef7eb2e8f9f7	61	(+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
<>	144:ef7eb2e8f9f7	62	(+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	63	add his own code by customization of function pointer HAL_USART_TxCpltCallback
<>	144:ef7eb2e8f9f7	64	(+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
<>	144:ef7eb2e8f9f7	65	(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	66	add his own code by customization of function pointer HAL_USART_RxCpltCallback
<>	144:ef7eb2e8f9f7	67	(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	68	add his own code by customization of function pointer HAL_USART_ErrorCallback
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	71	==============================
<>	144:ef7eb2e8f9f7	72	[..]
<>	144:ef7eb2e8f9f7	73	(+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	74	(+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	75	add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
<>	144:ef7eb2e8f9f7	76	(+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	77	add his own code by customization of function pointer HAL_USART_TxCpltCallback
<>	144:ef7eb2e8f9f7	78	(+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
<>	144:ef7eb2e8f9f7	79	(+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	80	add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
<>	144:ef7eb2e8f9f7	81	(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	82	add his own code by customization of function pointer HAL_USART_RxCpltCallback
<>	144:ef7eb2e8f9f7	83	(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	84	add his own code by customization of function pointer HAL_USART_ErrorCallback
<>	144:ef7eb2e8f9f7	85	(+) Pause the DMA Transfer using HAL_USART_DMAPause()
<>	144:ef7eb2e8f9f7	86	(+) Resume the DMA Transfer using HAL_USART_DMAResume()
<>	144:ef7eb2e8f9f7	87	(+) Stop the DMA Transfer using HAL_USART_DMAStop()
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	* USART HAL driver macros list *
<>	144:ef7eb2e8f9f7	90	=============================================
<>	144:ef7eb2e8f9f7	91	[..]
<>	144:ef7eb2e8f9f7	92	Below the list of most used macros in USART HAL driver.
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	(+) __HAL_USART_ENABLE: Enable the USART peripheral
<>	144:ef7eb2e8f9f7	95	(+) __HAL_USART_DISABLE: Disable the USART peripheral
<>	144:ef7eb2e8f9f7	96	(+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
<>	144:ef7eb2e8f9f7	97	(+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
<>	144:ef7eb2e8f9f7	98	(+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
<>	144:ef7eb2e8f9f7	99	(+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101	[..]
<>	144:ef7eb2e8f9f7	102	(@) You can refer to the USART HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	@endverbatim
<>	144:ef7eb2e8f9f7	105	******************************************************************************
<>	144:ef7eb2e8f9f7	106	* @attention
<>	144:ef7eb2e8f9f7	107	*
AnnaBridge	167:e84263d55307	108	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	109	*
<>	144:ef7eb2e8f9f7	110	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	111	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	112	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	113	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	114	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	115	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	116	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	117	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	118	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	119	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	120	*
<>	144:ef7eb2e8f9f7	121	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	122	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	123	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	124	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	125	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	126	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	127	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	128	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	129	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	130	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	131	*
<>	144:ef7eb2e8f9f7	132	******************************************************************************
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	136	#include "stm32f2xx_hal.h"
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	139	* @{
<>	144:ef7eb2e8f9f7	140	*/
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	/** @defgroup USART USART
<>	144:ef7eb2e8f9f7	143	* @brief HAL USART Synchronous module driver
<>	144:ef7eb2e8f9f7	144	* @{
<>	144:ef7eb2e8f9f7	145	*/
<>	144:ef7eb2e8f9f7	146	#ifdef HAL_USART_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	147	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	148	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	149	/** @addtogroup USART_Private_Constants
<>	144:ef7eb2e8f9f7	150	* @{
<>	144:ef7eb2e8f9f7	151	*/
<>	144:ef7eb2e8f9f7	152	#define DUMMY_DATA 0xFFFFU
<>	144:ef7eb2e8f9f7	153	#define USART_TIMEOUT_VALUE 22000U
<>	144:ef7eb2e8f9f7	154	/**
<>	144:ef7eb2e8f9f7	155	* @}
<>	144:ef7eb2e8f9f7	156	*/
<>	144:ef7eb2e8f9f7	157	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	158	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	159	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	160	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	161	/** @addtogroup USART_Private_Functions
<>	144:ef7eb2e8f9f7	162	* @{
<>	144:ef7eb2e8f9f7	163	*/
<>	144:ef7eb2e8f9f7	164	static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	165	static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	166	static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	167	static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	168	static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	169	static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	170	static void USART_SetConfig (USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	171	static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	172	static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	173	static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	174	static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	175	static void USART_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	176	static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	177	static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	178	static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	181	/**
<>	144:ef7eb2e8f9f7	182	* @}
<>	144:ef7eb2e8f9f7	183	*/
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	186	/** @defgroup USART_Exported_Functions USART Exported Functions
<>	144:ef7eb2e8f9f7	187	* @{
<>	144:ef7eb2e8f9f7	188	*/
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	191	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	192	*
<>	144:ef7eb2e8f9f7	193	@verbatim
<>	144:ef7eb2e8f9f7	194	==============================================================================
<>	144:ef7eb2e8f9f7	195	##### Initialization and Configuration functions #####
<>	144:ef7eb2e8f9f7	196	==============================================================================
<>	144:ef7eb2e8f9f7	197	[..]
<>	144:ef7eb2e8f9f7	198	This subsection provides a set of functions allowing to initialize the USART
<>	144:ef7eb2e8f9f7	199	in asynchronous and in synchronous modes.
<>	144:ef7eb2e8f9f7	200	(+) For the asynchronous mode only these parameters can be configured:
<>	144:ef7eb2e8f9f7	201	(++) Baud Rate
<>	144:ef7eb2e8f9f7	202	(++) Word Length
<>	144:ef7eb2e8f9f7	203	(++) Stop Bit
<>	144:ef7eb2e8f9f7	204	(++) Parity: If the parity is enabled, then the MSB bit of the data written
<>	144:ef7eb2e8f9f7	205	in the data register is transmitted but is changed by the parity bit.
<>	144:ef7eb2e8f9f7	206	Depending on the frame length defined by the M bit (8-bits or 9-bits),
<>	144:ef7eb2e8f9f7	207	please refer to Reference manual for possible USART frame formats.
<>	144:ef7eb2e8f9f7	208	(++) USART polarity
<>	144:ef7eb2e8f9f7	209	(++) USART phase
<>	144:ef7eb2e8f9f7	210	(++) USART LastBit
<>	144:ef7eb2e8f9f7	211	(++) Receiver/transmitter modes
<>	144:ef7eb2e8f9f7	212
<>	144:ef7eb2e8f9f7	213	[..]
<>	144:ef7eb2e8f9f7	214	The HAL_USART_Init() function follows the USART synchronous configuration
<>	144:ef7eb2e8f9f7	215	procedure (details for the procedure are available in reference manual (RM0329)).
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	@endverbatim
<>	144:ef7eb2e8f9f7	218	* @{
<>	144:ef7eb2e8f9f7	219	*/
<>	144:ef7eb2e8f9f7	220
<>	144:ef7eb2e8f9f7	221	/**
<>	144:ef7eb2e8f9f7	222	* @brief Initializes the USART mode according to the specified
<>	144:ef7eb2e8f9f7	223	* parameters in the USART_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	224	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	225	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	226	* @retval HAL status
<>	144:ef7eb2e8f9f7	227	*/
<>	144:ef7eb2e8f9f7	228	HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	229	{
<>	144:ef7eb2e8f9f7	230	/* Check the USART handle allocation */
<>	144:ef7eb2e8f9f7	231	if(husart == NULL)
<>	144:ef7eb2e8f9f7	232	{
<>	144:ef7eb2e8f9f7	233	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	234	}
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	/* Check the parameters */
<>	144:ef7eb2e8f9f7	237	assert_param(IS_USART_INSTANCE(husart->Instance));
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	if(husart->State == HAL_USART_STATE_RESET)
<>	144:ef7eb2e8f9f7	240	{
<>	144:ef7eb2e8f9f7	241	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	242	husart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	243	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	244	HAL_USART_MspInit(husart);
<>	144:ef7eb2e8f9f7	245	}
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	husart->State = HAL_USART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	/* Set the USART Communication parameters */
<>	144:ef7eb2e8f9f7	250	USART_SetConfig(husart);
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252	/* In USART mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	253	- LINEN bit in the USART_CR2 register
<>	144:ef7eb2e8f9f7	254	- HDSEL, SCEN and IREN bits in the USART_CR3 register */
<>	144:ef7eb2e8f9f7	255	CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
<>	144:ef7eb2e8f9f7	256	CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL \| USART_CR3_IREN));
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	259	__HAL_USART_ENABLE(husart);
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	/* Initialize the USART state */
<>	144:ef7eb2e8f9f7	262	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	263	husart->State= HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	264
<>	144:ef7eb2e8f9f7	265	return HAL_OK;
<>	144:ef7eb2e8f9f7	266	}
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	/**
<>	144:ef7eb2e8f9f7	269	* @brief DeInitializes the USART peripheral.
<>	144:ef7eb2e8f9f7	270	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	271	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	272	* @retval HAL status
<>	144:ef7eb2e8f9f7	273	*/
<>	144:ef7eb2e8f9f7	274	HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	275	{
<>	144:ef7eb2e8f9f7	276	/* Check the USART handle allocation */
<>	144:ef7eb2e8f9f7	277	if(husart == NULL)
<>	144:ef7eb2e8f9f7	278	{
<>	144:ef7eb2e8f9f7	279	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	280	}
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/* Check the parameters */
<>	144:ef7eb2e8f9f7	283	assert_param(IS_USART_INSTANCE(husart->Instance));
<>	144:ef7eb2e8f9f7	284
<>	144:ef7eb2e8f9f7	285	husart->State = HAL_USART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	286
<>	144:ef7eb2e8f9f7	287	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	288	__HAL_USART_DISABLE(husart);
<>	144:ef7eb2e8f9f7	289
<>	144:ef7eb2e8f9f7	290	/* DeInit the low level hardware */
<>	144:ef7eb2e8f9f7	291	HAL_USART_MspDeInit(husart);
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	294	husart->State = HAL_USART_STATE_RESET;
<>	144:ef7eb2e8f9f7	295
<>	144:ef7eb2e8f9f7	296	/* Release Lock */
<>	144:ef7eb2e8f9f7	297	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	298
<>	144:ef7eb2e8f9f7	299	return HAL_OK;
<>	144:ef7eb2e8f9f7	300	}
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	/**
<>	144:ef7eb2e8f9f7	303	* @brief USART MSP Init.
<>	144:ef7eb2e8f9f7	304	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	305	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	306	* @retval None
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308	__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	309	{
<>	144:ef7eb2e8f9f7	310	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	311	UNUSED(husart);
<>	144:ef7eb2e8f9f7	312	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	313	the HAL_USART_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	314	*/
<>	144:ef7eb2e8f9f7	315	}
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/**
<>	144:ef7eb2e8f9f7	318	* @brief USART MSP DeInit.
<>	144:ef7eb2e8f9f7	319	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	320	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	321	* @retval None
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323	__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	324	{
<>	144:ef7eb2e8f9f7	325	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	326	UNUSED(husart);
<>	144:ef7eb2e8f9f7	327	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	328	the HAL_USART_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	329	*/
<>	144:ef7eb2e8f9f7	330	}
<>	144:ef7eb2e8f9f7	331
<>	144:ef7eb2e8f9f7	332	/**
<>	144:ef7eb2e8f9f7	333	* @}
<>	144:ef7eb2e8f9f7	334	*/
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/** @defgroup USART_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	337	* @brief USART Transmit and Receive functions
<>	144:ef7eb2e8f9f7	338	*
<>	144:ef7eb2e8f9f7	339	@verbatim
<>	144:ef7eb2e8f9f7	340	==============================================================================
<>	144:ef7eb2e8f9f7	341	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	342	==============================================================================
<>	144:ef7eb2e8f9f7	343	[..]
<>	144:ef7eb2e8f9f7	344	This subsection provides a set of functions allowing to manage the USART synchronous
<>	144:ef7eb2e8f9f7	345	data transfers.
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	[..]
<>	144:ef7eb2e8f9f7	348	The USART supports master mode only: it cannot receive or send data related to an input
<>	144:ef7eb2e8f9f7	349	clock (SCLK is always an output).
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	352	(++) Blocking mode: The communication is performed in polling mode.
<>	144:ef7eb2e8f9f7	353	The HAL status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	354	after finishing transfer.
<>	144:ef7eb2e8f9f7	355	(++) No-Blocking mode: The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	356	or DMA, These API's return the HAL status.
<>	144:ef7eb2e8f9f7	357	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	358	dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	359	using DMA mode.
<>	144:ef7eb2e8f9f7	360	The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
<>	144:ef7eb2e8f9f7	361	user callbacks
<>	144:ef7eb2e8f9f7	362	will be executed respectively at the end of the transmit or Receive process
<>	144:ef7eb2e8f9f7	363	The HAL_USART_ErrorCallback() user callback will be executed when a communication
<>	144:ef7eb2e8f9f7	364	error is detected
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	(#) Blocking mode APIs are :
<>	144:ef7eb2e8f9f7	367	(++) HAL_USART_Transmit() in simplex mode
<>	144:ef7eb2e8f9f7	368	(++) HAL_USART_Receive() in full duplex receive only
<>	144:ef7eb2e8f9f7	369	(++) HAL_USART_TransmitReceive() in full duplex mode
<>	144:ef7eb2e8f9f7	370
<>	144:ef7eb2e8f9f7	371	(#) Non Blocking mode APIs with Interrupt are :
<>	144:ef7eb2e8f9f7	372	(++) HAL_USART_Transmit_IT()in simplex mode
<>	144:ef7eb2e8f9f7	373	(++) HAL_USART_Receive_IT() in full duplex receive only
<>	144:ef7eb2e8f9f7	374	(++) HAL_USART_TransmitReceive_IT() in full duplex mode
<>	144:ef7eb2e8f9f7	375	(++) HAL_USART_IRQHandler()
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	(#) Non Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	378	(++) HAL_USART_Transmit_DMA()in simplex mode
<>	144:ef7eb2e8f9f7	379	(++) HAL_USART_Receive_DMA() in full duplex receive only
<>	144:ef7eb2e8f9f7	380	(++) HAL_USART_TransmitReceie_DMA() in full duplex mode
<>	144:ef7eb2e8f9f7	381	(++) HAL_USART_DMAPause()
<>	144:ef7eb2e8f9f7	382	(++) HAL_USART_DMAResume()
<>	144:ef7eb2e8f9f7	383	(++) HAL_USART_DMAStop()
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<>	144:ef7eb2e8f9f7	386	(++) HAL_USART_TxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	387	(++) HAL_USART_TxCpltCallback()
<>	144:ef7eb2e8f9f7	388	(++) HAL_USART_RxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	389	(++) HAL_USART_RxCpltCallback()
<>	144:ef7eb2e8f9f7	390	(++) HAL_USART_ErrorCallback()
<>	144:ef7eb2e8f9f7	391	(++) HAL_USART_TxRxCpltCallback()
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	@endverbatim
<>	144:ef7eb2e8f9f7	394	* @{
<>	144:ef7eb2e8f9f7	395	*/
<>	144:ef7eb2e8f9f7	396
<>	144:ef7eb2e8f9f7	397	/**
<>	144:ef7eb2e8f9f7	398	* @brief Simplex Send an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	399	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	400	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	401	* @param pTxData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	402	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	403	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	404	* @retval HAL status
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406	HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef husart, uint8_t pTxData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	407	{
<>	144:ef7eb2e8f9f7	408	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	409	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	412	{
AnnaBridge	167:e84263d55307	413	if((pTxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	414	{
<>	144:ef7eb2e8f9f7	415	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	416	}
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/* Process Locked */
<>	144:ef7eb2e8f9f7	419	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	422	husart->State = HAL_USART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/* Init tickstart for timeout managment */
<>	144:ef7eb2e8f9f7	425	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	428	husart->TxXferCount = Size;
AnnaBridge	167:e84263d55307	429	while(husart->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	430	{
<>	144:ef7eb2e8f9f7	431	husart->TxXferCount--;
<>	144:ef7eb2e8f9f7	432	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	433	{
<>	144:ef7eb2e8f9f7	434	/* Wait for TC flag in order to write data in DR */
<>	144:ef7eb2e8f9f7	435	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	436	{
<>	144:ef7eb2e8f9f7	437	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	438	}
<>	144:ef7eb2e8f9f7	439	tmp = (uint16_t*) pTxData;
AnnaBridge	167:e84263d55307	440	husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	441	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	442	{
<>	144:ef7eb2e8f9f7	443	pTxData += 2U;
<>	144:ef7eb2e8f9f7	444	}
<>	144:ef7eb2e8f9f7	445	else
<>	144:ef7eb2e8f9f7	446	{
<>	144:ef7eb2e8f9f7	447	pTxData += 1U;
<>	144:ef7eb2e8f9f7	448	}
<>	144:ef7eb2e8f9f7	449	}
<>	144:ef7eb2e8f9f7	450	else
<>	144:ef7eb2e8f9f7	451	{
<>	144:ef7eb2e8f9f7	452	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	453	{
<>	144:ef7eb2e8f9f7	454	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	455	}
AnnaBridge	167:e84263d55307	456	husart->Instance->DR = (*pTxData++ & (uint8_t)0xFF);
<>	144:ef7eb2e8f9f7	457	}
<>	144:ef7eb2e8f9f7	458	}
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	461	{
<>	144:ef7eb2e8f9f7	462	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	463	}
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	466
<>	144:ef7eb2e8f9f7	467	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	468	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	return HAL_OK;
<>	144:ef7eb2e8f9f7	471	}
<>	144:ef7eb2e8f9f7	472	else
<>	144:ef7eb2e8f9f7	473	{
<>	144:ef7eb2e8f9f7	474	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	475	}
<>	144:ef7eb2e8f9f7	476	}
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	/**
<>	144:ef7eb2e8f9f7	479	* @brief Full-Duplex Receive an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	480	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	481	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	482	* @param pRxData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	483	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	484	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	485	* @retval HAL status
<>	144:ef7eb2e8f9f7	486	*/
<>	144:ef7eb2e8f9f7	487	HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef husart, uint8_t pRxData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	488	{
<>	144:ef7eb2e8f9f7	489	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	490	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	491
<>	144:ef7eb2e8f9f7	492	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	493	{
AnnaBridge	167:e84263d55307	494	if((pRxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	495	{
<>	144:ef7eb2e8f9f7	496	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	497	}
<>	144:ef7eb2e8f9f7	498	/* Process Locked */
<>	144:ef7eb2e8f9f7	499	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	500
<>	144:ef7eb2e8f9f7	501	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	502	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	503
<>	144:ef7eb2e8f9f7	504	/* Init tickstart for timeout managment */
<>	144:ef7eb2e8f9f7	505	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	508	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	509	/* Check the remain data to be received */
AnnaBridge	167:e84263d55307	510	while(husart->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	511	{
<>	144:ef7eb2e8f9f7	512	husart->RxXferCount--;
<>	144:ef7eb2e8f9f7	513	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	514	{
<>	144:ef7eb2e8f9f7	515	/* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
<>	144:ef7eb2e8f9f7	516	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	517	{
<>	144:ef7eb2e8f9f7	518	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	519	}
<>	144:ef7eb2e8f9f7	520	/* Send dummy byte in order to generate clock */
AnnaBridge	167:e84263d55307	521	husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/* Wait for RXNE Flag */
<>	144:ef7eb2e8f9f7	524	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	525	{
<>	144:ef7eb2e8f9f7	526	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	527	}
<>	144:ef7eb2e8f9f7	528	tmp = (uint16_t*) pRxData ;
<>	144:ef7eb2e8f9f7	529	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	530	{
AnnaBridge	167:e84263d55307	531	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	532	pRxData +=2;
<>	144:ef7eb2e8f9f7	533	}
<>	144:ef7eb2e8f9f7	534	else
<>	144:ef7eb2e8f9f7	535	{
AnnaBridge	167:e84263d55307	536	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
<>	144:ef7eb2e8f9f7	537	pRxData +=1;
<>	144:ef7eb2e8f9f7	538	}
<>	144:ef7eb2e8f9f7	539	}
<>	144:ef7eb2e8f9f7	540	else
<>	144:ef7eb2e8f9f7	541	{
<>	144:ef7eb2e8f9f7	542	/* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
<>	144:ef7eb2e8f9f7	543	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	544	{
<>	144:ef7eb2e8f9f7	545	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	546	}
<>	144:ef7eb2e8f9f7	547
<>	144:ef7eb2e8f9f7	548	/* Send Dummy Byte in order to generate clock */
AnnaBridge	167:e84263d55307	549	husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/* Wait until RXNE flag is set to receive the byte */
<>	144:ef7eb2e8f9f7	552	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	553	{
<>	144:ef7eb2e8f9f7	554	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	555	}
<>	144:ef7eb2e8f9f7	556	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	557	{
<>	144:ef7eb2e8f9f7	558	/* Receive data */
AnnaBridge	167:e84263d55307	559	*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	560	}
<>	144:ef7eb2e8f9f7	561	else
<>	144:ef7eb2e8f9f7	562	{
<>	144:ef7eb2e8f9f7	563	/* Receive data */
AnnaBridge	167:e84263d55307	564	*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
<>	144:ef7eb2e8f9f7	565	}
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	}
<>	144:ef7eb2e8f9f7	568	}
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	573	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	return HAL_OK;
<>	144:ef7eb2e8f9f7	576	}
<>	144:ef7eb2e8f9f7	577	else
<>	144:ef7eb2e8f9f7	578	{
<>	144:ef7eb2e8f9f7	579	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	580	}
<>	144:ef7eb2e8f9f7	581	}
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	/**
<>	144:ef7eb2e8f9f7	584	* @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
<>	144:ef7eb2e8f9f7	585	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	586	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	587	* @param pTxData: Pointer to data transmitted buffer
<>	144:ef7eb2e8f9f7	588	* @param pRxData: Pointer to data received buffer
<>	144:ef7eb2e8f9f7	589	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	590	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	591	* @retval HAL status
<>	144:ef7eb2e8f9f7	592	*/
<>	144:ef7eb2e8f9f7	593	HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef husart, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	594	{
<>	144:ef7eb2e8f9f7	595	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	596	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	599	{
AnnaBridge	167:e84263d55307	600	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	601	{
<>	144:ef7eb2e8f9f7	602	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	603	}
<>	144:ef7eb2e8f9f7	604	/* Process Locked */
<>	144:ef7eb2e8f9f7	605	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	608	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	/* Init tickstart for timeout managment */
<>	144:ef7eb2e8f9f7	611	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	614	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	615	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	616	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	/* Check the remain data to be received */
AnnaBridge	167:e84263d55307	619	while(husart->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	620	{
<>	144:ef7eb2e8f9f7	621	husart->TxXferCount--;
<>	144:ef7eb2e8f9f7	622	husart->RxXferCount--;
<>	144:ef7eb2e8f9f7	623	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	624	{
<>	144:ef7eb2e8f9f7	625	/* Wait for TC flag in order to write data in DR */
<>	144:ef7eb2e8f9f7	626	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	627	{
<>	144:ef7eb2e8f9f7	628	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	629	}
<>	144:ef7eb2e8f9f7	630	tmp = (uint16_t*) pTxData;
AnnaBridge	167:e84263d55307	631	husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	632	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	633	{
AnnaBridge	167:e84263d55307	634	pTxData += 2;
<>	144:ef7eb2e8f9f7	635	}
<>	144:ef7eb2e8f9f7	636	else
<>	144:ef7eb2e8f9f7	637	{
AnnaBridge	167:e84263d55307	638	pTxData += 1;
<>	144:ef7eb2e8f9f7	639	}
<>	144:ef7eb2e8f9f7	640
<>	144:ef7eb2e8f9f7	641	/* Wait for RXNE Flag */
<>	144:ef7eb2e8f9f7	642	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	643	{
<>	144:ef7eb2e8f9f7	644	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	645	}
<>	144:ef7eb2e8f9f7	646	tmp = (uint16_t*) pRxData ;
<>	144:ef7eb2e8f9f7	647	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	648	{
AnnaBridge	167:e84263d55307	649	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	650	pRxData += 2U;
<>	144:ef7eb2e8f9f7	651	}
<>	144:ef7eb2e8f9f7	652	else
<>	144:ef7eb2e8f9f7	653	{
AnnaBridge	167:e84263d55307	654	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
<>	144:ef7eb2e8f9f7	655	pRxData += 1U;
<>	144:ef7eb2e8f9f7	656	}
<>	144:ef7eb2e8f9f7	657	}
<>	144:ef7eb2e8f9f7	658	else
<>	144:ef7eb2e8f9f7	659	{
<>	144:ef7eb2e8f9f7	660	/* Wait for TC flag in order to write data in DR */
<>	144:ef7eb2e8f9f7	661	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	662	{
<>	144:ef7eb2e8f9f7	663	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	664	}
AnnaBridge	167:e84263d55307	665	husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	/* Wait for RXNE Flag */
<>	144:ef7eb2e8f9f7	668	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	669	{
<>	144:ef7eb2e8f9f7	670	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	671	}
<>	144:ef7eb2e8f9f7	672	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	/* Receive data */
AnnaBridge	167:e84263d55307	675	*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	676	}
<>	144:ef7eb2e8f9f7	677	else
<>	144:ef7eb2e8f9f7	678	{
<>	144:ef7eb2e8f9f7	679	/* Receive data */
AnnaBridge	167:e84263d55307	680	*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
<>	144:ef7eb2e8f9f7	681	}
<>	144:ef7eb2e8f9f7	682	}
<>	144:ef7eb2e8f9f7	683	}
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	688	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	return HAL_OK;
<>	144:ef7eb2e8f9f7	691	}
<>	144:ef7eb2e8f9f7	692	else
<>	144:ef7eb2e8f9f7	693	{
<>	144:ef7eb2e8f9f7	694	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	695	}
<>	144:ef7eb2e8f9f7	696	}
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	/**
<>	144:ef7eb2e8f9f7	699	* @brief Simplex Send an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	700	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	701	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	702	* @param pTxData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	703	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	704	* @retval HAL status
<>	144:ef7eb2e8f9f7	705	* @note The USART errors are not managed to avoid the overrun error.
<>	144:ef7eb2e8f9f7	706	*/
<>	144:ef7eb2e8f9f7	707	HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef husart, uint8_t pTxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	708	{
<>	144:ef7eb2e8f9f7	709	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	710	{
AnnaBridge	167:e84263d55307	711	if((pTxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	712	{
<>	144:ef7eb2e8f9f7	713	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	714	}
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716	/* Process Locked */
<>	144:ef7eb2e8f9f7	717	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	720	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	721	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	724	husart->State = HAL_USART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	/* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
<>	144:ef7eb2e8f9f7	727	are not managed by the USART transmit process to avoid the overrun interrupt
<>	144:ef7eb2e8f9f7	728	when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
<>	144:ef7eb2e8f9f7	729	to benefit for the frame error and noise interrupts the USART mode should be
<>	144:ef7eb2e8f9f7	730	configured only for transmit "USART_MODE_TX"
<>	144:ef7eb2e8f9f7	731	The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
<>	144:ef7eb2e8f9f7	732	Noise error interrupt */
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	735	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/* Enable the USART Transmit Data Register Empty Interrupt */
<>	144:ef7eb2e8f9f7	738	SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	return HAL_OK;
<>	144:ef7eb2e8f9f7	741	}
<>	144:ef7eb2e8f9f7	742	else
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	745	}
<>	144:ef7eb2e8f9f7	746	}
<>	144:ef7eb2e8f9f7	747
<>	144:ef7eb2e8f9f7	748	/**
<>	144:ef7eb2e8f9f7	749	* @brief Simplex Receive an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	750	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	751	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	752	* @param pRxData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	753	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	754	* @retval HAL status
<>	144:ef7eb2e8f9f7	755	*/
<>	144:ef7eb2e8f9f7	756	HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef husart, uint8_t pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	757	{
<>	144:ef7eb2e8f9f7	758	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	759	{
AnnaBridge	167:e84263d55307	760	if((pRxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	761	{
<>	144:ef7eb2e8f9f7	762	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	763	}
<>	144:ef7eb2e8f9f7	764	/* Process Locked */
<>	144:ef7eb2e8f9f7	765	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	768	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	769	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	772	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	775	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	776
<>	144:ef7eb2e8f9f7	777	/* Enable the USART Parity Error and Data Register not empty Interrupts */
<>	144:ef7eb2e8f9f7	778	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE \| USART_CR1_RXNEIE);
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	781	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	/* Send dummy byte in order to generate the clock for the slave to send data */
AnnaBridge	167:e84263d55307	784	husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	return HAL_OK;
<>	144:ef7eb2e8f9f7	787	}
<>	144:ef7eb2e8f9f7	788	else
<>	144:ef7eb2e8f9f7	789	{
<>	144:ef7eb2e8f9f7	790	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	791	}
<>	144:ef7eb2e8f9f7	792	}
<>	144:ef7eb2e8f9f7	793
<>	144:ef7eb2e8f9f7	794	/**
<>	144:ef7eb2e8f9f7	795	* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
<>	144:ef7eb2e8f9f7	796	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	797	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	798	* @param pTxData: Pointer to data transmitted buffer
<>	144:ef7eb2e8f9f7	799	* @param pRxData: Pointer to data received buffer
<>	144:ef7eb2e8f9f7	800	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	801	* @retval HAL status
<>	144:ef7eb2e8f9f7	802	*/
<>	144:ef7eb2e8f9f7	803	HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef husart, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	804	{
<>	144:ef7eb2e8f9f7	805	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	806	{
AnnaBridge	167:e84263d55307	807	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	808	{
<>	144:ef7eb2e8f9f7	809	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	810	}
<>	144:ef7eb2e8f9f7	811	/* Process Locked */
<>	144:ef7eb2e8f9f7	812	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	813
<>	144:ef7eb2e8f9f7	814	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	815	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	816	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	817	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	818	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	819	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	820
<>	144:ef7eb2e8f9f7	821	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	822	husart->State = HAL_USART_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	825	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	826
<>	144:ef7eb2e8f9f7	827	/* Enable the USART Data Register not empty Interrupt */
<>	144:ef7eb2e8f9f7	828	SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/* Enable the USART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	831	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	834	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	835
<>	144:ef7eb2e8f9f7	836	/* Enable the USART Transmit Data Register Empty Interrupt */
<>	144:ef7eb2e8f9f7	837	SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	838
<>	144:ef7eb2e8f9f7	839	return HAL_OK;
<>	144:ef7eb2e8f9f7	840	}
<>	144:ef7eb2e8f9f7	841	else
<>	144:ef7eb2e8f9f7	842	{
<>	144:ef7eb2e8f9f7	843	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	844	}
<>	144:ef7eb2e8f9f7	845	}
<>	144:ef7eb2e8f9f7	846
<>	144:ef7eb2e8f9f7	847	/**
<>	144:ef7eb2e8f9f7	848	* @brief Simplex Send an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	849	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	850	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	851	* @param pTxData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	852	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	853	* @retval HAL status
<>	144:ef7eb2e8f9f7	854	*/
<>	144:ef7eb2e8f9f7	855	HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef husart, uint8_t pTxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	856	{
<>	144:ef7eb2e8f9f7	857	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	860	{
AnnaBridge	167:e84263d55307	861	if((pTxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	862	{
<>	144:ef7eb2e8f9f7	863	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	864	}
<>	144:ef7eb2e8f9f7	865	/* Process Locked */
<>	144:ef7eb2e8f9f7	866	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	869	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	870	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	873	husart->State = HAL_USART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	/* Set the USART DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	876	husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	879	husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	882	husart->hdmatx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	/* Set the DMA abort callback */
<>	144:ef7eb2e8f9f7	885	husart->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/* Enable the USART transmit DMA Stream */
<>	144:ef7eb2e8f9f7	888	tmp = (uint32_t*)&pTxData;
<>	144:ef7eb2e8f9f7	889	HAL_DMA_Start_IT(husart->hdmatx, (uint32_t)tmp, (uint32_t)&husart->Instance->DR, Size);
<>	144:ef7eb2e8f9f7	890
<>	144:ef7eb2e8f9f7	891	/* Clear the TC flag in the SR register by writing 0 to it */
<>	144:ef7eb2e8f9f7	892	__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	895	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	896
<>	144:ef7eb2e8f9f7	897	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	898	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	899	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	900
<>	144:ef7eb2e8f9f7	901	return HAL_OK;
<>	144:ef7eb2e8f9f7	902	}
<>	144:ef7eb2e8f9f7	903	else
<>	144:ef7eb2e8f9f7	904	{
<>	144:ef7eb2e8f9f7	905	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	906	}
<>	144:ef7eb2e8f9f7	907	}
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	/**
<>	144:ef7eb2e8f9f7	910	* @brief Full-Duplex Receive an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	911	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	912	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	913	* @param pRxData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	914	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	915	* @retval HAL status
<>	144:ef7eb2e8f9f7	916	* @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.
<>	144:ef7eb2e8f9f7	917	* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
<>	144:ef7eb2e8f9f7	918	*/
<>	144:ef7eb2e8f9f7	919	HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef husart, uint8_t pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	920	{
<>	144:ef7eb2e8f9f7	921	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	922
<>	144:ef7eb2e8f9f7	923	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	924	{
AnnaBridge	167:e84263d55307	925	if((pRxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	926	{
<>	144:ef7eb2e8f9f7	927	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	928	}
<>	144:ef7eb2e8f9f7	929
<>	144:ef7eb2e8f9f7	930	/* Process Locked */
<>	144:ef7eb2e8f9f7	931	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	932
<>	144:ef7eb2e8f9f7	933	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	934	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	935	husart->pTxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	936	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	939	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	940
<>	144:ef7eb2e8f9f7	941	/* Set the USART DMA Rx transfer complete callback */
<>	144:ef7eb2e8f9f7	942	husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	945	husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* Set the USART DMA Rx transfer error callback */
<>	144:ef7eb2e8f9f7	948	husart->hdmarx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/* Set the DMA abort callback */
<>	144:ef7eb2e8f9f7	951	husart->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	952
<>	144:ef7eb2e8f9f7	953	/* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
<>	144:ef7eb2e8f9f7	954	is performed in DMA reception complete callback */
<>	144:ef7eb2e8f9f7	955	husart->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	956	husart->hdmatx->XferCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	959	husart->hdmatx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	960
<>	144:ef7eb2e8f9f7	961	/* Set the DMA AbortCpltCallback */
<>	144:ef7eb2e8f9f7	962	husart->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	963
<>	144:ef7eb2e8f9f7	964	/* Enable the USART receive DMA Stream */
<>	144:ef7eb2e8f9f7	965	tmp = (uint32_t*)&pRxData;
<>	144:ef7eb2e8f9f7	966	HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, (uint32_t)tmp, Size);
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	/* Enable the USART transmit DMA Stream: the transmit stream is used in order
<>	144:ef7eb2e8f9f7	969	to generate in the non-blocking mode the clock to the slave device,
<>	144:ef7eb2e8f9f7	970	this mode isn't a simplex receive mode but a full-duplex receive one */
<>	144:ef7eb2e8f9f7	971	HAL_DMA_Start_IT(husart->hdmatx, (uint32_t)tmp, (uint32_t)&husart->Instance->DR, Size);
<>	144:ef7eb2e8f9f7	972
AnnaBridge	167:e84263d55307	973	/* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
<>	144:ef7eb2e8f9f7	974	__HAL_USART_CLEAR_OREFLAG(husart);
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	977	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/* Enable the USART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	980	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	983	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985	/* Enable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	986	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	987	SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	990	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	991	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	992
<>	144:ef7eb2e8f9f7	993	return HAL_OK;
<>	144:ef7eb2e8f9f7	994	}
<>	144:ef7eb2e8f9f7	995	else
<>	144:ef7eb2e8f9f7	996	{
<>	144:ef7eb2e8f9f7	997	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	998	}
<>	144:ef7eb2e8f9f7	999	}
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	/**
<>	144:ef7eb2e8f9f7	1002	* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	1003	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1004	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1005	* @param pTxData: Pointer to data transmitted buffer
<>	144:ef7eb2e8f9f7	1006	* @param pRxData: Pointer to data received buffer
<>	144:ef7eb2e8f9f7	1007	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	1008	* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
<>	144:ef7eb2e8f9f7	1009	* @retval HAL status
<>	144:ef7eb2e8f9f7	1010	*/
<>	144:ef7eb2e8f9f7	1011	HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef husart, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1012	{
<>	144:ef7eb2e8f9f7	1013	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	1014
<>	144:ef7eb2e8f9f7	1015	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	1016	{
AnnaBridge	167:e84263d55307	1017	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1018	{
<>	144:ef7eb2e8f9f7	1019	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1020	}
<>	144:ef7eb2e8f9f7	1021	/* Process Locked */
<>	144:ef7eb2e8f9f7	1022	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	1025	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1026	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	1027	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1030	husart->State = HAL_USART_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* Set the USART DMA Rx transfer complete callback */
<>	144:ef7eb2e8f9f7	1033	husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1036	husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	/* Set the USART DMA Tx transfer complete callback */
<>	144:ef7eb2e8f9f7	1039	husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1042	husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	/* Set the USART DMA Tx transfer error callback */
<>	144:ef7eb2e8f9f7	1045	husart->hdmatx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* Set the USART DMA Rx transfer error callback */
<>	144:ef7eb2e8f9f7	1048	husart->hdmarx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	/* Set the DMA abort callback */
<>	144:ef7eb2e8f9f7	1051	husart->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	/* Enable the USART receive DMA Stream */
<>	144:ef7eb2e8f9f7	1054	tmp = (uint32_t*)&pRxData;
<>	144:ef7eb2e8f9f7	1055	HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, (uint32_t)tmp, Size);
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	/* Enable the USART transmit DMA Stream */
<>	144:ef7eb2e8f9f7	1058	tmp = (uint32_t*)&pTxData;
<>	144:ef7eb2e8f9f7	1059	HAL_DMA_Start_IT(husart->hdmatx, (uint32_t)tmp, (uint32_t)&husart->Instance->DR, Size);
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/* Clear the TC flag in the SR register by writing 0 to it */
<>	144:ef7eb2e8f9f7	1062	__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
<>	144:ef7eb2e8f9f7	1063
<>	144:ef7eb2e8f9f7	1064	/* Clear the Overrun flag: mandatory for the second transfer in circular mode */
<>	144:ef7eb2e8f9f7	1065	__HAL_USART_CLEAR_OREFLAG(husart);
<>	144:ef7eb2e8f9f7	1066
<>	144:ef7eb2e8f9f7	1067	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1068	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	1069
<>	144:ef7eb2e8f9f7	1070	/* Enable the USART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	1071	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1072
<>	144:ef7eb2e8f9f7	1073	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	1074	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1075
<>	144:ef7eb2e8f9f7	1076	/* Enable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	1077	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	1078	SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	1081	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	1082	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1083
<>	144:ef7eb2e8f9f7	1084	return HAL_OK;
<>	144:ef7eb2e8f9f7	1085	}
<>	144:ef7eb2e8f9f7	1086	else
<>	144:ef7eb2e8f9f7	1087	{
<>	144:ef7eb2e8f9f7	1088	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1089	}
<>	144:ef7eb2e8f9f7	1090	}
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	/**
<>	144:ef7eb2e8f9f7	1093	* @brief Pauses the DMA Transfer.
<>	144:ef7eb2e8f9f7	1094	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1095	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1096	* @retval HAL status
<>	144:ef7eb2e8f9f7	1097	*/
<>	144:ef7eb2e8f9f7	1098	HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1099	{
<>	144:ef7eb2e8f9f7	1100	/* Process Locked */
<>	144:ef7eb2e8f9f7	1101	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/* Disable the USART DMA Tx request */
<>	144:ef7eb2e8f9f7	1104	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1107	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	return HAL_OK;
<>	144:ef7eb2e8f9f7	1110	}
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/**
<>	144:ef7eb2e8f9f7	1113	* @brief Resumes the DMA Transfer.
<>	144:ef7eb2e8f9f7	1114	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1115	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1116	* @retval HAL status
<>	144:ef7eb2e8f9f7	1117	*/
<>	144:ef7eb2e8f9f7	1118	HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1119	{
<>	144:ef7eb2e8f9f7	1120	/* Process Locked */
<>	144:ef7eb2e8f9f7	1121	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/* Enable the USART DMA Tx request */
<>	144:ef7eb2e8f9f7	1124	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1127	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	return HAL_OK;
<>	144:ef7eb2e8f9f7	1130	}
<>	144:ef7eb2e8f9f7	1131
<>	144:ef7eb2e8f9f7	1132	/**
<>	144:ef7eb2e8f9f7	1133	* @brief Stops the DMA Transfer.
<>	144:ef7eb2e8f9f7	1134	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1135	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1136	* @retval HAL status
<>	144:ef7eb2e8f9f7	1137	*/
<>	144:ef7eb2e8f9f7	1138	HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1139	{
<>	144:ef7eb2e8f9f7	1140	uint32_t dmarequest = 0x00U;
<>	144:ef7eb2e8f9f7	1141	/* The Lock is not implemented on this API to allow the user application
<>	144:ef7eb2e8f9f7	1142	to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
<>	144:ef7eb2e8f9f7	1143	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<>	144:ef7eb2e8f9f7	1144	and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
<>	144:ef7eb2e8f9f7	1145	*/
<>	144:ef7eb2e8f9f7	1146
<>	144:ef7eb2e8f9f7	1147	/* Stop USART DMA Tx request if ongoing */
<>	144:ef7eb2e8f9f7	1148	dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1149	if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
<>	144:ef7eb2e8f9f7	1150	{
<>	144:ef7eb2e8f9f7	1151	USART_EndTxTransfer(husart);
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	/* Abort the USART DMA Tx channel */
<>	144:ef7eb2e8f9f7	1154	if(husart->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	1155	{
<>	144:ef7eb2e8f9f7	1156	HAL_DMA_Abort(husart->hdmatx);
<>	144:ef7eb2e8f9f7	1157	}
<>	144:ef7eb2e8f9f7	1158
<>	144:ef7eb2e8f9f7	1159	/* Disable the USART Tx DMA request */
<>	144:ef7eb2e8f9f7	1160	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1161	}
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	/* Stop USART DMA Rx request if ongoing */
<>	144:ef7eb2e8f9f7	1164	dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1165	if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
<>	144:ef7eb2e8f9f7	1166	{
<>	144:ef7eb2e8f9f7	1167	USART_EndRxTransfer(husart);
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169	/* Abort the USART DMA Rx channel */
<>	144:ef7eb2e8f9f7	1170	if(husart->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1171	{
<>	144:ef7eb2e8f9f7	1172	HAL_DMA_Abort(husart->hdmarx);
<>	144:ef7eb2e8f9f7	1173	}
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	/* Disable the USART Rx DMA request */
<>	144:ef7eb2e8f9f7	1176	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1177	}
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	return HAL_OK;
<>	144:ef7eb2e8f9f7	1180	}
<>	144:ef7eb2e8f9f7	1181
<>	144:ef7eb2e8f9f7	1182	/**
AnnaBridge	167:e84263d55307	1183	* @brief Abort ongoing transfer (blocking mode).
AnnaBridge	167:e84263d55307	1184	* @param husart USART handle.
AnnaBridge	167:e84263d55307	1185	* @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
AnnaBridge	167:e84263d55307	1186	* as described by TransferType parameter) started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1187	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1188	* - Disable PPP Interrupts (depending of transfer direction)
AnnaBridge	167:e84263d55307	1189	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1190	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1191	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1192	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge	167:e84263d55307	1193	* @retval HAL status
AnnaBridge	167:e84263d55307	1194	*/
AnnaBridge	167:e84263d55307	1195	HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
AnnaBridge	167:e84263d55307	1196	{
AnnaBridge	167:e84263d55307	1197	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge	167:e84263d55307	1198	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
AnnaBridge	167:e84263d55307	1199	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
AnnaBridge	167:e84263d55307	1200
AnnaBridge	167:e84263d55307	1201	/* Disable the USART DMA Tx request if enabled */
AnnaBridge	167:e84263d55307	1202	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1203	{
AnnaBridge	167:e84263d55307	1204	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
AnnaBridge	167:e84263d55307	1205
AnnaBridge	167:e84263d55307	1206	/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1207	if(husart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1208	{
AnnaBridge	167:e84263d55307	1209	/* Set the USART DMA Abort callback to Null.
AnnaBridge	167:e84263d55307	1210	No call back execution at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1211	husart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1212
AnnaBridge	167:e84263d55307	1213	HAL_DMA_Abort(husart->hdmatx);
AnnaBridge	167:e84263d55307	1214	}
AnnaBridge	167:e84263d55307	1215	}
AnnaBridge	167:e84263d55307	1216
AnnaBridge	167:e84263d55307	1217	/* Disable the USART DMA Rx request if enabled */
AnnaBridge	167:e84263d55307	1218	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1219	{
AnnaBridge	167:e84263d55307	1220	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
AnnaBridge	167:e84263d55307	1221
AnnaBridge	167:e84263d55307	1222	/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1223	if(husart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1224	{
AnnaBridge	167:e84263d55307	1225	/* Set the USART DMA Abort callback to Null.
AnnaBridge	167:e84263d55307	1226	No call back execution at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1227	husart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1228
AnnaBridge	167:e84263d55307	1229	HAL_DMA_Abort(husart->hdmarx);
AnnaBridge	167:e84263d55307	1230	}
AnnaBridge	167:e84263d55307	1231	}
AnnaBridge	167:e84263d55307	1232
AnnaBridge	167:e84263d55307	1233	/* Reset Tx and Rx transfer counters */
AnnaBridge	167:e84263d55307	1234	husart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1235	husart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1236
AnnaBridge	167:e84263d55307	1237	/* Restore husart->State to Ready */
AnnaBridge	167:e84263d55307	1238	husart->State = HAL_USART_STATE_READY;
AnnaBridge	167:e84263d55307	1239
AnnaBridge	167:e84263d55307	1240	/* Reset Handle ErrorCode to No Error */
AnnaBridge	167:e84263d55307	1241	husart->ErrorCode = HAL_USART_ERROR_NONE;
AnnaBridge	167:e84263d55307	1242
AnnaBridge	167:e84263d55307	1243	return HAL_OK;
AnnaBridge	167:e84263d55307	1244	}
AnnaBridge	167:e84263d55307	1245
AnnaBridge	167:e84263d55307	1246	/**
AnnaBridge	167:e84263d55307	1247	* @brief Abort ongoing transfer (Interrupt mode).
AnnaBridge	167:e84263d55307	1248	* @param husart USART handle.
AnnaBridge	167:e84263d55307	1249	* @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
AnnaBridge	167:e84263d55307	1250	* as described by TransferType parameter) started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1251	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1252	* - Disable PPP Interrupts (depending of transfer direction)
AnnaBridge	167:e84263d55307	1253	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1254	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1255	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1256	* - At abort completion, call user abort complete callback
AnnaBridge	167:e84263d55307	1257	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge	167:e84263d55307	1258	* considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge	167:e84263d55307	1259	* @retval HAL status
AnnaBridge	167:e84263d55307	1260	*/
AnnaBridge	167:e84263d55307	1261	HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
AnnaBridge	167:e84263d55307	1262	{
AnnaBridge	167:e84263d55307	1263	uint32_t AbortCplt = 0x01U;
AnnaBridge	167:e84263d55307	1264
AnnaBridge	167:e84263d55307	1265	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge	167:e84263d55307	1266	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
AnnaBridge	167:e84263d55307	1267	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
AnnaBridge	167:e84263d55307	1268
AnnaBridge	167:e84263d55307	1269	/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
AnnaBridge	167:e84263d55307	1270	before any call to DMA Abort functions */
AnnaBridge	167:e84263d55307	1271	/* DMA Tx Handle is valid */
AnnaBridge	167:e84263d55307	1272	if(husart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1273	{
AnnaBridge	167:e84263d55307	1274	/* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
AnnaBridge	167:e84263d55307	1275	Otherwise, set it to NULL */
AnnaBridge	167:e84263d55307	1276	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1277	{
AnnaBridge	167:e84263d55307	1278	husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
AnnaBridge	167:e84263d55307	1279	}
AnnaBridge	167:e84263d55307	1280	else
AnnaBridge	167:e84263d55307	1281	{
AnnaBridge	167:e84263d55307	1282	husart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1283	}
AnnaBridge	167:e84263d55307	1284	}
AnnaBridge	167:e84263d55307	1285	/* DMA Rx Handle is valid */
AnnaBridge	167:e84263d55307	1286	if(husart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1287	{
AnnaBridge	167:e84263d55307	1288	/* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
AnnaBridge	167:e84263d55307	1289	Otherwise, set it to NULL */
AnnaBridge	167:e84263d55307	1290	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1291	{
AnnaBridge	167:e84263d55307	1292	husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
AnnaBridge	167:e84263d55307	1293	}
AnnaBridge	167:e84263d55307	1294	else
AnnaBridge	167:e84263d55307	1295	{
AnnaBridge	167:e84263d55307	1296	husart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1297	}
AnnaBridge	167:e84263d55307	1298	}
AnnaBridge	167:e84263d55307	1299
AnnaBridge	167:e84263d55307	1300	/* Disable the USART DMA Tx request if enabled */
AnnaBridge	167:e84263d55307	1301	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1302	{
AnnaBridge	167:e84263d55307	1303	/* Disable DMA Tx at USART level */
AnnaBridge	167:e84263d55307	1304	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
AnnaBridge	167:e84263d55307	1305
AnnaBridge	167:e84263d55307	1306	/* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
AnnaBridge	167:e84263d55307	1307	if(husart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1308	{
AnnaBridge	167:e84263d55307	1309	/* USART Tx DMA Abort callback has already been initialised :
AnnaBridge	167:e84263d55307	1310	will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1311
AnnaBridge	167:e84263d55307	1312	/* Abort DMA TX */
AnnaBridge	167:e84263d55307	1313	if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
AnnaBridge	167:e84263d55307	1314	{
AnnaBridge	167:e84263d55307	1315	husart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1316	}
AnnaBridge	167:e84263d55307	1317	else
AnnaBridge	167:e84263d55307	1318	{
AnnaBridge	167:e84263d55307	1319	AbortCplt = 0x00U;
AnnaBridge	167:e84263d55307	1320	}
AnnaBridge	167:e84263d55307	1321	}
AnnaBridge	167:e84263d55307	1322	}
AnnaBridge	167:e84263d55307	1323
AnnaBridge	167:e84263d55307	1324	/* Disable the USART DMA Rx request if enabled */
AnnaBridge	167:e84263d55307	1325	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1326	{
AnnaBridge	167:e84263d55307	1327	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
AnnaBridge	167:e84263d55307	1328
AnnaBridge	167:e84263d55307	1329	/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
AnnaBridge	167:e84263d55307	1330	if(husart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1331	{
AnnaBridge	167:e84263d55307	1332	/* USART Rx DMA Abort callback has already been initialised :
AnnaBridge	167:e84263d55307	1333	will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1334
AnnaBridge	167:e84263d55307	1335	/* Abort DMA RX */
AnnaBridge	167:e84263d55307	1336	if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
AnnaBridge	167:e84263d55307	1337	{
AnnaBridge	167:e84263d55307	1338	husart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1339	AbortCplt = 0x01U;
AnnaBridge	167:e84263d55307	1340	}
AnnaBridge	167:e84263d55307	1341	else
AnnaBridge	167:e84263d55307	1342	{
AnnaBridge	167:e84263d55307	1343	AbortCplt = 0x00U;
AnnaBridge	167:e84263d55307	1344	}
AnnaBridge	167:e84263d55307	1345	}
AnnaBridge	167:e84263d55307	1346	}
AnnaBridge	167:e84263d55307	1347
AnnaBridge	167:e84263d55307	1348	/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
AnnaBridge	167:e84263d55307	1349	if(AbortCplt == 0x01U)
AnnaBridge	167:e84263d55307	1350	{
AnnaBridge	167:e84263d55307	1351	/* Reset Tx and Rx transfer counters */
AnnaBridge	167:e84263d55307	1352	husart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1353	husart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1354
AnnaBridge	167:e84263d55307	1355	/* Reset errorCode */
AnnaBridge	167:e84263d55307	1356	husart->ErrorCode = HAL_USART_ERROR_NONE;
AnnaBridge	167:e84263d55307	1357
AnnaBridge	167:e84263d55307	1358	/* Restore husart->State to Ready */
AnnaBridge	167:e84263d55307	1359	husart->State = HAL_USART_STATE_READY;
AnnaBridge	167:e84263d55307	1360
AnnaBridge	167:e84263d55307	1361	/* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge	167:e84263d55307	1362	HAL_USART_AbortCpltCallback(husart);
AnnaBridge	167:e84263d55307	1363	}
AnnaBridge	167:e84263d55307	1364
AnnaBridge	167:e84263d55307	1365	return HAL_OK;
AnnaBridge	167:e84263d55307	1366	}
AnnaBridge	167:e84263d55307	1367
AnnaBridge	167:e84263d55307	1368	/**
<>	144:ef7eb2e8f9f7	1369	* @brief This function handles USART interrupt request.
<>	144:ef7eb2e8f9f7	1370	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1371	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1372	* @retval None
<>	144:ef7eb2e8f9f7	1373	*/
<>	144:ef7eb2e8f9f7	1374	void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1375	{
<>	144:ef7eb2e8f9f7	1376	uint32_t isrflags = READ_REG(husart->Instance->SR);
<>	144:ef7eb2e8f9f7	1377	uint32_t cr1its = READ_REG(husart->Instance->CR1);
<>	144:ef7eb2e8f9f7	1378	uint32_t cr3its = READ_REG(husart->Instance->CR3);
<>	144:ef7eb2e8f9f7	1379	uint32_t errorflags = 0x00U;
<>	144:ef7eb2e8f9f7	1380	uint32_t dmarequest = 0x00U;
<>	144:ef7eb2e8f9f7	1381
<>	144:ef7eb2e8f9f7	1382	/* If no error occurs */
<>	144:ef7eb2e8f9f7	1383	errorflags = (isrflags & (uint32_t)(USART_SR_PE \| USART_SR_FE \| USART_SR_ORE \| USART_SR_NE));
<>	144:ef7eb2e8f9f7	1384	if(errorflags == RESET)
<>	144:ef7eb2e8f9f7	1385	{
<>	144:ef7eb2e8f9f7	1386	/* USART in mode Receiver -------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1387	if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	144:ef7eb2e8f9f7	1388	{
<>	144:ef7eb2e8f9f7	1389	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1390	{
<>	144:ef7eb2e8f9f7	1391	USART_Receive_IT(husart);
<>	144:ef7eb2e8f9f7	1392	}
<>	144:ef7eb2e8f9f7	1393	else
<>	144:ef7eb2e8f9f7	1394	{
<>	144:ef7eb2e8f9f7	1395	USART_TransmitReceive_IT(husart);
<>	144:ef7eb2e8f9f7	1396	}
<>	144:ef7eb2e8f9f7	1397	return;
<>	144:ef7eb2e8f9f7	1398	}
<>	144:ef7eb2e8f9f7	1399	}
<>	144:ef7eb2e8f9f7	1400	/* If some errors occur */
<>	144:ef7eb2e8f9f7	1401	if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) \|\| ((cr1its & (USART_CR1_RXNEIE \| USART_CR1_PEIE)) != RESET)))
<>	144:ef7eb2e8f9f7	1402	{
<>	144:ef7eb2e8f9f7	1403	/* USART parity error interrupt occurred ----------------------------------*/
<>	144:ef7eb2e8f9f7	1404	if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<>	144:ef7eb2e8f9f7	1405	{
<>	144:ef7eb2e8f9f7	1406	husart->ErrorCode \|= HAL_USART_ERROR_PE;
<>	144:ef7eb2e8f9f7	1407	}
<>	144:ef7eb2e8f9f7	1408
<>	144:ef7eb2e8f9f7	1409	/* USART noise error interrupt occurred --------------------------------*/
<>	144:ef7eb2e8f9f7	1410	if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1411	{
<>	144:ef7eb2e8f9f7	1412	husart->ErrorCode \|= HAL_USART_ERROR_NE;
<>	144:ef7eb2e8f9f7	1413	}
<>	144:ef7eb2e8f9f7	1414
<>	144:ef7eb2e8f9f7	1415	/* USART frame error interrupt occurred --------------------------------*/
<>	144:ef7eb2e8f9f7	1416	if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1417	{
<>	144:ef7eb2e8f9f7	1418	husart->ErrorCode \|= HAL_USART_ERROR_FE;
<>	144:ef7eb2e8f9f7	1419	}
<>	144:ef7eb2e8f9f7	1420
<>	144:ef7eb2e8f9f7	1421	/* USART Over-Run interrupt occurred -----------------------------------*/
<>	144:ef7eb2e8f9f7	1422	if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1423	{
<>	144:ef7eb2e8f9f7	1424	husart->ErrorCode \|= HAL_USART_ERROR_ORE;
<>	144:ef7eb2e8f9f7	1425	}
<>	144:ef7eb2e8f9f7	1426
<>	144:ef7eb2e8f9f7	1427	if(husart->ErrorCode != HAL_USART_ERROR_NONE)
<>	144:ef7eb2e8f9f7	1428	{
<>	144:ef7eb2e8f9f7	1429	/* USART in mode Receiver -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1430	if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	144:ef7eb2e8f9f7	1431	{
<>	144:ef7eb2e8f9f7	1432	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1433	{
<>	144:ef7eb2e8f9f7	1434	USART_Receive_IT(husart);
<>	144:ef7eb2e8f9f7	1435	}
<>	144:ef7eb2e8f9f7	1436	else
<>	144:ef7eb2e8f9f7	1437	{
<>	144:ef7eb2e8f9f7	1438	USART_TransmitReceive_IT(husart);
<>	144:ef7eb2e8f9f7	1439	}
<>	144:ef7eb2e8f9f7	1440	}
<>	144:ef7eb2e8f9f7	1441	/* If Overrun error occurs, or if any error occurs in DMA mode reception,
<>	144:ef7eb2e8f9f7	1442	consider error as blocking */
<>	144:ef7eb2e8f9f7	1443	dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1444	if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) \|\| dmarequest)
<>	144:ef7eb2e8f9f7	1445	{
<>	144:ef7eb2e8f9f7	1446	/* Set the USART state ready to be able to start again the process,
<>	144:ef7eb2e8f9f7	1447	Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<>	144:ef7eb2e8f9f7	1448	USART_EndRxTransfer(husart);
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/* Disable the USART DMA Rx request if enabled */
<>	144:ef7eb2e8f9f7	1451	if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<>	144:ef7eb2e8f9f7	1452	{
<>	144:ef7eb2e8f9f7	1453	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455	/* Abort the USART DMA Rx channel */
<>	144:ef7eb2e8f9f7	1456	if(husart->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1457	{
<>	144:ef7eb2e8f9f7	1458	/* Set the USART DMA Abort callback :
<>	144:ef7eb2e8f9f7	1459	will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	1460	husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
<>	144:ef7eb2e8f9f7	1463	{
<>	144:ef7eb2e8f9f7	1464	/* Call Directly XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	1465	husart->hdmarx->XferAbortCallback(husart->hdmarx);
<>	144:ef7eb2e8f9f7	1466	}
<>	144:ef7eb2e8f9f7	1467	}
<>	144:ef7eb2e8f9f7	1468	else
<>	144:ef7eb2e8f9f7	1469	{
<>	144:ef7eb2e8f9f7	1470	/* Call user error callback */
<>	144:ef7eb2e8f9f7	1471	HAL_USART_ErrorCallback(husart);
<>	144:ef7eb2e8f9f7	1472	}
<>	144:ef7eb2e8f9f7	1473	}
<>	144:ef7eb2e8f9f7	1474	else
<>	144:ef7eb2e8f9f7	1475	{
<>	144:ef7eb2e8f9f7	1476	/* Call user error callback */
<>	144:ef7eb2e8f9f7	1477	HAL_USART_ErrorCallback(husart);
<>	144:ef7eb2e8f9f7	1478	}
<>	144:ef7eb2e8f9f7	1479	}
<>	144:ef7eb2e8f9f7	1480	else
<>	144:ef7eb2e8f9f7	1481	{
<>	144:ef7eb2e8f9f7	1482	/* Call user error callback */
<>	144:ef7eb2e8f9f7	1483	HAL_USART_ErrorCallback(husart);
<>	144:ef7eb2e8f9f7	1484	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1485	}
<>	144:ef7eb2e8f9f7	1486	}
<>	144:ef7eb2e8f9f7	1487	return;
<>	144:ef7eb2e8f9f7	1488	}
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	/* USART in mode Transmitter -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1491	if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<>	144:ef7eb2e8f9f7	1492	{
<>	144:ef7eb2e8f9f7	1493	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1494	{
<>	144:ef7eb2e8f9f7	1495	USART_Transmit_IT(husart);
<>	144:ef7eb2e8f9f7	1496	}
<>	144:ef7eb2e8f9f7	1497	else
<>	144:ef7eb2e8f9f7	1498	{
<>	144:ef7eb2e8f9f7	1499	USART_TransmitReceive_IT(husart);
<>	144:ef7eb2e8f9f7	1500	}
<>	144:ef7eb2e8f9f7	1501	return;
<>	144:ef7eb2e8f9f7	1502	}
<>	144:ef7eb2e8f9f7	1503
<>	144:ef7eb2e8f9f7	1504	/* USART in mode Transmitter (transmission end) ----------------------------*/
<>	144:ef7eb2e8f9f7	1505	if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<>	144:ef7eb2e8f9f7	1506	{
<>	144:ef7eb2e8f9f7	1507	USART_EndTransmit_IT(husart);
<>	144:ef7eb2e8f9f7	1508	return;
<>	144:ef7eb2e8f9f7	1509	}
<>	144:ef7eb2e8f9f7	1510	}
<>	144:ef7eb2e8f9f7	1511
<>	144:ef7eb2e8f9f7	1512	/**
<>	144:ef7eb2e8f9f7	1513	* @brief Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1514	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1515	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1516	* @retval None
<>	144:ef7eb2e8f9f7	1517	*/
<>	144:ef7eb2e8f9f7	1518	__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1519	{
<>	144:ef7eb2e8f9f7	1520	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1521	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1522	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1523	the HAL_USART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1524	*/
<>	144:ef7eb2e8f9f7	1525	}
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/**
<>	144:ef7eb2e8f9f7	1528	* @brief Tx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1529	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1530	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1531	* @retval None
<>	144:ef7eb2e8f9f7	1532	*/
<>	144:ef7eb2e8f9f7	1533	__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1534	{
<>	144:ef7eb2e8f9f7	1535	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1536	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1537	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1538	the HAL_USART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1539	*/
<>	144:ef7eb2e8f9f7	1540	}
<>	144:ef7eb2e8f9f7	1541
<>	144:ef7eb2e8f9f7	1542	/**
<>	144:ef7eb2e8f9f7	1543	* @brief Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1544	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1545	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1546	* @retval None
<>	144:ef7eb2e8f9f7	1547	*/
<>	144:ef7eb2e8f9f7	1548	__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1549	{
<>	144:ef7eb2e8f9f7	1550	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1551	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1552	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1553	the HAL_USART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1554	*/
<>	144:ef7eb2e8f9f7	1555	}
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	/**
<>	144:ef7eb2e8f9f7	1558	* @brief Rx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1559	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1560	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1561	* @retval None
<>	144:ef7eb2e8f9f7	1562	*/
<>	144:ef7eb2e8f9f7	1563	__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1564	{
<>	144:ef7eb2e8f9f7	1565	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1566	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1567	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1568	the HAL_USART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1569	*/
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/**
<>	144:ef7eb2e8f9f7	1573	* @brief Tx/Rx Transfers completed callback for the non-blocking process.
<>	144:ef7eb2e8f9f7	1574	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1575	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1576	* @retval None
<>	144:ef7eb2e8f9f7	1577	*/
<>	144:ef7eb2e8f9f7	1578	__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1579	{
<>	144:ef7eb2e8f9f7	1580	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1581	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1582	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1583	the HAL_USART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1584	*/
<>	144:ef7eb2e8f9f7	1585	}
<>	144:ef7eb2e8f9f7	1586
<>	144:ef7eb2e8f9f7	1587	/**
<>	144:ef7eb2e8f9f7	1588	* @brief USART error callbacks.
<>	144:ef7eb2e8f9f7	1589	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1590	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1591	* @retval None
<>	144:ef7eb2e8f9f7	1592	*/
<>	144:ef7eb2e8f9f7	1593	__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1594	{
<>	144:ef7eb2e8f9f7	1595	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1596	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1597	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1598	the HAL_USART_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1599	*/
<>	144:ef7eb2e8f9f7	1600	}
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/**
AnnaBridge	167:e84263d55307	1603	* @brief USART Abort Complete callback.
AnnaBridge	167:e84263d55307	1604	* @param husart USART handle.
AnnaBridge	167:e84263d55307	1605	* @retval None
AnnaBridge	167:e84263d55307	1606	*/
AnnaBridge	167:e84263d55307	1607	__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
AnnaBridge	167:e84263d55307	1608	{
AnnaBridge	167:e84263d55307	1609	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	1610	UNUSED(husart);
AnnaBridge	167:e84263d55307	1611
AnnaBridge	167:e84263d55307	1612	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	167:e84263d55307	1613	the HAL_USART_AbortCpltCallback can be implemented in the user file.
AnnaBridge	167:e84263d55307	1614	*/
AnnaBridge	167:e84263d55307	1615	}
AnnaBridge	167:e84263d55307	1616
AnnaBridge	167:e84263d55307	1617	/**
<>	144:ef7eb2e8f9f7	1618	* @}
<>	144:ef7eb2e8f9f7	1619	*/
<>	144:ef7eb2e8f9f7	1620
<>	144:ef7eb2e8f9f7	1621	/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	1622	* @brief USART State and Errors functions
<>	144:ef7eb2e8f9f7	1623	*
<>	144:ef7eb2e8f9f7	1624	@verbatim
<>	144:ef7eb2e8f9f7	1625	==============================================================================
<>	144:ef7eb2e8f9f7	1626	##### Peripheral State and Errors functions #####
<>	144:ef7eb2e8f9f7	1627	==============================================================================
<>	144:ef7eb2e8f9f7	1628	[..]
<>	144:ef7eb2e8f9f7	1629	This subsection provides a set of functions allowing to return the State of
<>	144:ef7eb2e8f9f7	1630	USART communication
<>	144:ef7eb2e8f9f7	1631	process, return Peripheral Errors occurred during communication process
<>	144:ef7eb2e8f9f7	1632	(+) HAL_USART_GetState() API can be helpful to check in run-time the state
<>	144:ef7eb2e8f9f7	1633	of the USART peripheral.
<>	144:ef7eb2e8f9f7	1634	(+) HAL_USART_GetError() check in run-time errors that could be occurred during
<>	144:ef7eb2e8f9f7	1635	communication.
<>	144:ef7eb2e8f9f7	1636	@endverbatim
<>	144:ef7eb2e8f9f7	1637	* @{
<>	144:ef7eb2e8f9f7	1638	*/
<>	144:ef7eb2e8f9f7	1639
<>	144:ef7eb2e8f9f7	1640	/**
<>	144:ef7eb2e8f9f7	1641	* @brief Returns the USART state.
<>	144:ef7eb2e8f9f7	1642	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1643	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1644	* @retval HAL state
<>	144:ef7eb2e8f9f7	1645	*/
<>	144:ef7eb2e8f9f7	1646	HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1647	{
<>	144:ef7eb2e8f9f7	1648	return husart->State;
<>	144:ef7eb2e8f9f7	1649	}
<>	144:ef7eb2e8f9f7	1650
<>	144:ef7eb2e8f9f7	1651	/**
<>	144:ef7eb2e8f9f7	1652	* @brief Return the USART error code
<>	144:ef7eb2e8f9f7	1653	* @param husart : pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1654	* the configuration information for the specified USART.
<>	144:ef7eb2e8f9f7	1655	* @retval USART Error Code
<>	144:ef7eb2e8f9f7	1656	*/
<>	144:ef7eb2e8f9f7	1657	uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1658	{
<>	144:ef7eb2e8f9f7	1659	return husart->ErrorCode;
<>	144:ef7eb2e8f9f7	1660	}
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	/**
<>	144:ef7eb2e8f9f7	1663	* @}
<>	144:ef7eb2e8f9f7	1664	*/
<>	144:ef7eb2e8f9f7	1665
<>	144:ef7eb2e8f9f7	1666	/**
<>	144:ef7eb2e8f9f7	1667	* @brief DMA USART transmit process complete callback.
<>	144:ef7eb2e8f9f7	1668	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	1669	* @retval None
<>	144:ef7eb2e8f9f7	1670	*/
<>	144:ef7eb2e8f9f7	1671	static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1672	{
<>	144:ef7eb2e8f9f7	1673	USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	1674	/* DMA Normal mode */
<>	144:ef7eb2e8f9f7	1675	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<>	144:ef7eb2e8f9f7	1676	{
AnnaBridge	167:e84263d55307	1677	husart->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	1678	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1679	{
<>	144:ef7eb2e8f9f7	1680	/* Disable the DMA transfer for transmit request by resetting the DMAT bit
<>	144:ef7eb2e8f9f7	1681	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	1682	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1683
<>	144:ef7eb2e8f9f7	1684	/* Enable the USART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	1685	SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	1686	}
<>	144:ef7eb2e8f9f7	1687	}
<>	144:ef7eb2e8f9f7	1688	/* DMA Circular mode */
<>	144:ef7eb2e8f9f7	1689	else
<>	144:ef7eb2e8f9f7	1690	{
<>	144:ef7eb2e8f9f7	1691	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1692	{
<>	144:ef7eb2e8f9f7	1693	HAL_USART_TxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	1694	}
<>	144:ef7eb2e8f9f7	1695	}
<>	144:ef7eb2e8f9f7	1696	}
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/**
<>	144:ef7eb2e8f9f7	1699	* @brief DMA USART transmit process half complete callback
<>	144:ef7eb2e8f9f7	1700	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1701	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	1702	* @retval None
<>	144:ef7eb2e8f9f7	1703	*/
<>	144:ef7eb2e8f9f7	1704	static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1705	{
<>	144:ef7eb2e8f9f7	1706	USART_HandleTypeDef* husart = (USART_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	1707
<>	144:ef7eb2e8f9f7	1708	HAL_USART_TxHalfCpltCallback(husart);
<>	144:ef7eb2e8f9f7	1709	}
<>	144:ef7eb2e8f9f7	1710
<>	144:ef7eb2e8f9f7	1711	/**
<>	144:ef7eb2e8f9f7	1712	* @brief DMA USART receive process complete callback.
<>	144:ef7eb2e8f9f7	1713	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	1714	* @retval None
<>	144:ef7eb2e8f9f7	1715	*/
<>	144:ef7eb2e8f9f7	1716	static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1717	{
<>	144:ef7eb2e8f9f7	1718	USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	1719	/* DMA Normal mode */
<>	144:ef7eb2e8f9f7	1720	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<>	144:ef7eb2e8f9f7	1721	{
AnnaBridge	167:e84263d55307	1722	husart->RxXferCount = 0x00;
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	1725	CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1726	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1727
<>	144:ef7eb2e8f9f7	1728	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1729	{
<>	144:ef7eb2e8f9f7	1730	/* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
<>	144:ef7eb2e8f9f7	1731	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	1732	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	husart->State= HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	1735	HAL_USART_RxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	1736	}
<>	144:ef7eb2e8f9f7	1737	/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
<>	144:ef7eb2e8f9f7	1738	else
<>	144:ef7eb2e8f9f7	1739	{
<>	144:ef7eb2e8f9f7	1740	/* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
<>	144:ef7eb2e8f9f7	1741	in the USART CR3 register */
<>	144:ef7eb2e8f9f7	1742	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1743	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1744
<>	144:ef7eb2e8f9f7	1745	husart->State= HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	1746	HAL_USART_TxRxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	1747	}
<>	144:ef7eb2e8f9f7	1748	}
<>	144:ef7eb2e8f9f7	1749	/* DMA circular mode */
<>	144:ef7eb2e8f9f7	1750	else
<>	144:ef7eb2e8f9f7	1751	{
<>	144:ef7eb2e8f9f7	1752	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1753	{
<>	144:ef7eb2e8f9f7	1754	HAL_USART_RxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	1755	}
<>	144:ef7eb2e8f9f7	1756	/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
<>	144:ef7eb2e8f9f7	1757	else
<>	144:ef7eb2e8f9f7	1758	{
<>	144:ef7eb2e8f9f7	1759	HAL_USART_TxRxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	1760	}
<>	144:ef7eb2e8f9f7	1761	}
<>	144:ef7eb2e8f9f7	1762	}
<>	144:ef7eb2e8f9f7	1763
<>	144:ef7eb2e8f9f7	1764	/**
<>	144:ef7eb2e8f9f7	1765	* @brief DMA USART receive process half complete callback
<>	144:ef7eb2e8f9f7	1766	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1767	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	1768	* @retval None
<>	144:ef7eb2e8f9f7	1769	*/
<>	144:ef7eb2e8f9f7	1770	static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1771	{
<>	144:ef7eb2e8f9f7	1772	USART_HandleTypeDef* husart = (USART_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	1773
<>	144:ef7eb2e8f9f7	1774	HAL_USART_RxHalfCpltCallback(husart);
<>	144:ef7eb2e8f9f7	1775	}
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/**
<>	144:ef7eb2e8f9f7	1778	* @brief DMA USART communication error callback.
<>	144:ef7eb2e8f9f7	1779	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	1780	* @retval None
<>	144:ef7eb2e8f9f7	1781	*/
<>	144:ef7eb2e8f9f7	1782	static void USART_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1783	{
<>	144:ef7eb2e8f9f7	1784	uint32_t dmarequest = 0x00U;
<>	144:ef7eb2e8f9f7	1785	USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	1786	husart->RxXferCount = 0x00;
AnnaBridge	167:e84263d55307	1787	husart->TxXferCount = 0x00;
<>	144:ef7eb2e8f9f7	1788
<>	144:ef7eb2e8f9f7	1789	/* Stop USART DMA Tx request if ongoing */
<>	144:ef7eb2e8f9f7	1790	dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1791	if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
<>	144:ef7eb2e8f9f7	1792	{
<>	144:ef7eb2e8f9f7	1793	USART_EndTxTransfer(husart);
<>	144:ef7eb2e8f9f7	1794	}
<>	144:ef7eb2e8f9f7	1795
<>	144:ef7eb2e8f9f7	1796	/* Stop USART DMA Rx request if ongoing */
<>	144:ef7eb2e8f9f7	1797	dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1798	if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
<>	144:ef7eb2e8f9f7	1799	{
<>	144:ef7eb2e8f9f7	1800	USART_EndRxTransfer(husart);
<>	144:ef7eb2e8f9f7	1801	}
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	husart->ErrorCode \|= HAL_USART_ERROR_DMA;
<>	144:ef7eb2e8f9f7	1804	husart->State= HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	1805
<>	144:ef7eb2e8f9f7	1806	HAL_USART_ErrorCallback(husart);
<>	144:ef7eb2e8f9f7	1807	}
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	/**
<>	144:ef7eb2e8f9f7	1810	* @brief This function handles USART Communication Timeout.
<>	144:ef7eb2e8f9f7	1811	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1812	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1813	* @param Flag: specifies the USART flag to check.
<>	144:ef7eb2e8f9f7	1814	* @param Status: The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	1815	* @param Tickstart: Tick start value.
<>	144:ef7eb2e8f9f7	1816	* @param Timeout: Timeout duration.
<>	144:ef7eb2e8f9f7	1817	* @retval HAL status
<>	144:ef7eb2e8f9f7	1818	*/
<>	144:ef7eb2e8f9f7	1819	static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1820	{
<>	144:ef7eb2e8f9f7	1821	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	1822	while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
<>	144:ef7eb2e8f9f7	1823	{
<>	144:ef7eb2e8f9f7	1824	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	1825	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1826	{
<>	144:ef7eb2e8f9f7	1827	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	1828	{
<>	144:ef7eb2e8f9f7	1829	/* Disable the USART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	1830	CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	1831
<>	144:ef7eb2e8f9f7	1832	/* Disable the USART RXNE Interrupt */
<>	144:ef7eb2e8f9f7	1833	CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
<>	144:ef7eb2e8f9f7	1834
<>	144:ef7eb2e8f9f7	1835	/* Disable the USART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	1836	CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1837
<>	144:ef7eb2e8f9f7	1838	/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	1839	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1840
<>	144:ef7eb2e8f9f7	1841	husart->State= HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	1842
<>	144:ef7eb2e8f9f7	1843	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1844	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	1845
<>	144:ef7eb2e8f9f7	1846	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1847	}
<>	144:ef7eb2e8f9f7	1848	}
<>	144:ef7eb2e8f9f7	1849	}
<>	144:ef7eb2e8f9f7	1850	return HAL_OK;
<>	144:ef7eb2e8f9f7	1851	}
<>	144:ef7eb2e8f9f7	1852
<>	144:ef7eb2e8f9f7	1853	/**
<>	144:ef7eb2e8f9f7	1854	* @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
<>	144:ef7eb2e8f9f7	1855	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1856	* @retval None
<>	144:ef7eb2e8f9f7	1857	*/
<>	144:ef7eb2e8f9f7	1858	static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1859	{
<>	144:ef7eb2e8f9f7	1860	/* Disable TXEIE and TCIE interrupts */
<>	144:ef7eb2e8f9f7	1861	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	144:ef7eb2e8f9f7	1862
<>	144:ef7eb2e8f9f7	1863	/* At end of Tx process, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	1864	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	1865	}
<>	144:ef7eb2e8f9f7	1866
<>	144:ef7eb2e8f9f7	1867	/**
<>	144:ef7eb2e8f9f7	1868	* @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
<>	144:ef7eb2e8f9f7	1869	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1870	* @retval None
<>	144:ef7eb2e8f9f7	1871	*/
<>	144:ef7eb2e8f9f7	1872	static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1873	{
<>	144:ef7eb2e8f9f7	1874	/* Disable RXNE, PE and ERR interrupts */
<>	144:ef7eb2e8f9f7	1875	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	144:ef7eb2e8f9f7	1876	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1877
<>	144:ef7eb2e8f9f7	1878	/* At end of Rx process, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	1879	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	1880	}
<>	144:ef7eb2e8f9f7	1881
<>	144:ef7eb2e8f9f7	1882	/**
<>	144:ef7eb2e8f9f7	1883	* @brief DMA USART communication abort callback, when initiated by HAL services on Error
<>	144:ef7eb2e8f9f7	1884	* (To be called at end of DMA Abort procedure following error occurrence).
<>	144:ef7eb2e8f9f7	1885	* @param hdma DMA handle.
<>	144:ef7eb2e8f9f7	1886	* @retval None
<>	144:ef7eb2e8f9f7	1887	*/
<>	144:ef7eb2e8f9f7	1888	static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1889	{
<>	144:ef7eb2e8f9f7	1890	USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	1891	husart->RxXferCount = 0x00;
AnnaBridge	167:e84263d55307	1892	husart->TxXferCount = 0x00;
<>	144:ef7eb2e8f9f7	1893
<>	144:ef7eb2e8f9f7	1894	HAL_USART_ErrorCallback(husart);
<>	144:ef7eb2e8f9f7	1895	}
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	/**
AnnaBridge	167:e84263d55307	1898	* @brief DMA USART Tx communication abort callback, when initiated by user
AnnaBridge	167:e84263d55307	1899	* (To be called at end of DMA Tx Abort procedure following user abort request).
AnnaBridge	167:e84263d55307	1900	* @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge	167:e84263d55307	1901	* Abort still ongoing for Rx DMA Handle.
AnnaBridge	167:e84263d55307	1902	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	1903	* @retval None
AnnaBridge	167:e84263d55307	1904	*/
AnnaBridge	167:e84263d55307	1905	static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	1906	{
AnnaBridge	167:e84263d55307	1907	USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	1908
AnnaBridge	167:e84263d55307	1909	husart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1910
AnnaBridge	167:e84263d55307	1911	/* Check if an Abort process is still ongoing */
AnnaBridge	167:e84263d55307	1912	if(husart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1913	{
AnnaBridge	167:e84263d55307	1914	if(husart->hdmarx->XferAbortCallback != NULL)
AnnaBridge	167:e84263d55307	1915	{
AnnaBridge	167:e84263d55307	1916	return;
AnnaBridge	167:e84263d55307	1917	}
AnnaBridge	167:e84263d55307	1918	}
AnnaBridge	167:e84263d55307	1919
AnnaBridge	167:e84263d55307	1920	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
AnnaBridge	167:e84263d55307	1921	husart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1922	husart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1923
AnnaBridge	167:e84263d55307	1924	/* Reset errorCode */
AnnaBridge	167:e84263d55307	1925	husart->ErrorCode = HAL_USART_ERROR_NONE;
AnnaBridge	167:e84263d55307	1926
AnnaBridge	167:e84263d55307	1927	/* Restore husart->State to Ready */
AnnaBridge	167:e84263d55307	1928	husart->State = HAL_USART_STATE_READY;
AnnaBridge	167:e84263d55307	1929
AnnaBridge	167:e84263d55307	1930	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	1931	HAL_USART_AbortCpltCallback(husart);
AnnaBridge	167:e84263d55307	1932	}
AnnaBridge	167:e84263d55307	1933
AnnaBridge	167:e84263d55307	1934	/**
AnnaBridge	167:e84263d55307	1935	* @brief DMA USART Rx communication abort callback, when initiated by user
AnnaBridge	167:e84263d55307	1936	* (To be called at end of DMA Rx Abort procedure following user abort request).
AnnaBridge	167:e84263d55307	1937	* @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge	167:e84263d55307	1938	* Abort still ongoing for Tx DMA Handle.
AnnaBridge	167:e84263d55307	1939	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	1940	* @retval None
AnnaBridge	167:e84263d55307	1941	*/
AnnaBridge	167:e84263d55307	1942	static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	1943	{
AnnaBridge	167:e84263d55307	1944	USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	1945
AnnaBridge	167:e84263d55307	1946	husart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1947
AnnaBridge	167:e84263d55307	1948	/* Check if an Abort process is still ongoing */
AnnaBridge	167:e84263d55307	1949	if(husart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1950	{
AnnaBridge	167:e84263d55307	1951	if(husart->hdmatx->XferAbortCallback != NULL)
AnnaBridge	167:e84263d55307	1952	{
AnnaBridge	167:e84263d55307	1953	return;
AnnaBridge	167:e84263d55307	1954	}
AnnaBridge	167:e84263d55307	1955	}
AnnaBridge	167:e84263d55307	1956
AnnaBridge	167:e84263d55307	1957	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
AnnaBridge	167:e84263d55307	1958	husart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1959	husart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1960
AnnaBridge	167:e84263d55307	1961	/* Reset errorCode */
AnnaBridge	167:e84263d55307	1962	husart->ErrorCode = HAL_USART_ERROR_NONE;
AnnaBridge	167:e84263d55307	1963
AnnaBridge	167:e84263d55307	1964	/* Restore husart->State to Ready */
AnnaBridge	167:e84263d55307	1965	husart->State = HAL_USART_STATE_READY;
AnnaBridge	167:e84263d55307	1966
AnnaBridge	167:e84263d55307	1967	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	1968	HAL_USART_AbortCpltCallback(husart);
AnnaBridge	167:e84263d55307	1969	}
AnnaBridge	167:e84263d55307	1970
AnnaBridge	167:e84263d55307	1971	/**
<>	144:ef7eb2e8f9f7	1972	* @brief Simplex Send an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	1973	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1974	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	1975	* @retval HAL status
<>	144:ef7eb2e8f9f7	1976	* @note The USART errors are not managed to avoid the overrun error.
<>	144:ef7eb2e8f9f7	1977	*/
<>	144:ef7eb2e8f9f7	1978	static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1979	{
<>	144:ef7eb2e8f9f7	1980	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1983	{
<>	144:ef7eb2e8f9f7	1984	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	1985	{
<>	144:ef7eb2e8f9f7	1986	tmp = (uint16_t*) husart->pTxBuffPtr;
AnnaBridge	167:e84263d55307	1987	husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	1988	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	1989	{
AnnaBridge	167:e84263d55307	1990	husart->pTxBuffPtr += 2;
<>	144:ef7eb2e8f9f7	1991	}
<>	144:ef7eb2e8f9f7	1992	else
<>	144:ef7eb2e8f9f7	1993	{
AnnaBridge	167:e84263d55307	1994	husart->pTxBuffPtr += 1;
<>	144:ef7eb2e8f9f7	1995	}
<>	144:ef7eb2e8f9f7	1996	}
<>	144:ef7eb2e8f9f7	1997	else
<>	144:ef7eb2e8f9f7	1998	{
AnnaBridge	167:e84263d55307	1999	husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	2000	}
<>	144:ef7eb2e8f9f7	2001
AnnaBridge	167:e84263d55307	2002	if(--husart->TxXferCount == 0)
<>	144:ef7eb2e8f9f7	2003	{
<>	144:ef7eb2e8f9f7	2004	/* Disable the USART Transmit data register empty Interrupt */
<>	144:ef7eb2e8f9f7	2005	CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007	/* Enable the USART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2008	SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	2009	}
<>	144:ef7eb2e8f9f7	2010	return HAL_OK;
<>	144:ef7eb2e8f9f7	2011	}
<>	144:ef7eb2e8f9f7	2012	else
<>	144:ef7eb2e8f9f7	2013	{
<>	144:ef7eb2e8f9f7	2014	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2015	}
<>	144:ef7eb2e8f9f7	2016	}
<>	144:ef7eb2e8f9f7	2017
<>	144:ef7eb2e8f9f7	2018	/**
<>	144:ef7eb2e8f9f7	2019	* @brief Wraps up transmission in non blocking mode.
<>	144:ef7eb2e8f9f7	2020	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2021	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	2022	* @retval HAL status
<>	144:ef7eb2e8f9f7	2023	*/
<>	144:ef7eb2e8f9f7	2024	static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2025	{
<>	144:ef7eb2e8f9f7	2026	/* Disable the USART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2027	CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	2028
<>	144:ef7eb2e8f9f7	2029	/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	2030	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2031
<>	144:ef7eb2e8f9f7	2032	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	2033
<>	144:ef7eb2e8f9f7	2034	HAL_USART_TxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	2035
<>	144:ef7eb2e8f9f7	2036	return HAL_OK;
<>	144:ef7eb2e8f9f7	2037	}
<>	144:ef7eb2e8f9f7	2038
<>	144:ef7eb2e8f9f7	2039	/**
<>	144:ef7eb2e8f9f7	2040	* @brief Simplex Receive an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	2041	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2042	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	2043	* @retval HAL status
<>	144:ef7eb2e8f9f7	2044	*/
<>	144:ef7eb2e8f9f7	2045	static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2046	{
<>	144:ef7eb2e8f9f7	2047	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	2048	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	2049	{
<>	144:ef7eb2e8f9f7	2050	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	2051	{
<>	144:ef7eb2e8f9f7	2052	tmp = (uint16_t*) husart->pRxBuffPtr;
<>	144:ef7eb2e8f9f7	2053	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2054	{
AnnaBridge	167:e84263d55307	2055	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
AnnaBridge	167:e84263d55307	2056	husart->pRxBuffPtr += 2;
<>	144:ef7eb2e8f9f7	2057	}
<>	144:ef7eb2e8f9f7	2058	else
<>	144:ef7eb2e8f9f7	2059	{
AnnaBridge	167:e84263d55307	2060	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
AnnaBridge	167:e84263d55307	2061	husart->pRxBuffPtr += 1;
<>	144:ef7eb2e8f9f7	2062	}
AnnaBridge	167:e84263d55307	2063	if(--husart->RxXferCount != 0x00)
<>	144:ef7eb2e8f9f7	2064	{
<>	144:ef7eb2e8f9f7	2065	/* Send dummy byte in order to generate the clock for the slave to send the next data */
AnnaBridge	167:e84263d55307	2066	husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	2067	}
<>	144:ef7eb2e8f9f7	2068	}
<>	144:ef7eb2e8f9f7	2069	else
<>	144:ef7eb2e8f9f7	2070	{
<>	144:ef7eb2e8f9f7	2071	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2072	{
AnnaBridge	167:e84263d55307	2073	*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	2074	}
<>	144:ef7eb2e8f9f7	2075	else
<>	144:ef7eb2e8f9f7	2076	{
AnnaBridge	167:e84263d55307	2077	*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
<>	144:ef7eb2e8f9f7	2078	}
<>	144:ef7eb2e8f9f7	2079
AnnaBridge	167:e84263d55307	2080	if(--husart->RxXferCount != 0x00)
<>	144:ef7eb2e8f9f7	2081	{
<>	144:ef7eb2e8f9f7	2082	/* Send dummy byte in order to generate the clock for the slave to send the next data */
AnnaBridge	167:e84263d55307	2083	husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
<>	144:ef7eb2e8f9f7	2084	}
<>	144:ef7eb2e8f9f7	2085	}
<>	144:ef7eb2e8f9f7	2086
AnnaBridge	167:e84263d55307	2087	if(husart->RxXferCount == 0)
<>	144:ef7eb2e8f9f7	2088	{
<>	144:ef7eb2e8f9f7	2089	/* Disable the USART RXNE Interrupt */
<>	144:ef7eb2e8f9f7	2090	CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
<>	144:ef7eb2e8f9f7	2091
<>	144:ef7eb2e8f9f7	2092	/* Disable the USART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	2093	CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	2094
<>	144:ef7eb2e8f9f7	2095	/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	2096	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2097
<>	144:ef7eb2e8f9f7	2098	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	2099	HAL_USART_RxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	2100
<>	144:ef7eb2e8f9f7	2101	return HAL_OK;
<>	144:ef7eb2e8f9f7	2102	}
<>	144:ef7eb2e8f9f7	2103	return HAL_OK;
<>	144:ef7eb2e8f9f7	2104	}
<>	144:ef7eb2e8f9f7	2105	else
<>	144:ef7eb2e8f9f7	2106	{
<>	144:ef7eb2e8f9f7	2107	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2108	}
<>	144:ef7eb2e8f9f7	2109	}
<>	144:ef7eb2e8f9f7	2110
<>	144:ef7eb2e8f9f7	2111	/**
<>	144:ef7eb2e8f9f7	2112	* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
<>	144:ef7eb2e8f9f7	2113	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2114	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	2115	* @retval HAL status
<>	144:ef7eb2e8f9f7	2116	*/
<>	144:ef7eb2e8f9f7	2117	static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2118	{
<>	144:ef7eb2e8f9f7	2119	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	2120
<>	144:ef7eb2e8f9f7	2121	if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
<>	144:ef7eb2e8f9f7	2122	{
AnnaBridge	167:e84263d55307	2123	if(husart->TxXferCount != 0x00)
<>	144:ef7eb2e8f9f7	2124	{
<>	144:ef7eb2e8f9f7	2125	if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
<>	144:ef7eb2e8f9f7	2126	{
<>	144:ef7eb2e8f9f7	2127	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	2128	{
<>	144:ef7eb2e8f9f7	2129	tmp = (uint16_t*) husart->pTxBuffPtr;
AnnaBridge	167:e84263d55307	2130	husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	2131	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2132	{
AnnaBridge	167:e84263d55307	2133	husart->pTxBuffPtr += 2;
<>	144:ef7eb2e8f9f7	2134	}
<>	144:ef7eb2e8f9f7	2135	else
<>	144:ef7eb2e8f9f7	2136	{
AnnaBridge	167:e84263d55307	2137	husart->pTxBuffPtr += 1;
<>	144:ef7eb2e8f9f7	2138	}
<>	144:ef7eb2e8f9f7	2139	}
<>	144:ef7eb2e8f9f7	2140	else
<>	144:ef7eb2e8f9f7	2141	{
AnnaBridge	167:e84263d55307	2142	husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	2143	}
<>	144:ef7eb2e8f9f7	2144	husart->TxXferCount--;
<>	144:ef7eb2e8f9f7	2145
<>	144:ef7eb2e8f9f7	2146	/* Check the latest data transmitted */
AnnaBridge	167:e84263d55307	2147	if(husart->TxXferCount == 0)
<>	144:ef7eb2e8f9f7	2148	{
<>	144:ef7eb2e8f9f7	2149	CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	2150	}
<>	144:ef7eb2e8f9f7	2151	}
<>	144:ef7eb2e8f9f7	2152	}
<>	144:ef7eb2e8f9f7	2153
AnnaBridge	167:e84263d55307	2154	if(husart->RxXferCount != 0x00)
<>	144:ef7eb2e8f9f7	2155	{
<>	144:ef7eb2e8f9f7	2156	if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
<>	144:ef7eb2e8f9f7	2157	{
<>	144:ef7eb2e8f9f7	2158	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	2159	{
<>	144:ef7eb2e8f9f7	2160	tmp = (uint16_t*) husart->pRxBuffPtr;
<>	144:ef7eb2e8f9f7	2161	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2162	{
AnnaBridge	167:e84263d55307	2163	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
AnnaBridge	167:e84263d55307	2164	husart->pRxBuffPtr += 2;
<>	144:ef7eb2e8f9f7	2165	}
<>	144:ef7eb2e8f9f7	2166	else
<>	144:ef7eb2e8f9f7	2167	{
AnnaBridge	167:e84263d55307	2168	*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
AnnaBridge	167:e84263d55307	2169	husart->pRxBuffPtr += 1;
<>	144:ef7eb2e8f9f7	2170	}
<>	144:ef7eb2e8f9f7	2171	}
<>	144:ef7eb2e8f9f7	2172	else
<>	144:ef7eb2e8f9f7	2173	{
<>	144:ef7eb2e8f9f7	2174	if(husart->Init.Parity == USART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2175	{
AnnaBridge	167:e84263d55307	2176	*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	2177	}
<>	144:ef7eb2e8f9f7	2178	else
<>	144:ef7eb2e8f9f7	2179	{
AnnaBridge	167:e84263d55307	2180	*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
<>	144:ef7eb2e8f9f7	2181	}
<>	144:ef7eb2e8f9f7	2182	}
<>	144:ef7eb2e8f9f7	2183	husart->RxXferCount--;
<>	144:ef7eb2e8f9f7	2184	}
<>	144:ef7eb2e8f9f7	2185	}
<>	144:ef7eb2e8f9f7	2186
<>	144:ef7eb2e8f9f7	2187	/* Check the latest data received */
AnnaBridge	167:e84263d55307	2188	if(husart->RxXferCount == 0)
<>	144:ef7eb2e8f9f7	2189	{
<>	144:ef7eb2e8f9f7	2190	/* Disable the USART RXNE Interrupt */
<>	144:ef7eb2e8f9f7	2191	CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
<>	144:ef7eb2e8f9f7	2192
<>	144:ef7eb2e8f9f7	2193	/* Disable the USART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	2194	CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	2195
<>	144:ef7eb2e8f9f7	2196	/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	2197	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2198
<>	144:ef7eb2e8f9f7	2199	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	2200
<>	144:ef7eb2e8f9f7	2201	HAL_USART_TxRxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	2202
<>	144:ef7eb2e8f9f7	2203	return HAL_OK;
<>	144:ef7eb2e8f9f7	2204	}
<>	144:ef7eb2e8f9f7	2205
<>	144:ef7eb2e8f9f7	2206	return HAL_OK;
<>	144:ef7eb2e8f9f7	2207	}
<>	144:ef7eb2e8f9f7	2208	else
<>	144:ef7eb2e8f9f7	2209	{
<>	144:ef7eb2e8f9f7	2210	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2211	}
<>	144:ef7eb2e8f9f7	2212	}
<>	144:ef7eb2e8f9f7	2213
<>	144:ef7eb2e8f9f7	2214	/**
<>	144:ef7eb2e8f9f7	2215	* @brief Configures the USART pferipheral.
<>	144:ef7eb2e8f9f7	2216	* @param husart: pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2217	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	2218	* @retval None
<>	144:ef7eb2e8f9f7	2219	*/
<>	144:ef7eb2e8f9f7	2220	static void USART_SetConfig(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2221	{
<>	144:ef7eb2e8f9f7	2222	uint32_t tmpreg = 0x00U;
<>	144:ef7eb2e8f9f7	2223
<>	144:ef7eb2e8f9f7	2224	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2225	assert_param(IS_USART_INSTANCE(husart->Instance));
<>	144:ef7eb2e8f9f7	2226	assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
<>	144:ef7eb2e8f9f7	2227	assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
<>	144:ef7eb2e8f9f7	2228	assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
<>	144:ef7eb2e8f9f7	2229	assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	2230	assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
<>	144:ef7eb2e8f9f7	2231	assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
<>	144:ef7eb2e8f9f7	2232	assert_param(IS_USART_PARITY(husart->Init.Parity));
<>	144:ef7eb2e8f9f7	2233	assert_param(IS_USART_MODE(husart->Init.Mode));
<>	144:ef7eb2e8f9f7	2234
<>	144:ef7eb2e8f9f7	2235	/* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
<>	144:ef7eb2e8f9f7	2236	receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
<>	144:ef7eb2e8f9f7	2237	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TE \| USART_CR1_RE));
<>	144:ef7eb2e8f9f7	2238
<>	144:ef7eb2e8f9f7	2239	/---------------------------- USART CR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	2240	tmpreg = husart->Instance->CR2;
<>	144:ef7eb2e8f9f7	2241	/* Clear CLKEN, CPOL, CPHA and LBCL bits */
<>	144:ef7eb2e8f9f7	2242	tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA \| USART_CR2_CPOL \| USART_CR2_CLKEN \| USART_CR2_LBCL \| USART_CR2_STOP));
<>	144:ef7eb2e8f9f7	2243	/* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
<>	144:ef7eb2e8f9f7	2244	/* Set CPOL bit according to husart->Init.CLKPolarity value */
<>	144:ef7eb2e8f9f7	2245	/* Set CPHA bit according to husart->Init.CLKPhase value */
<>	144:ef7eb2e8f9f7	2246	/* Set LBCL bit according to husart->Init.CLKLastBit value */
<>	144:ef7eb2e8f9f7	2247	/* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
<>	144:ef7eb2e8f9f7	2248	tmpreg \|= (uint32_t)(USART_CLOCK_ENABLE\| husart->Init.CLKPolarity \|
<>	144:ef7eb2e8f9f7	2249	husart->Init.CLKPhase\| husart->Init.CLKLastBit \| husart->Init.StopBits);
<>	144:ef7eb2e8f9f7	2250	/* Write to USART CR2 */
<>	144:ef7eb2e8f9f7	2251	WRITE_REG(husart->Instance->CR2, (uint32_t)tmpreg);
<>	144:ef7eb2e8f9f7	2252
<>	144:ef7eb2e8f9f7	2253	/-------------------------- USART CR1 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2254	tmpreg = husart->Instance->CR1;
<>	144:ef7eb2e8f9f7	2255
<>	144:ef7eb2e8f9f7	2256	/* Clear M, PCE, PS, TE, RE and OVER8 bits */
<>	144:ef7eb2e8f9f7	2257	tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M \| USART_CR1_PCE \| USART_CR1_PS \| USART_CR1_TE \| \
<>	144:ef7eb2e8f9f7	2258	USART_CR1_RE \| USART_CR1_OVER8));
<>	144:ef7eb2e8f9f7	2259
<>	144:ef7eb2e8f9f7	2260	/* Configure the USART Word Length, Parity and mode:
<>	144:ef7eb2e8f9f7	2261	Set the M bits according to husart->Init.WordLength value
<>	144:ef7eb2e8f9f7	2262	Set PCE and PS bits according to husart->Init.Parity value
<>	144:ef7eb2e8f9f7	2263	Set TE and RE bits according to husart->Init.Mode value
<>	144:ef7eb2e8f9f7	2264	Force OVER8 bit to 1 in order to reach the max USART frequencies */
<>	144:ef7eb2e8f9f7	2265	tmpreg \|= (uint32_t)husart->Init.WordLength \| husart->Init.Parity \| husart->Init.Mode \| USART_CR1_OVER8;
<>	144:ef7eb2e8f9f7	2266
<>	144:ef7eb2e8f9f7	2267	/* Write to USART CR1 */
<>	144:ef7eb2e8f9f7	2268	WRITE_REG(husart->Instance->CR1, (uint32_t)tmpreg);
<>	144:ef7eb2e8f9f7	2269
<>	144:ef7eb2e8f9f7	2270	/-------------------------- USART CR3 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2271	/* Clear CTSE and RTSE bits */
<>	144:ef7eb2e8f9f7	2272	CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE \| USART_CR3_CTSE));
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274	/-------------------------- USART BRR Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2275	if((husart->Instance == USART1) \|\| (husart->Instance == USART6))
<>	144:ef7eb2e8f9f7	2276	{
<>	144:ef7eb2e8f9f7	2277	husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2278	}
<>	144:ef7eb2e8f9f7	2279	else
<>	144:ef7eb2e8f9f7	2280	{
<>	144:ef7eb2e8f9f7	2281	husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2282	}
<>	144:ef7eb2e8f9f7	2283	}
<>	144:ef7eb2e8f9f7	2284
<>	144:ef7eb2e8f9f7	2285	/**
<>	144:ef7eb2e8f9f7	2286	* @}
<>	144:ef7eb2e8f9f7	2287	*/
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	#endif /* HAL_USART_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2290	/**
<>	144:ef7eb2e8f9f7	2291	* @}
<>	144:ef7eb2e8f9f7	2292	*/
<>	144:ef7eb2e8f9f7	2293
<>	144:ef7eb2e8f9f7	2294	/**
<>	144:ef7eb2e8f9f7	2295	* @}
<>	144:ef7eb2e8f9f7	2296	*/
<>	144:ef7eb2e8f9f7	2297
<>	144:ef7eb2e8f9f7	2298	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/