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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_uart.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_uart.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief UART HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	@verbatim
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	18	==============================================================================
<>	144:ef7eb2e8f9f7	19	[..]
<>	144:ef7eb2e8f9f7	20	The UART HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	21
<>	144:ef7eb2e8f9f7	22	(#) Declare a UART_HandleTypeDef handle structure.
<>	144:ef7eb2e8f9f7	23
<>	144:ef7eb2e8f9f7	24	(#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
<>	144:ef7eb2e8f9f7	25	(##) Enable the USARTx interface clock.
<>	144:ef7eb2e8f9f7	26	(##) UART pins configuration:
<>	144:ef7eb2e8f9f7	27	(+++) Enable the clock for the UART GPIOs.
<>	144:ef7eb2e8f9f7	28	(+++) Configure these UART pins as alternate function pull-up.
<>	144:ef7eb2e8f9f7	29	(##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	30	and HAL_UART_Receive_IT() APIs):
<>	144:ef7eb2e8f9f7	31	(+++) Configure the USARTx interrupt priority.
<>	144:ef7eb2e8f9f7	32	(+++) Enable the NVIC USART IRQ handle.
<>	144:ef7eb2e8f9f7	33	(##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	34	and HAL_UART_Receive_DMA() APIs):
<>	144:ef7eb2e8f9f7	35	(+++) Declare a DMA handle structure for the Tx/Rx stream.
<>	144:ef7eb2e8f9f7	36	(+++) Enable the DMAx interface clock.
<>	144:ef7eb2e8f9f7	37	(+++) Configure the declared DMA handle structure with the required
<>	144:ef7eb2e8f9f7	38	Tx/Rx parameters.
<>	144:ef7eb2e8f9f7	39	(+++) Configure the DMA Tx/Rx Stream.
<>	144:ef7eb2e8f9f7	40	(+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
<>	144:ef7eb2e8f9f7	41	(+++) Configure the priority and enable the NVIC for the transfer complete
<>	144:ef7eb2e8f9f7	42	interrupt on the DMA Tx/Rx Stream.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
<>	144:ef7eb2e8f9f7	45	flow control and Mode(Receiver/Transmitter) in the Init structure.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) For the UART asynchronous mode, initialize the UART registers by calling
<>	144:ef7eb2e8f9f7	48	the HAL_UART_Init() API.
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(#) For the UART Half duplex mode, initialize the UART registers by calling
<>	144:ef7eb2e8f9f7	51	the HAL_HalfDuplex_Init() API.
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	(#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	(#) For the Multi-Processor mode, initialize the UART registers by calling
<>	144:ef7eb2e8f9f7	56	the HAL_MultiProcessor_Init() API.
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	[..]
<>	144:ef7eb2e8f9f7	59	(@) The specific UART interrupts (Transmission complete interrupt,
<>	144:ef7eb2e8f9f7	60	RXNE interrupt and Error Interrupts) will be managed using the macros
<>	144:ef7eb2e8f9f7	61	__HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
<>	144:ef7eb2e8f9f7	62	and receive process.
<>	144:ef7eb2e8f9f7	63
<>	144:ef7eb2e8f9f7	64	[..]
<>	144:ef7eb2e8f9f7	65	(@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
<>	144:ef7eb2e8f9f7	66	low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
<>	144:ef7eb2e8f9f7	67	HAL_UART_MspInit() API.
<>	144:ef7eb2e8f9f7	68
<>	144:ef7eb2e8f9f7	69	[..]
<>	144:ef7eb2e8f9f7	70	Three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	73	=================================
<>	144:ef7eb2e8f9f7	74	[..]
<>	144:ef7eb2e8f9f7	75	(+) Send an amount of data in blocking mode using HAL_UART_Transmit()
<>	144:ef7eb2e8f9f7	76	(+) Receive an amount of data in blocking mode using HAL_UART_Receive()
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	79	===================================
<>	144:ef7eb2e8f9f7	80	[..]
<>	144:ef7eb2e8f9f7	81	(+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	82	(+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	83	add his own code by customization of function pointer HAL_UART_TxCpltCallback
<>	144:ef7eb2e8f9f7	84	(+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
<>	144:ef7eb2e8f9f7	85	(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	86	add his own code by customization of function pointer HAL_UART_RxCpltCallback
<>	144:ef7eb2e8f9f7	87	(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	88	add his own code by customization of function pointer HAL_UART_ErrorCallback
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	91	==============================
<>	144:ef7eb2e8f9f7	92	[..]
<>	144:ef7eb2e8f9f7	93	(+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	94	(+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	95	add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
<>	144:ef7eb2e8f9f7	96	(+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	97	add his own code by customization of function pointer HAL_UART_TxCpltCallback
<>	144:ef7eb2e8f9f7	98	(+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
<>	144:ef7eb2e8f9f7	99	(+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	100	add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
<>	144:ef7eb2e8f9f7	101	(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	102	add his own code by customization of function pointer HAL_UART_RxCpltCallback
<>	144:ef7eb2e8f9f7	103	(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	104	add his own code by customization of function pointer HAL_UART_ErrorCallback
<>	144:ef7eb2e8f9f7	105	(+) Pause the DMA Transfer using HAL_UART_DMAPause()
<>	144:ef7eb2e8f9f7	106	(+) Resume the DMA Transfer using HAL_UART_DMAResume()
<>	144:ef7eb2e8f9f7	107	(+) Stop the DMA Transfer using HAL_UART_DMAStop()
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	* UART HAL driver macros list *
<>	144:ef7eb2e8f9f7	110	=============================================
<>	144:ef7eb2e8f9f7	111	[..]
<>	144:ef7eb2e8f9f7	112	Below the list of most used macros in UART HAL driver.
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	(+) __HAL_UART_ENABLE: Enable the UART peripheral
<>	144:ef7eb2e8f9f7	115	(+) __HAL_UART_DISABLE: Disable the UART peripheral
<>	144:ef7eb2e8f9f7	116	(+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
<>	144:ef7eb2e8f9f7	117	(+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
<>	144:ef7eb2e8f9f7	118	(+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
<>	144:ef7eb2e8f9f7	119	(+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
<>	144:ef7eb2e8f9f7	120	(+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
<>	144:ef7eb2e8f9f7	121
<>	144:ef7eb2e8f9f7	122	[..]
<>	144:ef7eb2e8f9f7	123	(@) You can refer to the UART HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	@endverbatim
<>	144:ef7eb2e8f9f7	126	******************************************************************************
<>	144:ef7eb2e8f9f7	127	* @attention
<>	144:ef7eb2e8f9f7	128	*
AnnaBridge	167:e84263d55307	129	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	130	*
<>	144:ef7eb2e8f9f7	131	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	132	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	133	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	134	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	135	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	136	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	137	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	138	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	139	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	140	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	141	*
<>	144:ef7eb2e8f9f7	142	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	143	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	144	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	145	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	146	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	147	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	148	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	149	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	150	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	151	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	152	*
<>	144:ef7eb2e8f9f7	153	******************************************************************************
<>	144:ef7eb2e8f9f7	154	*/
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	157	#include "stm32f2xx_hal.h"
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	160	* @{
<>	144:ef7eb2e8f9f7	161	*/
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	/** @defgroup UART UART
<>	144:ef7eb2e8f9f7	164	* @brief HAL UART module driver
<>	144:ef7eb2e8f9f7	165	* @{
<>	144:ef7eb2e8f9f7	166	*/
<>	144:ef7eb2e8f9f7	167	#ifdef HAL_UART_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	170	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	171	/** @addtogroup UART_Private_Constants
<>	144:ef7eb2e8f9f7	172	* @{
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174	/**
<>	144:ef7eb2e8f9f7	175	* @}
<>	144:ef7eb2e8f9f7	176	*/
<>	144:ef7eb2e8f9f7	177	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	178	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	179	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	180	/** @addtogroup UART_Private_Functions UART Private Functions
<>	144:ef7eb2e8f9f7	181	* @{
<>	144:ef7eb2e8f9f7	182	*/
<>	144:ef7eb2e8f9f7	183	static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	184	static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	185	static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	186	static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	187	static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	188	static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	189	static void UART_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	190	static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	191	static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	192	static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	193	static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	194	static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	195	static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	196	static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	197	static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	198	static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	199	static void UART_SetConfig (UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	200	/**
<>	144:ef7eb2e8f9f7	201	* @}
<>	144:ef7eb2e8f9f7	202	*/
<>	144:ef7eb2e8f9f7	203
<>	144:ef7eb2e8f9f7	204	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	205	/** @defgroup UART_Exported_Functions UART Exported Functions
<>	144:ef7eb2e8f9f7	206	* @{
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208
<>	144:ef7eb2e8f9f7	209	/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	210	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	211	*
<>	144:ef7eb2e8f9f7	212	@verbatim
<>	144:ef7eb2e8f9f7	213	===============================================================================
<>	144:ef7eb2e8f9f7	214	##### Initialization and Configuration functions #####
<>	144:ef7eb2e8f9f7	215	===============================================================================
<>	144:ef7eb2e8f9f7	216	[..]
<>	144:ef7eb2e8f9f7	217	This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<>	144:ef7eb2e8f9f7	218	in asynchronous mode.
<>	144:ef7eb2e8f9f7	219	(+) For the asynchronous mode only these parameters can be configured:
<>	144:ef7eb2e8f9f7	220	(++) Baud Rate
<>	144:ef7eb2e8f9f7	221	(++) Word Length
<>	144:ef7eb2e8f9f7	222	(++) Stop Bit
<>	144:ef7eb2e8f9f7	223	(++) Parity: If the parity is enabled, then the MSB bit of the data written
<>	144:ef7eb2e8f9f7	224	in the data register is transmitted but is changed by the parity bit.
<>	144:ef7eb2e8f9f7	225	Depending on the frame length defined by the M bit (8-bits or 9-bits),
<>	144:ef7eb2e8f9f7	226	please refer to Reference manual for possible UART frame formats.
<>	144:ef7eb2e8f9f7	227	(++) Hardware flow control
<>	144:ef7eb2e8f9f7	228	(++) Receiver/transmitter modes
<>	144:ef7eb2e8f9f7	229	(++) Over Sampling Method
<>	144:ef7eb2e8f9f7	230	[..]
<>	144:ef7eb2e8f9f7	231	The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
<>	144:ef7eb2e8f9f7	232	follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
<>	144:ef7eb2e8f9f7	233	configuration procedures (details for the procedures are available in reference manual (RM0329)).
<>	144:ef7eb2e8f9f7	234
<>	144:ef7eb2e8f9f7	235	@endverbatim
<>	144:ef7eb2e8f9f7	236	* @{
<>	144:ef7eb2e8f9f7	237	*/
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/**
<>	144:ef7eb2e8f9f7	240	* @brief Initializes the UART mode according to the specified parameters in
<>	144:ef7eb2e8f9f7	241	* the UART_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	242	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	243	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	244	* @retval HAL status
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246	HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	247	{
<>	144:ef7eb2e8f9f7	248	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	249	if(huart == NULL)
<>	144:ef7eb2e8f9f7	250	{
<>	144:ef7eb2e8f9f7	251	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	252	}
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/* Check the parameters */
<>	144:ef7eb2e8f9f7	255	if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
<>	144:ef7eb2e8f9f7	256	{
<>	144:ef7eb2e8f9f7	257	/* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
<>	144:ef7eb2e8f9f7	258	assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	259	assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
<>	144:ef7eb2e8f9f7	260	}
<>	144:ef7eb2e8f9f7	261	else
<>	144:ef7eb2e8f9f7	262	{
<>	144:ef7eb2e8f9f7	263	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	264	}
<>	144:ef7eb2e8f9f7	265	assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
<>	144:ef7eb2e8f9f7	266	assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	269	{
<>	144:ef7eb2e8f9f7	270	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	271	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	272	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	273	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	274	}
<>	144:ef7eb2e8f9f7	275
<>	144:ef7eb2e8f9f7	276	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278	/* Disable the peripheral */
<>	144:ef7eb2e8f9f7	279	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	280
<>	144:ef7eb2e8f9f7	281	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	282	UART_SetConfig(huart);
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	/* In asynchronous mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	285	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	286	- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
<>	144:ef7eb2e8f9f7	287	CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	144:ef7eb2e8f9f7	288	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL \| USART_CR3_IREN));
<>	144:ef7eb2e8f9f7	289
<>	144:ef7eb2e8f9f7	290	/* Enable the peripheral */
<>	144:ef7eb2e8f9f7	291	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/* Initialize the UART state */
<>	144:ef7eb2e8f9f7	294	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	295	huart->gState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	296	huart->RxState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	return HAL_OK;
<>	144:ef7eb2e8f9f7	299	}
<>	144:ef7eb2e8f9f7	300
<>	144:ef7eb2e8f9f7	301	/**
<>	144:ef7eb2e8f9f7	302	* @brief Initializes the half-duplex mode according to the specified
<>	144:ef7eb2e8f9f7	303	* parameters in the UART_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	304	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	305	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	306	* @retval HAL status
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308	HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	309	{
<>	144:ef7eb2e8f9f7	310	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	311	if(huart == NULL)
<>	144:ef7eb2e8f9f7	312	{
<>	144:ef7eb2e8f9f7	313	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	314	}
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	/* Check the parameters */
<>	144:ef7eb2e8f9f7	317	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	318	assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
<>	144:ef7eb2e8f9f7	319	assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	322	{
<>	144:ef7eb2e8f9f7	323	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	324	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	325	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	326	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	327	}
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/* Disable the peripheral */
<>	144:ef7eb2e8f9f7	332	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	335	UART_SetConfig(huart);
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/* In half-duplex mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	338	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	339	- SCEN and IREN bits in the USART_CR3 register.*/
<>	144:ef7eb2e8f9f7	340	CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	144:ef7eb2e8f9f7	341	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN \| USART_CR3_SCEN));
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
<>	144:ef7eb2e8f9f7	344	SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/* Enable the peripheral */
<>	144:ef7eb2e8f9f7	347	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	/* Initialize the UART state*/
<>	144:ef7eb2e8f9f7	350	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	351	huart->gState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	352	huart->RxState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	return HAL_OK;
<>	144:ef7eb2e8f9f7	355	}
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/**
<>	144:ef7eb2e8f9f7	358	* @brief Initializes the LIN mode according to the specified
<>	144:ef7eb2e8f9f7	359	* parameters in the UART_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	360	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	361	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	362	* @param BreakDetectLength: Specifies the LIN break detection length.
<>	144:ef7eb2e8f9f7	363	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	364	* @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
<>	144:ef7eb2e8f9f7	365	* @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
<>	144:ef7eb2e8f9f7	366	* @retval HAL status
<>	144:ef7eb2e8f9f7	367	*/
<>	144:ef7eb2e8f9f7	368	HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
<>	144:ef7eb2e8f9f7	369	{
<>	144:ef7eb2e8f9f7	370	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	371	if(huart == NULL)
<>	144:ef7eb2e8f9f7	372	{
<>	144:ef7eb2e8f9f7	373	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	374	}
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/* Check the parameters */
<>	144:ef7eb2e8f9f7	377	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	378	assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
<>	144:ef7eb2e8f9f7	379	assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
<>	144:ef7eb2e8f9f7	380	assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	383	{
<>	144:ef7eb2e8f9f7	384	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	385	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	386	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	387	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	388	}
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	/* Disable the peripheral */
<>	144:ef7eb2e8f9f7	393	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	396	UART_SetConfig(huart);
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/* In LIN mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	399	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	400	- SCEN and IREN bits in the USART_CR3 register.*/
<>	144:ef7eb2e8f9f7	401	CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<>	144:ef7eb2e8f9f7	402	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL \| USART_CR3_IREN \| USART_CR3_SCEN));
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/* Enable the LIN mode by setting the LINEN bit in the CR2 register */
<>	144:ef7eb2e8f9f7	405	SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
<>	144:ef7eb2e8f9f7	406
<>	144:ef7eb2e8f9f7	407	/* Set the USART LIN Break detection length. */
<>	144:ef7eb2e8f9f7	408	CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
<>	144:ef7eb2e8f9f7	409	SET_BIT(huart->Instance->CR2, BreakDetectLength);
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	/* Enable the peripheral */
<>	144:ef7eb2e8f9f7	412	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	/* Initialize the UART state*/
<>	144:ef7eb2e8f9f7	415	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	416	huart->gState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	417	huart->RxState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	return HAL_OK;
<>	144:ef7eb2e8f9f7	420	}
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/**
<>	144:ef7eb2e8f9f7	423	* @brief Initializes the Multi-Processor mode according to the specified
<>	144:ef7eb2e8f9f7	424	* parameters in the UART_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	425	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	426	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	427	* @param Address: USART address
<>	144:ef7eb2e8f9f7	428	* @param WakeUpMethod: specifies the USART wake-up method.
<>	144:ef7eb2e8f9f7	429	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	430	* @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
<>	144:ef7eb2e8f9f7	431	* @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
<>	144:ef7eb2e8f9f7	432	* @retval HAL status
<>	144:ef7eb2e8f9f7	433	*/
<>	144:ef7eb2e8f9f7	434	HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
<>	144:ef7eb2e8f9f7	435	{
<>	144:ef7eb2e8f9f7	436	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	437	if(huart == NULL)
<>	144:ef7eb2e8f9f7	438	{
<>	144:ef7eb2e8f9f7	439	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	440	}
<>	144:ef7eb2e8f9f7	441
<>	144:ef7eb2e8f9f7	442	/* Check the parameters */
<>	144:ef7eb2e8f9f7	443	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	444	assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
<>	144:ef7eb2e8f9f7	445	assert_param(IS_UART_ADDRESS(Address));
<>	144:ef7eb2e8f9f7	446	assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
<>	144:ef7eb2e8f9f7	447	assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	450	{
<>	144:ef7eb2e8f9f7	451	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	452	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	453	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	454	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	455	}
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/* Disable the peripheral */
<>	144:ef7eb2e8f9f7	460	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	461
<>	144:ef7eb2e8f9f7	462	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	463	UART_SetConfig(huart);
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	/* In Multi-Processor mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	466	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	467	- SCEN, HDSEL and IREN bits in the USART_CR3 register */
<>	144:ef7eb2e8f9f7	468	CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	144:ef7eb2e8f9f7	469	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL \| USART_CR3_IREN));
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	/* Clear the USART address */
<>	144:ef7eb2e8f9f7	472	CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
<>	144:ef7eb2e8f9f7	473	/* Set the USART address node */
<>	144:ef7eb2e8f9f7	474	SET_BIT(huart->Instance->CR2, Address);
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/* Set the wake up method by setting the WAKE bit in the CR1 register */
<>	144:ef7eb2e8f9f7	477	CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
<>	144:ef7eb2e8f9f7	478	SET_BIT(huart->Instance->CR1, WakeUpMethod);
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/* Enable the peripheral */
<>	144:ef7eb2e8f9f7	481	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/* Initialize the UART state */
<>	144:ef7eb2e8f9f7	484	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	485	huart->gState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	486	huart->RxState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	return HAL_OK;
<>	144:ef7eb2e8f9f7	489	}
<>	144:ef7eb2e8f9f7	490
<>	144:ef7eb2e8f9f7	491	/**
<>	144:ef7eb2e8f9f7	492	* @brief DeInitializes the UART peripheral.
<>	144:ef7eb2e8f9f7	493	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	494	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	495	* @retval HAL status
<>	144:ef7eb2e8f9f7	496	*/
<>	144:ef7eb2e8f9f7	497	HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	498	{
<>	144:ef7eb2e8f9f7	499	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	500	if(huart == NULL)
<>	144:ef7eb2e8f9f7	501	{
<>	144:ef7eb2e8f9f7	502	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	503	}
<>	144:ef7eb2e8f9f7	504
<>	144:ef7eb2e8f9f7	505	/* Check the parameters */
<>	144:ef7eb2e8f9f7	506	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	507
<>	144:ef7eb2e8f9f7	508	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	509
<>	144:ef7eb2e8f9f7	510	/* DeInit the low level hardware */
<>	144:ef7eb2e8f9f7	511	HAL_UART_MspDeInit(huart);
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	huart->ErrorCode = HAL_UART_ERROR_NONE;
AnnaBridge	167:e84263d55307	514	huart->gState = HAL_UART_STATE_RESET;
<>	144:ef7eb2e8f9f7	515	huart->RxState = HAL_UART_STATE_RESET;
<>	144:ef7eb2e8f9f7	516
<>	144:ef7eb2e8f9f7	517	/* Process Lock */
<>	144:ef7eb2e8f9f7	518	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	519
<>	144:ef7eb2e8f9f7	520	return HAL_OK;
<>	144:ef7eb2e8f9f7	521	}
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/**
<>	144:ef7eb2e8f9f7	524	* @brief UART MSP Init.
<>	144:ef7eb2e8f9f7	525	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	526	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	527	* @retval None
<>	144:ef7eb2e8f9f7	528	*/
<>	144:ef7eb2e8f9f7	529	__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	530	{
<>	144:ef7eb2e8f9f7	531	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	532	UNUSED(huart);
<>	144:ef7eb2e8f9f7	533	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	534	the HAL_UART_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	535	*/
<>	144:ef7eb2e8f9f7	536	}
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	/**
<>	144:ef7eb2e8f9f7	539	* @brief UART MSP DeInit.
<>	144:ef7eb2e8f9f7	540	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	541	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	542	* @retval None
<>	144:ef7eb2e8f9f7	543	*/
<>	144:ef7eb2e8f9f7	544	__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	545	{
<>	144:ef7eb2e8f9f7	546	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	547	UNUSED(huart);
<>	144:ef7eb2e8f9f7	548	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	549	the HAL_UART_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	550	*/
<>	144:ef7eb2e8f9f7	551	}
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/**
<>	144:ef7eb2e8f9f7	554	* @}
<>	144:ef7eb2e8f9f7	555	*/
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	/** @defgroup UART_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	558	* @brief UART Transmit and Receive functions
<>	144:ef7eb2e8f9f7	559	*
<>	144:ef7eb2e8f9f7	560	@verbatim
<>	144:ef7eb2e8f9f7	561	==============================================================================
<>	144:ef7eb2e8f9f7	562	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	563	==============================================================================
<>	144:ef7eb2e8f9f7	564	[..]
<>	144:ef7eb2e8f9f7	565	This subsection provides a set of functions allowing to manage the UART asynchronous
<>	144:ef7eb2e8f9f7	566	and Half duplex data transfers.
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	569	(++) Blocking mode: The communication is performed in polling mode.
<>	144:ef7eb2e8f9f7	570	The HAL status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	571	after finishing transfer.
<>	144:ef7eb2e8f9f7	572	(++) Non blocking mode: The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	573	or DMA, these APIs return the HAL status.
<>	144:ef7eb2e8f9f7	574	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	575	dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	576	using DMA mode.
<>	144:ef7eb2e8f9f7	577	The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
<>	144:ef7eb2e8f9f7	578	will be executed respectively at the end of the transmit or receive process.
<>	144:ef7eb2e8f9f7	579	The HAL_UART_ErrorCallback() user callback will be executed when
<>	144:ef7eb2e8f9f7	580	a communication error is detected.
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	(#) Blocking mode APIs are:
<>	144:ef7eb2e8f9f7	583	(++) HAL_UART_Transmit()
<>	144:ef7eb2e8f9f7	584	(++) HAL_UART_Receive()
<>	144:ef7eb2e8f9f7	585
<>	144:ef7eb2e8f9f7	586	(#) Non Blocking mode APIs with Interrupt are:
<>	144:ef7eb2e8f9f7	587	(++) HAL_UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	588	(++) HAL_UART_Receive_IT()
<>	144:ef7eb2e8f9f7	589	(++) HAL_UART_IRQHandler()
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	(#) Non Blocking mode functions with DMA are:
<>	144:ef7eb2e8f9f7	592	(++) HAL_UART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	593	(++) HAL_UART_Receive_DMA()
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	(#) A set of Transfer Complete Callbacks are provided in non blocking mode:
<>	144:ef7eb2e8f9f7	596	(++) HAL_UART_TxCpltCallback()
<>	144:ef7eb2e8f9f7	597	(++) HAL_UART_RxCpltCallback()
<>	144:ef7eb2e8f9f7	598	(++) HAL_UART_ErrorCallback()
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	[..]
<>	144:ef7eb2e8f9f7	601	(@) In the Half duplex communication, it is forbidden to run the transmit
<>	144:ef7eb2e8f9f7	602	and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
<>	144:ef7eb2e8f9f7	603	can't be useful.
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	@endverbatim
<>	144:ef7eb2e8f9f7	606	* @{
<>	144:ef7eb2e8f9f7	607	*/
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	/**
<>	144:ef7eb2e8f9f7	610	* @brief Sends an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	611	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	612	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	613	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	614	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	615	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	616	* @retval HAL status
<>	144:ef7eb2e8f9f7	617	*/
<>	144:ef7eb2e8f9f7	618	HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	619	{
<>	144:ef7eb2e8f9f7	620	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	621	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	622
<>	144:ef7eb2e8f9f7	623	/* Check that a Tx process is not already ongoing */
<>	144:ef7eb2e8f9f7	624	if(huart->gState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	625	{
AnnaBridge	167:e84263d55307	626	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	627	{
<>	144:ef7eb2e8f9f7	628	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	629	}
<>	144:ef7eb2e8f9f7	630
<>	144:ef7eb2e8f9f7	631	/* Process Locked */
<>	144:ef7eb2e8f9f7	632	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	635	huart->gState = HAL_UART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	636
<>	144:ef7eb2e8f9f7	637	/* Init tickstart for timeout managment */
<>	144:ef7eb2e8f9f7	638	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	huart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	641	huart->TxXferCount = Size;
AnnaBridge	167:e84263d55307	642	while(huart->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	643	{
<>	144:ef7eb2e8f9f7	644	huart->TxXferCount--;
<>	144:ef7eb2e8f9f7	645	if(huart->Init.WordLength == UART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	646	{
<>	144:ef7eb2e8f9f7	647	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	648	{
<>	144:ef7eb2e8f9f7	649	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	650	}
<>	144:ef7eb2e8f9f7	651	tmp = (uint16_t*) pData;
AnnaBridge	167:e84263d55307	652	huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	653	if(huart->Init.Parity == UART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	654	{
<>	144:ef7eb2e8f9f7	655	pData +=2;
<>	144:ef7eb2e8f9f7	656	}
<>	144:ef7eb2e8f9f7	657	else
<>	144:ef7eb2e8f9f7	658	{
<>	144:ef7eb2e8f9f7	659	pData +=1;
<>	144:ef7eb2e8f9f7	660	}
<>	144:ef7eb2e8f9f7	661	}
<>	144:ef7eb2e8f9f7	662	else
<>	144:ef7eb2e8f9f7	663	{
<>	144:ef7eb2e8f9f7	664	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	665	{
<>	144:ef7eb2e8f9f7	666	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	667	}
AnnaBridge	167:e84263d55307	668	huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
<>	144:ef7eb2e8f9f7	669	}
<>	144:ef7eb2e8f9f7	670	}
<>	144:ef7eb2e8f9f7	671
<>	144:ef7eb2e8f9f7	672	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	675	}
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	/* At end of Tx process, restore huart->gState to Ready */
<>	144:ef7eb2e8f9f7	678	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	681	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	return HAL_OK;
<>	144:ef7eb2e8f9f7	684	}
<>	144:ef7eb2e8f9f7	685	else
<>	144:ef7eb2e8f9f7	686	{
<>	144:ef7eb2e8f9f7	687	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	688	}
<>	144:ef7eb2e8f9f7	689	}
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	/**
<>	144:ef7eb2e8f9f7	692	* @brief Receives an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	693	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	694	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	695	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	696	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	697	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	698	* @retval HAL status
<>	144:ef7eb2e8f9f7	699	*/
<>	144:ef7eb2e8f9f7	700	HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	701	{
<>	144:ef7eb2e8f9f7	702	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	703	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	704
<>	144:ef7eb2e8f9f7	705	/* Check that a Rx process is not already ongoing */
<>	144:ef7eb2e8f9f7	706	if(huart->RxState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	707	{
AnnaBridge	167:e84263d55307	708	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	709	{
<>	144:ef7eb2e8f9f7	710	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	711	}
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	/* Process Locked */
<>	144:ef7eb2e8f9f7	714	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	717	huart->RxState = HAL_UART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	/* Init tickstart for timeout managment */
<>	144:ef7eb2e8f9f7	720	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	721
<>	144:ef7eb2e8f9f7	722	huart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	723	huart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	724
<>	144:ef7eb2e8f9f7	725	/* Check the remain data to be received */
AnnaBridge	167:e84263d55307	726	while(huart->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	727	{
<>	144:ef7eb2e8f9f7	728	huart->RxXferCount--;
<>	144:ef7eb2e8f9f7	729	if(huart->Init.WordLength == UART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	730	{
<>	144:ef7eb2e8f9f7	731	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	732	{
<>	144:ef7eb2e8f9f7	733	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	734	}
<>	144:ef7eb2e8f9f7	735	tmp = (uint16_t*) pData ;
<>	144:ef7eb2e8f9f7	736	if(huart->Init.Parity == UART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	737	{
AnnaBridge	167:e84263d55307	738	*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	739	pData +=2;
<>	144:ef7eb2e8f9f7	740	}
<>	144:ef7eb2e8f9f7	741	else
<>	144:ef7eb2e8f9f7	742	{
AnnaBridge	167:e84263d55307	743	*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
<>	144:ef7eb2e8f9f7	744	pData +=1;
<>	144:ef7eb2e8f9f7	745	}
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	}
<>	144:ef7eb2e8f9f7	748	else
<>	144:ef7eb2e8f9f7	749	{
<>	144:ef7eb2e8f9f7	750	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	751	{
<>	144:ef7eb2e8f9f7	752	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	753	}
<>	144:ef7eb2e8f9f7	754	if(huart->Init.Parity == UART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	755	{
AnnaBridge	167:e84263d55307	756	*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	757	}
<>	144:ef7eb2e8f9f7	758	else
<>	144:ef7eb2e8f9f7	759	{
AnnaBridge	167:e84263d55307	760	*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
<>	144:ef7eb2e8f9f7	761	}
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	}
<>	144:ef7eb2e8f9f7	764	}
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/* At end of Rx process, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	767	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	768
<>	144:ef7eb2e8f9f7	769	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	770	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	return HAL_OK;
<>	144:ef7eb2e8f9f7	773	}
<>	144:ef7eb2e8f9f7	774	else
<>	144:ef7eb2e8f9f7	775	{
<>	144:ef7eb2e8f9f7	776	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	777	}
<>	144:ef7eb2e8f9f7	778	}
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/**
<>	144:ef7eb2e8f9f7	781	* @brief Sends an amount of data in non blocking mode.
<>	144:ef7eb2e8f9f7	782	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	783	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	784	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	785	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	786	* @retval HAL status
<>	144:ef7eb2e8f9f7	787	*/
<>	144:ef7eb2e8f9f7	788	HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	789	{
<>	144:ef7eb2e8f9f7	790	/* Check that a Tx process is not already ongoing */
<>	144:ef7eb2e8f9f7	791	if(huart->gState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	792	{
AnnaBridge	167:e84263d55307	793	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	794	{
<>	144:ef7eb2e8f9f7	795	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	796	}
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	/* Process Locked */
<>	144:ef7eb2e8f9f7	799	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	huart->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	802	huart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	803	huart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	804
<>	144:ef7eb2e8f9f7	805	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	806	huart->gState = HAL_UART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	807
<>	144:ef7eb2e8f9f7	808	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	809	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	/* Enable the UART Transmit data register empty Interrupt */
<>	144:ef7eb2e8f9f7	812	SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	813
<>	144:ef7eb2e8f9f7	814	return HAL_OK;
<>	144:ef7eb2e8f9f7	815	}
<>	144:ef7eb2e8f9f7	816	else
<>	144:ef7eb2e8f9f7	817	{
<>	144:ef7eb2e8f9f7	818	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	819	}
<>	144:ef7eb2e8f9f7	820	}
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/**
<>	144:ef7eb2e8f9f7	823	* @brief Receives an amount of data in non blocking mode
<>	144:ef7eb2e8f9f7	824	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	825	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	826	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	827	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	828	* @retval HAL status
<>	144:ef7eb2e8f9f7	829	*/
<>	144:ef7eb2e8f9f7	830	HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	831	{
<>	144:ef7eb2e8f9f7	832	/* Check that a Rx process is not already ongoing */
<>	144:ef7eb2e8f9f7	833	if(huart->RxState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	834	{
AnnaBridge	167:e84263d55307	835	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	836	{
<>	144:ef7eb2e8f9f7	837	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	838	}
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	/* Process Locked */
<>	144:ef7eb2e8f9f7	841	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	huart->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	844	huart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	845	huart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	846
<>	144:ef7eb2e8f9f7	847	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	848	huart->RxState = HAL_UART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	849
<>	144:ef7eb2e8f9f7	850	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	851	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	852
<>	144:ef7eb2e8f9f7	853	/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	854	SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	855
<>	144:ef7eb2e8f9f7	856	/* Enable the UART Parity Error and Data Register not empty Interrupts */
<>	144:ef7eb2e8f9f7	857	SET_BIT(huart->Instance->CR1, USART_CR1_PEIE \| USART_CR1_RXNEIE);
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	return HAL_OK;
<>	144:ef7eb2e8f9f7	860	}
<>	144:ef7eb2e8f9f7	861	else
<>	144:ef7eb2e8f9f7	862	{
<>	144:ef7eb2e8f9f7	863	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	864	}
<>	144:ef7eb2e8f9f7	865	}
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	/**
<>	144:ef7eb2e8f9f7	868	* @brief Sends an amount of data in non blocking mode.
<>	144:ef7eb2e8f9f7	869	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	870	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	871	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	872	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	873	* @retval HAL status
<>	144:ef7eb2e8f9f7	874	*/
<>	144:ef7eb2e8f9f7	875	HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	876	{
<>	144:ef7eb2e8f9f7	877	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	878
<>	144:ef7eb2e8f9f7	879	/* Check that a Tx process is not already ongoing */
<>	144:ef7eb2e8f9f7	880	if(huart->gState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	881	{
AnnaBridge	167:e84263d55307	882	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	883	{
<>	144:ef7eb2e8f9f7	884	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	885	}
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/* Process Locked */
<>	144:ef7eb2e8f9f7	888	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	889
<>	144:ef7eb2e8f9f7	890	huart->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	891	huart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	892	huart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	895	huart->gState = HAL_UART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	896
<>	144:ef7eb2e8f9f7	897	/* Set the UART DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	898	huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	899
<>	144:ef7eb2e8f9f7	900	/* Set the UART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	901	huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	902
<>	144:ef7eb2e8f9f7	903	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	904	huart->hdmatx->XferErrorCallback = UART_DMAError;
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/* Set the DMA abort callback */
<>	144:ef7eb2e8f9f7	907	huart->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	/* Enable the UART transmit DMA Stream */
<>	144:ef7eb2e8f9f7	910	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	911	HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)tmp, (uint32_t)&huart->Instance->DR, Size);
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/* Clear the TC flag in the SR register by writing 0 to it */
<>	144:ef7eb2e8f9f7	914	__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	917	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	920	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	921	SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	922
<>	144:ef7eb2e8f9f7	923	return HAL_OK;
<>	144:ef7eb2e8f9f7	924	}
<>	144:ef7eb2e8f9f7	925	else
<>	144:ef7eb2e8f9f7	926	{
<>	144:ef7eb2e8f9f7	927	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	928	}
<>	144:ef7eb2e8f9f7	929	}
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	/**
<>	144:ef7eb2e8f9f7	932	* @brief Receives an amount of data in non blocking mode.
<>	144:ef7eb2e8f9f7	933	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	934	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	935	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	936	* @param Size: Amount of data to be received
<>	144:ef7eb2e8f9f7	937	* @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
<>	144:ef7eb2e8f9f7	938	* @retval HAL status
<>	144:ef7eb2e8f9f7	939	*/
<>	144:ef7eb2e8f9f7	940	HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	941	{
<>	144:ef7eb2e8f9f7	942	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Check that a Rx process is not already ongoing */
<>	144:ef7eb2e8f9f7	945	if(huart->RxState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	946	{
AnnaBridge	167:e84263d55307	947	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	948	{
<>	144:ef7eb2e8f9f7	949	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	950	}
<>	144:ef7eb2e8f9f7	951
<>	144:ef7eb2e8f9f7	952	/* Process Locked */
<>	144:ef7eb2e8f9f7	953	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	huart->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	956	huart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	959	huart->RxState = HAL_UART_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	960
<>	144:ef7eb2e8f9f7	961	/* Set the UART DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	962	huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	963
<>	144:ef7eb2e8f9f7	964	/* Set the UART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	965	huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	966
<>	144:ef7eb2e8f9f7	967	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	968	huart->hdmarx->XferErrorCallback = UART_DMAError;
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970	/* Set the DMA abort callback */
<>	144:ef7eb2e8f9f7	971	huart->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	972
<>	144:ef7eb2e8f9f7	973	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	974	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	975	HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, (uint32_t)tmp, Size);
<>	144:ef7eb2e8f9f7	976
AnnaBridge	167:e84263d55307	977	/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
AnnaBridge	167:e84263d55307	978	__HAL_UART_CLEAR_OREFLAG(huart);
AnnaBridge	167:e84263d55307	979
AnnaBridge	167:e84263d55307	980	/* Process Unlocked */
AnnaBridge	167:e84263d55307	981	__HAL_UNLOCK(huart);
AnnaBridge	167:e84263d55307	982
<>	144:ef7eb2e8f9f7	983	/* Enable the UART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	984	SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	987	SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
AnnaBridge	167:e84263d55307	988
<>	144:ef7eb2e8f9f7	989	/* Enable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	990	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	991	SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	992
<>	144:ef7eb2e8f9f7	993	return HAL_OK;
<>	144:ef7eb2e8f9f7	994	}
<>	144:ef7eb2e8f9f7	995	else
<>	144:ef7eb2e8f9f7	996	{
<>	144:ef7eb2e8f9f7	997	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	998	}
<>	144:ef7eb2e8f9f7	999	}
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	/**
<>	144:ef7eb2e8f9f7	1002	* @brief Pauses the DMA Transfer.
<>	144:ef7eb2e8f9f7	1003	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1004	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1005	* @retval HAL status
<>	144:ef7eb2e8f9f7	1006	*/
<>	144:ef7eb2e8f9f7	1007	HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1008	{
<>	144:ef7eb2e8f9f7	1009	uint32_t dmarequest = 0x00U;
<>	144:ef7eb2e8f9f7	1010
<>	144:ef7eb2e8f9f7	1011	/* Process Locked */
<>	144:ef7eb2e8f9f7	1012	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1013	dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1014	if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
<>	144:ef7eb2e8f9f7	1015	{
<>	144:ef7eb2e8f9f7	1016	/* Disable the UART DMA Tx request */
<>	144:ef7eb2e8f9f7	1017	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1018	}
<>	144:ef7eb2e8f9f7	1019	dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1020	if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
<>	144:ef7eb2e8f9f7	1021	{
<>	144:ef7eb2e8f9f7	1022	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	1023	CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1024	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/* Disable the UART DMA Rx request */
<>	144:ef7eb2e8f9f7	1027	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1028	}
<>	144:ef7eb2e8f9f7	1029
<>	144:ef7eb2e8f9f7	1030	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1031	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1032
<>	144:ef7eb2e8f9f7	1033	return HAL_OK;
<>	144:ef7eb2e8f9f7	1034	}
<>	144:ef7eb2e8f9f7	1035
<>	144:ef7eb2e8f9f7	1036	/**
<>	144:ef7eb2e8f9f7	1037	* @brief Resumes the DMA Transfer.
<>	144:ef7eb2e8f9f7	1038	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1039	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1040	* @retval HAL status
<>	144:ef7eb2e8f9f7	1041	*/
<>	144:ef7eb2e8f9f7	1042	HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1043	{
<>	144:ef7eb2e8f9f7	1044	/* Process Locked */
<>	144:ef7eb2e8f9f7	1045	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	if(huart->gState == HAL_UART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1048	{
<>	144:ef7eb2e8f9f7	1049	/* Enable the UART DMA Tx request */
<>	144:ef7eb2e8f9f7	1050	SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1051	}
<>	144:ef7eb2e8f9f7	1052	if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1053	{
<>	144:ef7eb2e8f9f7	1054	/* Clear the Overrun flag before resuming the Rx transfer*/
<>	144:ef7eb2e8f9f7	1055	__HAL_UART_CLEAR_OREFLAG(huart);
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	1058	SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1059	SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/* Enable the UART DMA Rx request */
<>	144:ef7eb2e8f9f7	1062	SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1063	}
<>	144:ef7eb2e8f9f7	1064
<>	144:ef7eb2e8f9f7	1065	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1066	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	return HAL_OK;
<>	144:ef7eb2e8f9f7	1069	}
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	/**
<>	144:ef7eb2e8f9f7	1072	* @brief Stops the DMA Transfer.
<>	144:ef7eb2e8f9f7	1073	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1074	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1075	* @retval HAL status
<>	144:ef7eb2e8f9f7	1076	*/
<>	144:ef7eb2e8f9f7	1077	HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1078	{
<>	144:ef7eb2e8f9f7	1079	uint32_t dmarequest = 0x00U;
<>	144:ef7eb2e8f9f7	1080	/* The Lock is not implemented on this API to allow the user application
<>	144:ef7eb2e8f9f7	1081	to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
<>	144:ef7eb2e8f9f7	1082	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<>	144:ef7eb2e8f9f7	1083	and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
<>	144:ef7eb2e8f9f7	1084	*/
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	/* Stop UART DMA Tx request if ongoing */
<>	144:ef7eb2e8f9f7	1087	dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1088	if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
<>	144:ef7eb2e8f9f7	1089	{
<>	144:ef7eb2e8f9f7	1090	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	/* Abort the UART DMA Tx channel */
<>	144:ef7eb2e8f9f7	1093	if(huart->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	1094	{
<>	144:ef7eb2e8f9f7	1095	HAL_DMA_Abort(huart->hdmatx);
<>	144:ef7eb2e8f9f7	1096	}
<>	144:ef7eb2e8f9f7	1097	UART_EndTxTransfer(huart);
<>	144:ef7eb2e8f9f7	1098	}
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	/* Stop UART DMA Rx request if ongoing */
<>	144:ef7eb2e8f9f7	1101	dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1102	if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
<>	144:ef7eb2e8f9f7	1103	{
<>	144:ef7eb2e8f9f7	1104	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Abort the UART DMA Rx channel */
<>	144:ef7eb2e8f9f7	1107	if(huart->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1108	{
<>	144:ef7eb2e8f9f7	1109	HAL_DMA_Abort(huart->hdmarx);
<>	144:ef7eb2e8f9f7	1110	}
<>	144:ef7eb2e8f9f7	1111	UART_EndRxTransfer(huart);
<>	144:ef7eb2e8f9f7	1112	}
<>	144:ef7eb2e8f9f7	1113
<>	144:ef7eb2e8f9f7	1114	return HAL_OK;
<>	144:ef7eb2e8f9f7	1115	}
<>	144:ef7eb2e8f9f7	1116
<>	144:ef7eb2e8f9f7	1117	/**
AnnaBridge	167:e84263d55307	1118	* @brief Abort ongoing transfers (blocking mode).
AnnaBridge	167:e84263d55307	1119	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1120	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1121	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1122	* - Disable PPP Interrupts
AnnaBridge	167:e84263d55307	1123	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1124	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1125	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1126	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge	167:e84263d55307	1127	* @retval HAL status
AnnaBridge	167:e84263d55307	1128	*/
AnnaBridge	167:e84263d55307	1129	HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1130	{
AnnaBridge	167:e84263d55307	1131	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge	167:e84263d55307	1132	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
AnnaBridge	167:e84263d55307	1133	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
AnnaBridge	167:e84263d55307	1134
AnnaBridge	167:e84263d55307	1135	/* Disable the UART DMA Tx request if enabled */
AnnaBridge	167:e84263d55307	1136	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1137	{
AnnaBridge	167:e84263d55307	1138	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
AnnaBridge	167:e84263d55307	1139
AnnaBridge	167:e84263d55307	1140	/* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1141	if(huart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1142	{
AnnaBridge	167:e84263d55307	1143	/* Set the UART DMA Abort callback to Null.
AnnaBridge	167:e84263d55307	1144	No call back execution at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1145	huart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1146
AnnaBridge	167:e84263d55307	1147	HAL_DMA_Abort(huart->hdmatx);
AnnaBridge	167:e84263d55307	1148	}
AnnaBridge	167:e84263d55307	1149	}
AnnaBridge	167:e84263d55307	1150
AnnaBridge	167:e84263d55307	1151	/* Disable the UART DMA Rx request if enabled */
AnnaBridge	167:e84263d55307	1152	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1153	{
AnnaBridge	167:e84263d55307	1154	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
AnnaBridge	167:e84263d55307	1155
AnnaBridge	167:e84263d55307	1156	/* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1157	if(huart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1158	{
AnnaBridge	167:e84263d55307	1159	/* Set the UART DMA Abort callback to Null.
AnnaBridge	167:e84263d55307	1160	No call back execution at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1161	huart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1162
AnnaBridge	167:e84263d55307	1163	HAL_DMA_Abort(huart->hdmarx);
AnnaBridge	167:e84263d55307	1164	}
AnnaBridge	167:e84263d55307	1165	}
AnnaBridge	167:e84263d55307	1166
AnnaBridge	167:e84263d55307	1167	/* Reset Tx and Rx transfer counters */
AnnaBridge	167:e84263d55307	1168	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1169	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1170
AnnaBridge	167:e84263d55307	1171	/* Reset ErrorCode */
AnnaBridge	167:e84263d55307	1172	huart->ErrorCode = HAL_UART_ERROR_NONE;
AnnaBridge	167:e84263d55307	1173
AnnaBridge	167:e84263d55307	1174	/* Restore huart->RxState and huart->gState to Ready */
AnnaBridge	167:e84263d55307	1175	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1176	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1177
AnnaBridge	167:e84263d55307	1178	return HAL_OK;
AnnaBridge	167:e84263d55307	1179	}
AnnaBridge	167:e84263d55307	1180
AnnaBridge	167:e84263d55307	1181	/**
AnnaBridge	167:e84263d55307	1182	* @brief Abort ongoing Transmit transfer (blocking mode).
AnnaBridge	167:e84263d55307	1183	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1184	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1185	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1186	* - Disable PPP Interrupts
AnnaBridge	167:e84263d55307	1187	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1188	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1189	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1190	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge	167:e84263d55307	1191	* @retval HAL status
AnnaBridge	167:e84263d55307	1192	*/
AnnaBridge	167:e84263d55307	1193	HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1194	{
AnnaBridge	167:e84263d55307	1195	/* Disable TXEIE and TCIE interrupts */
AnnaBridge	167:e84263d55307	1196	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
AnnaBridge	167:e84263d55307	1197
AnnaBridge	167:e84263d55307	1198	/* Disable the UART DMA Tx request if enabled */
AnnaBridge	167:e84263d55307	1199	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1200	{
AnnaBridge	167:e84263d55307	1201	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
AnnaBridge	167:e84263d55307	1202
AnnaBridge	167:e84263d55307	1203	/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1204	if(huart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1205	{
AnnaBridge	167:e84263d55307	1206	/* Set the UART DMA Abort callback to Null.
AnnaBridge	167:e84263d55307	1207	No call back execution at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1208	huart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1209
AnnaBridge	167:e84263d55307	1210	HAL_DMA_Abort(huart->hdmatx);
AnnaBridge	167:e84263d55307	1211	}
AnnaBridge	167:e84263d55307	1212	}
AnnaBridge	167:e84263d55307	1213
AnnaBridge	167:e84263d55307	1214	/* Reset Tx transfer counter */
AnnaBridge	167:e84263d55307	1215	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1216
AnnaBridge	167:e84263d55307	1217	/* Restore huart->gState to Ready */
AnnaBridge	167:e84263d55307	1218	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1219
AnnaBridge	167:e84263d55307	1220	return HAL_OK;
AnnaBridge	167:e84263d55307	1221	}
AnnaBridge	167:e84263d55307	1222
AnnaBridge	167:e84263d55307	1223	/**
AnnaBridge	167:e84263d55307	1224	* @brief Abort ongoing Receive transfer (blocking mode).
AnnaBridge	167:e84263d55307	1225	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1226	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1227	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1228	* - Disable PPP Interrupts
AnnaBridge	167:e84263d55307	1229	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1230	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1231	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1232	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge	167:e84263d55307	1233	* @retval HAL status
AnnaBridge	167:e84263d55307	1234	*/
AnnaBridge	167:e84263d55307	1235	HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1236	{
AnnaBridge	167:e84263d55307	1237	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge	167:e84263d55307	1238	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
AnnaBridge	167:e84263d55307	1239	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
AnnaBridge	167:e84263d55307	1240
AnnaBridge	167:e84263d55307	1241	/* Disable the UART DMA Rx request if enabled */
AnnaBridge	167:e84263d55307	1242	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1243	{
AnnaBridge	167:e84263d55307	1244	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
AnnaBridge	167:e84263d55307	1245
AnnaBridge	167:e84263d55307	1246	/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1247	if(huart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1248	{
AnnaBridge	167:e84263d55307	1249	/* Set the UART DMA Abort callback to Null.
AnnaBridge	167:e84263d55307	1250	No call back execution at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1251	huart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1252
AnnaBridge	167:e84263d55307	1253	HAL_DMA_Abort(huart->hdmarx);
AnnaBridge	167:e84263d55307	1254	}
AnnaBridge	167:e84263d55307	1255	}
AnnaBridge	167:e84263d55307	1256
AnnaBridge	167:e84263d55307	1257	/* Reset Rx transfer counter */
AnnaBridge	167:e84263d55307	1258	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1259
AnnaBridge	167:e84263d55307	1260	/* Restore huart->RxState to Ready */
AnnaBridge	167:e84263d55307	1261	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1262
AnnaBridge	167:e84263d55307	1263	return HAL_OK;
AnnaBridge	167:e84263d55307	1264	}
AnnaBridge	167:e84263d55307	1265
AnnaBridge	167:e84263d55307	1266	/**
AnnaBridge	167:e84263d55307	1267	* @brief Abort ongoing transfers (Interrupt mode).
AnnaBridge	167:e84263d55307	1268	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1269	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1270	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1271	* - Disable PPP Interrupts
AnnaBridge	167:e84263d55307	1272	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1273	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1274	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1275	* - At abort completion, call user abort complete callback
AnnaBridge	167:e84263d55307	1276	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge	167:e84263d55307	1277	* considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge	167:e84263d55307	1278	* @retval HAL status
AnnaBridge	167:e84263d55307	1279	*/
AnnaBridge	167:e84263d55307	1280	HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1281	{
AnnaBridge	167:e84263d55307	1282	uint32_t AbortCplt = 0x01U;
AnnaBridge	167:e84263d55307	1283
AnnaBridge	167:e84263d55307	1284	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge	167:e84263d55307	1285	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
AnnaBridge	167:e84263d55307	1286	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
AnnaBridge	167:e84263d55307	1287
AnnaBridge	167:e84263d55307	1288	/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
AnnaBridge	167:e84263d55307	1289	before any call to DMA Abort functions */
AnnaBridge	167:e84263d55307	1290	/* DMA Tx Handle is valid */
AnnaBridge	167:e84263d55307	1291	if(huart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1292	{
AnnaBridge	167:e84263d55307	1293	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
AnnaBridge	167:e84263d55307	1294	Otherwise, set it to NULL */
AnnaBridge	167:e84263d55307	1295	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1296	{
AnnaBridge	167:e84263d55307	1297	huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
AnnaBridge	167:e84263d55307	1298	}
AnnaBridge	167:e84263d55307	1299	else
AnnaBridge	167:e84263d55307	1300	{
AnnaBridge	167:e84263d55307	1301	huart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1302	}
AnnaBridge	167:e84263d55307	1303	}
AnnaBridge	167:e84263d55307	1304	/* DMA Rx Handle is valid */
AnnaBridge	167:e84263d55307	1305	if(huart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1306	{
AnnaBridge	167:e84263d55307	1307	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
AnnaBridge	167:e84263d55307	1308	Otherwise, set it to NULL */
AnnaBridge	167:e84263d55307	1309	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1310	{
AnnaBridge	167:e84263d55307	1311	huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
AnnaBridge	167:e84263d55307	1312	}
AnnaBridge	167:e84263d55307	1313	else
AnnaBridge	167:e84263d55307	1314	{
AnnaBridge	167:e84263d55307	1315	huart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1316	}
AnnaBridge	167:e84263d55307	1317	}
AnnaBridge	167:e84263d55307	1318
AnnaBridge	167:e84263d55307	1319	/* Disable the UART DMA Tx request if enabled */
AnnaBridge	167:e84263d55307	1320	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1321	{
AnnaBridge	167:e84263d55307	1322	/* Disable DMA Tx at UART level */
AnnaBridge	167:e84263d55307	1323	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
AnnaBridge	167:e84263d55307	1324
AnnaBridge	167:e84263d55307	1325	/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
AnnaBridge	167:e84263d55307	1326	if(huart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1327	{
AnnaBridge	167:e84263d55307	1328	/* UART Tx DMA Abort callback has already been initialised :
AnnaBridge	167:e84263d55307	1329	will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1330
AnnaBridge	167:e84263d55307	1331	/* Abort DMA TX */
AnnaBridge	167:e84263d55307	1332	if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
AnnaBridge	167:e84263d55307	1333	{
AnnaBridge	167:e84263d55307	1334	huart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1335	}
AnnaBridge	167:e84263d55307	1336	else
AnnaBridge	167:e84263d55307	1337	{
AnnaBridge	167:e84263d55307	1338	AbortCplt = 0x00U;
AnnaBridge	167:e84263d55307	1339	}
AnnaBridge	167:e84263d55307	1340	}
AnnaBridge	167:e84263d55307	1341	}
AnnaBridge	167:e84263d55307	1342
AnnaBridge	167:e84263d55307	1343	/* Disable the UART DMA Rx request if enabled */
AnnaBridge	167:e84263d55307	1344	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1345	{
AnnaBridge	167:e84263d55307	1346	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
AnnaBridge	167:e84263d55307	1347
AnnaBridge	167:e84263d55307	1348	/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
AnnaBridge	167:e84263d55307	1349	if(huart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1350	{
AnnaBridge	167:e84263d55307	1351	/* UART Rx DMA Abort callback has already been initialised :
AnnaBridge	167:e84263d55307	1352	will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1353
AnnaBridge	167:e84263d55307	1354	/* Abort DMA RX */
AnnaBridge	167:e84263d55307	1355	if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
AnnaBridge	167:e84263d55307	1356	{
AnnaBridge	167:e84263d55307	1357	huart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1358	AbortCplt = 0x01U;
AnnaBridge	167:e84263d55307	1359	}
AnnaBridge	167:e84263d55307	1360	else
AnnaBridge	167:e84263d55307	1361	{
AnnaBridge	167:e84263d55307	1362	AbortCplt = 0x00U;
AnnaBridge	167:e84263d55307	1363	}
AnnaBridge	167:e84263d55307	1364	}
AnnaBridge	167:e84263d55307	1365	}
AnnaBridge	167:e84263d55307	1366
AnnaBridge	167:e84263d55307	1367	/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
AnnaBridge	167:e84263d55307	1368	if(AbortCplt == 0x01U)
AnnaBridge	167:e84263d55307	1369	{
AnnaBridge	167:e84263d55307	1370	/* Reset Tx and Rx transfer counters */
AnnaBridge	167:e84263d55307	1371	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1372	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1373
AnnaBridge	167:e84263d55307	1374	/* Reset ErrorCode */
AnnaBridge	167:e84263d55307	1375	huart->ErrorCode = HAL_UART_ERROR_NONE;
AnnaBridge	167:e84263d55307	1376
AnnaBridge	167:e84263d55307	1377	/* Restore huart->gState and huart->RxState to Ready */
AnnaBridge	167:e84263d55307	1378	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1379	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1380
AnnaBridge	167:e84263d55307	1381	/* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge	167:e84263d55307	1382	HAL_UART_AbortCpltCallback(huart);
AnnaBridge	167:e84263d55307	1383	}
AnnaBridge	167:e84263d55307	1384
AnnaBridge	167:e84263d55307	1385	return HAL_OK;
AnnaBridge	167:e84263d55307	1386	}
AnnaBridge	167:e84263d55307	1387
AnnaBridge	167:e84263d55307	1388	/**
AnnaBridge	167:e84263d55307	1389	* @brief Abort ongoing Transmit transfer (Interrupt mode).
AnnaBridge	167:e84263d55307	1390	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1391	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1392	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1393	* - Disable PPP Interrupts
AnnaBridge	167:e84263d55307	1394	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1395	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1396	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1397	* - At abort completion, call user abort complete callback
AnnaBridge	167:e84263d55307	1398	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge	167:e84263d55307	1399	* considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge	167:e84263d55307	1400	* @retval HAL status
AnnaBridge	167:e84263d55307	1401	*/
AnnaBridge	167:e84263d55307	1402	HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1403	{
AnnaBridge	167:e84263d55307	1404	/* Disable TXEIE and TCIE interrupts */
AnnaBridge	167:e84263d55307	1405	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
AnnaBridge	167:e84263d55307	1406
AnnaBridge	167:e84263d55307	1407	/* Disable the UART DMA Tx request if enabled */
AnnaBridge	167:e84263d55307	1408	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
AnnaBridge	167:e84263d55307	1409	{
AnnaBridge	167:e84263d55307	1410	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
AnnaBridge	167:e84263d55307	1411
AnnaBridge	167:e84263d55307	1412	/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1413	if(huart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1414	{
AnnaBridge	167:e84263d55307	1415	/* Set the UART DMA Abort callback :
AnnaBridge	167:e84263d55307	1416	will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1417	huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
AnnaBridge	167:e84263d55307	1418
AnnaBridge	167:e84263d55307	1419	/* Abort DMA TX */
AnnaBridge	167:e84263d55307	1420	if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
AnnaBridge	167:e84263d55307	1421	{
AnnaBridge	167:e84263d55307	1422	/* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
AnnaBridge	167:e84263d55307	1423	huart->hdmatx->XferAbortCallback(huart->hdmatx);
AnnaBridge	167:e84263d55307	1424	}
AnnaBridge	167:e84263d55307	1425	}
AnnaBridge	167:e84263d55307	1426	else
AnnaBridge	167:e84263d55307	1427	{
AnnaBridge	167:e84263d55307	1428	/* Reset Tx transfer counter */
AnnaBridge	167:e84263d55307	1429	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1430
AnnaBridge	167:e84263d55307	1431	/* Restore huart->gState to Ready */
AnnaBridge	167:e84263d55307	1432	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1433
AnnaBridge	167:e84263d55307	1434	/* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge	167:e84263d55307	1435	HAL_UART_AbortTransmitCpltCallback(huart);
AnnaBridge	167:e84263d55307	1436	}
AnnaBridge	167:e84263d55307	1437	}
AnnaBridge	167:e84263d55307	1438	else
AnnaBridge	167:e84263d55307	1439	{
AnnaBridge	167:e84263d55307	1440	/* Reset Tx transfer counter */
AnnaBridge	167:e84263d55307	1441	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1442
AnnaBridge	167:e84263d55307	1443	/* Restore huart->gState to Ready */
AnnaBridge	167:e84263d55307	1444	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1445
AnnaBridge	167:e84263d55307	1446	/* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge	167:e84263d55307	1447	HAL_UART_AbortTransmitCpltCallback(huart);
AnnaBridge	167:e84263d55307	1448	}
AnnaBridge	167:e84263d55307	1449
AnnaBridge	167:e84263d55307	1450	return HAL_OK;
AnnaBridge	167:e84263d55307	1451	}
AnnaBridge	167:e84263d55307	1452
AnnaBridge	167:e84263d55307	1453	/**
AnnaBridge	167:e84263d55307	1454	* @brief Abort ongoing Receive transfer (Interrupt mode).
AnnaBridge	167:e84263d55307	1455	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1456	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1457	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1458	* - Disable PPP Interrupts
AnnaBridge	167:e84263d55307	1459	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1460	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1461	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1462	* - At abort completion, call user abort complete callback
AnnaBridge	167:e84263d55307	1463	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge	167:e84263d55307	1464	* considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge	167:e84263d55307	1465	* @retval HAL status
AnnaBridge	167:e84263d55307	1466	*/
AnnaBridge	167:e84263d55307	1467	HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1468	{
AnnaBridge	167:e84263d55307	1469	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge	167:e84263d55307	1470	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
AnnaBridge	167:e84263d55307	1471	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
AnnaBridge	167:e84263d55307	1472
AnnaBridge	167:e84263d55307	1473	/* Disable the UART DMA Rx request if enabled */
AnnaBridge	167:e84263d55307	1474	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
AnnaBridge	167:e84263d55307	1475	{
AnnaBridge	167:e84263d55307	1476	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
AnnaBridge	167:e84263d55307	1477
AnnaBridge	167:e84263d55307	1478	/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1479	if(huart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1480	{
AnnaBridge	167:e84263d55307	1481	/* Set the UART DMA Abort callback :
AnnaBridge	167:e84263d55307	1482	will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1483	huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
AnnaBridge	167:e84263d55307	1484
AnnaBridge	167:e84263d55307	1485	/* Abort DMA RX */
AnnaBridge	167:e84263d55307	1486	if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
AnnaBridge	167:e84263d55307	1487	{
AnnaBridge	167:e84263d55307	1488	/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
AnnaBridge	167:e84263d55307	1489	huart->hdmarx->XferAbortCallback(huart->hdmarx);
AnnaBridge	167:e84263d55307	1490	}
AnnaBridge	167:e84263d55307	1491	}
AnnaBridge	167:e84263d55307	1492	else
AnnaBridge	167:e84263d55307	1493	{
AnnaBridge	167:e84263d55307	1494	/* Reset Rx transfer counter */
AnnaBridge	167:e84263d55307	1495	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1496
AnnaBridge	167:e84263d55307	1497	/* Restore huart->RxState to Ready */
AnnaBridge	167:e84263d55307	1498	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1499
AnnaBridge	167:e84263d55307	1500	/* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge	167:e84263d55307	1501	HAL_UART_AbortReceiveCpltCallback(huart);
AnnaBridge	167:e84263d55307	1502	}
AnnaBridge	167:e84263d55307	1503	}
AnnaBridge	167:e84263d55307	1504	else
AnnaBridge	167:e84263d55307	1505	{
AnnaBridge	167:e84263d55307	1506	/* Reset Rx transfer counter */
AnnaBridge	167:e84263d55307	1507	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	1508
AnnaBridge	167:e84263d55307	1509	/* Restore huart->RxState to Ready */
AnnaBridge	167:e84263d55307	1510	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	1511
AnnaBridge	167:e84263d55307	1512	/* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge	167:e84263d55307	1513	HAL_UART_AbortReceiveCpltCallback(huart);
AnnaBridge	167:e84263d55307	1514	}
AnnaBridge	167:e84263d55307	1515
AnnaBridge	167:e84263d55307	1516	return HAL_OK;
AnnaBridge	167:e84263d55307	1517	}
AnnaBridge	167:e84263d55307	1518
AnnaBridge	167:e84263d55307	1519	/**
<>	144:ef7eb2e8f9f7	1520	* @brief This function handles UART interrupt request.
<>	144:ef7eb2e8f9f7	1521	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1522	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1523	* @retval None
<>	144:ef7eb2e8f9f7	1524	*/
<>	144:ef7eb2e8f9f7	1525	void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1526	{
<>	144:ef7eb2e8f9f7	1527	uint32_t isrflags = READ_REG(huart->Instance->SR);
<>	144:ef7eb2e8f9f7	1528	uint32_t cr1its = READ_REG(huart->Instance->CR1);
<>	144:ef7eb2e8f9f7	1529	uint32_t cr3its = READ_REG(huart->Instance->CR3);
<>	144:ef7eb2e8f9f7	1530	uint32_t errorflags = 0x00U;
<>	144:ef7eb2e8f9f7	1531	uint32_t dmarequest = 0x00U;
<>	144:ef7eb2e8f9f7	1532
<>	144:ef7eb2e8f9f7	1533	/* If no error occurs */
<>	144:ef7eb2e8f9f7	1534	errorflags = (isrflags & (uint32_t)(USART_SR_PE \| USART_SR_FE \| USART_SR_ORE \| USART_SR_NE));
<>	144:ef7eb2e8f9f7	1535	if(errorflags == RESET)
<>	144:ef7eb2e8f9f7	1536	{
<>	144:ef7eb2e8f9f7	1537	/* UART in mode Receiver -------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1538	if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	144:ef7eb2e8f9f7	1539	{
<>	144:ef7eb2e8f9f7	1540	UART_Receive_IT(huart);
<>	144:ef7eb2e8f9f7	1541	return;
<>	144:ef7eb2e8f9f7	1542	}
<>	144:ef7eb2e8f9f7	1543	}
<>	144:ef7eb2e8f9f7	1544
<>	144:ef7eb2e8f9f7	1545	/* If some errors occur */
<>	144:ef7eb2e8f9f7	1546	if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) \|\| ((cr1its & (USART_CR1_RXNEIE \| USART_CR1_PEIE)) != RESET)))
<>	144:ef7eb2e8f9f7	1547	{
<>	144:ef7eb2e8f9f7	1548	/* UART parity error interrupt occurred ----------------------------------*/
<>	144:ef7eb2e8f9f7	1549	if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<>	144:ef7eb2e8f9f7	1550	{
<>	144:ef7eb2e8f9f7	1551	huart->ErrorCode \|= HAL_UART_ERROR_PE;
<>	144:ef7eb2e8f9f7	1552	}
<>	144:ef7eb2e8f9f7	1553
<>	144:ef7eb2e8f9f7	1554	/* UART noise error interrupt occurred -----------------------------------*/
<>	144:ef7eb2e8f9f7	1555	if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1556	{
<>	144:ef7eb2e8f9f7	1557	huart->ErrorCode \|= HAL_UART_ERROR_NE;
<>	144:ef7eb2e8f9f7	1558	}
<>	144:ef7eb2e8f9f7	1559
<>	144:ef7eb2e8f9f7	1560	/* UART frame error interrupt occurred -----------------------------------*/
<>	144:ef7eb2e8f9f7	1561	if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1562	{
<>	144:ef7eb2e8f9f7	1563	huart->ErrorCode \|= HAL_UART_ERROR_FE;
<>	144:ef7eb2e8f9f7	1564	}
<>	144:ef7eb2e8f9f7	1565
<>	144:ef7eb2e8f9f7	1566	/* UART Over-Run interrupt occurred --------------------------------------*/
<>	144:ef7eb2e8f9f7	1567	if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1568	{
<>	144:ef7eb2e8f9f7	1569	huart->ErrorCode \|= HAL_UART_ERROR_ORE;
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/* Call UART Error Call back function if need be --------------------------*/
<>	144:ef7eb2e8f9f7	1573	if(huart->ErrorCode != HAL_UART_ERROR_NONE)
<>	144:ef7eb2e8f9f7	1574	{
<>	144:ef7eb2e8f9f7	1575	/* UART in mode Receiver -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	1576	if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	144:ef7eb2e8f9f7	1577	{
<>	144:ef7eb2e8f9f7	1578	UART_Receive_IT(huart);
<>	144:ef7eb2e8f9f7	1579	}
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* If Overrun error occurs, or if any error occurs in DMA mode reception,
<>	144:ef7eb2e8f9f7	1582	consider error as blocking */
<>	144:ef7eb2e8f9f7	1583	dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1584	if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) \|\| dmarequest)
<>	144:ef7eb2e8f9f7	1585	{
<>	144:ef7eb2e8f9f7	1586	/* Blocking error : transfer is aborted
<>	144:ef7eb2e8f9f7	1587	Set the UART state ready to be able to start again the process,
<>	144:ef7eb2e8f9f7	1588	Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<>	144:ef7eb2e8f9f7	1589	UART_EndRxTransfer(huart);
<>	144:ef7eb2e8f9f7	1590
<>	144:ef7eb2e8f9f7	1591	/* Disable the UART DMA Rx request if enabled */
<>	144:ef7eb2e8f9f7	1592	if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<>	144:ef7eb2e8f9f7	1593	{
<>	144:ef7eb2e8f9f7	1594	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1595
<>	144:ef7eb2e8f9f7	1596	/* Abort the UART DMA Rx channel */
<>	144:ef7eb2e8f9f7	1597	if(huart->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1598	{
<>	144:ef7eb2e8f9f7	1599	/* Set the UART DMA Abort callback :
<>	144:ef7eb2e8f9f7	1600	will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	1601	huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
<>	144:ef7eb2e8f9f7	1602	if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<>	144:ef7eb2e8f9f7	1603	{
<>	144:ef7eb2e8f9f7	1604	/* Call Directly XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	1605	huart->hdmarx->XferAbortCallback(huart->hdmarx);
<>	144:ef7eb2e8f9f7	1606	}
<>	144:ef7eb2e8f9f7	1607	}
<>	144:ef7eb2e8f9f7	1608	else
<>	144:ef7eb2e8f9f7	1609	{
<>	144:ef7eb2e8f9f7	1610	/* Call user error callback */
<>	144:ef7eb2e8f9f7	1611	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1612	}
<>	144:ef7eb2e8f9f7	1613	}
<>	144:ef7eb2e8f9f7	1614	else
<>	144:ef7eb2e8f9f7	1615	{
<>	144:ef7eb2e8f9f7	1616	/* Call user error callback */
<>	144:ef7eb2e8f9f7	1617	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1618	}
<>	144:ef7eb2e8f9f7	1619	}
<>	144:ef7eb2e8f9f7	1620	else
<>	144:ef7eb2e8f9f7	1621	{
<>	144:ef7eb2e8f9f7	1622	/* Non Blocking error : transfer could go on.
<>	144:ef7eb2e8f9f7	1623	Error is notified to user through user error callback */
<>	144:ef7eb2e8f9f7	1624	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1625	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1626	}
<>	144:ef7eb2e8f9f7	1627	}
<>	144:ef7eb2e8f9f7	1628	return;
<>	144:ef7eb2e8f9f7	1629	} /* End if some error occurs */
<>	144:ef7eb2e8f9f7	1630
<>	144:ef7eb2e8f9f7	1631	/* UART in mode Transmitter ------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1632	if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<>	144:ef7eb2e8f9f7	1633	{
<>	144:ef7eb2e8f9f7	1634	UART_Transmit_IT(huart);
<>	144:ef7eb2e8f9f7	1635	return;
<>	144:ef7eb2e8f9f7	1636	}
<>	144:ef7eb2e8f9f7	1637
<>	144:ef7eb2e8f9f7	1638	/* UART in mode Transmitter end --------------------------------------------*/
<>	144:ef7eb2e8f9f7	1639	if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<>	144:ef7eb2e8f9f7	1640	{
<>	144:ef7eb2e8f9f7	1641	UART_EndTransmit_IT(huart);
<>	144:ef7eb2e8f9f7	1642	return;
<>	144:ef7eb2e8f9f7	1643	}
<>	144:ef7eb2e8f9f7	1644	}
<>	144:ef7eb2e8f9f7	1645
<>	144:ef7eb2e8f9f7	1646	/**
<>	144:ef7eb2e8f9f7	1647	* @brief Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1648	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1649	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1650	* @retval None
<>	144:ef7eb2e8f9f7	1651	*/
<>	144:ef7eb2e8f9f7	1652	__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1653	{
<>	144:ef7eb2e8f9f7	1654	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1655	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1656	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1657	the HAL_UART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1658	*/
<>	144:ef7eb2e8f9f7	1659	}
<>	144:ef7eb2e8f9f7	1660
<>	144:ef7eb2e8f9f7	1661	/**
<>	144:ef7eb2e8f9f7	1662	* @brief Tx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1663	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1664	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1665	* @retval None
<>	144:ef7eb2e8f9f7	1666	*/
<>	144:ef7eb2e8f9f7	1667	__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1668	{
<>	144:ef7eb2e8f9f7	1669	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1670	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1671	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1672	the HAL_UART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1673	*/
<>	144:ef7eb2e8f9f7	1674	}
<>	144:ef7eb2e8f9f7	1675
<>	144:ef7eb2e8f9f7	1676	/**
<>	144:ef7eb2e8f9f7	1677	* @brief Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1678	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1679	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1680	* @retval None
<>	144:ef7eb2e8f9f7	1681	*/
<>	144:ef7eb2e8f9f7	1682	__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1683	{
<>	144:ef7eb2e8f9f7	1684	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1685	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1686	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1687	the HAL_UART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1688	*/
<>	144:ef7eb2e8f9f7	1689	}
<>	144:ef7eb2e8f9f7	1690
<>	144:ef7eb2e8f9f7	1691	/**
<>	144:ef7eb2e8f9f7	1692	* @brief Rx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1693	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1694	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1695	* @retval None
<>	144:ef7eb2e8f9f7	1696	*/
<>	144:ef7eb2e8f9f7	1697	__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1698	{
<>	144:ef7eb2e8f9f7	1699	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1700	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1701	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1702	the HAL_UART_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1703	*/
<>	144:ef7eb2e8f9f7	1704	}
<>	144:ef7eb2e8f9f7	1705
<>	144:ef7eb2e8f9f7	1706	/**
<>	144:ef7eb2e8f9f7	1707	* @brief UART error callbacks.
<>	144:ef7eb2e8f9f7	1708	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1709	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1710	* @retval None
<>	144:ef7eb2e8f9f7	1711	*/
<>	144:ef7eb2e8f9f7	1712	__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1713	{
<>	144:ef7eb2e8f9f7	1714	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1715	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1716	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1717	the HAL_UART_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1718	*/
<>	144:ef7eb2e8f9f7	1719	}
<>	144:ef7eb2e8f9f7	1720
<>	144:ef7eb2e8f9f7	1721	/**
AnnaBridge	167:e84263d55307	1722	* @brief UART Abort Complete callback.
AnnaBridge	167:e84263d55307	1723	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1724	* @retval None
AnnaBridge	167:e84263d55307	1725	*/
AnnaBridge	167:e84263d55307	1726	__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1727	{
AnnaBridge	167:e84263d55307	1728	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	1729	UNUSED(huart);
AnnaBridge	167:e84263d55307	1730
AnnaBridge	167:e84263d55307	1731	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	167:e84263d55307	1732	the HAL_UART_AbortCpltCallback can be implemented in the user file.
AnnaBridge	167:e84263d55307	1733	*/
AnnaBridge	167:e84263d55307	1734	}
AnnaBridge	167:e84263d55307	1735	/**
AnnaBridge	167:e84263d55307	1736	* @brief UART Abort Complete callback.
AnnaBridge	167:e84263d55307	1737	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1738	* @retval None
AnnaBridge	167:e84263d55307	1739	*/
AnnaBridge	167:e84263d55307	1740	__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1741	{
AnnaBridge	167:e84263d55307	1742	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	1743	UNUSED(huart);
AnnaBridge	167:e84263d55307	1744
AnnaBridge	167:e84263d55307	1745	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	167:e84263d55307	1746	the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
AnnaBridge	167:e84263d55307	1747	*/
AnnaBridge	167:e84263d55307	1748	}
AnnaBridge	167:e84263d55307	1749
AnnaBridge	167:e84263d55307	1750	/**
AnnaBridge	167:e84263d55307	1751	* @brief UART Abort Receive Complete callback.
AnnaBridge	167:e84263d55307	1752	* @param huart UART handle.
AnnaBridge	167:e84263d55307	1753	* @retval None
AnnaBridge	167:e84263d55307	1754	*/
AnnaBridge	167:e84263d55307	1755	__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
AnnaBridge	167:e84263d55307	1756	{
AnnaBridge	167:e84263d55307	1757	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	1758	UNUSED(huart);
AnnaBridge	167:e84263d55307	1759
AnnaBridge	167:e84263d55307	1760	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	167:e84263d55307	1761	the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
AnnaBridge	167:e84263d55307	1762	*/
AnnaBridge	167:e84263d55307	1763	}
AnnaBridge	167:e84263d55307	1764
AnnaBridge	167:e84263d55307	1765	/**
<>	144:ef7eb2e8f9f7	1766	* @}
<>	144:ef7eb2e8f9f7	1767	*/
<>	144:ef7eb2e8f9f7	1768
<>	144:ef7eb2e8f9f7	1769	/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1770	* @brief UART control functions
<>	144:ef7eb2e8f9f7	1771	*
<>	144:ef7eb2e8f9f7	1772	@verbatim
<>	144:ef7eb2e8f9f7	1773	==============================================================================
<>	144:ef7eb2e8f9f7	1774	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	1775	==============================================================================
<>	144:ef7eb2e8f9f7	1776	[..]
<>	144:ef7eb2e8f9f7	1777	This subsection provides a set of functions allowing to control the UART:
<>	144:ef7eb2e8f9f7	1778	(+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
<>	144:ef7eb2e8f9f7	1779	(+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
<>	144:ef7eb2e8f9f7	1780	(+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
<>	144:ef7eb2e8f9f7	1781
<>	144:ef7eb2e8f9f7	1782	@endverbatim
<>	144:ef7eb2e8f9f7	1783	* @{
<>	144:ef7eb2e8f9f7	1784	*/
<>	144:ef7eb2e8f9f7	1785
<>	144:ef7eb2e8f9f7	1786	/**
<>	144:ef7eb2e8f9f7	1787	* @brief Transmits break characters.
<>	144:ef7eb2e8f9f7	1788	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1789	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1790	* @retval HAL status
<>	144:ef7eb2e8f9f7	1791	*/
<>	144:ef7eb2e8f9f7	1792	HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1793	{
<>	144:ef7eb2e8f9f7	1794	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1795	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797	/* Process Locked */
<>	144:ef7eb2e8f9f7	1798	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1799
<>	144:ef7eb2e8f9f7	1800	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1801
<>	144:ef7eb2e8f9f7	1802	/* Send break characters */
<>	144:ef7eb2e8f9f7	1803	SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
<>	144:ef7eb2e8f9f7	1804
<>	144:ef7eb2e8f9f7	1805	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1806
<>	144:ef7eb2e8f9f7	1807	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1808	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1809
<>	144:ef7eb2e8f9f7	1810	return HAL_OK;
<>	144:ef7eb2e8f9f7	1811	}
<>	144:ef7eb2e8f9f7	1812
<>	144:ef7eb2e8f9f7	1813	/**
<>	144:ef7eb2e8f9f7	1814	* @brief Enters the UART in mute mode.
<>	144:ef7eb2e8f9f7	1815	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1816	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1817	* @retval HAL status
<>	144:ef7eb2e8f9f7	1818	*/
<>	144:ef7eb2e8f9f7	1819	HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1820	{
<>	144:ef7eb2e8f9f7	1821	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1822	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	1823
<>	144:ef7eb2e8f9f7	1824	/* Process Locked */
<>	144:ef7eb2e8f9f7	1825	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1826
<>	144:ef7eb2e8f9f7	1827	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1828
<>	144:ef7eb2e8f9f7	1829	/* Enable the USART mute mode by setting the RWU bit in the CR1 register */
<>	144:ef7eb2e8f9f7	1830	SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
<>	144:ef7eb2e8f9f7	1831
<>	144:ef7eb2e8f9f7	1832	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1833
<>	144:ef7eb2e8f9f7	1834	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1835	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1836
<>	144:ef7eb2e8f9f7	1837	return HAL_OK;
<>	144:ef7eb2e8f9f7	1838	}
<>	144:ef7eb2e8f9f7	1839
<>	144:ef7eb2e8f9f7	1840	/**
<>	144:ef7eb2e8f9f7	1841	* @brief Exits the UART mute mode: wake up software.
<>	144:ef7eb2e8f9f7	1842	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1843	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1844	* @retval HAL status
<>	144:ef7eb2e8f9f7	1845	*/
<>	144:ef7eb2e8f9f7	1846	HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1847	{
<>	144:ef7eb2e8f9f7	1848	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1849	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	1850
<>	144:ef7eb2e8f9f7	1851	/* Process Locked */
<>	144:ef7eb2e8f9f7	1852	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1853
<>	144:ef7eb2e8f9f7	1854	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1855
<>	144:ef7eb2e8f9f7	1856	/* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
<>	144:ef7eb2e8f9f7	1857	CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
<>	144:ef7eb2e8f9f7	1858
<>	144:ef7eb2e8f9f7	1859	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1860
<>	144:ef7eb2e8f9f7	1861	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1862	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1863
<>	144:ef7eb2e8f9f7	1864	return HAL_OK;
<>	144:ef7eb2e8f9f7	1865	}
<>	144:ef7eb2e8f9f7	1866
<>	144:ef7eb2e8f9f7	1867	/**
<>	144:ef7eb2e8f9f7	1868	* @brief Enables the UART transmitter and disables the UART receiver.
<>	144:ef7eb2e8f9f7	1869	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1870	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1871	* @retval HAL status
<>	144:ef7eb2e8f9f7	1872	*/
<>	144:ef7eb2e8f9f7	1873	HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1874	{
AnnaBridge	167:e84263d55307	1875	uint32_t tmpreg = 0x00U;
<>	144:ef7eb2e8f9f7	1876
<>	144:ef7eb2e8f9f7	1877	/* Process Locked */
<>	144:ef7eb2e8f9f7	1878	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1879
<>	144:ef7eb2e8f9f7	1880	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1881
<>	144:ef7eb2e8f9f7	1882	/-------------------------- USART CR1 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	1883	tmpreg = huart->Instance->CR1;
<>	144:ef7eb2e8f9f7	1884
<>	144:ef7eb2e8f9f7	1885	/* Clear TE and RE bits */
<>	144:ef7eb2e8f9f7	1886	tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE \| USART_CR1_RE));
<>	144:ef7eb2e8f9f7	1887
<>	144:ef7eb2e8f9f7	1888	/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
<>	144:ef7eb2e8f9f7	1889	tmpreg \|= (uint32_t)USART_CR1_TE;
<>	144:ef7eb2e8f9f7	1890
<>	144:ef7eb2e8f9f7	1891	/* Write to USART CR1 */
<>	144:ef7eb2e8f9f7	1892	WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
<>	144:ef7eb2e8f9f7	1893
<>	144:ef7eb2e8f9f7	1894	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1895
<>	144:ef7eb2e8f9f7	1896	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1897	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	return HAL_OK;
<>	144:ef7eb2e8f9f7	1900	}
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902	/**
<>	144:ef7eb2e8f9f7	1903	* @brief Enables the UART receiver and disables the UART transmitter.
<>	144:ef7eb2e8f9f7	1904	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1905	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1906	* @retval HAL status
<>	144:ef7eb2e8f9f7	1907	*/
<>	144:ef7eb2e8f9f7	1908	HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1909	{
<>	144:ef7eb2e8f9f7	1910	uint32_t tmpreg = 0x00U;
<>	144:ef7eb2e8f9f7	1911
<>	144:ef7eb2e8f9f7	1912	/* Process Locked */
<>	144:ef7eb2e8f9f7	1913	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1914
<>	144:ef7eb2e8f9f7	1915	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1916
<>	144:ef7eb2e8f9f7	1917	/-------------------------- USART CR1 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	1918	tmpreg = huart->Instance->CR1;
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/* Clear TE and RE bits */
<>	144:ef7eb2e8f9f7	1921	tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE \| USART_CR1_RE));
<>	144:ef7eb2e8f9f7	1922
<>	144:ef7eb2e8f9f7	1923	/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
<>	144:ef7eb2e8f9f7	1924	tmpreg \|= (uint32_t)USART_CR1_RE;
<>	144:ef7eb2e8f9f7	1925
<>	144:ef7eb2e8f9f7	1926	/* Write to USART CR1 */
<>	144:ef7eb2e8f9f7	1927	WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
<>	144:ef7eb2e8f9f7	1928
<>	144:ef7eb2e8f9f7	1929	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1930
<>	144:ef7eb2e8f9f7	1931	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1932	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1933
<>	144:ef7eb2e8f9f7	1934	return HAL_OK;
<>	144:ef7eb2e8f9f7	1935	}
<>	144:ef7eb2e8f9f7	1936
<>	144:ef7eb2e8f9f7	1937	/**
<>	144:ef7eb2e8f9f7	1938	* @}
<>	144:ef7eb2e8f9f7	1939	*/
<>	144:ef7eb2e8f9f7	1940
<>	144:ef7eb2e8f9f7	1941	/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	1942	* @brief UART State and Errors functions
<>	144:ef7eb2e8f9f7	1943	*
<>	144:ef7eb2e8f9f7	1944	@verbatim
<>	144:ef7eb2e8f9f7	1945	==============================================================================
<>	144:ef7eb2e8f9f7	1946	##### Peripheral State and Errors functions #####
<>	144:ef7eb2e8f9f7	1947	==============================================================================
<>	144:ef7eb2e8f9f7	1948	[..]
<>	144:ef7eb2e8f9f7	1949	This subsection provides a set of functions allowing to return the State of
<>	144:ef7eb2e8f9f7	1950	UART communication process, return Peripheral Errors occurred during communication
<>	144:ef7eb2e8f9f7	1951	process
<>	144:ef7eb2e8f9f7	1952	(+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
<>	144:ef7eb2e8f9f7	1953	(+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
<>	144:ef7eb2e8f9f7	1954
<>	144:ef7eb2e8f9f7	1955	@endverbatim
<>	144:ef7eb2e8f9f7	1956	* @{
<>	144:ef7eb2e8f9f7	1957	*/
<>	144:ef7eb2e8f9f7	1958
<>	144:ef7eb2e8f9f7	1959	/**
<>	144:ef7eb2e8f9f7	1960	* @brief Returns the UART state.
<>	144:ef7eb2e8f9f7	1961	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1962	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1963	* @retval HAL state
<>	144:ef7eb2e8f9f7	1964	*/
<>	144:ef7eb2e8f9f7	1965	HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1966	{
<>	144:ef7eb2e8f9f7	1967	uint32_t temp1= 0x00U, temp2 = 0x00U;
<>	144:ef7eb2e8f9f7	1968	temp1 = huart->gState;
<>	144:ef7eb2e8f9f7	1969	temp2 = huart->RxState;
<>	144:ef7eb2e8f9f7	1970
<>	144:ef7eb2e8f9f7	1971	return (HAL_UART_StateTypeDef)(temp1 \| temp2);
<>	144:ef7eb2e8f9f7	1972	}
<>	144:ef7eb2e8f9f7	1973
<>	144:ef7eb2e8f9f7	1974	/**
<>	144:ef7eb2e8f9f7	1975	* @brief Return the UART error code
<>	144:ef7eb2e8f9f7	1976	* @param huart : pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1977	* the configuration information for the specified UART.
<>	144:ef7eb2e8f9f7	1978	* @retval UART Error Code
<>	144:ef7eb2e8f9f7	1979	*/
<>	144:ef7eb2e8f9f7	1980	uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1981	{
<>	144:ef7eb2e8f9f7	1982	return huart->ErrorCode;
<>	144:ef7eb2e8f9f7	1983	}
<>	144:ef7eb2e8f9f7	1984
<>	144:ef7eb2e8f9f7	1985	/**
<>	144:ef7eb2e8f9f7	1986	* @}
<>	144:ef7eb2e8f9f7	1987	*/
<>	144:ef7eb2e8f9f7	1988
<>	144:ef7eb2e8f9f7	1989	/**
<>	144:ef7eb2e8f9f7	1990	* @brief DMA UART transmit process complete callback.
<>	144:ef7eb2e8f9f7	1991	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	1992	* @retval None
<>	144:ef7eb2e8f9f7	1993	*/
<>	144:ef7eb2e8f9f7	1994	static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1995	{
<>	144:ef7eb2e8f9f7	1996	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	1997	/* DMA Normal mode*/
<>	144:ef7eb2e8f9f7	1998	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<>	144:ef7eb2e8f9f7	1999	{
AnnaBridge	167:e84263d55307	2000	huart->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2001
<>	144:ef7eb2e8f9f7	2002	/* Disable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	2003	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	2004	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	2005
<>	144:ef7eb2e8f9f7	2006	/* Enable the UART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2007	SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	2008
<>	144:ef7eb2e8f9f7	2009	}
<>	144:ef7eb2e8f9f7	2010	/* DMA Circular mode */
<>	144:ef7eb2e8f9f7	2011	else
<>	144:ef7eb2e8f9f7	2012	{
<>	144:ef7eb2e8f9f7	2013	HAL_UART_TxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	2014	}
<>	144:ef7eb2e8f9f7	2015	}
<>	144:ef7eb2e8f9f7	2016
<>	144:ef7eb2e8f9f7	2017	/**
<>	144:ef7eb2e8f9f7	2018	* @brief DMA UART transmit process half complete callback
<>	144:ef7eb2e8f9f7	2019	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2020	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2021	* @retval None
<>	144:ef7eb2e8f9f7	2022	*/
<>	144:ef7eb2e8f9f7	2023	static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2024	{
<>	144:ef7eb2e8f9f7	2025	UART_HandleTypeDef* huart = (UART_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2026
<>	144:ef7eb2e8f9f7	2027	HAL_UART_TxHalfCpltCallback(huart);
<>	144:ef7eb2e8f9f7	2028	}
<>	144:ef7eb2e8f9f7	2029
<>	144:ef7eb2e8f9f7	2030	/**
<>	144:ef7eb2e8f9f7	2031	* @brief DMA UART receive process complete callback.
<>	144:ef7eb2e8f9f7	2032	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2033	* @retval None
<>	144:ef7eb2e8f9f7	2034	*/
<>	144:ef7eb2e8f9f7	2035	static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2036	{
<>	144:ef7eb2e8f9f7	2037	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2038	/* DMA Normal mode*/
<>	144:ef7eb2e8f9f7	2039	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<>	144:ef7eb2e8f9f7	2040	{
AnnaBridge	167:e84263d55307	2041	huart->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2042
<>	144:ef7eb2e8f9f7	2043	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	2044	CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	2045	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2046
<>	144:ef7eb2e8f9f7	2047	/* Disable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	2048	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	2049	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	2050
<>	144:ef7eb2e8f9f7	2051	/* At end of Rx process, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	2052	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2053	}
<>	144:ef7eb2e8f9f7	2054	HAL_UART_RxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	2055	}
<>	144:ef7eb2e8f9f7	2056
<>	144:ef7eb2e8f9f7	2057	/**
<>	144:ef7eb2e8f9f7	2058	* @brief DMA UART receive process half complete callback
<>	144:ef7eb2e8f9f7	2059	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2060	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2061	* @retval None
<>	144:ef7eb2e8f9f7	2062	*/
<>	144:ef7eb2e8f9f7	2063	static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2064	{
<>	144:ef7eb2e8f9f7	2065	UART_HandleTypeDef* huart = (UART_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2066
<>	144:ef7eb2e8f9f7	2067	HAL_UART_RxHalfCpltCallback(huart);
<>	144:ef7eb2e8f9f7	2068	}
<>	144:ef7eb2e8f9f7	2069
<>	144:ef7eb2e8f9f7	2070	/**
<>	144:ef7eb2e8f9f7	2071	* @brief DMA UART communication error callback.
<>	144:ef7eb2e8f9f7	2072	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2073	* @retval None
<>	144:ef7eb2e8f9f7	2074	*/
<>	144:ef7eb2e8f9f7	2075	static void UART_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2076	{
<>	144:ef7eb2e8f9f7	2077	uint32_t dmarequest = 0x00U;
<>	144:ef7eb2e8f9f7	2078	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2079
<>	144:ef7eb2e8f9f7	2080	/* Stop UART DMA Tx request if ongoing */
<>	144:ef7eb2e8f9f7	2081	dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	2082	if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
<>	144:ef7eb2e8f9f7	2083	{
AnnaBridge	167:e84263d55307	2084	huart->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2085	UART_EndTxTransfer(huart);
<>	144:ef7eb2e8f9f7	2086	}
<>	144:ef7eb2e8f9f7	2087
<>	144:ef7eb2e8f9f7	2088	/* Stop UART DMA Rx request if ongoing */
<>	144:ef7eb2e8f9f7	2089	dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	2090	if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
<>	144:ef7eb2e8f9f7	2091	{
AnnaBridge	167:e84263d55307	2092	huart->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2093	UART_EndRxTransfer(huart);
<>	144:ef7eb2e8f9f7	2094	}
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096	huart->ErrorCode \|= HAL_UART_ERROR_DMA;
<>	144:ef7eb2e8f9f7	2097	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	2098	}
<>	144:ef7eb2e8f9f7	2099
<>	144:ef7eb2e8f9f7	2100	/**
<>	144:ef7eb2e8f9f7	2101	* @brief This function handles UART Communication Timeout.
<>	144:ef7eb2e8f9f7	2102	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2103	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	2104	* @param Flag: specifies the UART flag to check.
<>	144:ef7eb2e8f9f7	2105	* @param Status: The new Flag status (SET or RESET).
AnnaBridge	167:e84263d55307	2106	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	2107	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	2108	* @retval HAL status
<>	144:ef7eb2e8f9f7	2109	*/
<>	144:ef7eb2e8f9f7	2110	static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2111	{
<>	144:ef7eb2e8f9f7	2112	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	2113	while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
<>	144:ef7eb2e8f9f7	2114	{
<>	144:ef7eb2e8f9f7	2115	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	2116	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	2117	{
<>	144:ef7eb2e8f9f7	2118	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	2119	{
<>	144:ef7eb2e8f9f7	2120	/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<>	144:ef7eb2e8f9f7	2121	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE));
<>	144:ef7eb2e8f9f7	2122	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2123
<>	144:ef7eb2e8f9f7	2124	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2125	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2126
<>	144:ef7eb2e8f9f7	2127	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2128	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	2129
<>	144:ef7eb2e8f9f7	2130	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2131	}
<>	144:ef7eb2e8f9f7	2132	}
<>	144:ef7eb2e8f9f7	2133	}
<>	144:ef7eb2e8f9f7	2134
<>	144:ef7eb2e8f9f7	2135	return HAL_OK;
<>	144:ef7eb2e8f9f7	2136	}
<>	144:ef7eb2e8f9f7	2137
<>	144:ef7eb2e8f9f7	2138	/**
<>	144:ef7eb2e8f9f7	2139	* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
<>	144:ef7eb2e8f9f7	2140	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	2141	* @retval None
<>	144:ef7eb2e8f9f7	2142	*/
<>	144:ef7eb2e8f9f7	2143	static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2144	{
<>	144:ef7eb2e8f9f7	2145	/* Disable TXEIE and TCIE interrupts */
<>	144:ef7eb2e8f9f7	2146	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	144:ef7eb2e8f9f7	2147
<>	144:ef7eb2e8f9f7	2148	/* At end of Tx process, restore huart->gState to Ready */
<>	144:ef7eb2e8f9f7	2149	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2150	}
<>	144:ef7eb2e8f9f7	2151
<>	144:ef7eb2e8f9f7	2152	/**
<>	144:ef7eb2e8f9f7	2153	* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
<>	144:ef7eb2e8f9f7	2154	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	2155	* @retval None
<>	144:ef7eb2e8f9f7	2156	*/
<>	144:ef7eb2e8f9f7	2157	static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2158	{
<>	144:ef7eb2e8f9f7	2159	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	2160	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	144:ef7eb2e8f9f7	2161	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2162
<>	144:ef7eb2e8f9f7	2163	/* At end of Rx process, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	2164	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2165	}
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	/**
<>	144:ef7eb2e8f9f7	2168	* @brief DMA UART communication abort callback, when initiated by HAL services on Error
<>	144:ef7eb2e8f9f7	2169	* (To be called at end of DMA Abort procedure following error occurrence).
<>	144:ef7eb2e8f9f7	2170	* @param hdma DMA handle.
<>	144:ef7eb2e8f9f7	2171	* @retval None
<>	144:ef7eb2e8f9f7	2172	*/
<>	144:ef7eb2e8f9f7	2173	static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2174	{
<>	144:ef7eb2e8f9f7	2175	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	2176	huart->RxXferCount = 0;
AnnaBridge	167:e84263d55307	2177	huart->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	2180	}
<>	144:ef7eb2e8f9f7	2181
<>	144:ef7eb2e8f9f7	2182	/**
AnnaBridge	167:e84263d55307	2183	* @brief DMA UART Tx communication abort callback, when initiated by user
AnnaBridge	167:e84263d55307	2184	* (To be called at end of DMA Tx Abort procedure following user abort request).
AnnaBridge	167:e84263d55307	2185	* @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge	167:e84263d55307	2186	* Abort still ongoing for Rx DMA Handle.
AnnaBridge	167:e84263d55307	2187	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	2188	* @retval None
AnnaBridge	167:e84263d55307	2189	*/
AnnaBridge	167:e84263d55307	2190	static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	2191	{
AnnaBridge	167:e84263d55307	2192	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	2193
AnnaBridge	167:e84263d55307	2194	huart->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2195
AnnaBridge	167:e84263d55307	2196	/* Check if an Abort process is still ongoing */
AnnaBridge	167:e84263d55307	2197	if(huart->hdmarx != NULL)
AnnaBridge	167:e84263d55307	2198	{
AnnaBridge	167:e84263d55307	2199	if(huart->hdmarx->XferAbortCallback != NULL)
AnnaBridge	167:e84263d55307	2200	{
AnnaBridge	167:e84263d55307	2201	return;
AnnaBridge	167:e84263d55307	2202	}
AnnaBridge	167:e84263d55307	2203	}
AnnaBridge	167:e84263d55307	2204
AnnaBridge	167:e84263d55307	2205	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
AnnaBridge	167:e84263d55307	2206	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	2207	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	2208
AnnaBridge	167:e84263d55307	2209	/* Reset ErrorCode */
AnnaBridge	167:e84263d55307	2210	huart->ErrorCode = HAL_UART_ERROR_NONE;
AnnaBridge	167:e84263d55307	2211
AnnaBridge	167:e84263d55307	2212	/* Restore huart->gState and huart->RxState to Ready */
AnnaBridge	167:e84263d55307	2213	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	2214	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	2215
AnnaBridge	167:e84263d55307	2216	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	2217	HAL_UART_AbortCpltCallback(huart);
AnnaBridge	167:e84263d55307	2218	}
AnnaBridge	167:e84263d55307	2219
AnnaBridge	167:e84263d55307	2220	/**
AnnaBridge	167:e84263d55307	2221	* @brief DMA UART Rx communication abort callback, when initiated by user
AnnaBridge	167:e84263d55307	2222	* (To be called at end of DMA Rx Abort procedure following user abort request).
AnnaBridge	167:e84263d55307	2223	* @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge	167:e84263d55307	2224	* Abort still ongoing for Tx DMA Handle.
AnnaBridge	167:e84263d55307	2225	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	2226	* @retval None
AnnaBridge	167:e84263d55307	2227	*/
AnnaBridge	167:e84263d55307	2228	static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	2229	{
AnnaBridge	167:e84263d55307	2230	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	2231
AnnaBridge	167:e84263d55307	2232	huart->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2233
AnnaBridge	167:e84263d55307	2234	/* Check if an Abort process is still ongoing */
AnnaBridge	167:e84263d55307	2235	if(huart->hdmatx != NULL)
AnnaBridge	167:e84263d55307	2236	{
AnnaBridge	167:e84263d55307	2237	if(huart->hdmatx->XferAbortCallback != NULL)
AnnaBridge	167:e84263d55307	2238	{
AnnaBridge	167:e84263d55307	2239	return;
AnnaBridge	167:e84263d55307	2240	}
AnnaBridge	167:e84263d55307	2241	}
AnnaBridge	167:e84263d55307	2242
AnnaBridge	167:e84263d55307	2243	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
AnnaBridge	167:e84263d55307	2244	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	2245	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	2246
AnnaBridge	167:e84263d55307	2247	/* Reset ErrorCode */
AnnaBridge	167:e84263d55307	2248	huart->ErrorCode = HAL_UART_ERROR_NONE;
AnnaBridge	167:e84263d55307	2249
AnnaBridge	167:e84263d55307	2250	/* Restore huart->gState and huart->RxState to Ready */
AnnaBridge	167:e84263d55307	2251	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	2252	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	2253
AnnaBridge	167:e84263d55307	2254	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	2255	HAL_UART_AbortCpltCallback(huart);
AnnaBridge	167:e84263d55307	2256	}
AnnaBridge	167:e84263d55307	2257
AnnaBridge	167:e84263d55307	2258	/**
AnnaBridge	167:e84263d55307	2259	* @brief DMA UART Tx communication abort callback, when initiated by user by a call to
AnnaBridge	167:e84263d55307	2260	* HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
AnnaBridge	167:e84263d55307	2261	* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
AnnaBridge	167:e84263d55307	2262	* and leads to user Tx Abort Complete callback execution).
AnnaBridge	167:e84263d55307	2263	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	2264	* @retval None
AnnaBridge	167:e84263d55307	2265	*/
AnnaBridge	167:e84263d55307	2266	static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	2267	{
AnnaBridge	167:e84263d55307	2268	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	2269
AnnaBridge	167:e84263d55307	2270	huart->TxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	2271
AnnaBridge	167:e84263d55307	2272	/* Restore huart->gState to Ready */
AnnaBridge	167:e84263d55307	2273	huart->gState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	2274
AnnaBridge	167:e84263d55307	2275	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	2276	HAL_UART_AbortTransmitCpltCallback(huart);
AnnaBridge	167:e84263d55307	2277	}
AnnaBridge	167:e84263d55307	2278
AnnaBridge	167:e84263d55307	2279	/**
AnnaBridge	167:e84263d55307	2280	* @brief DMA UART Rx communication abort callback, when initiated by user by a call to
AnnaBridge	167:e84263d55307	2281	* HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
AnnaBridge	167:e84263d55307	2282	* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
AnnaBridge	167:e84263d55307	2283	* and leads to user Rx Abort Complete callback execution).
AnnaBridge	167:e84263d55307	2284	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	2285	* @retval None
AnnaBridge	167:e84263d55307	2286	*/
AnnaBridge	167:e84263d55307	2287	static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	2288	{
AnnaBridge	167:e84263d55307	2289	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge	167:e84263d55307	2290
AnnaBridge	167:e84263d55307	2291	huart->RxXferCount = 0x00U;
AnnaBridge	167:e84263d55307	2292
AnnaBridge	167:e84263d55307	2293	/* Restore huart->RxState to Ready */
AnnaBridge	167:e84263d55307	2294	huart->RxState = HAL_UART_STATE_READY;
AnnaBridge	167:e84263d55307	2295
AnnaBridge	167:e84263d55307	2296	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	2297	HAL_UART_AbortReceiveCpltCallback(huart);
AnnaBridge	167:e84263d55307	2298	}
AnnaBridge	167:e84263d55307	2299
AnnaBridge	167:e84263d55307	2300	/**
<>	144:ef7eb2e8f9f7	2301	* @brief Sends an amount of data in non blocking mode.
<>	144:ef7eb2e8f9f7	2302	* @param huart: Pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2303	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	2304	* @retval HAL status
<>	144:ef7eb2e8f9f7	2305	*/
<>	144:ef7eb2e8f9f7	2306	static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2307	{
<>	144:ef7eb2e8f9f7	2308	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	2309
<>	144:ef7eb2e8f9f7	2310	/* Check that a Tx process is ongoing */
<>	144:ef7eb2e8f9f7	2311	if(huart->gState == HAL_UART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	2312	{
<>	144:ef7eb2e8f9f7	2313	if(huart->Init.WordLength == UART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	2314	{
<>	144:ef7eb2e8f9f7	2315	tmp = (uint16_t*) huart->pTxBuffPtr;
AnnaBridge	167:e84263d55307	2316	huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
<>	144:ef7eb2e8f9f7	2317	if(huart->Init.Parity == UART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2318	{
<>	144:ef7eb2e8f9f7	2319	huart->pTxBuffPtr += 2;
<>	144:ef7eb2e8f9f7	2320	}
<>	144:ef7eb2e8f9f7	2321	else
<>	144:ef7eb2e8f9f7	2322	{
<>	144:ef7eb2e8f9f7	2323	huart->pTxBuffPtr += 1;
<>	144:ef7eb2e8f9f7	2324	}
<>	144:ef7eb2e8f9f7	2325	}
<>	144:ef7eb2e8f9f7	2326	else
<>	144:ef7eb2e8f9f7	2327	{
AnnaBridge	167:e84263d55307	2328	huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	2329	}
<>	144:ef7eb2e8f9f7	2330
<>	144:ef7eb2e8f9f7	2331	if(--huart->TxXferCount == 0)
<>	144:ef7eb2e8f9f7	2332	{
<>	144:ef7eb2e8f9f7	2333	/* Disable the UART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2334	CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	2335
<>	144:ef7eb2e8f9f7	2336	/* Enable the UART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2337	SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	2338	}
<>	144:ef7eb2e8f9f7	2339	return HAL_OK;
<>	144:ef7eb2e8f9f7	2340	}
<>	144:ef7eb2e8f9f7	2341	else
<>	144:ef7eb2e8f9f7	2342	{
<>	144:ef7eb2e8f9f7	2343	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2344	}
<>	144:ef7eb2e8f9f7	2345	}
<>	144:ef7eb2e8f9f7	2346
<>	144:ef7eb2e8f9f7	2347	/**
<>	144:ef7eb2e8f9f7	2348	* @brief Wraps up transmission in non blocking mode.
<>	144:ef7eb2e8f9f7	2349	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2350	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	2351	* @retval HAL status
<>	144:ef7eb2e8f9f7	2352	*/
<>	144:ef7eb2e8f9f7	2353	static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2354	{
<>	144:ef7eb2e8f9f7	2355	/* Disable the UART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2356	CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	2357
<>	144:ef7eb2e8f9f7	2358	/* Tx process is ended, restore huart->gState to Ready */
<>	144:ef7eb2e8f9f7	2359	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2360
<>	144:ef7eb2e8f9f7	2361	HAL_UART_TxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	2362
<>	144:ef7eb2e8f9f7	2363	return HAL_OK;
<>	144:ef7eb2e8f9f7	2364	}
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/**
<>	144:ef7eb2e8f9f7	2367	* @brief Receives an amount of data in non blocking mode
<>	144:ef7eb2e8f9f7	2368	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2369	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	2370	* @retval HAL status
<>	144:ef7eb2e8f9f7	2371	*/
<>	144:ef7eb2e8f9f7	2372	static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2373	{
<>	144:ef7eb2e8f9f7	2374	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	2375
<>	144:ef7eb2e8f9f7	2376	/* Check that a Rx process is ongoing */
<>	144:ef7eb2e8f9f7	2377	if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	2378	{
<>	144:ef7eb2e8f9f7	2379	if(huart->Init.WordLength == UART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	2380	{
<>	144:ef7eb2e8f9f7	2381	tmp = (uint16_t*) huart->pRxBuffPtr;
<>	144:ef7eb2e8f9f7	2382	if(huart->Init.Parity == UART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2383	{
AnnaBridge	167:e84263d55307	2384	*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
AnnaBridge	167:e84263d55307	2385	huart->pRxBuffPtr += 2;
<>	144:ef7eb2e8f9f7	2386	}
<>	144:ef7eb2e8f9f7	2387	else
<>	144:ef7eb2e8f9f7	2388	{
AnnaBridge	167:e84263d55307	2389	*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
AnnaBridge	167:e84263d55307	2390	huart->pRxBuffPtr += 1;
<>	144:ef7eb2e8f9f7	2391	}
<>	144:ef7eb2e8f9f7	2392	}
<>	144:ef7eb2e8f9f7	2393	else
<>	144:ef7eb2e8f9f7	2394	{
<>	144:ef7eb2e8f9f7	2395	if(huart->Init.Parity == UART_PARITY_NONE)
<>	144:ef7eb2e8f9f7	2396	{
AnnaBridge	167:e84263d55307	2397	*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
<>	144:ef7eb2e8f9f7	2398	}
<>	144:ef7eb2e8f9f7	2399	else
<>	144:ef7eb2e8f9f7	2400	{
AnnaBridge	167:e84263d55307	2401	*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
<>	144:ef7eb2e8f9f7	2402	}
<>	144:ef7eb2e8f9f7	2403	}
<>	144:ef7eb2e8f9f7	2404
<>	144:ef7eb2e8f9f7	2405	if(--huart->RxXferCount == 0)
<>	144:ef7eb2e8f9f7	2406	{
<>	144:ef7eb2e8f9f7	2407	/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
<>	144:ef7eb2e8f9f7	2408	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	144:ef7eb2e8f9f7	2409
<>	144:ef7eb2e8f9f7	2410	/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	2411	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2412
<>	144:ef7eb2e8f9f7	2413	/* Rx process is completed, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	2414	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2415
<>	144:ef7eb2e8f9f7	2416	HAL_UART_RxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	2417
<>	144:ef7eb2e8f9f7	2418	return HAL_OK;
<>	144:ef7eb2e8f9f7	2419	}
<>	144:ef7eb2e8f9f7	2420	return HAL_OK;
<>	144:ef7eb2e8f9f7	2421	}
<>	144:ef7eb2e8f9f7	2422	else
<>	144:ef7eb2e8f9f7	2423	{
<>	144:ef7eb2e8f9f7	2424	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2425	}
<>	144:ef7eb2e8f9f7	2426	}
<>	144:ef7eb2e8f9f7	2427
<>	144:ef7eb2e8f9f7	2428	/**
<>	144:ef7eb2e8f9f7	2429	* @brief Configures the UART peripheral.
<>	144:ef7eb2e8f9f7	2430	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2431	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	2432	* @retval None
<>	144:ef7eb2e8f9f7	2433	*/
<>	144:ef7eb2e8f9f7	2434	static void UART_SetConfig(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2435	{
<>	144:ef7eb2e8f9f7	2436	uint32_t tmpreg = 0x00U;
<>	144:ef7eb2e8f9f7	2437
<>	144:ef7eb2e8f9f7	2438	/* Check the parameters */
AnnaBridge	167:e84263d55307	2439	assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	2440	assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
<>	144:ef7eb2e8f9f7	2441	assert_param(IS_UART_PARITY(huart->Init.Parity));
<>	144:ef7eb2e8f9f7	2442	assert_param(IS_UART_MODE(huart->Init.Mode));
<>	144:ef7eb2e8f9f7	2443
<>	144:ef7eb2e8f9f7	2444	/-------------------------- USART CR2 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2445	tmpreg = huart->Instance->CR2;
<>	144:ef7eb2e8f9f7	2446
<>	144:ef7eb2e8f9f7	2447	/* Clear STOP[13:12] bits */
<>	144:ef7eb2e8f9f7	2448	tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
<>	144:ef7eb2e8f9f7	2449
<>	144:ef7eb2e8f9f7	2450	/* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */
<>	144:ef7eb2e8f9f7	2451	tmpreg \|= (uint32_t)huart->Init.StopBits;
<>	144:ef7eb2e8f9f7	2452
<>	144:ef7eb2e8f9f7	2453	/* Write to USART CR2 */
<>	144:ef7eb2e8f9f7	2454	WRITE_REG(huart->Instance->CR2, (uint32_t)tmpreg);
<>	144:ef7eb2e8f9f7	2455
<>	144:ef7eb2e8f9f7	2456	/-------------------------- USART CR1 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2457	tmpreg = huart->Instance->CR1;
<>	144:ef7eb2e8f9f7	2458
<>	144:ef7eb2e8f9f7	2459	/* Clear M, PCE, PS, TE and RE bits */
<>	144:ef7eb2e8f9f7	2460	tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M \| USART_CR1_PCE \| USART_CR1_PS \| USART_CR1_TE \| \
<>	144:ef7eb2e8f9f7	2461	USART_CR1_RE \| USART_CR1_OVER8));
<>	144:ef7eb2e8f9f7	2462
<>	144:ef7eb2e8f9f7	2463	/* Configure the UART Word Length, Parity and mode:
<>	144:ef7eb2e8f9f7	2464	Set the M bits according to huart->Init.WordLength value
<>	144:ef7eb2e8f9f7	2465	Set PCE and PS bits according to huart->Init.Parity value
<>	144:ef7eb2e8f9f7	2466	Set TE and RE bits according to huart->Init.Mode value
<>	144:ef7eb2e8f9f7	2467	Set OVER8 bit according to huart->Init.OverSampling value */
<>	144:ef7eb2e8f9f7	2468	tmpreg \|= (uint32_t)huart->Init.WordLength \| huart->Init.Parity \| huart->Init.Mode \| huart->Init.OverSampling;
<>	144:ef7eb2e8f9f7	2469
<>	144:ef7eb2e8f9f7	2470	/* Write to USART CR1 */
<>	144:ef7eb2e8f9f7	2471	WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
<>	144:ef7eb2e8f9f7	2472
<>	144:ef7eb2e8f9f7	2473	/-------------------------- USART CR3 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2474	tmpreg = huart->Instance->CR3;
<>	144:ef7eb2e8f9f7	2475
<>	144:ef7eb2e8f9f7	2476	/* Clear CTSE and RTSE bits */
<>	144:ef7eb2e8f9f7	2477	tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_RTSE \| USART_CR3_CTSE));
<>	144:ef7eb2e8f9f7	2478
<>	144:ef7eb2e8f9f7	2479	/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
<>	144:ef7eb2e8f9f7	2480	tmpreg \|= huart->Init.HwFlowCtl;
<>	144:ef7eb2e8f9f7	2481
<>	144:ef7eb2e8f9f7	2482	/* Write to USART CR3 */
<>	144:ef7eb2e8f9f7	2483	WRITE_REG(huart->Instance->CR3, (uint32_t)tmpreg);
<>	144:ef7eb2e8f9f7	2484
<>	144:ef7eb2e8f9f7	2485	/* Check the Over Sampling */
<>	144:ef7eb2e8f9f7	2486	if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
<>	144:ef7eb2e8f9f7	2487	{
<>	144:ef7eb2e8f9f7	2488	/-------------------------- USART BRR Configuration ---------------------/
<>	144:ef7eb2e8f9f7	2489	if((huart->Instance == USART1) \|\| (huart->Instance == USART6))
<>	144:ef7eb2e8f9f7	2490	{
<>	144:ef7eb2e8f9f7	2491	huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2492	}
<>	144:ef7eb2e8f9f7	2493	else
<>	144:ef7eb2e8f9f7	2494	{
<>	144:ef7eb2e8f9f7	2495	huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2496	}
<>	144:ef7eb2e8f9f7	2497	}
<>	144:ef7eb2e8f9f7	2498	else
<>	144:ef7eb2e8f9f7	2499	{
<>	144:ef7eb2e8f9f7	2500	/-------------------------- USART BRR Configuration ---------------------/
<>	144:ef7eb2e8f9f7	2501	if((huart->Instance == USART1) \|\| (huart->Instance == USART6))
<>	144:ef7eb2e8f9f7	2502	{
<>	144:ef7eb2e8f9f7	2503	huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2504	}
<>	144:ef7eb2e8f9f7	2505	else
<>	144:ef7eb2e8f9f7	2506	{
<>	144:ef7eb2e8f9f7	2507	huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2508	}
<>	144:ef7eb2e8f9f7	2509	}
<>	144:ef7eb2e8f9f7	2510	}
<>	144:ef7eb2e8f9f7	2511
<>	144:ef7eb2e8f9f7	2512	/**
<>	144:ef7eb2e8f9f7	2513	* @}
<>	144:ef7eb2e8f9f7	2514	*/
<>	144:ef7eb2e8f9f7	2515
<>	144:ef7eb2e8f9f7	2516	#endif /* HAL_UART_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2517	/**
<>	144:ef7eb2e8f9f7	2518	* @}
<>	144:ef7eb2e8f9f7	2519	*/
<>	144:ef7eb2e8f9f7	2520
<>	144:ef7eb2e8f9f7	2521	/**
<>	144:ef7eb2e8f9f7	2522	* @}
<>	144:ef7eb2e8f9f7	2523	*/
<>	144:ef7eb2e8f9f7	2524
<>	144:ef7eb2e8f9f7	2525	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/