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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 The Timer Extension features include:
<> 144:ef7eb2e8f9f7 20 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 21 (++) Input Capture
<> 144:ef7eb2e8f9f7 22 (++) Output Compare
<> 144:ef7eb2e8f9f7 23 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 24 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 25 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 26 interconnect several timers together.
<> 144:ef7eb2e8f9f7 27 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 28 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 29 positioning purposes
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 32 ==============================================================================
<> 144:ef7eb2e8f9f7 33 [..]
<> 144:ef7eb2e8f9f7 34 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 35 depending from feature used :
<> 144:ef7eb2e8f9f7 36 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 37 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 38 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 39 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 42 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 43 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 44 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 45 __GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 46 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 49 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 50 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 51 any start function.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 54 initialization function of this driver:
<> 144:ef7eb2e8f9f7 55 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 56 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 57 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 58 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 59 the commutation event).
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 62 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 64 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 65 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 @endverbatim
<> 144:ef7eb2e8f9f7 69 ******************************************************************************
<> 144:ef7eb2e8f9f7 70 * @attention
<> 144:ef7eb2e8f9f7 71 *
AnnaBridge 167:e84263d55307 72 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 75 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 76 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 77 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 78 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 79 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 80 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 81 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 82 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 83 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 88 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 92 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 93 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 94 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 107 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 118 * @{
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 /** @defgroup TIMEx_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 132 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 @verbatim
<> 144:ef7eb2e8f9f7 135 ==============================================================================
<> 144:ef7eb2e8f9f7 136 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 137 ==============================================================================
<> 144:ef7eb2e8f9f7 138 [..]
<> 144:ef7eb2e8f9f7 139 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 140 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 141 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 142 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 143 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 144 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 145 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 146 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 147 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 @endverbatim
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 154 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 155 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 156 * @param sConfig: TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 157 * @retval HAL status
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 164 if(htim == NULL)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge 167:e84263d55307 172 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 175 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 178 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 181 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 184 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 187 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 190 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 191 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 192 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 195 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 198 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 199 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 202 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 203 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 206 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 207 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 208 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 209 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 210 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 211 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 212 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 217 register to 101 */
<> 144:ef7eb2e8f9f7 218 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 219 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 222 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 return HAL_OK;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 229 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 230 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 231 * @retval HAL status
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Check the parameters */
<> 144:ef7eb2e8f9f7 236 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 241 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 244 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Change TIM state */
<> 144:ef7eb2e8f9f7 247 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Release Lock */
<> 144:ef7eb2e8f9f7 250 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 return HAL_OK;
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 257 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 258 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 259 * @retval None
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 264 UNUSED(htim);
<> 144:ef7eb2e8f9f7 265 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 266 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 272 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 273 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 274 * @retval None
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 279 UNUSED(htim);
<> 144:ef7eb2e8f9f7 280 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 281 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 287 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 288 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 289 * @retval HAL status
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* Check the parameters */
<> 144:ef7eb2e8f9f7 294 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 297 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 298 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 301 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Return function status */
<> 144:ef7eb2e8f9f7 304 return HAL_OK;
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 309 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 310 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 311 * @retval HAL status
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 /* Check the parameters */
<> 144:ef7eb2e8f9f7 316 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 319 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 320 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 323 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Return function status */
<> 144:ef7eb2e8f9f7 326 return HAL_OK;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 331 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 332 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 333 * @retval HAL status
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 /* Check the parameters */
<> 144:ef7eb2e8f9f7 338 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 341 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 344 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 345 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 348 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Return function status */
<> 144:ef7eb2e8f9f7 351 return HAL_OK;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 356 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 357 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 358 * @retval HAL status
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Check the parameters */
<> 144:ef7eb2e8f9f7 363 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 366 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 367 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 370 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 373 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Return function status */
<> 144:ef7eb2e8f9f7 376 return HAL_OK;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 381 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 382 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 383 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 384 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 385 * @retval HAL status
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Check the parameters */
<> 144:ef7eb2e8f9f7 390 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 397 {
AnnaBridge 167:e84263d55307 398 if(((uint32_t)pData == 0U ) && (Length > 0))
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402 else
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 408 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 409 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 412 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 413 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 414 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Enable the DMA Stream for Capture 1*/
<> 144:ef7eb2e8f9f7 417 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 420 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 423 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Return function status */
<> 144:ef7eb2e8f9f7 426 return HAL_OK;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 431 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 432 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 433 * @retval HAL status
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 /* Check the parameters */
<> 144:ef7eb2e8f9f7 438 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 441 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 446 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 449 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Return function status */
<> 144:ef7eb2e8f9f7 452 return HAL_OK;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @}
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 459 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 460 *
<> 144:ef7eb2e8f9f7 461 @verbatim
<> 144:ef7eb2e8f9f7 462 ==============================================================================
<> 144:ef7eb2e8f9f7 463 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 464 ==============================================================================
<> 144:ef7eb2e8f9f7 465 [..]
<> 144:ef7eb2e8f9f7 466 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 467 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 468 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 469 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 470 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 471 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 472 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 @endverbatim
<> 144:ef7eb2e8f9f7 475 * @{
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 480 * output.
<> 144:ef7eb2e8f9f7 481 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 482 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 483 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 484 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 485 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 486 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 487 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 488 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 489 * @retval HAL status
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 /* Check the parameters */
<> 144:ef7eb2e8f9f7 494 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 497 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 500 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 503 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Return function status */
<> 144:ef7eb2e8f9f7 506 return HAL_OK;
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 511 * output.
<> 144:ef7eb2e8f9f7 512 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 513 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 514 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 515 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 516 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 517 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 518 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 519 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 520 * @retval HAL status
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* Check the parameters */
<> 144:ef7eb2e8f9f7 525 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 528 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 531 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 534 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Return function status */
<> 144:ef7eb2e8f9f7 537 return HAL_OK;
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 542 * on the complementary output.
<> 144:ef7eb2e8f9f7 543 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 544 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 545 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 546 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 547 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 548 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 549 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 550 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 551 * @retval HAL status
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* Check the parameters */
<> 144:ef7eb2e8f9f7 556 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 switch (Channel)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 563 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565 break;
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 570 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572 break;
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 577 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 break;
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 584 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 break;
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 default:
<> 144:ef7eb2e8f9f7 589 break;
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 593 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 596 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 599 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 602 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Return function status */
<> 144:ef7eb2e8f9f7 605 return HAL_OK;
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 610 * on the complementary output.
<> 144:ef7eb2e8f9f7 611 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 612 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 613 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 614 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 615 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 616 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 617 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 618 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 619 * @retval HAL status
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 /* Check the parameters */
<> 144:ef7eb2e8f9f7 624 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 switch (Channel)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 631 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633 break;
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 638 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 break;
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 645 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 break;
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 652 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 break;
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 default:
<> 144:ef7eb2e8f9f7 657 break;
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 661 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 664 if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 670 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 673 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Return function status */
<> 144:ef7eb2e8f9f7 676 return HAL_OK;
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 681 * on the complementary output.
<> 144:ef7eb2e8f9f7 682 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 683 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 684 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 685 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 686 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 687 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 688 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 689 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 690 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 691 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 692 * @retval HAL status
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 /* Check the parameters */
<> 144:ef7eb2e8f9f7 697 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 704 {
AnnaBridge 167:e84263d55307 705 if(((uint32_t)pData == 0U ) && (Length > 0))
<> 144:ef7eb2e8f9f7 706 {
<> 144:ef7eb2e8f9f7 707 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 else
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714 switch (Channel)
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 719 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 722 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 725 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 728 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 break;
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 735 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 738 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 741 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 744 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 745 }
<> 144:ef7eb2e8f9f7 746 break;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 751 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 754 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 757 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 760 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762 break;
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 765 {
<> 144:ef7eb2e8f9f7 766 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 767 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 770 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 773 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 776 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 break;
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 default:
<> 144:ef7eb2e8f9f7 781 break;
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 785 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 788 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 791 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Return function status */
<> 144:ef7eb2e8f9f7 794 return HAL_OK;
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /**
<> 144:ef7eb2e8f9f7 798 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 799 * on the complementary output.
<> 144:ef7eb2e8f9f7 800 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 801 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 802 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 803 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 804 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 805 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 806 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 807 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 808 * @retval HAL status
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 /* Check the parameters */
<> 144:ef7eb2e8f9f7 813 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 switch (Channel)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 820 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822 break;
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 827 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 break;
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 834 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836 break;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 841 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843 break;
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 default:
<> 144:ef7eb2e8f9f7 846 break;
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 850 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 853 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 856 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Change the htim state */
<> 144:ef7eb2e8f9f7 859 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Return function status */
<> 144:ef7eb2e8f9f7 862 return HAL_OK;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864 /**
<> 144:ef7eb2e8f9f7 865 * @}
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 869 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 870 *
<> 144:ef7eb2e8f9f7 871 @verbatim
<> 144:ef7eb2e8f9f7 872 ==============================================================================
<> 144:ef7eb2e8f9f7 873 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 874 ==============================================================================
<> 144:ef7eb2e8f9f7 875 [..]
<> 144:ef7eb2e8f9f7 876 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 877 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 878 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 879 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 880 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 881 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 882 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 883 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 884 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 885 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 886 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 887 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 888 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 889 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 890 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 891 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 892 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 @endverbatim
<> 144:ef7eb2e8f9f7 895 * @{
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /**
<> 144:ef7eb2e8f9f7 899 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 900 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 901 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 902 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 903 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 904 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 905 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 906 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 907 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 908 * @retval HAL status
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 /* Check the parameters */
<> 144:ef7eb2e8f9f7 913 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 916 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 919 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 922 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Return function status */
<> 144:ef7eb2e8f9f7 925 return HAL_OK;
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /**
<> 144:ef7eb2e8f9f7 929 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 930 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 931 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 932 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 933 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 934 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 935 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 936 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 937 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 938 * @retval HAL status
<> 144:ef7eb2e8f9f7 939 */
<> 144:ef7eb2e8f9f7 940 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 /* Check the parameters */
<> 144:ef7eb2e8f9f7 943 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 946 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 949 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 952 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Return function status */
<> 144:ef7eb2e8f9f7 955 return HAL_OK;
<> 144:ef7eb2e8f9f7 956 }
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /**
<> 144:ef7eb2e8f9f7 959 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 960 * complementary output.
<> 144:ef7eb2e8f9f7 961 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 962 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 963 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 964 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 965 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 966 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 967 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 968 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 969 * @retval HAL status
<> 144:ef7eb2e8f9f7 970 */
<> 144:ef7eb2e8f9f7 971 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 /* Check the parameters */
<> 144:ef7eb2e8f9f7 974 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 switch (Channel)
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 981 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 982 }
<> 144:ef7eb2e8f9f7 983 break;
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 988 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 989 }
<> 144:ef7eb2e8f9f7 990 break;
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 995 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 break;
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1002 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004 break;
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 default:
<> 144:ef7eb2e8f9f7 1007 break;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1011 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1014 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1017 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1020 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /* Return function status */
<> 144:ef7eb2e8f9f7 1023 return HAL_OK;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
<> 144:ef7eb2e8f9f7 1027 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1028 * complementary output.
<> 144:ef7eb2e8f9f7 1029 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1030 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1031 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1032 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1033 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1034 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1035 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1036 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1037 * @retval HAL status
<> 144:ef7eb2e8f9f7 1038 */
<> 144:ef7eb2e8f9f7 1039 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1042 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 switch (Channel)
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1047 {
<> 144:ef7eb2e8f9f7 1048 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1049 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051 break;
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1056 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058 break;
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1061 {
<> 144:ef7eb2e8f9f7 1062 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1063 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065 break;
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1070 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 break;
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 default:
<> 144:ef7eb2e8f9f7 1075 break;
<> 144:ef7eb2e8f9f7 1076 }
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1079 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1082 if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1088 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1091 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Return function status */
<> 144:ef7eb2e8f9f7 1094 return HAL_OK;
<> 144:ef7eb2e8f9f7 1095 }
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /**
<> 144:ef7eb2e8f9f7 1098 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1099 * complementary output
<> 144:ef7eb2e8f9f7 1100 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1101 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1102 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1103 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1104 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1105 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1106 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1107 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1108 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1109 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1110 * @retval HAL status
<> 144:ef7eb2e8f9f7 1111 */
<> 144:ef7eb2e8f9f7 1112 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1115 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1122 {
AnnaBridge 167:e84263d55307 1123 if(((uint32_t)pData == 0U ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1124 {
<> 144:ef7eb2e8f9f7 1125 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127 else
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1130 }
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132 switch (Channel)
<> 144:ef7eb2e8f9f7 1133 {
<> 144:ef7eb2e8f9f7 1134 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1135 {
<> 144:ef7eb2e8f9f7 1136 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1137 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1140 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1143 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1146 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148 break;
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1153 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1156 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1159 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1162 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1163 }
<> 144:ef7eb2e8f9f7 1164 break;
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1167 {
<> 144:ef7eb2e8f9f7 1168 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1169 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1172 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1175 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1178 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1179 }
<> 144:ef7eb2e8f9f7 1180 break;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1183 {
<> 144:ef7eb2e8f9f7 1184 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1185 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1188 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1191 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1194 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196 break;
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 default:
<> 144:ef7eb2e8f9f7 1199 break;
<> 144:ef7eb2e8f9f7 1200 }
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1203 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1206 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1209 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Return function status */
<> 144:ef7eb2e8f9f7 1212 return HAL_OK;
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /**
<> 144:ef7eb2e8f9f7 1216 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1217 * output
<> 144:ef7eb2e8f9f7 1218 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1219 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1220 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1221 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1222 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1223 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1224 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1225 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1226 * @retval HAL status
<> 144:ef7eb2e8f9f7 1227 */
<> 144:ef7eb2e8f9f7 1228 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1231 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 switch (Channel)
<> 144:ef7eb2e8f9f7 1234 {
<> 144:ef7eb2e8f9f7 1235 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1236 {
<> 144:ef7eb2e8f9f7 1237 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1238 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1239 }
<> 144:ef7eb2e8f9f7 1240 break;
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1243 {
<> 144:ef7eb2e8f9f7 1244 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1245 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1246 }
<> 144:ef7eb2e8f9f7 1247 break;
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1250 {
<> 144:ef7eb2e8f9f7 1251 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1252 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1253 }
<> 144:ef7eb2e8f9f7 1254 break;
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1257 {
<> 144:ef7eb2e8f9f7 1258 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1259 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261 break;
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 default:
<> 144:ef7eb2e8f9f7 1264 break;
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1268 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1271 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1274 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1277 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Return function status */
<> 144:ef7eb2e8f9f7 1280 return HAL_OK;
<> 144:ef7eb2e8f9f7 1281 }
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /**
<> 144:ef7eb2e8f9f7 1284 * @}
<> 144:ef7eb2e8f9f7 1285 */
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1288 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1289 *
<> 144:ef7eb2e8f9f7 1290 @verbatim
<> 144:ef7eb2e8f9f7 1291 ==============================================================================
<> 144:ef7eb2e8f9f7 1292 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1293 ==============================================================================
<> 144:ef7eb2e8f9f7 1294 [..]
<> 144:ef7eb2e8f9f7 1295 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1296 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1297 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1298 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1299 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 @endverbatim
<> 144:ef7eb2e8f9f7 1302 * @{
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /**
<> 144:ef7eb2e8f9f7 1306 * @brief Starts the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1307 * output.
<> 144:ef7eb2e8f9f7 1308 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1309 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1310 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1311 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1312 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1313 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1314 * @retval HAL status
<> 144:ef7eb2e8f9f7 1315 */
<> 144:ef7eb2e8f9f7 1316 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1319 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1322 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1325 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Return function status */
<> 144:ef7eb2e8f9f7 1328 return HAL_OK;
<> 144:ef7eb2e8f9f7 1329 }
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 /**
<> 144:ef7eb2e8f9f7 1332 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1333 * output.
<> 144:ef7eb2e8f9f7 1334 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1335 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1336 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1337 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1338 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1339 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1340 * @retval HAL status
<> 144:ef7eb2e8f9f7 1341 */
<> 144:ef7eb2e8f9f7 1342 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1343 {
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1346 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1349 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1352 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1355 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1356
<> 144:ef7eb2e8f9f7 1357 /* Return function status */
<> 144:ef7eb2e8f9f7 1358 return HAL_OK;
<> 144:ef7eb2e8f9f7 1359 }
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 /**
<> 144:ef7eb2e8f9f7 1362 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1363 * complementary channel.
<> 144:ef7eb2e8f9f7 1364 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1365 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1366 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1367 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1368 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1369 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1370 * @retval HAL status
<> 144:ef7eb2e8f9f7 1371 */
<> 144:ef7eb2e8f9f7 1372 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1373 {
<> 144:ef7eb2e8f9f7 1374 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1375 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1378 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1381 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1384 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1387 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /* Return function status */
<> 144:ef7eb2e8f9f7 1390 return HAL_OK;
<> 144:ef7eb2e8f9f7 1391 }
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /**
<> 144:ef7eb2e8f9f7 1394 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1395 * complementary channel.
<> 144:ef7eb2e8f9f7 1396 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1397 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1398 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1399 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1402 * @retval HAL status
<> 144:ef7eb2e8f9f7 1403 */
<> 144:ef7eb2e8f9f7 1404 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1405 {
<> 144:ef7eb2e8f9f7 1406 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1407 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1410 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1413 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1416 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1419 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1422 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /* Return function status */
<> 144:ef7eb2e8f9f7 1425 return HAL_OK;
<> 144:ef7eb2e8f9f7 1426 }
<> 144:ef7eb2e8f9f7 1427 /**
<> 144:ef7eb2e8f9f7 1428 * @}
<> 144:ef7eb2e8f9f7 1429 */
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1432 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1433 *
<> 144:ef7eb2e8f9f7 1434 @verbatim
<> 144:ef7eb2e8f9f7 1435 ==============================================================================
<> 144:ef7eb2e8f9f7 1436 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1437 ==============================================================================
<> 144:ef7eb2e8f9f7 1438 [..]
<> 144:ef7eb2e8f9f7 1439 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1440 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 1441 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 1442 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1443 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 1444 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1445 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 @endverbatim
<> 144:ef7eb2e8f9f7 1448 * @{
<> 144:ef7eb2e8f9f7 1449 */
<> 144:ef7eb2e8f9f7 1450 /**
<> 144:ef7eb2e8f9f7 1451 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1452 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1453 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1454 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1455 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1456 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1457 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1458 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1459 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1460 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1461 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1462 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1463 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1464 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1465 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1466 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1467 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1468 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1469 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1470 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1471 * @retval HAL status
<> 144:ef7eb2e8f9f7 1472 */
<> 144:ef7eb2e8f9f7 1473 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1474 {
<> 144:ef7eb2e8f9f7 1475 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1476 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1477 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1482 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1483 {
<> 144:ef7eb2e8f9f7 1484 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1485 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1486 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1487 }
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1490 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1491 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1492 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1493 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 return HAL_OK;
<> 144:ef7eb2e8f9f7 1498 }
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /**
<> 144:ef7eb2e8f9f7 1501 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1502 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1503 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1504 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1505 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1506 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1507 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1508 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1509 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1510 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1511 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1512 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1513 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1514 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1515 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1516 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1517 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1518 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1519 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1520 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1521 * @retval HAL status
<> 144:ef7eb2e8f9f7 1522 */
<> 144:ef7eb2e8f9f7 1523 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1524 {
<> 144:ef7eb2e8f9f7 1525 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1526 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1527 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1530
<> 144:ef7eb2e8f9f7 1531 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1532 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1533 {
<> 144:ef7eb2e8f9f7 1534 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1535 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1536 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1537 }
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1540 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1541 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1542 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1543 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1546 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 return HAL_OK;
<> 144:ef7eb2e8f9f7 1551 }
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /**
<> 144:ef7eb2e8f9f7 1554 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1555 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1556 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1557 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1558 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1559 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1560 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1561 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1562 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1563 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1564 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1565 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1566 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1567 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1568 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1569 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1570 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1571 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1572 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1573 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1574 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1575 * @retval HAL status
<> 144:ef7eb2e8f9f7 1576 */
<> 144:ef7eb2e8f9f7 1577 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1578 {
<> 144:ef7eb2e8f9f7 1579 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1580 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1581 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1582
<> 144:ef7eb2e8f9f7 1583 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1586 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1587 {
<> 144:ef7eb2e8f9f7 1588 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1589 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1590 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1591 }
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1594 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1595 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1596 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1597 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1600 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1601 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1602 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1603 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1606 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 return HAL_OK;
<> 144:ef7eb2e8f9f7 1611 }
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613 /**
<> 144:ef7eb2e8f9f7 1614 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 1615 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1616 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1617 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1618 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1619 * mode.
<> 144:ef7eb2e8f9f7 1620 * @retval HAL status
<> 144:ef7eb2e8f9f7 1621 */
<> 144:ef7eb2e8f9f7 1622 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1623 {
<> 144:ef7eb2e8f9f7 1624 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1625 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1626 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1627 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1634 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1635 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1636 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1639 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1640 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1641 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 return HAL_OK;
<> 144:ef7eb2e8f9f7 1648 }
<> 144:ef7eb2e8f9f7 1649
<> 144:ef7eb2e8f9f7 1650 /**
<> 144:ef7eb2e8f9f7 1651 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1652 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 1653 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1654 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1655 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
<> 144:ef7eb2e8f9f7 1656 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1657 * @retval HAL status
<> 144:ef7eb2e8f9f7 1658 */
AnnaBridge 167:e84263d55307 1659 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
AnnaBridge 167:e84263d55307 1660 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1661 {
AnnaBridge 167:e84263d55307 1662 uint32_t tmpbdtr = 0;
AnnaBridge 167:e84263d55307 1663
<> 144:ef7eb2e8f9f7 1664 /* Check the parameters */
AnnaBridge 167:e84263d55307 1665 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1666 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1667 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1668 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
AnnaBridge 167:e84263d55307 1669 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1670 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1671 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1672 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 1673
AnnaBridge 167:e84263d55307 1674 /* Check input state */
<> 144:ef7eb2e8f9f7 1675 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 1678 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 144:ef7eb2e8f9f7 1679
AnnaBridge 167:e84263d55307 1680 /* Set the BDTR bits */
AnnaBridge 167:e84263d55307 1681 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
AnnaBridge 167:e84263d55307 1682 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
AnnaBridge 167:e84263d55307 1683 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
AnnaBridge 167:e84263d55307 1684 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
AnnaBridge 167:e84263d55307 1685 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
AnnaBridge 167:e84263d55307 1686 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
AnnaBridge 167:e84263d55307 1687 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
AnnaBridge 167:e84263d55307 1688 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
AnnaBridge 167:e84263d55307 1689
AnnaBridge 167:e84263d55307 1690 /* Set TIMx_BDTR */
AnnaBridge 167:e84263d55307 1691 htim->Instance->BDTR = tmpbdtr;
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 __HAL_UNLOCK(htim);
AnnaBridge 167:e84263d55307 1694
<> 144:ef7eb2e8f9f7 1695 return HAL_OK;
<> 144:ef7eb2e8f9f7 1696 }
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 /**
<> 144:ef7eb2e8f9f7 1699 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
<> 144:ef7eb2e8f9f7 1700 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1701 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1702 * @param Remap: specifies the TIM input remapping source.
<> 144:ef7eb2e8f9f7 1703 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1704 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
<> 144:ef7eb2e8f9f7 1705 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
<> 144:ef7eb2e8f9f7 1706 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
<> 144:ef7eb2e8f9f7 1707 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
<> 144:ef7eb2e8f9f7 1708 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
<> 144:ef7eb2e8f9f7 1709 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
<> 144:ef7eb2e8f9f7 1710 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
<> 144:ef7eb2e8f9f7 1711 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
<> 144:ef7eb2e8f9f7 1712 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
<> 144:ef7eb2e8f9f7 1713 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
<> 144:ef7eb2e8f9f7 1714 * (HSE divided by a programmable prescaler)
<> 144:ef7eb2e8f9f7 1715 * @retval HAL status
<> 144:ef7eb2e8f9f7 1716 */
<> 144:ef7eb2e8f9f7 1717 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 1718 {
<> 144:ef7eb2e8f9f7 1719 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /* Check parameters */
<> 144:ef7eb2e8f9f7 1722 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1723 assert_param(IS_TIM_REMAP(Remap));
<> 144:ef7eb2e8f9f7 1724
<> 144:ef7eb2e8f9f7 1725 /* Set the Timer remapping configuration */
<> 144:ef7eb2e8f9f7 1726 htim->Instance->OR = Remap;
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1729
<> 144:ef7eb2e8f9f7 1730 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732 return HAL_OK;
<> 144:ef7eb2e8f9f7 1733 }
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 /**
<> 144:ef7eb2e8f9f7 1736 * @}
<> 144:ef7eb2e8f9f7 1737 */
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1740 * @brief Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1741 *
<> 144:ef7eb2e8f9f7 1742 @verbatim
<> 144:ef7eb2e8f9f7 1743 ==============================================================================
<> 144:ef7eb2e8f9f7 1744 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 1745 ==============================================================================
<> 144:ef7eb2e8f9f7 1746 [..]
<> 144:ef7eb2e8f9f7 1747 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 1748 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 1749 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 @endverbatim
<> 144:ef7eb2e8f9f7 1752 * @{
<> 144:ef7eb2e8f9f7 1753 */
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 /**
<> 144:ef7eb2e8f9f7 1756 * @brief Hall commutation changed callback in non blocking mode
<> 144:ef7eb2e8f9f7 1757 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1758 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1759 * @retval None
<> 144:ef7eb2e8f9f7 1760 */
<> 144:ef7eb2e8f9f7 1761 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1762 {
<> 144:ef7eb2e8f9f7 1763 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1764 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1765 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1766 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1767 */
<> 144:ef7eb2e8f9f7 1768 }
<> 144:ef7eb2e8f9f7 1769
<> 144:ef7eb2e8f9f7 1770 /**
<> 144:ef7eb2e8f9f7 1771 * @brief Hall Break detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 1772 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1773 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1774 * @retval None
<> 144:ef7eb2e8f9f7 1775 */
<> 144:ef7eb2e8f9f7 1776 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1777 {
<> 144:ef7eb2e8f9f7 1778 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1779 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1780 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1781 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1782 */
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784 /**
<> 144:ef7eb2e8f9f7 1785 * @}
<> 144:ef7eb2e8f9f7 1786 */
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1789 * @brief Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1790 *
<> 144:ef7eb2e8f9f7 1791 @verbatim
<> 144:ef7eb2e8f9f7 1792 ==============================================================================
<> 144:ef7eb2e8f9f7 1793 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1794 ==============================================================================
<> 144:ef7eb2e8f9f7 1795 [..]
<> 144:ef7eb2e8f9f7 1796 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1797 and the data flow.
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 @endverbatim
<> 144:ef7eb2e8f9f7 1800 * @{
<> 144:ef7eb2e8f9f7 1801 */
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 /**
<> 144:ef7eb2e8f9f7 1804 * @brief Return the TIM Hall Sensor interface state
<> 144:ef7eb2e8f9f7 1805 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1806 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1807 * @retval HAL state
<> 144:ef7eb2e8f9f7 1808 */
<> 144:ef7eb2e8f9f7 1809 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1810 {
<> 144:ef7eb2e8f9f7 1811 return htim->State;
<> 144:ef7eb2e8f9f7 1812 }
<> 144:ef7eb2e8f9f7 1813
<> 144:ef7eb2e8f9f7 1814 /**
<> 144:ef7eb2e8f9f7 1815 * @}
<> 144:ef7eb2e8f9f7 1816 */
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /**
<> 144:ef7eb2e8f9f7 1819 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 1820 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1821 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1822 * @retval None
<> 144:ef7eb2e8f9f7 1823 */
<> 144:ef7eb2e8f9f7 1824 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1825 {
<> 144:ef7eb2e8f9f7 1826 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1827
<> 144:ef7eb2e8f9f7 1828 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 1831 }
<> 144:ef7eb2e8f9f7 1832 /**
<> 144:ef7eb2e8f9f7 1833 * @}
<> 144:ef7eb2e8f9f7 1834 */
<> 144:ef7eb2e8f9f7 1835
<> 144:ef7eb2e8f9f7 1836 /**
<> 144:ef7eb2e8f9f7 1837 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 1838 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 1839 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1840 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1841 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1842 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1843 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1844 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 1845 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 1846 * @retval None
<> 144:ef7eb2e8f9f7 1847 */
<> 144:ef7eb2e8f9f7 1848 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 1849 {
<> 144:ef7eb2e8f9f7 1850 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1853 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 1854 assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 1857
<> 144:ef7eb2e8f9f7 1858 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1859 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1862 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 1863 }
<> 144:ef7eb2e8f9f7 1864
<> 144:ef7eb2e8f9f7 1865 /**
<> 144:ef7eb2e8f9f7 1866 * @}
<> 144:ef7eb2e8f9f7 1867 */
<> 144:ef7eb2e8f9f7 1868
<> 144:ef7eb2e8f9f7 1869 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1870 /**
<> 144:ef7eb2e8f9f7 1871 * @}
<> 144:ef7eb2e8f9f7 1872 */
<> 144:ef7eb2e8f9f7 1873
<> 144:ef7eb2e8f9f7 1874 /**
<> 144:ef7eb2e8f9f7 1875 * @}
<> 144:ef7eb2e8f9f7 1876 */
<> 144:ef7eb2e8f9f7 1877 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/