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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_tim.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief Header file of TIM HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
AnnaBridge	167:e84263d55307	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F2xx_HAL_TIM_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F2xx_HAL_TIM_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f2xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup TIM
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup TIM_Exported_Types TIM Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief TIM Time base Configuration Structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	144:ef7eb2e8f9f7	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	144:ef7eb2e8f9f7	71	This parameter can be a value of @ref TIM_Counter_Mode */
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
<>	144:ef7eb2e8f9f7	74	Auto-Reload Register at the next update event.
<>	144:ef7eb2e8f9f7	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<>	144:ef7eb2e8f9f7	76
<>	144:ef7eb2e8f9f7	77	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	144:ef7eb2e8f9f7	78	This parameter can be a value of @ref TIM_ClockDivision */
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	144:ef7eb2e8f9f7	81	reaches zero, an update event is generated and counting restarts
<>	144:ef7eb2e8f9f7	82	from the RCR value (N).
<>	144:ef7eb2e8f9f7	83	This means in PWM mode that (N+1) corresponds to:
<>	144:ef7eb2e8f9f7	84	- the number of PWM periods in edge-aligned mode
<>	144:ef7eb2e8f9f7	85	- the number of half PWM period in center-aligned mode
<>	144:ef7eb2e8f9f7	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	144:ef7eb2e8f9f7	87	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	167:e84263d55307	88
AnnaBridge	167:e84263d55307	89	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
AnnaBridge	167:e84263d55307	90	This parameter can be a value of @ref TIM_AutoReloadPreload */
<>	144:ef7eb2e8f9f7	91	} TIM_Base_InitTypeDef;
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	/**
<>	144:ef7eb2e8f9f7	94	* @brief TIM Output Compare Configuration Structure definition
<>	144:ef7eb2e8f9f7	95	*/
<>	144:ef7eb2e8f9f7	96
<>	144:ef7eb2e8f9f7	97	typedef struct
<>	144:ef7eb2e8f9f7	98	{
<>	144:ef7eb2e8f9f7	99	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	144:ef7eb2e8f9f7	100	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	103	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	106	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	144:ef7eb2e8f9f7	109	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<>	144:ef7eb2e8f9f7	110	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
<>	144:ef7eb2e8f9f7	113	This parameter can be a value of @ref TIM_Output_Fast_State
<>	144:ef7eb2e8f9f7	114	@note This parameter is valid only in PWM1 and PWM2 mode. */
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116
<>	144:ef7eb2e8f9f7	117	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	118	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<>	144:ef7eb2e8f9f7	119	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	122	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<>	144:ef7eb2e8f9f7	123	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	124	} TIM_OC_InitTypeDef;
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	/**
<>	144:ef7eb2e8f9f7	127	* @brief TIM One Pulse Mode Configuration Structure definition
<>	144:ef7eb2e8f9f7	128	*/
<>	144:ef7eb2e8f9f7	129	typedef struct
<>	144:ef7eb2e8f9f7	130	{
<>	144:ef7eb2e8f9f7	131	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	144:ef7eb2e8f9f7	132	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	144:ef7eb2e8f9f7	133
<>	144:ef7eb2e8f9f7	134	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	135	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	138	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	144:ef7eb2e8f9f7	141	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<>	144:ef7eb2e8f9f7	142	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	145	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<>	144:ef7eb2e8f9f7	146	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	147
<>	144:ef7eb2e8f9f7	148	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	149	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<>	144:ef7eb2e8f9f7	150	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	151
<>	144:ef7eb2e8f9f7	152	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	153	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155	uint32_t ICSelection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	156	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	157
<>	144:ef7eb2e8f9f7	158	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	159	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	160	} TIM_OnePulse_InitTypeDef;
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	/**
<>	144:ef7eb2e8f9f7	164	* @brief TIM Input Capture Configuration Structure definition
<>	144:ef7eb2e8f9f7	165	*/
<>	144:ef7eb2e8f9f7	166
<>	144:ef7eb2e8f9f7	167	typedef struct
<>	144:ef7eb2e8f9f7	168	{
<>	144:ef7eb2e8f9f7	169	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	170	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	uint32_t ICSelection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	173	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	176	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	179	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	180	} TIM_IC_InitTypeDef;
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	/**
<>	144:ef7eb2e8f9f7	183	* @brief TIM Encoder Configuration Structure definition
<>	144:ef7eb2e8f9f7	184	*/
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186	typedef struct
<>	144:ef7eb2e8f9f7	187	{
<>	144:ef7eb2e8f9f7	188	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	189	This parameter can be a value of @ref TIM_Encoder_Mode */
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	192	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	193
<>	144:ef7eb2e8f9f7	194	uint32_t IC1Selection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	195	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	198	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200	uint32_t IC1Filter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	201	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	204	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	uint32_t IC2Selection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	207	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	208
<>	144:ef7eb2e8f9f7	209	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	210	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	uint32_t IC2Filter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	213	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	214	} TIM_Encoder_InitTypeDef;
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	/**
<>	144:ef7eb2e8f9f7	217	* @brief Clock Configuration Handle Structure definition
<>	144:ef7eb2e8f9f7	218	*/
<>	144:ef7eb2e8f9f7	219	typedef struct
<>	144:ef7eb2e8f9f7	220	{
<>	144:ef7eb2e8f9f7	221	uint32_t ClockSource; /*!< TIM clock sources.
<>	144:ef7eb2e8f9f7	222	This parameter can be a value of @ref TIM_Clock_Source */
<>	144:ef7eb2e8f9f7	223	uint32_t ClockPolarity; /*!< TIM clock polarity.
<>	144:ef7eb2e8f9f7	224	This parameter can be a value of @ref TIM_Clock_Polarity */
<>	144:ef7eb2e8f9f7	225	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
<>	144:ef7eb2e8f9f7	226	This parameter can be a value of @ref TIM_Clock_Prescaler */
<>	144:ef7eb2e8f9f7	227	uint32_t ClockFilter; /*!< TIM clock filter.
<>	144:ef7eb2e8f9f7	228	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	229	}TIM_ClockConfigTypeDef;
<>	144:ef7eb2e8f9f7	230
<>	144:ef7eb2e8f9f7	231	/**
<>	144:ef7eb2e8f9f7	232	* @brief Clear Input Configuration Handle Structure definition
<>	144:ef7eb2e8f9f7	233	*/
<>	144:ef7eb2e8f9f7	234	typedef struct
<>	144:ef7eb2e8f9f7	235	{
<>	144:ef7eb2e8f9f7	236	uint32_t ClearInputState; /*!< TIM clear Input state.
<>	144:ef7eb2e8f9f7	237	This parameter can be ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	238	uint32_t ClearInputSource; /*!< TIM clear Input sources.
<>	144:ef7eb2e8f9f7	239	This parameter can be a value of @ref TIM_ClearInput_Source */
<>	144:ef7eb2e8f9f7	240	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
<>	144:ef7eb2e8f9f7	241	This parameter can be a value of @ref TIM_ClearInput_Polarity */
<>	144:ef7eb2e8f9f7	242	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
<>	144:ef7eb2e8f9f7	243	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
<>	144:ef7eb2e8f9f7	244	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
<>	144:ef7eb2e8f9f7	245	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	246	}TIM_ClearInputConfigTypeDef;
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	/**
<>	144:ef7eb2e8f9f7	249	* @brief TIM Slave configuration Structure definition
<>	144:ef7eb2e8f9f7	250	*/
<>	144:ef7eb2e8f9f7	251	typedef struct {
<>	144:ef7eb2e8f9f7	252	uint32_t SlaveMode; /*!< Slave mode selection
<>	144:ef7eb2e8f9f7	253	This parameter can be a value of @ref TIM_Slave_Mode */
<>	144:ef7eb2e8f9f7	254	uint32_t InputTrigger; /*!< Input Trigger source
<>	144:ef7eb2e8f9f7	255	This parameter can be a value of @ref TIM_Trigger_Selection */
<>	144:ef7eb2e8f9f7	256	uint32_t TriggerPolarity; /*!< Input Trigger polarity
<>	144:ef7eb2e8f9f7	257	This parameter can be a value of @ref TIM_Trigger_Polarity */
<>	144:ef7eb2e8f9f7	258	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
<>	144:ef7eb2e8f9f7	259	This parameter can be a value of @ref TIM_Trigger_Prescaler */
<>	144:ef7eb2e8f9f7	260	uint32_t TriggerFilter; /*!< Input trigger filter
<>	144:ef7eb2e8f9f7	261	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	262
<>	144:ef7eb2e8f9f7	263	}TIM_SlaveConfigTypeDef;
<>	144:ef7eb2e8f9f7	264
<>	144:ef7eb2e8f9f7	265	/**
<>	144:ef7eb2e8f9f7	266	* @brief HAL State structures definition
<>	144:ef7eb2e8f9f7	267	*/
<>	144:ef7eb2e8f9f7	268	typedef enum
<>	144:ef7eb2e8f9f7	269	{
<>	144:ef7eb2e8f9f7	270	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
<>	144:ef7eb2e8f9f7	271	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
<>	144:ef7eb2e8f9f7	272	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
<>	144:ef7eb2e8f9f7	273	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
<>	144:ef7eb2e8f9f7	274	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
<>	144:ef7eb2e8f9f7	275	}HAL_TIM_StateTypeDef;
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/**
<>	144:ef7eb2e8f9f7	278	* @brief HAL Active channel structures definition
<>	144:ef7eb2e8f9f7	279	*/
<>	144:ef7eb2e8f9f7	280	typedef enum
<>	144:ef7eb2e8f9f7	281	{
<>	144:ef7eb2e8f9f7	282	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
<>	144:ef7eb2e8f9f7	283	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
<>	144:ef7eb2e8f9f7	284	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
<>	144:ef7eb2e8f9f7	285	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
<>	144:ef7eb2e8f9f7	286	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
<>	144:ef7eb2e8f9f7	287	}HAL_TIM_ActiveChannel;
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/**
<>	144:ef7eb2e8f9f7	290	* @brief TIM Time Base Handle Structure definition
<>	144:ef7eb2e8f9f7	291	*/
<>	144:ef7eb2e8f9f7	292	typedef struct
<>	144:ef7eb2e8f9f7	293	{
<>	144:ef7eb2e8f9f7	294	TIM_TypeDef Instance; /!< Register base address */
<>	144:ef7eb2e8f9f7	295	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
<>	144:ef7eb2e8f9f7	296	HAL_TIM_ActiveChannel Channel; /!< Active channel /
<>	144:ef7eb2e8f9f7	297	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
<>	144:ef7eb2e8f9f7	298	This array is accessed by a @ref DMA_Handle_index */
<>	144:ef7eb2e8f9f7	299	HAL_LockTypeDef Lock; /!< Locking object /
<>	144:ef7eb2e8f9f7	300	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
<>	144:ef7eb2e8f9f7	301	}TIM_HandleTypeDef;
<>	144:ef7eb2e8f9f7	302	/**
<>	144:ef7eb2e8f9f7	303	* @}
<>	144:ef7eb2e8f9f7	304	*/
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	307	/** @defgroup TIM_Exported_Constants TIM Exported Constants
<>	144:ef7eb2e8f9f7	308	* @{
<>	144:ef7eb2e8f9f7	309	*/
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
<>	144:ef7eb2e8f9f7	312	* @{
<>	144:ef7eb2e8f9f7	313	*/
AnnaBridge	167:e84263d55307	314	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	315	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	316	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	317	/**
<>	144:ef7eb2e8f9f7	318	* @}
<>	144:ef7eb2e8f9f7	319	*/
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
<>	144:ef7eb2e8f9f7	322	* @{
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
AnnaBridge	167:e84263d55307	325	#define TIM_ETRPOLARITY_NONINVERTED 0x0000U /!< Polarity for ETR source /
<>	144:ef7eb2e8f9f7	326	/**
<>	144:ef7eb2e8f9f7	327	* @}
<>	144:ef7eb2e8f9f7	328	*/
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
<>	144:ef7eb2e8f9f7	331	* @{
<>	144:ef7eb2e8f9f7	332	*/
AnnaBridge	167:e84263d55307	333	#define TIM_ETRPRESCALER_DIV1 0x0000U /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	334	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
<>	144:ef7eb2e8f9f7	335	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
<>	144:ef7eb2e8f9f7	336	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
<>	144:ef7eb2e8f9f7	337	/**
<>	144:ef7eb2e8f9f7	338	* @}
<>	144:ef7eb2e8f9f7	339	*/
<>	144:ef7eb2e8f9f7	340
<>	144:ef7eb2e8f9f7	341	/** @defgroup TIM_Counter_Mode TIM Counter Mode
<>	144:ef7eb2e8f9f7	342	* @{
<>	144:ef7eb2e8f9f7	343	*/
AnnaBridge	167:e84263d55307	344	#define TIM_COUNTERMODE_UP 0x0000U
<>	144:ef7eb2e8f9f7	345	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
<>	144:ef7eb2e8f9f7	346	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
<>	144:ef7eb2e8f9f7	347	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
<>	144:ef7eb2e8f9f7	348	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
<>	144:ef7eb2e8f9f7	349	/**
<>	144:ef7eb2e8f9f7	350	* @}
<>	144:ef7eb2e8f9f7	351	*/
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	/** @defgroup TIM_ClockDivision TIM Clock Division
<>	144:ef7eb2e8f9f7	354	* @{
<>	144:ef7eb2e8f9f7	355	*/
AnnaBridge	167:e84263d55307	356	#define TIM_CLOCKDIVISION_DIV1 0x0000U
<>	144:ef7eb2e8f9f7	357	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
<>	144:ef7eb2e8f9f7	358	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
<>	144:ef7eb2e8f9f7	359	/**
<>	144:ef7eb2e8f9f7	360	* @}
<>	144:ef7eb2e8f9f7	361	*/
AnnaBridge	167:e84263d55307	362
AnnaBridge	167:e84263d55307	363	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
AnnaBridge	167:e84263d55307	364	* @{
AnnaBridge	167:e84263d55307	365	*/
AnnaBridge	167:e84263d55307	366	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /!< TIMx_ARR register is not buffered /
AnnaBridge	167:e84263d55307	367	#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /!< TIMx_ARR register is buffered /
AnnaBridge	167:e84263d55307	368
AnnaBridge	167:e84263d55307	369	/**
AnnaBridge	167:e84263d55307	370	* @}
AnnaBridge	167:e84263d55307	371	*/
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
<>	144:ef7eb2e8f9f7	374	* @{
<>	144:ef7eb2e8f9f7	375	*/
AnnaBridge	167:e84263d55307	376	#define TIM_OCMODE_TIMING 0x0000U
<>	144:ef7eb2e8f9f7	377	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	378	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	379	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	380	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	381	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
<>	144:ef7eb2e8f9f7	382	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	383	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @}
<>	144:ef7eb2e8f9f7	387	*/
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
<>	144:ef7eb2e8f9f7	390	* @{
<>	144:ef7eb2e8f9f7	391	*/
AnnaBridge	167:e84263d55307	392	#define TIM_OCFAST_DISABLE 0x0000U
<>	144:ef7eb2e8f9f7	393	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
<>	144:ef7eb2e8f9f7	394	/**
<>	144:ef7eb2e8f9f7	395	* @}
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
<>	144:ef7eb2e8f9f7	399	* @{
<>	144:ef7eb2e8f9f7	400	*/
AnnaBridge	167:e84263d55307	401	#define TIM_OCPOLARITY_HIGH 0x0000U
<>	144:ef7eb2e8f9f7	402	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
<>	144:ef7eb2e8f9f7	403	/**
<>	144:ef7eb2e8f9f7	404	* @}
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406
<>	144:ef7eb2e8f9f7	407	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
<>	144:ef7eb2e8f9f7	408	* @{
<>	144:ef7eb2e8f9f7	409	*/
AnnaBridge	167:e84263d55307	410	#define TIM_OCNPOLARITY_HIGH 0x0000U
<>	144:ef7eb2e8f9f7	411	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
<>	144:ef7eb2e8f9f7	412	/**
<>	144:ef7eb2e8f9f7	413	* @}
<>	144:ef7eb2e8f9f7	414	*/
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
<>	144:ef7eb2e8f9f7	417	* @{
<>	144:ef7eb2e8f9f7	418	*/
<>	144:ef7eb2e8f9f7	419	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge	167:e84263d55307	420	#define TIM_OCIDLESTATE_RESET 0x0000U
<>	144:ef7eb2e8f9f7	421	/**
<>	144:ef7eb2e8f9f7	422	* @}
<>	144:ef7eb2e8f9f7	423	*/
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
<>	144:ef7eb2e8f9f7	426	* @{
<>	144:ef7eb2e8f9f7	427	*/
<>	144:ef7eb2e8f9f7	428	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
AnnaBridge	167:e84263d55307	429	#define TIM_OCNIDLESTATE_RESET 0x0000U
<>	144:ef7eb2e8f9f7	430	/**
<>	144:ef7eb2e8f9f7	431	* @}
<>	144:ef7eb2e8f9f7	432	*/
<>	144:ef7eb2e8f9f7	433
<>	144:ef7eb2e8f9f7	434	/** @defgroup TIM_Channel TIM Channel
<>	144:ef7eb2e8f9f7	435	* @{
<>	144:ef7eb2e8f9f7	436	*/
AnnaBridge	167:e84263d55307	437	#define TIM_CHANNEL_1 0x0000U
AnnaBridge	167:e84263d55307	438	#define TIM_CHANNEL_2 0x0004U
AnnaBridge	167:e84263d55307	439	#define TIM_CHANNEL_3 0x0008U
AnnaBridge	167:e84263d55307	440	#define TIM_CHANNEL_4 0x000CU
<>	144:ef7eb2e8f9f7	441	#define TIM_CHANNEL_ALL ((uint32_t)0x0018U)
<>	144:ef7eb2e8f9f7	442
<>	144:ef7eb2e8f9f7	443	/**
<>	144:ef7eb2e8f9f7	444	* @}
<>	144:ef7eb2e8f9f7	445	*/
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
<>	144:ef7eb2e8f9f7	448	* @{
<>	144:ef7eb2e8f9f7	449	*/
<>	144:ef7eb2e8f9f7	450	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
<>	144:ef7eb2e8f9f7	451	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	452	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	453	/**
<>	144:ef7eb2e8f9f7	454	* @}
<>	144:ef7eb2e8f9f7	455	*/
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
<>	144:ef7eb2e8f9f7	458	* @{
<>	144:ef7eb2e8f9f7	459	*/
<>	144:ef7eb2e8f9f7	460	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	144:ef7eb2e8f9f7	461	connected to IC1, IC2, IC3 or IC4, respectively */
<>	144:ef7eb2e8f9f7	462	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	144:ef7eb2e8f9f7	463	connected to IC2, IC1, IC4 or IC3, respectively */
<>	144:ef7eb2e8f9f7	464	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/**
<>	144:ef7eb2e8f9f7	467	* @}
<>	144:ef7eb2e8f9f7	468	*/
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
<>	144:ef7eb2e8f9f7	471	* @{
<>	144:ef7eb2e8f9f7	472	*/
AnnaBridge	167:e84263d55307	473	#define TIM_ICPSC_DIV1 0x0000U /!< Capture performed each time an edge is detected on the capture input /
<>	144:ef7eb2e8f9f7	474	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
<>	144:ef7eb2e8f9f7	475	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
<>	144:ef7eb2e8f9f7	476	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
<>	144:ef7eb2e8f9f7	477	/**
<>	144:ef7eb2e8f9f7	478	* @}
<>	144:ef7eb2e8f9f7	479	*/
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
<>	144:ef7eb2e8f9f7	482	* @{
<>	144:ef7eb2e8f9f7	483	*/
<>	144:ef7eb2e8f9f7	484	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge	167:e84263d55307	485	#define TIM_OPMODE_REPETITIVE 0x0000U
<>	144:ef7eb2e8f9f7	486	/**
<>	144:ef7eb2e8f9f7	487	* @}
<>	144:ef7eb2e8f9f7	488	*/
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
<>	144:ef7eb2e8f9f7	491	* @{
<>	144:ef7eb2e8f9f7	492	*/
<>	144:ef7eb2e8f9f7	493	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
<>	144:ef7eb2e8f9f7	494	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
<>	144:ef7eb2e8f9f7	495	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
<>	144:ef7eb2e8f9f7	496
<>	144:ef7eb2e8f9f7	497	/**
<>	144:ef7eb2e8f9f7	498	* @}
<>	144:ef7eb2e8f9f7	499	*/
<>	144:ef7eb2e8f9f7	500
<>	144:ef7eb2e8f9f7	501	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
<>	144:ef7eb2e8f9f7	502	* @{
<>	144:ef7eb2e8f9f7	503	*/
<>	144:ef7eb2e8f9f7	504	#define TIM_IT_UPDATE (TIM_DIER_UIE)
<>	144:ef7eb2e8f9f7	505	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
<>	144:ef7eb2e8f9f7	506	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
<>	144:ef7eb2e8f9f7	507	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
<>	144:ef7eb2e8f9f7	508	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
<>	144:ef7eb2e8f9f7	509	#define TIM_IT_COM (TIM_DIER_COMIE)
<>	144:ef7eb2e8f9f7	510	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
<>	144:ef7eb2e8f9f7	511	#define TIM_IT_BREAK (TIM_DIER_BIE)
<>	144:ef7eb2e8f9f7	512	/**
<>	144:ef7eb2e8f9f7	513	* @}
<>	144:ef7eb2e8f9f7	514	*/
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	/** @defgroup TIM_Commutation_Source TIM Commutation Source
<>	144:ef7eb2e8f9f7	517	* @{
<>	144:ef7eb2e8f9f7	518	*/
<>	144:ef7eb2e8f9f7	519	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
AnnaBridge	167:e84263d55307	520	#define TIM_COMMUTATION_SOFTWARE 0x0000U
<>	144:ef7eb2e8f9f7	521	/**
<>	144:ef7eb2e8f9f7	522	* @}
<>	144:ef7eb2e8f9f7	523	*/
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	/** @defgroup TIM_DMA_sources TIM DMA sources
<>	144:ef7eb2e8f9f7	526	* @{
<>	144:ef7eb2e8f9f7	527	*/
<>	144:ef7eb2e8f9f7	528	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
<>	144:ef7eb2e8f9f7	529	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
<>	144:ef7eb2e8f9f7	530	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
<>	144:ef7eb2e8f9f7	531	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
<>	144:ef7eb2e8f9f7	532	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
<>	144:ef7eb2e8f9f7	533	#define TIM_DMA_COM (TIM_DIER_COMDE)
<>	144:ef7eb2e8f9f7	534	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
<>	144:ef7eb2e8f9f7	535	/**
<>	144:ef7eb2e8f9f7	536	* @}
<>	144:ef7eb2e8f9f7	537	*/
<>	144:ef7eb2e8f9f7	538
<>	144:ef7eb2e8f9f7	539	/** @defgroup TIM_Event_Source TIM Event Source
<>	144:ef7eb2e8f9f7	540	* @{
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
<>	144:ef7eb2e8f9f7	543	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
<>	144:ef7eb2e8f9f7	544	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
<>	144:ef7eb2e8f9f7	545	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
<>	144:ef7eb2e8f9f7	546	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
<>	144:ef7eb2e8f9f7	547	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
<>	144:ef7eb2e8f9f7	548	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
<>	144:ef7eb2e8f9f7	549	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/**
<>	144:ef7eb2e8f9f7	552	* @}
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/** @defgroup TIM_Flag_definition TIM Flag definition
<>	144:ef7eb2e8f9f7	556	* @{
<>	144:ef7eb2e8f9f7	557	*/
<>	144:ef7eb2e8f9f7	558	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
<>	144:ef7eb2e8f9f7	559	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
<>	144:ef7eb2e8f9f7	560	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
<>	144:ef7eb2e8f9f7	561	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
<>	144:ef7eb2e8f9f7	562	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
<>	144:ef7eb2e8f9f7	563	#define TIM_FLAG_COM (TIM_SR_COMIF)
<>	144:ef7eb2e8f9f7	564	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
<>	144:ef7eb2e8f9f7	565	#define TIM_FLAG_BREAK (TIM_SR_BIF)
<>	144:ef7eb2e8f9f7	566	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
<>	144:ef7eb2e8f9f7	567	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
<>	144:ef7eb2e8f9f7	568	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
<>	144:ef7eb2e8f9f7	569	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
<>	144:ef7eb2e8f9f7	570	/**
<>	144:ef7eb2e8f9f7	571	* @}
<>	144:ef7eb2e8f9f7	572	*/
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/** @defgroup TIM_Clock_Source TIM Clock Source
<>	144:ef7eb2e8f9f7	575	* @{
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
<>	144:ef7eb2e8f9f7	578	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge	167:e84263d55307	579	#define TIM_CLOCKSOURCE_ITR0 0x0000U
<>	144:ef7eb2e8f9f7	580	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
<>	144:ef7eb2e8f9f7	581	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
<>	144:ef7eb2e8f9f7	582	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
<>	144:ef7eb2e8f9f7	583	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	584	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	585	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	586	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
<>	144:ef7eb2e8f9f7	587	/**
<>	144:ef7eb2e8f9f7	588	* @}
<>	144:ef7eb2e8f9f7	589	*/
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
<>	144:ef7eb2e8f9f7	592	* @{
<>	144:ef7eb2e8f9f7	593	*/
<>	144:ef7eb2e8f9f7	594	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
<>	144:ef7eb2e8f9f7	595	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
<>	144:ef7eb2e8f9f7	596	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	597	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	598	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	599	/**
<>	144:ef7eb2e8f9f7	600	* @}
<>	144:ef7eb2e8f9f7	601	*/
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
<>	144:ef7eb2e8f9f7	604	* @{
<>	144:ef7eb2e8f9f7	605	*/
<>	144:ef7eb2e8f9f7	606	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	607	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	608	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	609	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	610	/**
<>	144:ef7eb2e8f9f7	611	* @}
<>	144:ef7eb2e8f9f7	612	*/
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
<>	144:ef7eb2e8f9f7	615	* @{
<>	144:ef7eb2e8f9f7	616	*/
AnnaBridge	167:e84263d55307	617	#define TIM_CLEARINPUTSOURCE_ETR 0x0001U
AnnaBridge	167:e84263d55307	618	#define TIM_CLEARINPUTSOURCE_NONE 0x0000U
<>	144:ef7eb2e8f9f7	619	/**
<>	144:ef7eb2e8f9f7	620	* @}
<>	144:ef7eb2e8f9f7	621	*/
<>	144:ef7eb2e8f9f7	622
<>	144:ef7eb2e8f9f7	623	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
<>	144:ef7eb2e8f9f7	624	* @{
<>	144:ef7eb2e8f9f7	625	*/
<>	144:ef7eb2e8f9f7	626	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
<>	144:ef7eb2e8f9f7	627	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
<>	144:ef7eb2e8f9f7	628	/**
<>	144:ef7eb2e8f9f7	629	* @}
<>	144:ef7eb2e8f9f7	630	*/
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
<>	144:ef7eb2e8f9f7	633	* @{
<>	144:ef7eb2e8f9f7	634	*/
<>	144:ef7eb2e8f9f7	635	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	636	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	637	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	638	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	639	/**
<>	144:ef7eb2e8f9f7	640	* @}
<>	144:ef7eb2e8f9f7	641	*/
<>	144:ef7eb2e8f9f7	642
<>	144:ef7eb2e8f9f7	643	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
<>	144:ef7eb2e8f9f7	644	* @{
<>	144:ef7eb2e8f9f7	645	*/
AnnaBridge	167:e84263d55307	646	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge	167:e84263d55307	647	#define TIM_OSSR_DISABLE 0x0000U
<>	144:ef7eb2e8f9f7	648	/**
<>	144:ef7eb2e8f9f7	649	* @}
<>	144:ef7eb2e8f9f7	650	*/
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
<>	144:ef7eb2e8f9f7	653	* @{
<>	144:ef7eb2e8f9f7	654	*/
AnnaBridge	167:e84263d55307	655	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge	167:e84263d55307	656	#define TIM_OSSI_DISABLE 0x0000U
<>	144:ef7eb2e8f9f7	657	/**
<>	144:ef7eb2e8f9f7	658	* @}
<>	144:ef7eb2e8f9f7	659	*/
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	/** @defgroup TIM_Lock_level TIM Lock level
<>	144:ef7eb2e8f9f7	662	* @{
<>	144:ef7eb2e8f9f7	663	*/
AnnaBridge	167:e84263d55307	664	#define TIM_LOCKLEVEL_OFF 0x0000U
<>	144:ef7eb2e8f9f7	665	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
<>	144:ef7eb2e8f9f7	666	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
<>	144:ef7eb2e8f9f7	667	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
<>	144:ef7eb2e8f9f7	668	/**
<>	144:ef7eb2e8f9f7	669	* @}
<>	144:ef7eb2e8f9f7	670	*/
<>	144:ef7eb2e8f9f7	671	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
<>	144:ef7eb2e8f9f7	672	* @{
AnnaBridge	167:e84263d55307	673	*/
<>	144:ef7eb2e8f9f7	674	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
AnnaBridge	167:e84263d55307	675	#define TIM_BREAK_DISABLE 0x0000U
<>	144:ef7eb2e8f9f7	676	/**
<>	144:ef7eb2e8f9f7	677	* @}
<>	144:ef7eb2e8f9f7	678	*/
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	/** @defgroup TIM_Break_Polarity TIM Break Polarity
<>	144:ef7eb2e8f9f7	681	* @{
<>	144:ef7eb2e8f9f7	682	*/
AnnaBridge	167:e84263d55307	683	#define TIM_BREAKPOLARITY_LOW 0x0000U
<>	144:ef7eb2e8f9f7	684	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
<>	144:ef7eb2e8f9f7	685	/**
<>	144:ef7eb2e8f9f7	686	* @}
<>	144:ef7eb2e8f9f7	687	*/
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
<>	144:ef7eb2e8f9f7	690	* @{
<>	144:ef7eb2e8f9f7	691	*/
<>	144:ef7eb2e8f9f7	692	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge	167:e84263d55307	693	#define TIM_AUTOMATICOUTPUT_DISABLE 0x0000U
<>	144:ef7eb2e8f9f7	694	/**
<>	144:ef7eb2e8f9f7	695	* @}
<>	144:ef7eb2e8f9f7	696	*/
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
<>	144:ef7eb2e8f9f7	699	* @{
<>	144:ef7eb2e8f9f7	700	*/
AnnaBridge	167:e84263d55307	701	#define TIM_TRGO_RESET 0x0000U
AnnaBridge	167:e84263d55307	702	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge	167:e84263d55307	703	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge	167:e84263d55307	704	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	167:e84263d55307	705	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge	167:e84263d55307	706	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
AnnaBridge	167:e84263d55307	707	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
AnnaBridge	167:e84263d55307	708	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
<>	144:ef7eb2e8f9f7	709	/**
<>	144:ef7eb2e8f9f7	710	* @}
<>	144:ef7eb2e8f9f7	711	*/
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	/** @defgroup TIM_Slave_Mode TIM Slave Mode
<>	144:ef7eb2e8f9f7	714	* @{
<>	144:ef7eb2e8f9f7	715	*/
AnnaBridge	167:e84263d55307	716	#define TIM_SLAVEMODE_DISABLE 0x0000U
AnnaBridge	167:e84263d55307	717	#define TIM_SLAVEMODE_RESET 0x0004U
AnnaBridge	167:e84263d55307	718	#define TIM_SLAVEMODE_GATED 0x0005U
AnnaBridge	167:e84263d55307	719	#define TIM_SLAVEMODE_TRIGGER 0x0006U
AnnaBridge	167:e84263d55307	720	#define TIM_SLAVEMODE_EXTERNAL1 0x0007U
<>	144:ef7eb2e8f9f7	721	/**
<>	144:ef7eb2e8f9f7	722	* @}
<>	144:ef7eb2e8f9f7	723	*/
<>	144:ef7eb2e8f9f7	724
<>	144:ef7eb2e8f9f7	725	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
<>	144:ef7eb2e8f9f7	726	* @{
<>	144:ef7eb2e8f9f7	727	*/
AnnaBridge	167:e84263d55307	728	#define TIM_MASTERSLAVEMODE_ENABLE 0x0080U
AnnaBridge	167:e84263d55307	729	#define TIM_MASTERSLAVEMODE_DISABLE 0x0000U
<>	144:ef7eb2e8f9f7	730	/**
<>	144:ef7eb2e8f9f7	731	* @}
<>	144:ef7eb2e8f9f7	732	*/
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
<>	144:ef7eb2e8f9f7	735	* @{
<>	144:ef7eb2e8f9f7	736	*/
AnnaBridge	167:e84263d55307	737	#define TIM_TS_ITR0 0x0000U
AnnaBridge	167:e84263d55307	738	#define TIM_TS_ITR1 0x0010U
AnnaBridge	167:e84263d55307	739	#define TIM_TS_ITR2 0x0020U
AnnaBridge	167:e84263d55307	740	#define TIM_TS_ITR3 0x0030U
AnnaBridge	167:e84263d55307	741	#define TIM_TS_TI1F_ED 0x0040U
AnnaBridge	167:e84263d55307	742	#define TIM_TS_TI1FP1 0x0050U
AnnaBridge	167:e84263d55307	743	#define TIM_TS_TI2FP2 0x0060U
AnnaBridge	167:e84263d55307	744	#define TIM_TS_ETRF 0x0070U
AnnaBridge	167:e84263d55307	745	#define TIM_TS_NONE 0xFFFFU
<>	144:ef7eb2e8f9f7	746	/**
<>	144:ef7eb2e8f9f7	747	* @}
<>	144:ef7eb2e8f9f7	748	*/
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
<>	144:ef7eb2e8f9f7	751	* @{
<>	144:ef7eb2e8f9f7	752	*/
AnnaBridge	167:e84263d55307	753	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
AnnaBridge	167:e84263d55307	754	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
<>	144:ef7eb2e8f9f7	755	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	756	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	757	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	758	/**
<>	144:ef7eb2e8f9f7	759	* @}
<>	144:ef7eb2e8f9f7	760	*/
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
<>	144:ef7eb2e8f9f7	763	* @{
<>	144:ef7eb2e8f9f7	764	*/
<>	144:ef7eb2e8f9f7	765	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	766	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	767	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	768	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	769	/**
<>	144:ef7eb2e8f9f7	770	* @}
<>	144:ef7eb2e8f9f7	771	*/
<>	144:ef7eb2e8f9f7	772
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
<>	144:ef7eb2e8f9f7	775	* @{
<>	144:ef7eb2e8f9f7	776	*/
AnnaBridge	167:e84263d55307	777	#define TIM_TI1SELECTION_CH1 0x0000U
<>	144:ef7eb2e8f9f7	778	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
<>	144:ef7eb2e8f9f7	779	/**
<>	144:ef7eb2e8f9f7	780	* @}
<>	144:ef7eb2e8f9f7	781	*/
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
<>	144:ef7eb2e8f9f7	784	* @{
<>	144:ef7eb2e8f9f7	785	*/
AnnaBridge	167:e84263d55307	786	#define TIM_DMABASE_CR1 0x00000000U
AnnaBridge	167:e84263d55307	787	#define TIM_DMABASE_CR2 0x00000001U
AnnaBridge	167:e84263d55307	788	#define TIM_DMABASE_SMCR 0x00000002U
AnnaBridge	167:e84263d55307	789	#define TIM_DMABASE_DIER 0x00000003U
AnnaBridge	167:e84263d55307	790	#define TIM_DMABASE_SR 0x00000004U
AnnaBridge	167:e84263d55307	791	#define TIM_DMABASE_EGR 0x00000005U
AnnaBridge	167:e84263d55307	792	#define TIM_DMABASE_CCMR1 0x00000006U
AnnaBridge	167:e84263d55307	793	#define TIM_DMABASE_CCMR2 0x00000007U
AnnaBridge	167:e84263d55307	794	#define TIM_DMABASE_CCER 0x00000008U
AnnaBridge	167:e84263d55307	795	#define TIM_DMABASE_CNT 0x00000009U
AnnaBridge	167:e84263d55307	796	#define TIM_DMABASE_PSC 0x0000000AU
AnnaBridge	167:e84263d55307	797	#define TIM_DMABASE_ARR 0x0000000BU
AnnaBridge	167:e84263d55307	798	#define TIM_DMABASE_RCR 0x0000000CU
AnnaBridge	167:e84263d55307	799	#define TIM_DMABASE_CCR1 0x0000000DU
AnnaBridge	167:e84263d55307	800	#define TIM_DMABASE_CCR2 0x0000000EU
AnnaBridge	167:e84263d55307	801	#define TIM_DMABASE_CCR3 0x0000000FU
AnnaBridge	167:e84263d55307	802	#define TIM_DMABASE_CCR4 0x00000010U
AnnaBridge	167:e84263d55307	803	#define TIM_DMABASE_BDTR 0x00000011U
AnnaBridge	167:e84263d55307	804	#define TIM_DMABASE_DCR 0x00000012U
AnnaBridge	167:e84263d55307	805	#define TIM_DMABASE_OR 0x00000013U
<>	144:ef7eb2e8f9f7	806	/**
<>	144:ef7eb2e8f9f7	807	* @}
<>	144:ef7eb2e8f9f7	808	*/
<>	144:ef7eb2e8f9f7	809
<>	144:ef7eb2e8f9f7	810	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
<>	144:ef7eb2e8f9f7	811	* @{
<>	144:ef7eb2e8f9f7	812	*/
AnnaBridge	167:e84263d55307	813	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
AnnaBridge	167:e84263d55307	814	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
AnnaBridge	167:e84263d55307	815	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
AnnaBridge	167:e84263d55307	816	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
AnnaBridge	167:e84263d55307	817	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
AnnaBridge	167:e84263d55307	818	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
AnnaBridge	167:e84263d55307	819	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
AnnaBridge	167:e84263d55307	820	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
AnnaBridge	167:e84263d55307	821	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
AnnaBridge	167:e84263d55307	822	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
AnnaBridge	167:e84263d55307	823	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
AnnaBridge	167:e84263d55307	824	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
AnnaBridge	167:e84263d55307	825	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
AnnaBridge	167:e84263d55307	826	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
AnnaBridge	167:e84263d55307	827	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
AnnaBridge	167:e84263d55307	828	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
AnnaBridge	167:e84263d55307	829	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
AnnaBridge	167:e84263d55307	830	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
<>	144:ef7eb2e8f9f7	831	/**
<>	144:ef7eb2e8f9f7	832	* @}
<>	144:ef7eb2e8f9f7	833	*/
<>	144:ef7eb2e8f9f7	834
<>	144:ef7eb2e8f9f7	835	/** @defgroup DMA_Handle_index DMA Handle index
<>	144:ef7eb2e8f9f7	836	* @{
<>	144:ef7eb2e8f9f7	837	*/
AnnaBridge	167:e84263d55307	838	#define TIM_DMA_ID_UPDATE (uint16_t)0x00 /!< Index of the DMA handle used for Update DMA requests /
AnnaBridge	167:e84263d55307	839	#define TIM_DMA_ID_CC1 (uint16_t)0x01 /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
AnnaBridge	167:e84263d55307	840	#define TIM_DMA_ID_CC2 (uint16_t)0x02 /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
AnnaBridge	167:e84263d55307	841	#define TIM_DMA_ID_CC3 (uint16_t)0x03 /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
AnnaBridge	167:e84263d55307	842	#define TIM_DMA_ID_CC4 (uint16_t)0x04 /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
AnnaBridge	167:e84263d55307	843	#define TIM_DMA_ID_COMMUTATION (uint16_t)0x05 /!< Index of the DMA handle used for Commutation DMA requests /
AnnaBridge	167:e84263d55307	844	#define TIM_DMA_ID_TRIGGER (uint16_t)0x06 /!< Index of the DMA handle used for Trigger DMA requests /
<>	144:ef7eb2e8f9f7	845	/**
<>	144:ef7eb2e8f9f7	846	* @}
<>	144:ef7eb2e8f9f7	847	*/
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	/** @defgroup Channel_CC_State Channel CC State
<>	144:ef7eb2e8f9f7	850	* @{
<>	144:ef7eb2e8f9f7	851	*/
AnnaBridge	167:e84263d55307	852	#define TIM_CCx_ENABLE 0x0001U
AnnaBridge	167:e84263d55307	853	#define TIM_CCx_DISABLE 0x0000U
AnnaBridge	167:e84263d55307	854	#define TIM_CCxN_ENABLE 0x0004U
AnnaBridge	167:e84263d55307	855	#define TIM_CCxN_DISABLE 0x0000U
<>	144:ef7eb2e8f9f7	856	/**
<>	144:ef7eb2e8f9f7	857	* @}
<>	144:ef7eb2e8f9f7	858	*/
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/**
<>	144:ef7eb2e8f9f7	861	* @}
<>	144:ef7eb2e8f9f7	862	*/
<>	144:ef7eb2e8f9f7	863
<>	144:ef7eb2e8f9f7	864	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	865	/** @defgroup TIM_Exported_Macros TIM Exported Macros
<>	144:ef7eb2e8f9f7	866	* @{
<>	144:ef7eb2e8f9f7	867	*/
<>	144:ef7eb2e8f9f7	868	/** @brief Reset TIM handle state
<>	144:ef7eb2e8f9f7	869	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	870	* @retval None
<>	144:ef7eb2e8f9f7	871	*/
<>	144:ef7eb2e8f9f7	872	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	873
<>	144:ef7eb2e8f9f7	874	/**
<>	144:ef7eb2e8f9f7	875	* @brief Enable the TIM peripheral.
<>	144:ef7eb2e8f9f7	876	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	877	* @retval None
<>	144:ef7eb2e8f9f7	878	*/
<>	144:ef7eb2e8f9f7	879	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/**
<>	144:ef7eb2e8f9f7	882	* @brief Enable the TIM main Output.
<>	144:ef7eb2e8f9f7	883	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	884	* @retval None
<>	144:ef7eb2e8f9f7	885	*/
<>	144:ef7eb2e8f9f7	886	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
<>	144:ef7eb2e8f9f7	887
<>	144:ef7eb2e8f9f7	888
<>	144:ef7eb2e8f9f7	889	/**
<>	144:ef7eb2e8f9f7	890	* @brief Disable the TIM peripheral.
<>	144:ef7eb2e8f9f7	891	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	892	* @retval None
<>	144:ef7eb2e8f9f7	893	*/
<>	144:ef7eb2e8f9f7	894	#define __HAL_TIM_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	895	do { \
<>	144:ef7eb2e8f9f7	896	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	897	{ \
<>	144:ef7eb2e8f9f7	898	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	899	{ \
<>	144:ef7eb2e8f9f7	900	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
<>	144:ef7eb2e8f9f7	901	} \
<>	144:ef7eb2e8f9f7	902	} \
<>	144:ef7eb2e8f9f7	903	} while(0)
<>	144:ef7eb2e8f9f7	904
<>	144:ef7eb2e8f9f7	905	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
<>	144:ef7eb2e8f9f7	906	channels have been disabled */
<>	144:ef7eb2e8f9f7	907	/**
<>	144:ef7eb2e8f9f7	908	* @brief Disable the TIM main Output.
<>	144:ef7eb2e8f9f7	909	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	910	* @retval None
<>	144:ef7eb2e8f9f7	911	*/
<>	144:ef7eb2e8f9f7	912	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	913	do { \
<>	144:ef7eb2e8f9f7	914	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	915	{ \
<>	144:ef7eb2e8f9f7	916	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	917	{ \
<>	144:ef7eb2e8f9f7	918	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
<>	144:ef7eb2e8f9f7	919	} \
<>	144:ef7eb2e8f9f7	920	} \
<>	144:ef7eb2e8f9f7	921	} while(0)
<>	144:ef7eb2e8f9f7	922
AnnaBridge	167:e84263d55307	923	/**
AnnaBridge	167:e84263d55307	924	* @brief Disable the TIM main Output.
AnnaBridge	167:e84263d55307	925	* @param __HANDLE__: TIM handle
AnnaBridge	167:e84263d55307	926	* @retval None
AnnaBridge	167:e84263d55307	927	* @note The Main Output Enable of a timer instance is disabled unconditionally
AnnaBridge	167:e84263d55307	928	*/
AnnaBridge	167:e84263d55307	929	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
AnnaBridge	167:e84263d55307	930
AnnaBridge	167:e84263d55307	931	/** @brief Enable the specified TIM interrupt.
AnnaBridge	167:e84263d55307	932	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	167:e84263d55307	933	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
AnnaBridge	167:e84263d55307	934	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	935	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	167:e84263d55307	936	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	167:e84263d55307	937	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	167:e84263d55307	938	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	167:e84263d55307	939	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	167:e84263d55307	940	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	167:e84263d55307	941	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	167:e84263d55307	942	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	167:e84263d55307	943	* @retval None
AnnaBridge	167:e84263d55307	944	*/
<>	144:ef7eb2e8f9f7	945	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
AnnaBridge	167:e84263d55307	946
AnnaBridge	167:e84263d55307	947	/** @brief Disable the specified TIM interrupt.
AnnaBridge	167:e84263d55307	948	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	167:e84263d55307	949	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
AnnaBridge	167:e84263d55307	950	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	951	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	167:e84263d55307	952	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	167:e84263d55307	953	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	167:e84263d55307	954	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	167:e84263d55307	955	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	167:e84263d55307	956	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	167:e84263d55307	957	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	167:e84263d55307	958	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	167:e84263d55307	959	* @retval None
AnnaBridge	167:e84263d55307	960	*/
<>	144:ef7eb2e8f9f7	961	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge	167:e84263d55307	962
AnnaBridge	167:e84263d55307	963	/** @brief Enable the specified DMA request.
AnnaBridge	167:e84263d55307	964	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	167:e84263d55307	965	* @param __DMA__: specifies the TIM DMA request to enable.
AnnaBridge	167:e84263d55307	966	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	967	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	167:e84263d55307	968	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge	167:e84263d55307	969	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge	167:e84263d55307	970	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge	167:e84263d55307	971	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	167:e84263d55307	972	* @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge	167:e84263d55307	973	* @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge	167:e84263d55307	974	* @retval None
AnnaBridge	167:e84263d55307	975	*/
AnnaBridge	167:e84263d55307	976	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
AnnaBridge	167:e84263d55307	977
AnnaBridge	167:e84263d55307	978	/** @brief Disable the specified DMA request.
AnnaBridge	167:e84263d55307	979	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	167:e84263d55307	980	* @param __DMA__: specifies the TIM DMA request to disable.
AnnaBridge	167:e84263d55307	981	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	982	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	167:e84263d55307	983	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge	167:e84263d55307	984	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge	167:e84263d55307	985	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge	167:e84263d55307	986	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	167:e84263d55307	987	* @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge	167:e84263d55307	988	* @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge	167:e84263d55307	989	* @retval None
AnnaBridge	167:e84263d55307	990	*/
<>	144:ef7eb2e8f9f7	991	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge	167:e84263d55307	992
AnnaBridge	167:e84263d55307	993	/** @brief Check whether the specified TIM interrupt flag is set or not.
AnnaBridge	167:e84263d55307	994	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	167:e84263d55307	995	* @param __FLAG__: specifies the TIM interrupt flag to check.
AnnaBridge	167:e84263d55307	996	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	997	* @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge	167:e84263d55307	998	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge	167:e84263d55307	999	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge	167:e84263d55307	1000	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge	167:e84263d55307	1001	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge	167:e84263d55307	1002	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge	167:e84263d55307	1003	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge	167:e84263d55307	1004	* @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge	167:e84263d55307	1005	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge	167:e84263d55307	1006	* @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge	167:e84263d55307	1007	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge	167:e84263d55307	1008	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge	167:e84263d55307	1009	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge	167:e84263d55307	1010	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge	167:e84263d55307	1011	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge	167:e84263d55307	1012	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge	167:e84263d55307	1013	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	167:e84263d55307	1014	*/
<>	144:ef7eb2e8f9f7	1015	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	167:e84263d55307	1016
AnnaBridge	167:e84263d55307	1017	/** @brief Clear the specified TIM interrupt flag.
AnnaBridge	167:e84263d55307	1018	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	167:e84263d55307	1019	* @param __FLAG__: specifies the TIM interrupt flag to clear.
AnnaBridge	167:e84263d55307	1020	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1021	* @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge	167:e84263d55307	1022	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge	167:e84263d55307	1023	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge	167:e84263d55307	1024	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge	167:e84263d55307	1025	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge	167:e84263d55307	1026	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge	167:e84263d55307	1027	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge	167:e84263d55307	1028	* @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge	167:e84263d55307	1029	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge	167:e84263d55307	1030	* @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge	167:e84263d55307	1031	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge	167:e84263d55307	1032	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge	167:e84263d55307	1033	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge	167:e84263d55307	1034	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge	167:e84263d55307	1035	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge	167:e84263d55307	1036	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge	167:e84263d55307	1037	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	167:e84263d55307	1038	*/
<>	144:ef7eb2e8f9f7	1039	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<>	144:ef7eb2e8f9f7	1040
AnnaBridge	167:e84263d55307	1041	/**
AnnaBridge	167:e84263d55307	1042	* @brief Check whether the specified TIM interrupt source is enabled or not.
AnnaBridge	167:e84263d55307	1043	* @param __HANDLE__: TIM handle
AnnaBridge	167:e84263d55307	1044	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
AnnaBridge	167:e84263d55307	1045	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1046	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	167:e84263d55307	1047	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	167:e84263d55307	1048	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	167:e84263d55307	1049	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	167:e84263d55307	1050	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	167:e84263d55307	1051	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	167:e84263d55307	1052	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	167:e84263d55307	1053	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	167:e84263d55307	1054	* @retval The state of TIM_IT (SET or RESET).
AnnaBridge	167:e84263d55307	1055	*/
<>	144:ef7eb2e8f9f7	1056	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	167:e84263d55307	1057
AnnaBridge	167:e84263d55307	1058	/** @brief Clear the TIM interrupt pending bits.
AnnaBridge	167:e84263d55307	1059	* @param __HANDLE__: TIM handle
AnnaBridge	167:e84263d55307	1060	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	167:e84263d55307	1061	* This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1062	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	167:e84263d55307	1063	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	167:e84263d55307	1064	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	167:e84263d55307	1065	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	167:e84263d55307	1066	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	167:e84263d55307	1067	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	167:e84263d55307	1068	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	167:e84263d55307	1069	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	167:e84263d55307	1070	* @retval None
AnnaBridge	167:e84263d55307	1071	*/
<>	144:ef7eb2e8f9f7	1072	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1073
AnnaBridge	167:e84263d55307	1074	/**
AnnaBridge	167:e84263d55307	1075	* @brief Indicates whether or not the TIM Counter is used as downcounter.
AnnaBridge	167:e84263d55307	1076	* @param __HANDLE__: TIM handle.
AnnaBridge	167:e84263d55307	1077	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
AnnaBridge	167:e84263d55307	1078	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
AnnaBridge	167:e84263d55307	1079	mode.
AnnaBridge	167:e84263d55307	1080	*/
<>	144:ef7eb2e8f9f7	1081	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge	167:e84263d55307	1082
AnnaBridge	167:e84263d55307	1083	/**
AnnaBridge	167:e84263d55307	1084	* @brief Set the TIM Prescaler on runtime.
AnnaBridge	167:e84263d55307	1085	* @param __HANDLE__: TIM handle.
AnnaBridge	167:e84263d55307	1086	* @param __PRESC__: specifies the Prescaler new value.
AnnaBridge	167:e84263d55307	1087	* @retval None
AnnaBridge	167:e84263d55307	1088	*/
<>	144:ef7eb2e8f9f7	1089	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	144:ef7eb2e8f9f7	1092	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
<>	144:ef7eb2e8f9f7	1093	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
<>	144:ef7eb2e8f9f7	1094	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
<>	144:ef7eb2e8f9f7	1095	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1098	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
<>	144:ef7eb2e8f9f7	1099	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
<>	144:ef7eb2e8f9f7	1100	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
<>	144:ef7eb2e8f9f7	1101	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	144:ef7eb2e8f9f7	1104	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
<>	144:ef7eb2e8f9f7	1105	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
<>	144:ef7eb2e8f9f7	1106	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
<>	144:ef7eb2e8f9f7	1107	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1110	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
<>	144:ef7eb2e8f9f7	1111	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
<>	144:ef7eb2e8f9f7	1112	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
<>	144:ef7eb2e8f9f7	1113	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
<>	144:ef7eb2e8f9f7	1114
<>	144:ef7eb2e8f9f7	1115	/**
<>	144:ef7eb2e8f9f7	1116	* @brief Sets the TIM Capture Compare Register value on runtime without
<>	144:ef7eb2e8f9f7	1117	* calling another time ConfigChannel function.
<>	144:ef7eb2e8f9f7	1118	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1119	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1120	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1121	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1122	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1123	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1124	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1125	* @param __COMPARE__: specifies the Capture Compare register new value.
<>	144:ef7eb2e8f9f7	1126	* @retval None
<>	144:ef7eb2e8f9f7	1127	*/
<>	144:ef7eb2e8f9f7	1128	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<>	144:ef7eb2e8f9f7	1129	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	/**
<>	144:ef7eb2e8f9f7	1132	* @brief Gets the TIM Capture Compare Register value on runtime
<>	144:ef7eb2e8f9f7	1133	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1134	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
<>	144:ef7eb2e8f9f7	1135	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1136	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
<>	144:ef7eb2e8f9f7	1137	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
<>	144:ef7eb2e8f9f7	1138	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
<>	144:ef7eb2e8f9f7	1139	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge	167:e84263d55307	1140	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
<>	144:ef7eb2e8f9f7	1141	*/
<>	144:ef7eb2e8f9f7	1142	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1143	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	/**
<>	144:ef7eb2e8f9f7	1146	* @brief Sets the TIM Counter Register value on runtime.
<>	144:ef7eb2e8f9f7	1147	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1148	* @param __COUNTER__: specifies the Counter register new value.
<>	144:ef7eb2e8f9f7	1149	* @retval None
<>	144:ef7eb2e8f9f7	1150	*/
<>	144:ef7eb2e8f9f7	1151	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	/**
<>	144:ef7eb2e8f9f7	1154	* @brief Gets the TIM Counter Register value on runtime.
<>	144:ef7eb2e8f9f7	1155	* @param __HANDLE__: TIM handle.
AnnaBridge	167:e84263d55307	1156	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
<>	144:ef7eb2e8f9f7	1157	*/
<>	144:ef7eb2e8f9f7	1158	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
<>	144:ef7eb2e8f9f7	1159
<>	144:ef7eb2e8f9f7	1160	/**
<>	144:ef7eb2e8f9f7	1161	* @brief Sets the TIM Autoreload Register value on runtime without calling
<>	144:ef7eb2e8f9f7	1162	* another time any Init function.
<>	144:ef7eb2e8f9f7	1163	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1164	* @param __AUTORELOAD__: specifies the Counter register new value.
<>	144:ef7eb2e8f9f7	1165	* @retval None
<>	144:ef7eb2e8f9f7	1166	*/
<>	144:ef7eb2e8f9f7	1167	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
<>	144:ef7eb2e8f9f7	1168	do{ \
<>	144:ef7eb2e8f9f7	1169	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
<>	144:ef7eb2e8f9f7	1170	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
<>	144:ef7eb2e8f9f7	1171	} while(0)
<>	144:ef7eb2e8f9f7	1172	/**
<>	144:ef7eb2e8f9f7	1173	* @brief Gets the TIM Autoreload Register value on runtime
<>	144:ef7eb2e8f9f7	1174	* @param __HANDLE__: TIM handle.
AnnaBridge	167:e84263d55307	1175	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
<>	144:ef7eb2e8f9f7	1176	*/
<>	144:ef7eb2e8f9f7	1177	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/**
<>	144:ef7eb2e8f9f7	1180	* @brief Sets the TIM Clock Division value on runtime without calling
<>	144:ef7eb2e8f9f7	1181	* another time any Init function.
<>	144:ef7eb2e8f9f7	1182	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1183	* @param __CKD__: specifies the clock division value.
<>	144:ef7eb2e8f9f7	1184	* This parameter can be one of the following value:
AnnaBridge	167:e84263d55307	1185	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge	167:e84263d55307	1186	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge	167:e84263d55307	1187	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
<>	144:ef7eb2e8f9f7	1188	* @retval None
<>	144:ef7eb2e8f9f7	1189	*/
<>	144:ef7eb2e8f9f7	1190	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
<>	144:ef7eb2e8f9f7	1191	do{ \
<>	144:ef7eb2e8f9f7	1192	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
<>	144:ef7eb2e8f9f7	1193	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
<>	144:ef7eb2e8f9f7	1194	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
<>	144:ef7eb2e8f9f7	1195	} while(0)
<>	144:ef7eb2e8f9f7	1196	/**
AnnaBridge	167:e84263d55307	1197	* @brief Gets the TIM Clock Division value on runtime.
<>	144:ef7eb2e8f9f7	1198	* @param __HANDLE__: TIM handle.
AnnaBridge	167:e84263d55307	1199	* @retval The clock division can be one of the following values:
AnnaBridge	167:e84263d55307	1200	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge	167:e84263d55307	1201	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge	167:e84263d55307	1202	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
<>	144:ef7eb2e8f9f7	1203	*/
<>	144:ef7eb2e8f9f7	1204	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<>	144:ef7eb2e8f9f7	1205
<>	144:ef7eb2e8f9f7	1206	/**
<>	144:ef7eb2e8f9f7	1207	* @brief Sets the TIM Input Capture prescaler on runtime without calling
<>	144:ef7eb2e8f9f7	1208	* another time HAL_TIM_IC_ConfigChannel() function.
<>	144:ef7eb2e8f9f7	1209	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1210	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1211	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1212	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1213	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1214	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1215	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1216	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
<>	144:ef7eb2e8f9f7	1217	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1218	* @arg TIM_ICPSC_DIV1: no prescaler
<>	144:ef7eb2e8f9f7	1219	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
<>	144:ef7eb2e8f9f7	1220	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
<>	144:ef7eb2e8f9f7	1221	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<>	144:ef7eb2e8f9f7	1222	* @retval None
<>	144:ef7eb2e8f9f7	1223	*/
<>	144:ef7eb2e8f9f7	1224	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	144:ef7eb2e8f9f7	1225	do{ \
<>	144:ef7eb2e8f9f7	1226	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
<>	144:ef7eb2e8f9f7	1227	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
<>	144:ef7eb2e8f9f7	1228	} while(0)
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	/**
AnnaBridge	167:e84263d55307	1231	* @brief Gets the TIM Input Capture prescaler on runtime.
<>	144:ef7eb2e8f9f7	1232	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1233	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1234	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1235	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
<>	144:ef7eb2e8f9f7	1236	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
<>	144:ef7eb2e8f9f7	1237	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
<>	144:ef7eb2e8f9f7	1238	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge	167:e84263d55307	1239	* @retval The input capture prescaler can be one of the following values:
AnnaBridge	167:e84263d55307	1240	* @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge	167:e84263d55307	1241	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge	167:e84263d55307	1242	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge	167:e84263d55307	1243	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<>	144:ef7eb2e8f9f7	1244	*/
<>	144:ef7eb2e8f9f7	1245	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1246	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<>	144:ef7eb2e8f9f7	1247	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
<>	144:ef7eb2e8f9f7	1248	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<>	144:ef7eb2e8f9f7	1249	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	/**
<>	144:ef7eb2e8f9f7	1252	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
<>	144:ef7eb2e8f9f7	1253	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1254	* @note When the USR bit of the TIMx_CR1 register is set, only counter
<>	144:ef7eb2e8f9f7	1255	* overflow/underflow generates an update interrupt or DMA request (if
<>	144:ef7eb2e8f9f7	1256	* enabled)
<>	144:ef7eb2e8f9f7	1257	* @retval None
<>	144:ef7eb2e8f9f7	1258	*/
<>	144:ef7eb2e8f9f7	1259	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1260	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	/**
<>	144:ef7eb2e8f9f7	1263	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
<>	144:ef7eb2e8f9f7	1264	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1265	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
<>	144:ef7eb2e8f9f7	1266	* following events generate an update interrupt or DMA request (if
<>	144:ef7eb2e8f9f7	1267	* enabled):
<>	144:ef7eb2e8f9f7	1268	* _ Counter overflow/underflow
<>	144:ef7eb2e8f9f7	1269	* _ Setting the UG bit
<>	144:ef7eb2e8f9f7	1270	* _ Update generation through the slave mode controller
<>	144:ef7eb2e8f9f7	1271	* @retval None
<>	144:ef7eb2e8f9f7	1272	*/
<>	144:ef7eb2e8f9f7	1273	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1274	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
<>	144:ef7eb2e8f9f7	1275
<>	144:ef7eb2e8f9f7	1276	/**
<>	144:ef7eb2e8f9f7	1277	* @brief Sets the TIM Capture x input polarity on runtime.
<>	144:ef7eb2e8f9f7	1278	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1279	* @param __CHANNEL__: TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1280	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1281	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1282	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1283	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1284	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1285	* @param __POLARITY__: Polarity for TIx source
<>	144:ef7eb2e8f9f7	1286	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
<>	144:ef7eb2e8f9f7	1287	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
<>	144:ef7eb2e8f9f7	1288	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
<>	144:ef7eb2e8f9f7	1289	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
<>	144:ef7eb2e8f9f7	1290	* @retval None
<>	144:ef7eb2e8f9f7	1291	*/
<>	144:ef7eb2e8f9f7	1292	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	144:ef7eb2e8f9f7	1293	do{ \
<>	144:ef7eb2e8f9f7	1294	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
<>	144:ef7eb2e8f9f7	1295	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
<>	144:ef7eb2e8f9f7	1296	}while(0)
<>	144:ef7eb2e8f9f7	1297	/**
<>	144:ef7eb2e8f9f7	1298	* @}
<>	144:ef7eb2e8f9f7	1299	*/
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301	/* Include TIM HAL Extension module */
<>	144:ef7eb2e8f9f7	1302	#include "stm32f2xx_hal_tim_ex.h"
<>	144:ef7eb2e8f9f7	1303
<>	144:ef7eb2e8f9f7	1304	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1305	/** @addtogroup TIM_Exported_Functions
<>	144:ef7eb2e8f9f7	1306	* @{
<>	144:ef7eb2e8f9f7	1307	*/
<>	144:ef7eb2e8f9f7	1308
<>	144:ef7eb2e8f9f7	1309	/** @addtogroup TIM_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1310	* @{
<>	144:ef7eb2e8f9f7	1311	*/
<>	144:ef7eb2e8f9f7	1312
<>	144:ef7eb2e8f9f7	1313	/* Time Base functions ********************************************************/
<>	144:ef7eb2e8f9f7	1314	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1315	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1316	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1317	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1318	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1319	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1320	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1321	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1322	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1323	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1324	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1325	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1326	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1327	/**
<>	144:ef7eb2e8f9f7	1328	* @}
<>	144:ef7eb2e8f9f7	1329	*/
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	/** @addtogroup TIM_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	1332	* @{
<>	144:ef7eb2e8f9f7	1333	*/
<>	144:ef7eb2e8f9f7	1334	/* Timer Output Compare functions **********************************************/
<>	144:ef7eb2e8f9f7	1335	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1336	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1337	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1338	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1339	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1340	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1341	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1342	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1343	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1344	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1345	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1346	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1347	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1348
<>	144:ef7eb2e8f9f7	1349	/**
<>	144:ef7eb2e8f9f7	1350	* @}
<>	144:ef7eb2e8f9f7	1351	*/
<>	144:ef7eb2e8f9f7	1352
<>	144:ef7eb2e8f9f7	1353	/** @addtogroup TIM_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	1354	* @{
<>	144:ef7eb2e8f9f7	1355	*/
<>	144:ef7eb2e8f9f7	1356	/* Timer PWM functions *********************************************************/
<>	144:ef7eb2e8f9f7	1357	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1358	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1359	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1360	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1361	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1362	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1363	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1364	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1365	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1366	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1367	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1368	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1369	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371	/**
<>	144:ef7eb2e8f9f7	1372	* @}
<>	144:ef7eb2e8f9f7	1373	*/
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	/** @addtogroup TIM_Exported_Functions_Group4
<>	144:ef7eb2e8f9f7	1376	* @{
<>	144:ef7eb2e8f9f7	1377	*/
<>	144:ef7eb2e8f9f7	1378	/* Timer Input Capture functions ***********************************************/
<>	144:ef7eb2e8f9f7	1379	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1380	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1381	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1382	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1383	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1384	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1385	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1386	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1387	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1388	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1389	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1390	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1391	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1392
<>	144:ef7eb2e8f9f7	1393	/**
<>	144:ef7eb2e8f9f7	1394	* @}
<>	144:ef7eb2e8f9f7	1395	*/
<>	144:ef7eb2e8f9f7	1396
<>	144:ef7eb2e8f9f7	1397	/** @addtogroup TIM_Exported_Functions_Group5
<>	144:ef7eb2e8f9f7	1398	* @{
<>	144:ef7eb2e8f9f7	1399	*/
<>	144:ef7eb2e8f9f7	1400	/* Timer One Pulse functions ***************************************************/
<>	144:ef7eb2e8f9f7	1401	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
<>	144:ef7eb2e8f9f7	1402	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1403	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1404	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1405	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1406	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1407	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1408
<>	144:ef7eb2e8f9f7	1409	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1410	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1411	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	/**
<>	144:ef7eb2e8f9f7	1414	* @}
<>	144:ef7eb2e8f9f7	1415	*/
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417	/** @addtogroup TIM_Exported_Functions_Group6
<>	144:ef7eb2e8f9f7	1418	* @{
<>	144:ef7eb2e8f9f7	1419	*/
<>	144:ef7eb2e8f9f7	1420	/* Timer Encoder functions *****************************************************/
<>	144:ef7eb2e8f9f7	1421	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
<>	144:ef7eb2e8f9f7	1422	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1423	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1424	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1425	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1426	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1427	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1428	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1429	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1430	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1431	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1432	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
<>	144:ef7eb2e8f9f7	1433	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/**
<>	144:ef7eb2e8f9f7	1436	* @}
<>	144:ef7eb2e8f9f7	1437	*/
<>	144:ef7eb2e8f9f7	1438
<>	144:ef7eb2e8f9f7	1439	/** @addtogroup TIM_Exported_Functions_Group7
<>	144:ef7eb2e8f9f7	1440	* @{
<>	144:ef7eb2e8f9f7	1441	*/
<>	144:ef7eb2e8f9f7	1442	/* Interrupt Handler functions **********************************************/
<>	144:ef7eb2e8f9f7	1443	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	/**
<>	144:ef7eb2e8f9f7	1446	* @}
<>	144:ef7eb2e8f9f7	1447	*/
<>	144:ef7eb2e8f9f7	1448
<>	144:ef7eb2e8f9f7	1449	/** @addtogroup TIM_Exported_Functions_Group8
<>	144:ef7eb2e8f9f7	1450	* @{
<>	144:ef7eb2e8f9f7	1451	*/
<>	144:ef7eb2e8f9f7	1452	/* Control functions *********************************************************/
<>	144:ef7eb2e8f9f7	1453	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1454	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1455	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1456	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
<>	144:ef7eb2e8f9f7	1457	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1458	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
<>	144:ef7eb2e8f9f7	1459	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
<>	144:ef7eb2e8f9f7	1460	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	144:ef7eb2e8f9f7	1461	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	144:ef7eb2e8f9f7	1462	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	144:ef7eb2e8f9f7	1463	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	144:ef7eb2e8f9f7	1464	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	144:ef7eb2e8f9f7	1465	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	144:ef7eb2e8f9f7	1466	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	144:ef7eb2e8f9f7	1467	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	144:ef7eb2e8f9f7	1468	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
<>	144:ef7eb2e8f9f7	1469	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1470
<>	144:ef7eb2e8f9f7	1471	/**
<>	144:ef7eb2e8f9f7	1472	* @}
<>	144:ef7eb2e8f9f7	1473	*/
<>	144:ef7eb2e8f9f7	1474
<>	144:ef7eb2e8f9f7	1475	/** @addtogroup TIM_Exported_Functions_Group9
<>	144:ef7eb2e8f9f7	1476	* @{
<>	144:ef7eb2e8f9f7	1477	*/
<>	144:ef7eb2e8f9f7	1478	/* Callback in non blocking modes (Interrupt and DMA) *************************/
<>	144:ef7eb2e8f9f7	1479	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1480	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1481	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1482	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1483	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1484	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1485
<>	144:ef7eb2e8f9f7	1486	/**
<>	144:ef7eb2e8f9f7	1487	* @}
<>	144:ef7eb2e8f9f7	1488	*/
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	/** @addtogroup TIM_Exported_Functions_Group10
<>	144:ef7eb2e8f9f7	1491	* @{
<>	144:ef7eb2e8f9f7	1492	*/
<>	144:ef7eb2e8f9f7	1493	/* Peripheral State functions **************************************************/
<>	144:ef7eb2e8f9f7	1494	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1495	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1496	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1497	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1498	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1499	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/**
<>	144:ef7eb2e8f9f7	1502	* @}
<>	144:ef7eb2e8f9f7	1503	*/
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	/**
<>	144:ef7eb2e8f9f7	1506	* @}
<>	144:ef7eb2e8f9f7	1507	*/
<>	144:ef7eb2e8f9f7	1508
<>	144:ef7eb2e8f9f7	1509	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1510	/** @defgroup TIM_Private_Macros TIM Private Macros
<>	144:ef7eb2e8f9f7	1511	* @{
<>	144:ef7eb2e8f9f7	1512	*/
<>	144:ef7eb2e8f9f7	1513
<>	144:ef7eb2e8f9f7	1514	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
<>	144:ef7eb2e8f9f7	1515	* @{
<>	144:ef7eb2e8f9f7	1516	*/
<>	144:ef7eb2e8f9f7	1517	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
<>	144:ef7eb2e8f9f7	1518	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
<>	144:ef7eb2e8f9f7	1519	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
<>	144:ef7eb2e8f9f7	1520	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
<>	144:ef7eb2e8f9f7	1521	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	1524	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1525	((DIV) == TIM_CLOCKDIVISION_DIV4))
<>	144:ef7eb2e8f9f7	1526
AnnaBridge	167:e84263d55307	1527	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
AnnaBridge	167:e84263d55307	1528	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
AnnaBridge	167:e84263d55307	1529
<>	144:ef7eb2e8f9f7	1530	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
<>	144:ef7eb2e8f9f7	1531	((MODE) == TIM_OCMODE_PWM2))
<>	144:ef7eb2e8f9f7	1532
<>	144:ef7eb2e8f9f7	1533	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
<>	144:ef7eb2e8f9f7	1534	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	1535	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	1536	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
<>	144:ef7eb2e8f9f7	1537	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	1538	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
<>	144:ef7eb2e8f9f7	1539
<>	144:ef7eb2e8f9f7	1540	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1541	((STATE) == TIM_OCFAST_ENABLE))
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	1544	((POLARITY) == TIM_OCPOLARITY_LOW))
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	1547	((POLARITY) == TIM_OCNPOLARITY_LOW))
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
<>	144:ef7eb2e8f9f7	1550	((STATE) == TIM_OCIDLESTATE_RESET))
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
<>	144:ef7eb2e8f9f7	1553	((STATE) == TIM_OCNIDLESTATE_RESET))
<>	144:ef7eb2e8f9f7	1554
<>	144:ef7eb2e8f9f7	1555	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1556	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1557	((CHANNEL) == TIM_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1558	((CHANNEL) == TIM_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	1559	((CHANNEL) == TIM_CHANNEL_ALL))
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1562	((CHANNEL) == TIM_CHANNEL_2))
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1565	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1566	((CHANNEL) == TIM_CHANNEL_3))
<>	144:ef7eb2e8f9f7	1567
<>	144:ef7eb2e8f9f7	1568	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
<>	144:ef7eb2e8f9f7	1569	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	1570	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
<>	144:ef7eb2e8f9f7	1573	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
<>	144:ef7eb2e8f9f7	1574	((SELECTION) == TIM_ICSELECTION_TRC))
<>	144:ef7eb2e8f9f7	1575
<>	144:ef7eb2e8f9f7	1576	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	1577	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1578	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1579	((PRESCALER) == TIM_ICPSC_DIV8))
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
<>	144:ef7eb2e8f9f7	1582	((MODE) == TIM_OPMODE_REPETITIVE))
<>	144:ef7eb2e8f9f7	1583
<>	144:ef7eb2e8f9f7	1584	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	144:ef7eb2e8f9f7	1585
<>	144:ef7eb2e8f9f7	1586	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
<>	144:ef7eb2e8f9f7	1587	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
<>	144:ef7eb2e8f9f7	1588	((MODE) == TIM_ENCODERMODE_TI12))
<>	144:ef7eb2e8f9f7	1589
<>	144:ef7eb2e8f9f7	1590	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	144:ef7eb2e8f9f7	1591
<>	144:ef7eb2e8f9f7	1592	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
<>	144:ef7eb2e8f9f7	1593	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
<>	144:ef7eb2e8f9f7	1594	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	1595	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	1596	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	1597	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	1598	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
<>	144:ef7eb2e8f9f7	1599	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
<>	144:ef7eb2e8f9f7	1600	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
<>	144:ef7eb2e8f9f7	1601	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
<>	144:ef7eb2e8f9f7	1604	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
<>	144:ef7eb2e8f9f7	1605	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
<>	144:ef7eb2e8f9f7	1606	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	1607	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
<>	144:ef7eb2e8f9f7	1608
<>	144:ef7eb2e8f9f7	1609	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	1610	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1611	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1612	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<>	144:ef7eb2e8f9f7	1615
<>	144:ef7eb2e8f9f7	1616	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1617	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
<>	144:ef7eb2e8f9f7	1618
<>	144:ef7eb2e8f9f7	1619	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
<>	144:ef7eb2e8f9f7	1620	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
<>	144:ef7eb2e8f9f7	1621
<>	144:ef7eb2e8f9f7	1622	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	1623	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1624	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1625	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	1626
<>	144:ef7eb2e8f9f7	1627	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<>	144:ef7eb2e8f9f7	1628
<>	144:ef7eb2e8f9f7	1629	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1630	((STATE) == TIM_OSSR_DISABLE))
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1633	((STATE) == TIM_OSSI_DISABLE))
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
<>	144:ef7eb2e8f9f7	1636	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1637	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1638	((LEVEL) == TIM_LOCKLEVEL_3))
<>	144:ef7eb2e8f9f7	1639
<>	144:ef7eb2e8f9f7	1640	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1641	((STATE) == TIM_BREAK_DISABLE))
<>	144:ef7eb2e8f9f7	1642
<>	144:ef7eb2e8f9f7	1643	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
<>	144:ef7eb2e8f9f7	1644	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
<>	144:ef7eb2e8f9f7	1645
<>	144:ef7eb2e8f9f7	1646	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1647	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
<>	144:ef7eb2e8f9f7	1648
<>	144:ef7eb2e8f9f7	1649	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
<>	144:ef7eb2e8f9f7	1650	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1651	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	1652	((SOURCE) == TIM_TRGO_OC1) \|\| \
<>	144:ef7eb2e8f9f7	1653	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
<>	144:ef7eb2e8f9f7	1654	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
<>	144:ef7eb2e8f9f7	1655	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
<>	144:ef7eb2e8f9f7	1656	((SOURCE) == TIM_TRGO_OC4REF))
<>	144:ef7eb2e8f9f7	1657
<>	144:ef7eb2e8f9f7	1658	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1659	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
<>	144:ef7eb2e8f9f7	1660	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
<>	144:ef7eb2e8f9f7	1661	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	1662	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1665	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
<>	144:ef7eb2e8f9f7	1666
<>	144:ef7eb2e8f9f7	1667	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	1668	((SELECTION) == TIM_TS_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	1669	((SELECTION) == TIM_TS_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	1670	((SELECTION) == TIM_TS_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	1671	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
<>	144:ef7eb2e8f9f7	1672	((SELECTION) == TIM_TS_TI1FP1) \|\| \
<>	144:ef7eb2e8f9f7	1673	((SELECTION) == TIM_TS_TI2FP2) \|\| \
<>	144:ef7eb2e8f9f7	1674	((SELECTION) == TIM_TS_ETRF))
<>	144:ef7eb2e8f9f7	1675
<>	144:ef7eb2e8f9f7	1676	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	1677	((SELECTION) == TIM_TS_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	1678	((SELECTION) == TIM_TS_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	1679	((SELECTION) == TIM_TS_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	1680	((SELECTION) == TIM_TS_NONE))
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
<>	144:ef7eb2e8f9f7	1683	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
<>	144:ef7eb2e8f9f7	1684	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
<>	144:ef7eb2e8f9f7	1685	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
<>	144:ef7eb2e8f9f7	1686	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
<>	144:ef7eb2e8f9f7	1687
<>	144:ef7eb2e8f9f7	1688	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	1689	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1690	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1691	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	1692
<>	144:ef7eb2e8f9f7	1693	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
<>	144:ef7eb2e8f9f7	1696	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
<>	144:ef7eb2e8f9f7	1699	((BASE) == TIM_DMABASE_CR2) \|\| \
<>	144:ef7eb2e8f9f7	1700	((BASE) == TIM_DMABASE_SMCR) \|\| \
<>	144:ef7eb2e8f9f7	1701	((BASE) == TIM_DMABASE_DIER) \|\| \
<>	144:ef7eb2e8f9f7	1702	((BASE) == TIM_DMABASE_SR) \|\| \
<>	144:ef7eb2e8f9f7	1703	((BASE) == TIM_DMABASE_EGR) \|\| \
<>	144:ef7eb2e8f9f7	1704	((BASE) == TIM_DMABASE_CCMR1) \|\| \
<>	144:ef7eb2e8f9f7	1705	((BASE) == TIM_DMABASE_CCMR2) \|\| \
<>	144:ef7eb2e8f9f7	1706	((BASE) == TIM_DMABASE_CCER) \|\| \
<>	144:ef7eb2e8f9f7	1707	((BASE) == TIM_DMABASE_CNT) \|\| \
<>	144:ef7eb2e8f9f7	1708	((BASE) == TIM_DMABASE_PSC) \|\| \
<>	144:ef7eb2e8f9f7	1709	((BASE) == TIM_DMABASE_ARR) \|\| \
<>	144:ef7eb2e8f9f7	1710	((BASE) == TIM_DMABASE_RCR) \|\| \
<>	144:ef7eb2e8f9f7	1711	((BASE) == TIM_DMABASE_CCR1) \|\| \
<>	144:ef7eb2e8f9f7	1712	((BASE) == TIM_DMABASE_CCR2) \|\| \
<>	144:ef7eb2e8f9f7	1713	((BASE) == TIM_DMABASE_CCR3) \|\| \
<>	144:ef7eb2e8f9f7	1714	((BASE) == TIM_DMABASE_CCR4) \|\| \
<>	144:ef7eb2e8f9f7	1715	((BASE) == TIM_DMABASE_BDTR) \|\| \
<>	144:ef7eb2e8f9f7	1716	((BASE) == TIM_DMABASE_DCR) \|\| \
<>	144:ef7eb2e8f9f7	1717	((BASE) == TIM_DMABASE_OR))
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
<>	144:ef7eb2e8f9f7	1720	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1721	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1722	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1723	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1724	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1725	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1726	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1727	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1728	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1729	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1730	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1731	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1732	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1733	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1734	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1735	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1736	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
<>	144:ef7eb2e8f9f7	1737
<>	144:ef7eb2e8f9f7	1738	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<>	144:ef7eb2e8f9f7	1739	/**
<>	144:ef7eb2e8f9f7	1740	* @}
<>	144:ef7eb2e8f9f7	1741	*/
<>	144:ef7eb2e8f9f7	1742
<>	144:ef7eb2e8f9f7	1743	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
<>	144:ef7eb2e8f9f7	1744	* @{
<>	144:ef7eb2e8f9f7	1745	*/
<>	144:ef7eb2e8f9f7	1746	/* The counter of a timer instance is disabled only if all the CCx and CCxN
<>	144:ef7eb2e8f9f7	1747	channels have been disabled */
<>	144:ef7eb2e8f9f7	1748	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
<>	144:ef7eb2e8f9f7	1749	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
<>	144:ef7eb2e8f9f7	1750	/**
<>	144:ef7eb2e8f9f7	1751	* @}
<>	144:ef7eb2e8f9f7	1752	*/
<>	144:ef7eb2e8f9f7	1753
<>	144:ef7eb2e8f9f7	1754	/**
<>	144:ef7eb2e8f9f7	1755	* @}
<>	144:ef7eb2e8f9f7	1756	*/
<>	144:ef7eb2e8f9f7	1757
<>	144:ef7eb2e8f9f7	1758	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1759	/** @defgroup TIM_Private_Functions TIM Private Functions
<>	144:ef7eb2e8f9f7	1760	* @{
<>	144:ef7eb2e8f9f7	1761	*/
<>	144:ef7eb2e8f9f7	1762	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
<>	144:ef7eb2e8f9f7	1763	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	1764	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	1765	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1766	void TIM_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1767	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1768	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<>	144:ef7eb2e8f9f7	1769	/**
<>	144:ef7eb2e8f9f7	1770	* @}
<>	144:ef7eb2e8f9f7	1771	*/
<>	144:ef7eb2e8f9f7	1772
<>	144:ef7eb2e8f9f7	1773	/**
<>	144:ef7eb2e8f9f7	1774	* @}
<>	144:ef7eb2e8f9f7	1775	*/
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/**
<>	144:ef7eb2e8f9f7	1778	* @}
<>	144:ef7eb2e8f9f7	1779	*/
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1782	}
<>	144:ef7eb2e8f9f7	1783	#endif
<>	144:ef7eb2e8f9f7	1784
<>	144:ef7eb2e8f9f7	1785	#endif /* __STM32F2xx_HAL_TIM_H */
<>	144:ef7eb2e8f9f7	1786
<>	144:ef7eb2e8f9f7	1787	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/