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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_tim.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief TIM HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Timer (TIM) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Time Base Initialization
<>	144:ef7eb2e8f9f7	11	* + Time Base Start
<>	144:ef7eb2e8f9f7	12	* + Time Base Start Interruption
<>	144:ef7eb2e8f9f7	13	* + Time Base Start DMA
<>	144:ef7eb2e8f9f7	14	* + Time Output Compare/PWM Initialization
<>	144:ef7eb2e8f9f7	15	* + Time Output Compare/PWM Channel Configuration
<>	144:ef7eb2e8f9f7	16	* + Time Output Compare/PWM Start
<>	144:ef7eb2e8f9f7	17	* + Time Output Compare/PWM Start Interruption
<>	144:ef7eb2e8f9f7	18	* + Time Output Compare/PWM Start DMA
<>	144:ef7eb2e8f9f7	19	* + Time Input Capture Initialization
<>	144:ef7eb2e8f9f7	20	* + Time Input Capture Channel Configuration
<>	144:ef7eb2e8f9f7	21	* + Time Input Capture Start
<>	144:ef7eb2e8f9f7	22	* + Time Input Capture Start Interruption
<>	144:ef7eb2e8f9f7	23	* + Time Input Capture Start DMA
<>	144:ef7eb2e8f9f7	24	* + Time One Pulse Initialization
<>	144:ef7eb2e8f9f7	25	* + Time One Pulse Channel Configuration
<>	144:ef7eb2e8f9f7	26	* + Time One Pulse Start
<>	144:ef7eb2e8f9f7	27	* + Time Encoder Interface Initialization
<>	144:ef7eb2e8f9f7	28	* + Time Encoder Interface Start
<>	144:ef7eb2e8f9f7	29	* + Time Encoder Interface Start Interruption
<>	144:ef7eb2e8f9f7	30	* + Time Encoder Interface Start DMA
<>	144:ef7eb2e8f9f7	31	* + Commutation Event configuration with Interruption and DMA
<>	144:ef7eb2e8f9f7	32	* + Time OCRef clear configuration
<>	144:ef7eb2e8f9f7	33	* + Time External Clock configuration
<>	144:ef7eb2e8f9f7	34	@verbatim
<>	144:ef7eb2e8f9f7	35	==============================================================================
<>	144:ef7eb2e8f9f7	36	##### TIMER Generic features #####
<>	144:ef7eb2e8f9f7	37	==============================================================================
<>	144:ef7eb2e8f9f7	38	[..] The Timer features include:
<>	144:ef7eb2e8f9f7	39	(#) 16-bit up, down, up/down auto-reload counter.
<>	144:ef7eb2e8f9f7	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<>	144:ef7eb2e8f9f7	41	counter clock frequency either by any factor between 1 and 65536.
<>	144:ef7eb2e8f9f7	42	(#) Up to 4 independent channels for:
<>	144:ef7eb2e8f9f7	43	(++) Input Capture
<>	144:ef7eb2e8f9f7	44	(++) Output Compare
<>	144:ef7eb2e8f9f7	45	(++) PWM generation (Edge and Center-aligned Mode)
<>	144:ef7eb2e8f9f7	46	(++) One-pulse mode output
<>	144:ef7eb2e8f9f7	47
<>	144:ef7eb2e8f9f7	48	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	49	==============================================================================
<>	144:ef7eb2e8f9f7	50	[..]
<>	144:ef7eb2e8f9f7	51	(#) Initialize the TIM low level resources by implementing the following functions
<>	144:ef7eb2e8f9f7	52	depending from feature used :
<>	144:ef7eb2e8f9f7	53	(++) Time Base : HAL_TIM_Base_MspInit()
<>	144:ef7eb2e8f9f7	54	(++) Input Capture : HAL_TIM_IC_MspInit()
<>	144:ef7eb2e8f9f7	55	(++) Output Compare : HAL_TIM_OC_MspInit()
<>	144:ef7eb2e8f9f7	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
<>	144:ef7eb2e8f9f7	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<>	144:ef7eb2e8f9f7	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	(#) Initialize the TIM low level resources :
<>	144:ef7eb2e8f9f7	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	62	(##) TIM pins configuration
<>	144:ef7eb2e8f9f7	63	(+++) Enable the clock for the TIM GPIOs using the following function:
<>	144:ef7eb2e8f9f7	64	__GPIOx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	(#) The external Clock can be configured, if needed (the default clock is the
<>	144:ef7eb2e8f9f7	68	internal clock from the APBx), using the following function:
<>	144:ef7eb2e8f9f7	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
<>	144:ef7eb2e8f9f7	70	any start function.
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	(#) Configure the TIM in the desired functioning mode using one of the
<>	144:ef7eb2e8f9f7	73	initialization function of this driver:
<>	144:ef7eb2e8f9f7	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<>	144:ef7eb2e8f9f7	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<>	144:ef7eb2e8f9f7	76	Output Compare signal.
<>	144:ef7eb2e8f9f7	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<>	144:ef7eb2e8f9f7	78	PWM signal.
<>	144:ef7eb2e8f9f7	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<>	144:ef7eb2e8f9f7	80	external signal.
<>	144:ef7eb2e8f9f7	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<>	144:ef7eb2e8f9f7	82	in One Pulse Mode.
<>	144:ef7eb2e8f9f7	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<>	144:ef7eb2e8f9f7	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<>	144:ef7eb2e8f9f7	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<>	144:ef7eb2e8f9f7	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<>	144:ef7eb2e8f9f7	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<>	144:ef7eb2e8f9f7	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<>	144:ef7eb2e8f9f7	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	(#) The DMA Burst is managed with the two following functions:
<>	144:ef7eb2e8f9f7	94	HAL_TIM_DMABurst_WriteStart()
<>	144:ef7eb2e8f9f7	95	HAL_TIM_DMABurst_ReadStart()
<>	144:ef7eb2e8f9f7	96
<>	144:ef7eb2e8f9f7	97	@endverbatim
<>	144:ef7eb2e8f9f7	98	******************************************************************************
<>	144:ef7eb2e8f9f7	99	* @attention
<>	144:ef7eb2e8f9f7	100	*
AnnaBridge	167:e84263d55307	101	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	102	*
<>	144:ef7eb2e8f9f7	103	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	104	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	105	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	106	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	108	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	109	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	111	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	112	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	113	*
<>	144:ef7eb2e8f9f7	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	124	*
<>	144:ef7eb2e8f9f7	125	******************************************************************************
<>	144:ef7eb2e8f9f7	126	*/
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	129	#include "stm32f2xx_hal.h"
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	132	* @{
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/** @defgroup TIM TIM
<>	144:ef7eb2e8f9f7	136	* @brief TIM HAL module driver
<>	144:ef7eb2e8f9f7	137	* @{
<>	144:ef7eb2e8f9f7	138	*/
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	#ifdef HAL_TIM_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	143	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	144	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	145	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	146	/** @addtogroup TIM_Private_Functions
<>	144:ef7eb2e8f9f7	147	* @{
<>	144:ef7eb2e8f9f7	148	*/
<>	144:ef7eb2e8f9f7	149	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	150	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	151	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	152	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	153
<>	144:ef7eb2e8f9f7	154	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	155	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	156	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	157	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	158	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	159	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	160	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	161	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<>	144:ef7eb2e8f9f7	164	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
<>	144:ef7eb2e8f9f7	167	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	168	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	169	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	170	TIM_SlaveConfigTypeDef * sSlaveConfig);
<>	144:ef7eb2e8f9f7	171	/**
<>	144:ef7eb2e8f9f7	172	* @}
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	176	/** @defgroup TIM_Exported_Functions TIM Exported Functions
<>	144:ef7eb2e8f9f7	177	* @{
<>	144:ef7eb2e8f9f7	178	*/
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<>	144:ef7eb2e8f9f7	181	* @brief Time Base functions
<>	144:ef7eb2e8f9f7	182	*
<>	144:ef7eb2e8f9f7	183	@verbatim
<>	144:ef7eb2e8f9f7	184	==============================================================================
<>	144:ef7eb2e8f9f7	185	##### Time Base functions #####
<>	144:ef7eb2e8f9f7	186	==============================================================================
<>	144:ef7eb2e8f9f7	187	[..]
<>	144:ef7eb2e8f9f7	188	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	189	(+) Initialize and configure the TIM base.
<>	144:ef7eb2e8f9f7	190	(+) De-initialize the TIM base.
<>	144:ef7eb2e8f9f7	191	(+) Start the Time Base.
<>	144:ef7eb2e8f9f7	192	(+) Stop the Time Base.
<>	144:ef7eb2e8f9f7	193	(+) Start the Time Base and enable interrupt.
<>	144:ef7eb2e8f9f7	194	(+) Stop the Time Base and disable interrupt.
<>	144:ef7eb2e8f9f7	195	(+) Start the Time Base and enable DMA transfer.
<>	144:ef7eb2e8f9f7	196	(+) Stop the Time Base and disable DMA transfer.
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198	@endverbatim
<>	144:ef7eb2e8f9f7	199	* @{
<>	144:ef7eb2e8f9f7	200	*/
<>	144:ef7eb2e8f9f7	201	/**
<>	144:ef7eb2e8f9f7	202	* @brief Initializes the TIM Time base Unit according to the specified
<>	144:ef7eb2e8f9f7	203	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	204	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	205	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	206	* @retval HAL status
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	209	{
<>	144:ef7eb2e8f9f7	210	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	211	if(htim == NULL)
<>	144:ef7eb2e8f9f7	212	{
<>	144:ef7eb2e8f9f7	213	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	214	}
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	/* Check the parameters */
<>	144:ef7eb2e8f9f7	217	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	218	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	219	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	167:e84263d55307	220	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	221
<>	144:ef7eb2e8f9f7	222	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	223	{
<>	144:ef7eb2e8f9f7	224	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	225	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	226	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	227	HAL_TIM_Base_MspInit(htim);
<>	144:ef7eb2e8f9f7	228	}
<>	144:ef7eb2e8f9f7	229
<>	144:ef7eb2e8f9f7	230	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	231	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	/* Set the Time Base configuration */
<>	144:ef7eb2e8f9f7	234	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	237	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	return HAL_OK;
<>	144:ef7eb2e8f9f7	240	}
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	/**
<>	144:ef7eb2e8f9f7	243	* @brief DeInitializes the TIM Base peripheral
<>	144:ef7eb2e8f9f7	244	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	245	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	246	* @retval HAL status
<>	144:ef7eb2e8f9f7	247	*/
<>	144:ef7eb2e8f9f7	248	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	249	{
<>	144:ef7eb2e8f9f7	250	/* Check the parameters */
<>	144:ef7eb2e8f9f7	251	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	252
<>	144:ef7eb2e8f9f7	253	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	256	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	259	HAL_TIM_Base_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	/* Change TIM state */
<>	144:ef7eb2e8f9f7	262	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/* Release Lock */
<>	144:ef7eb2e8f9f7	265	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	return HAL_OK;
<>	144:ef7eb2e8f9f7	268	}
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	/**
<>	144:ef7eb2e8f9f7	271	* @brief Initializes the TIM Base MSP.
<>	144:ef7eb2e8f9f7	272	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	273	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	274	* @retval None
<>	144:ef7eb2e8f9f7	275	*/
<>	144:ef7eb2e8f9f7	276	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	277	{
<>	144:ef7eb2e8f9f7	278	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	279	UNUSED(htim);
<>	144:ef7eb2e8f9f7	280	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	281	the HAL_TIM_Base_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283	}
<>	144:ef7eb2e8f9f7	284
<>	144:ef7eb2e8f9f7	285	/**
<>	144:ef7eb2e8f9f7	286	* @brief DeInitializes TIM Base MSP.
<>	144:ef7eb2e8f9f7	287	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	288	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	289	* @retval None
<>	144:ef7eb2e8f9f7	290	*/
<>	144:ef7eb2e8f9f7	291	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	292	{
<>	144:ef7eb2e8f9f7	293	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	294	UNUSED(htim);
<>	144:ef7eb2e8f9f7	295	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	296	the HAL_TIM_Base_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	297	*/
<>	144:ef7eb2e8f9f7	298	}
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/**
<>	144:ef7eb2e8f9f7	301	* @brief Starts the TIM Base generation.
<>	144:ef7eb2e8f9f7	302	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	303	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	304	* @retval HAL status
<>	144:ef7eb2e8f9f7	305	*/
<>	144:ef7eb2e8f9f7	306	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	307	{
<>	144:ef7eb2e8f9f7	308	/* Check the parameters */
<>	144:ef7eb2e8f9f7	309	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	312	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	315	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	318	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/* Return function status */
<>	144:ef7eb2e8f9f7	321	return HAL_OK;
<>	144:ef7eb2e8f9f7	322	}
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/**
<>	144:ef7eb2e8f9f7	325	* @brief Stops the TIM Base generation.
<>	144:ef7eb2e8f9f7	326	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	327	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	328	* @retval HAL status
<>	144:ef7eb2e8f9f7	329	*/
<>	144:ef7eb2e8f9f7	330	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	331	{
<>	144:ef7eb2e8f9f7	332	/* Check the parameters */
<>	144:ef7eb2e8f9f7	333	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	336	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	339	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	340
<>	144:ef7eb2e8f9f7	341	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	342	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	343
<>	144:ef7eb2e8f9f7	344	/* Return function status */
<>	144:ef7eb2e8f9f7	345	return HAL_OK;
<>	144:ef7eb2e8f9f7	346	}
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/**
<>	144:ef7eb2e8f9f7	349	* @brief Starts the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	350	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	351	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	352	* @retval HAL status
<>	144:ef7eb2e8f9f7	353	*/
<>	144:ef7eb2e8f9f7	354	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	355	{
<>	144:ef7eb2e8f9f7	356	/* Check the parameters */
<>	144:ef7eb2e8f9f7	357	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	/* Enable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	360	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	363	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	364
<>	144:ef7eb2e8f9f7	365	/* Return function status */
<>	144:ef7eb2e8f9f7	366	return HAL_OK;
<>	144:ef7eb2e8f9f7	367	}
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/**
<>	144:ef7eb2e8f9f7	370	* @brief Stops the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	371	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	372	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	373	* @retval HAL status
<>	144:ef7eb2e8f9f7	374	*/
<>	144:ef7eb2e8f9f7	375	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	376	{
<>	144:ef7eb2e8f9f7	377	/* Check the parameters */
<>	144:ef7eb2e8f9f7	378	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	379	/* Disable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	380	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	383	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/* Return function status */
<>	144:ef7eb2e8f9f7	386	return HAL_OK;
<>	144:ef7eb2e8f9f7	387	}
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/**
<>	144:ef7eb2e8f9f7	390	* @brief Starts the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	391	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	392	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	393	* @param pData: The source Buffer address.
<>	144:ef7eb2e8f9f7	394	* @param Length: The length of data to be transferred from memory to peripheral.
<>	144:ef7eb2e8f9f7	395	* @retval HAL status
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	398	{
<>	144:ef7eb2e8f9f7	399	/* Check the parameters */
<>	144:ef7eb2e8f9f7	400	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	401
<>	144:ef7eb2e8f9f7	402	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	403	{
<>	144:ef7eb2e8f9f7	404	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	405	}
<>	144:ef7eb2e8f9f7	406	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	407	{
AnnaBridge	167:e84263d55307	408	if((pData == 0U ) && (Length > 0))
<>	144:ef7eb2e8f9f7	409	{
<>	144:ef7eb2e8f9f7	410	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	411	}
<>	144:ef7eb2e8f9f7	412	else
<>	144:ef7eb2e8f9f7	413	{
<>	144:ef7eb2e8f9f7	414	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	415	}
<>	144:ef7eb2e8f9f7	416	}
<>	144:ef7eb2e8f9f7	417	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	418	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	421	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	422
<>	144:ef7eb2e8f9f7	423	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	424	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<>	144:ef7eb2e8f9f7	425
<>	144:ef7eb2e8f9f7	426	/* Enable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	427	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	430	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/* Return function status */
<>	144:ef7eb2e8f9f7	433	return HAL_OK;
<>	144:ef7eb2e8f9f7	434	}
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	/**
<>	144:ef7eb2e8f9f7	437	* @brief Stops the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	438	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	439	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	440	* @retval HAL status
<>	144:ef7eb2e8f9f7	441	*/
<>	144:ef7eb2e8f9f7	442	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	443	{
<>	144:ef7eb2e8f9f7	444	/* Check the parameters */
<>	144:ef7eb2e8f9f7	445	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	448	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	451	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	/* Change the htim state */
<>	144:ef7eb2e8f9f7	454	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	455
<>	144:ef7eb2e8f9f7	456	/* Return function status */
<>	144:ef7eb2e8f9f7	457	return HAL_OK;
<>	144:ef7eb2e8f9f7	458	}
<>	144:ef7eb2e8f9f7	459	/**
<>	144:ef7eb2e8f9f7	460	* @}
<>	144:ef7eb2e8f9f7	461	*/
<>	144:ef7eb2e8f9f7	462
<>	144:ef7eb2e8f9f7	463	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<>	144:ef7eb2e8f9f7	464	* @brief Time Output Compare functions
<>	144:ef7eb2e8f9f7	465	*
<>	144:ef7eb2e8f9f7	466	@verbatim
<>	144:ef7eb2e8f9f7	467	==============================================================================
<>	144:ef7eb2e8f9f7	468	##### Time Output Compare functions #####
<>	144:ef7eb2e8f9f7	469	==============================================================================
<>	144:ef7eb2e8f9f7	470	[..]
<>	144:ef7eb2e8f9f7	471	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	472	(+) Initialize and configure the TIM Output Compare.
<>	144:ef7eb2e8f9f7	473	(+) De-initialize the TIM Output Compare.
<>	144:ef7eb2e8f9f7	474	(+) Start the Time Output Compare.
<>	144:ef7eb2e8f9f7	475	(+) Stop the Time Output Compare.
<>	144:ef7eb2e8f9f7	476	(+) Start the Time Output Compare and enable interrupt.
<>	144:ef7eb2e8f9f7	477	(+) Stop the Time Output Compare and disable interrupt.
<>	144:ef7eb2e8f9f7	478	(+) Start the Time Output Compare and enable DMA transfer.
<>	144:ef7eb2e8f9f7	479	(+) Stop the Time Output Compare and disable DMA transfer.
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	@endverbatim
<>	144:ef7eb2e8f9f7	482	* @{
<>	144:ef7eb2e8f9f7	483	*/
<>	144:ef7eb2e8f9f7	484	/**
<>	144:ef7eb2e8f9f7	485	* @brief Initializes the TIM Output Compare according to the specified
<>	144:ef7eb2e8f9f7	486	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	487	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	488	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	489	* @retval HAL status
<>	144:ef7eb2e8f9f7	490	*/
<>	144:ef7eb2e8f9f7	491	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<>	144:ef7eb2e8f9f7	492	{
<>	144:ef7eb2e8f9f7	493	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	494	if(htim == NULL)
<>	144:ef7eb2e8f9f7	495	{
<>	144:ef7eb2e8f9f7	496	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	497	}
<>	144:ef7eb2e8f9f7	498
<>	144:ef7eb2e8f9f7	499	/* Check the parameters */
<>	144:ef7eb2e8f9f7	500	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	501	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	502	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	167:e84263d55307	503	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
AnnaBridge	167:e84263d55307	504
<>	144:ef7eb2e8f9f7	505	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	506	{
<>	144:ef7eb2e8f9f7	507	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	508	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	509	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	510	HAL_TIM_OC_MspInit(htim);
<>	144:ef7eb2e8f9f7	511	}
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	514	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	/* Init the base time for the Output Compare */
<>	144:ef7eb2e8f9f7	517	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	520	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	521
<>	144:ef7eb2e8f9f7	522	return HAL_OK;
<>	144:ef7eb2e8f9f7	523	}
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	/**
<>	144:ef7eb2e8f9f7	526	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	527	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	528	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	529	* @retval HAL status
<>	144:ef7eb2e8f9f7	530	*/
<>	144:ef7eb2e8f9f7	531	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	532	{
<>	144:ef7eb2e8f9f7	533	/* Check the parameters */
<>	144:ef7eb2e8f9f7	534	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	539	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	540
<>	144:ef7eb2e8f9f7	541	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	542	HAL_TIM_OC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	/* Change TIM state */
<>	144:ef7eb2e8f9f7	545	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	/* Release Lock */
<>	144:ef7eb2e8f9f7	548	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	return HAL_OK;
<>	144:ef7eb2e8f9f7	551	}
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/**
<>	144:ef7eb2e8f9f7	554	* @brief Initializes the TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	555	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	556	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	557	* @retval None
<>	144:ef7eb2e8f9f7	558	*/
<>	144:ef7eb2e8f9f7	559	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	560	{
<>	144:ef7eb2e8f9f7	561	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	562	UNUSED(htim);
<>	144:ef7eb2e8f9f7	563	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	564	the HAL_TIM_OC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	565	*/
<>	144:ef7eb2e8f9f7	566	}
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	/**
<>	144:ef7eb2e8f9f7	569	* @brief DeInitializes TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	570	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	571	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	572	* @retval None
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	575	{
<>	144:ef7eb2e8f9f7	576	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	577	UNUSED(htim);
<>	144:ef7eb2e8f9f7	578	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	579	the HAL_TIM_OC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	580	*/
<>	144:ef7eb2e8f9f7	581	}
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	/**
<>	144:ef7eb2e8f9f7	584	* @brief Starts the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	585	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	586	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	587	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	588	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	589	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	590	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	591	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	592	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	593	* @retval HAL status
<>	144:ef7eb2e8f9f7	594	*/
<>	144:ef7eb2e8f9f7	595	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	596	{
<>	144:ef7eb2e8f9f7	597	/* Check the parameters */
<>	144:ef7eb2e8f9f7	598	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	601	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	604	{
<>	144:ef7eb2e8f9f7	605	/* Enable the main output */
<>	144:ef7eb2e8f9f7	606	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	607	}
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	610	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/* Return function status */
<>	144:ef7eb2e8f9f7	613	return HAL_OK;
<>	144:ef7eb2e8f9f7	614	}
<>	144:ef7eb2e8f9f7	615
<>	144:ef7eb2e8f9f7	616	/**
<>	144:ef7eb2e8f9f7	617	* @brief Stops the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	618	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	619	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	620	* @param Channel: TIM Channel to be disabled.
<>	144:ef7eb2e8f9f7	621	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	622	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	623	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	624	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	625	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	626	* @retval HAL status
<>	144:ef7eb2e8f9f7	627	*/
<>	144:ef7eb2e8f9f7	628	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	629	{
<>	144:ef7eb2e8f9f7	630	/* Check the parameters */
<>	144:ef7eb2e8f9f7	631	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	634	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	635
<>	144:ef7eb2e8f9f7	636	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	637	{
<>	144:ef7eb2e8f9f7	638	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	639	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	640	}
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	643	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	/* Return function status */
<>	144:ef7eb2e8f9f7	646	return HAL_OK;
<>	144:ef7eb2e8f9f7	647	}
<>	144:ef7eb2e8f9f7	648
<>	144:ef7eb2e8f9f7	649	/**
<>	144:ef7eb2e8f9f7	650	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	651	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	652	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	653	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	654	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	655	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	656	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	657	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	658	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	659	* @retval HAL status
<>	144:ef7eb2e8f9f7	660	*/
<>	144:ef7eb2e8f9f7	661	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	662	{
<>	144:ef7eb2e8f9f7	663	/* Check the parameters */
<>	144:ef7eb2e8f9f7	664	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	665
<>	144:ef7eb2e8f9f7	666	switch (Channel)
<>	144:ef7eb2e8f9f7	667	{
<>	144:ef7eb2e8f9f7	668	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	669	{
<>	144:ef7eb2e8f9f7	670	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	671	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	672	}
<>	144:ef7eb2e8f9f7	673	break;
<>	144:ef7eb2e8f9f7	674
<>	144:ef7eb2e8f9f7	675	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	676	{
<>	144:ef7eb2e8f9f7	677	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	678	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	679	}
<>	144:ef7eb2e8f9f7	680	break;
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	683	{
<>	144:ef7eb2e8f9f7	684	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	685	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	686	}
<>	144:ef7eb2e8f9f7	687	break;
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	690	{
<>	144:ef7eb2e8f9f7	691	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	692	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	693	}
<>	144:ef7eb2e8f9f7	694	break;
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	default:
<>	144:ef7eb2e8f9f7	697	break;
<>	144:ef7eb2e8f9f7	698	}
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	701	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	704	{
<>	144:ef7eb2e8f9f7	705	/* Enable the main output */
<>	144:ef7eb2e8f9f7	706	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	707	}
<>	144:ef7eb2e8f9f7	708
<>	144:ef7eb2e8f9f7	709	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	710	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	711
<>	144:ef7eb2e8f9f7	712	/* Return function status */
<>	144:ef7eb2e8f9f7	713	return HAL_OK;
<>	144:ef7eb2e8f9f7	714	}
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716	/**
<>	144:ef7eb2e8f9f7	717	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	718	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	719	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	720	* @param Channel: TIM Channel to be disabled.
<>	144:ef7eb2e8f9f7	721	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	722	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	723	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	724	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	725	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	726	* @retval HAL status
<>	144:ef7eb2e8f9f7	727	*/
<>	144:ef7eb2e8f9f7	728	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	729	{
<>	144:ef7eb2e8f9f7	730	/* Check the parameters */
<>	144:ef7eb2e8f9f7	731	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	732
<>	144:ef7eb2e8f9f7	733	switch (Channel)
<>	144:ef7eb2e8f9f7	734	{
<>	144:ef7eb2e8f9f7	735	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	736	{
<>	144:ef7eb2e8f9f7	737	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	738	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	739	}
<>	144:ef7eb2e8f9f7	740	break;
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	745	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	746	}
<>	144:ef7eb2e8f9f7	747	break;
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	750	{
<>	144:ef7eb2e8f9f7	751	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	752	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	753	}
<>	144:ef7eb2e8f9f7	754	break;
<>	144:ef7eb2e8f9f7	755
<>	144:ef7eb2e8f9f7	756	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	757	{
<>	144:ef7eb2e8f9f7	758	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	759	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	760	}
<>	144:ef7eb2e8f9f7	761	break;
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	default:
<>	144:ef7eb2e8f9f7	764	break;
<>	144:ef7eb2e8f9f7	765	}
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	768	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	771	{
<>	144:ef7eb2e8f9f7	772	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	773	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	774	}
<>	144:ef7eb2e8f9f7	775
<>	144:ef7eb2e8f9f7	776	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	777	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	/* Return function status */
<>	144:ef7eb2e8f9f7	780	return HAL_OK;
<>	144:ef7eb2e8f9f7	781	}
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	/**
<>	144:ef7eb2e8f9f7	784	* @brief Starts the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	785	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	786	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	787	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	788	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	789	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	790	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	791	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	792	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	793	* @param pData: The source Buffer address.
<>	144:ef7eb2e8f9f7	794	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	795	* @retval HAL status
<>	144:ef7eb2e8f9f7	796	*/
<>	144:ef7eb2e8f9f7	797	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	798	{
<>	144:ef7eb2e8f9f7	799	/* Check the parameters */
<>	144:ef7eb2e8f9f7	800	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	801
<>	144:ef7eb2e8f9f7	802	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	803	{
<>	144:ef7eb2e8f9f7	804	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	805	}
<>	144:ef7eb2e8f9f7	806	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	807	{
AnnaBridge	167:e84263d55307	808	if(((uint32_t)pData == 0U ) && (Length > 0))
<>	144:ef7eb2e8f9f7	809	{
<>	144:ef7eb2e8f9f7	810	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	811	}
<>	144:ef7eb2e8f9f7	812	else
<>	144:ef7eb2e8f9f7	813	{
<>	144:ef7eb2e8f9f7	814	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	815	}
<>	144:ef7eb2e8f9f7	816	}
<>	144:ef7eb2e8f9f7	817	switch (Channel)
<>	144:ef7eb2e8f9f7	818	{
<>	144:ef7eb2e8f9f7	819	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	820	{
<>	144:ef7eb2e8f9f7	821	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	822	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	825	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	826
<>	144:ef7eb2e8f9f7	827	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	828	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	831	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	832	}
<>	144:ef7eb2e8f9f7	833	break;
<>	144:ef7eb2e8f9f7	834
<>	144:ef7eb2e8f9f7	835	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	836	{
<>	144:ef7eb2e8f9f7	837	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	838	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	841	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	844	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	845
<>	144:ef7eb2e8f9f7	846	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	847	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	848	}
<>	144:ef7eb2e8f9f7	849	break;
<>	144:ef7eb2e8f9f7	850
<>	144:ef7eb2e8f9f7	851	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	852	{
<>	144:ef7eb2e8f9f7	853	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	854	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	855
<>	144:ef7eb2e8f9f7	856	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	857	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	860	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	863	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	864	}
<>	144:ef7eb2e8f9f7	865	break;
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	868	{
<>	144:ef7eb2e8f9f7	869	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	870	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	873	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	876	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	879	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	880	}
<>	144:ef7eb2e8f9f7	881	break;
<>	144:ef7eb2e8f9f7	882
<>	144:ef7eb2e8f9f7	883	default:
<>	144:ef7eb2e8f9f7	884	break;
<>	144:ef7eb2e8f9f7	885	}
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	888	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	889
<>	144:ef7eb2e8f9f7	890	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	891	{
<>	144:ef7eb2e8f9f7	892	/* Enable the main output */
<>	144:ef7eb2e8f9f7	893	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	894	}
<>	144:ef7eb2e8f9f7	895
<>	144:ef7eb2e8f9f7	896	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	897	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	898
<>	144:ef7eb2e8f9f7	899	/* Return function status */
<>	144:ef7eb2e8f9f7	900	return HAL_OK;
<>	144:ef7eb2e8f9f7	901	}
<>	144:ef7eb2e8f9f7	902
<>	144:ef7eb2e8f9f7	903	/**
<>	144:ef7eb2e8f9f7	904	* @brief Stops the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	905	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	906	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	907	* @param Channel: TIM Channel to be disabled.
<>	144:ef7eb2e8f9f7	908	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	909	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	910	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	911	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	912	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	913	* @retval HAL status
<>	144:ef7eb2e8f9f7	914	*/
<>	144:ef7eb2e8f9f7	915	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	916	{
<>	144:ef7eb2e8f9f7	917	/* Check the parameters */
<>	144:ef7eb2e8f9f7	918	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	switch (Channel)
<>	144:ef7eb2e8f9f7	921	{
<>	144:ef7eb2e8f9f7	922	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	923	{
<>	144:ef7eb2e8f9f7	924	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	925	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	926	}
<>	144:ef7eb2e8f9f7	927	break;
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	930	{
<>	144:ef7eb2e8f9f7	931	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	932	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	933	}
<>	144:ef7eb2e8f9f7	934	break;
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	937	{
<>	144:ef7eb2e8f9f7	938	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	939	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	940	}
<>	144:ef7eb2e8f9f7	941	break;
<>	144:ef7eb2e8f9f7	942
<>	144:ef7eb2e8f9f7	943	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	944	{
<>	144:ef7eb2e8f9f7	945	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	946	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	947	}
<>	144:ef7eb2e8f9f7	948	break;
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	default:
<>	144:ef7eb2e8f9f7	951	break;
<>	144:ef7eb2e8f9f7	952	}
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	955	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	958	{
<>	144:ef7eb2e8f9f7	959	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	960	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	961	}
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	964	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	/* Change the htim state */
<>	144:ef7eb2e8f9f7	967	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	968
<>	144:ef7eb2e8f9f7	969	/* Return function status */
<>	144:ef7eb2e8f9f7	970	return HAL_OK;
<>	144:ef7eb2e8f9f7	971	}
<>	144:ef7eb2e8f9f7	972	/**
<>	144:ef7eb2e8f9f7	973	* @}
<>	144:ef7eb2e8f9f7	974	*/
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<>	144:ef7eb2e8f9f7	977	* @brief Time PWM functions
<>	144:ef7eb2e8f9f7	978	*
<>	144:ef7eb2e8f9f7	979	@verbatim
<>	144:ef7eb2e8f9f7	980	==============================================================================
<>	144:ef7eb2e8f9f7	981	##### Time PWM functions #####
<>	144:ef7eb2e8f9f7	982	==============================================================================
<>	144:ef7eb2e8f9f7	983	[..]
<>	144:ef7eb2e8f9f7	984	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	985	(+) Initialize and configure the TIM OPWM.
<>	144:ef7eb2e8f9f7	986	(+) De-initialize the TIM PWM.
<>	144:ef7eb2e8f9f7	987	(+) Start the Time PWM.
<>	144:ef7eb2e8f9f7	988	(+) Stop the Time PWM.
<>	144:ef7eb2e8f9f7	989	(+) Start the Time PWM and enable interrupt.
<>	144:ef7eb2e8f9f7	990	(+) Stop the Time PWM and disable interrupt.
<>	144:ef7eb2e8f9f7	991	(+) Start the Time PWM and enable DMA transfer.
<>	144:ef7eb2e8f9f7	992	(+) Stop the Time PWM and disable DMA transfer.
<>	144:ef7eb2e8f9f7	993
<>	144:ef7eb2e8f9f7	994	@endverbatim
<>	144:ef7eb2e8f9f7	995	* @{
<>	144:ef7eb2e8f9f7	996	*/
<>	144:ef7eb2e8f9f7	997	/**
<>	144:ef7eb2e8f9f7	998	* @brief Initializes the TIM PWM Time Base according to the specified
<>	144:ef7eb2e8f9f7	999	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1000	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1001	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1002	* @retval HAL status
<>	144:ef7eb2e8f9f7	1003	*/
<>	144:ef7eb2e8f9f7	1004	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1005	{
<>	144:ef7eb2e8f9f7	1006	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1007	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1008	{
<>	144:ef7eb2e8f9f7	1009	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1010	}
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1013	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1014	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1015	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	167:e84263d55307	1016	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
AnnaBridge	167:e84263d55307	1017
<>	144:ef7eb2e8f9f7	1018	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1019	{
<>	144:ef7eb2e8f9f7	1020	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1021	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1022	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1023	HAL_TIM_PWM_MspInit(htim);
<>	144:ef7eb2e8f9f7	1024	}
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1027	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/* Init the base time for the PWM */
<>	144:ef7eb2e8f9f7	1030	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1033	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	return HAL_OK;
<>	144:ef7eb2e8f9f7	1036	}
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	/**
<>	144:ef7eb2e8f9f7	1039	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	1040	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1041	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1042	* @retval HAL status
<>	144:ef7eb2e8f9f7	1043	*/
<>	144:ef7eb2e8f9f7	1044	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1045	{
<>	144:ef7eb2e8f9f7	1046	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1047	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1052	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1053
<>	144:ef7eb2e8f9f7	1054	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1055	HAL_TIM_PWM_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1058	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/* Release Lock */
<>	144:ef7eb2e8f9f7	1061	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1062
<>	144:ef7eb2e8f9f7	1063	return HAL_OK;
<>	144:ef7eb2e8f9f7	1064	}
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	/**
<>	144:ef7eb2e8f9f7	1067	* @brief Initializes the TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1068	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1069	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1070	* @retval None
<>	144:ef7eb2e8f9f7	1071	*/
<>	144:ef7eb2e8f9f7	1072	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1073	{
<>	144:ef7eb2e8f9f7	1074	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1075	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1076	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1077	the HAL_TIM_PWM_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1078	*/
<>	144:ef7eb2e8f9f7	1079	}
<>	144:ef7eb2e8f9f7	1080
<>	144:ef7eb2e8f9f7	1081	/**
<>	144:ef7eb2e8f9f7	1082	* @brief DeInitializes TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1083	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1084	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1085	* @retval None
<>	144:ef7eb2e8f9f7	1086	*/
<>	144:ef7eb2e8f9f7	1087	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1088	{
<>	144:ef7eb2e8f9f7	1089	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1090	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1091	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1092	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1093	*/
<>	144:ef7eb2e8f9f7	1094	}
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	/**
<>	144:ef7eb2e8f9f7	1097	* @brief Starts the PWM signal generation.
<>	144:ef7eb2e8f9f7	1098	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1099	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1100	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1101	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1102	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1103	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1104	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1105	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1106	* @retval HAL status
<>	144:ef7eb2e8f9f7	1107	*/
<>	144:ef7eb2e8f9f7	1108	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1109	{
<>	144:ef7eb2e8f9f7	1110	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1111	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1114	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1115
<>	144:ef7eb2e8f9f7	1116	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1117	{
<>	144:ef7eb2e8f9f7	1118	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1119	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1120	}
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1123	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	/* Return function status */
<>	144:ef7eb2e8f9f7	1126	return HAL_OK;
<>	144:ef7eb2e8f9f7	1127	}
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	/**
<>	144:ef7eb2e8f9f7	1130	* @brief Stops the PWM signal generation.
<>	144:ef7eb2e8f9f7	1131	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1132	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1133	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1134	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1135	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1136	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1137	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1138	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1139	* @retval HAL status
<>	144:ef7eb2e8f9f7	1140	*/
<>	144:ef7eb2e8f9f7	1141	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1142	{
<>	144:ef7eb2e8f9f7	1143	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1144	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1145
<>	144:ef7eb2e8f9f7	1146	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1147	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1148
<>	144:ef7eb2e8f9f7	1149	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1150	{
<>	144:ef7eb2e8f9f7	1151	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	1152	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1153	}
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1156	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1159	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	/* Return function status */
<>	144:ef7eb2e8f9f7	1162	return HAL_OK;
<>	144:ef7eb2e8f9f7	1163	}
<>	144:ef7eb2e8f9f7	1164
<>	144:ef7eb2e8f9f7	1165	/**
<>	144:ef7eb2e8f9f7	1166	* @brief Starts the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1167	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1168	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1169	* @param Channel: TIM Channel to be enabled.
<>	144:ef7eb2e8f9f7	1170	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1171	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1172	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1173	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1174	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1175	* @retval HAL status
<>	144:ef7eb2e8f9f7	1176	*/
<>	144:ef7eb2e8f9f7	1177	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1178	{
<>	144:ef7eb2e8f9f7	1179	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1180	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1181
<>	144:ef7eb2e8f9f7	1182	switch (Channel)
<>	144:ef7eb2e8f9f7	1183	{
<>	144:ef7eb2e8f9f7	1184	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1185	{
<>	144:ef7eb2e8f9f7	1186	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1187	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1188	}
<>	144:ef7eb2e8f9f7	1189	break;
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1192	{
<>	144:ef7eb2e8f9f7	1193	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1194	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1195	}
<>	144:ef7eb2e8f9f7	1196	break;
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1199	{
<>	144:ef7eb2e8f9f7	1200	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1201	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1202	}
<>	144:ef7eb2e8f9f7	1203	break;
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1206	{
<>	144:ef7eb2e8f9f7	1207	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1208	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1209	}
<>	144:ef7eb2e8f9f7	1210	break;
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	default:
<>	144:ef7eb2e8f9f7	1213	break;
<>	144:ef7eb2e8f9f7	1214	}
<>	144:ef7eb2e8f9f7	1215
<>	144:ef7eb2e8f9f7	1216	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1217	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1220	{
<>	144:ef7eb2e8f9f7	1221	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1222	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1223	}
<>	144:ef7eb2e8f9f7	1224
<>	144:ef7eb2e8f9f7	1225	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1226	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1227
<>	144:ef7eb2e8f9f7	1228	/* Return function status */
<>	144:ef7eb2e8f9f7	1229	return HAL_OK;
<>	144:ef7eb2e8f9f7	1230	}
<>	144:ef7eb2e8f9f7	1231
<>	144:ef7eb2e8f9f7	1232	/**
<>	144:ef7eb2e8f9f7	1233	* @brief Stops the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1234	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1235	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1236	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1237	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1238	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1239	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1240	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1241	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1242	* @retval HAL status
<>	144:ef7eb2e8f9f7	1243	*/
<>	144:ef7eb2e8f9f7	1244	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1245	{
<>	144:ef7eb2e8f9f7	1246	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1247	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1248
<>	144:ef7eb2e8f9f7	1249	switch (Channel)
<>	144:ef7eb2e8f9f7	1250	{
<>	144:ef7eb2e8f9f7	1251	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1252	{
<>	144:ef7eb2e8f9f7	1253	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1254	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1255	}
<>	144:ef7eb2e8f9f7	1256	break;
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1259	{
<>	144:ef7eb2e8f9f7	1260	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1261	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1262	}
<>	144:ef7eb2e8f9f7	1263	break;
<>	144:ef7eb2e8f9f7	1264
<>	144:ef7eb2e8f9f7	1265	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1266	{
<>	144:ef7eb2e8f9f7	1267	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1268	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1269	}
<>	144:ef7eb2e8f9f7	1270	break;
<>	144:ef7eb2e8f9f7	1271
<>	144:ef7eb2e8f9f7	1272	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1273	{
<>	144:ef7eb2e8f9f7	1274	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1275	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1276	}
<>	144:ef7eb2e8f9f7	1277	break;
<>	144:ef7eb2e8f9f7	1278
<>	144:ef7eb2e8f9f7	1279	default:
<>	144:ef7eb2e8f9f7	1280	break;
<>	144:ef7eb2e8f9f7	1281	}
<>	144:ef7eb2e8f9f7	1282
<>	144:ef7eb2e8f9f7	1283	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1284	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1285
<>	144:ef7eb2e8f9f7	1286	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1287	{
<>	144:ef7eb2e8f9f7	1288	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	1289	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1290	}
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1293	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1294
<>	144:ef7eb2e8f9f7	1295	/* Return function status */
<>	144:ef7eb2e8f9f7	1296	return HAL_OK;
<>	144:ef7eb2e8f9f7	1297	}
<>	144:ef7eb2e8f9f7	1298
<>	144:ef7eb2e8f9f7	1299	/**
<>	144:ef7eb2e8f9f7	1300	* @brief Starts the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1301	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1302	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1303	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1304	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1305	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1306	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1307	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1308	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1309	* @param pData: The source Buffer address.
<>	144:ef7eb2e8f9f7	1310	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	1311	* @retval HAL status
<>	144:ef7eb2e8f9f7	1312	*/
<>	144:ef7eb2e8f9f7	1313	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1314	{
<>	144:ef7eb2e8f9f7	1315	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1316	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1319	{
<>	144:ef7eb2e8f9f7	1320	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1321	}
<>	144:ef7eb2e8f9f7	1322	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1323	{
AnnaBridge	167:e84263d55307	1324	if(((uint32_t)pData == 0U ) && (Length > 0))
<>	144:ef7eb2e8f9f7	1325	{
<>	144:ef7eb2e8f9f7	1326	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1327	}
<>	144:ef7eb2e8f9f7	1328	else
<>	144:ef7eb2e8f9f7	1329	{
<>	144:ef7eb2e8f9f7	1330	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1331	}
<>	144:ef7eb2e8f9f7	1332	}
<>	144:ef7eb2e8f9f7	1333	switch (Channel)
<>	144:ef7eb2e8f9f7	1334	{
<>	144:ef7eb2e8f9f7	1335	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1336	{
<>	144:ef7eb2e8f9f7	1337	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1338	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1339
<>	144:ef7eb2e8f9f7	1340	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1341	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1342
<>	144:ef7eb2e8f9f7	1343	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1344	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	1345
<>	144:ef7eb2e8f9f7	1346	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1347	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1348	}
<>	144:ef7eb2e8f9f7	1349	break;
<>	144:ef7eb2e8f9f7	1350
<>	144:ef7eb2e8f9f7	1351	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1352	{
<>	144:ef7eb2e8f9f7	1353	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1354	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1355
<>	144:ef7eb2e8f9f7	1356	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1357	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1358
<>	144:ef7eb2e8f9f7	1359	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1360	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	1361
<>	144:ef7eb2e8f9f7	1362	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1363	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1364	}
<>	144:ef7eb2e8f9f7	1365	break;
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1368	{
<>	144:ef7eb2e8f9f7	1369	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1370	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1373	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1376	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378	/* Enable the TIM Output Capture/Compare 3 request */
<>	144:ef7eb2e8f9f7	1379	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1380	}
<>	144:ef7eb2e8f9f7	1381	break;
<>	144:ef7eb2e8f9f7	1382
<>	144:ef7eb2e8f9f7	1383	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1384	{
<>	144:ef7eb2e8f9f7	1385	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1386	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1389	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1390
<>	144:ef7eb2e8f9f7	1391	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1392	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1395	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1396	}
<>	144:ef7eb2e8f9f7	1397	break;
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399	default:
<>	144:ef7eb2e8f9f7	1400	break;
<>	144:ef7eb2e8f9f7	1401	}
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1404	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1405
<>	144:ef7eb2e8f9f7	1406	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1407	{
<>	144:ef7eb2e8f9f7	1408	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1409	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1410	}
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1413	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1414
<>	144:ef7eb2e8f9f7	1415	/* Return function status */
<>	144:ef7eb2e8f9f7	1416	return HAL_OK;
<>	144:ef7eb2e8f9f7	1417	}
<>	144:ef7eb2e8f9f7	1418
<>	144:ef7eb2e8f9f7	1419	/**
<>	144:ef7eb2e8f9f7	1420	* @brief Stops the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1421	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1422	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1423	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1424	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1425	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1426	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1427	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1428	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1429	* @retval HAL status
<>	144:ef7eb2e8f9f7	1430	*/
<>	144:ef7eb2e8f9f7	1431	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1432	{
<>	144:ef7eb2e8f9f7	1433	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1434	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1435
<>	144:ef7eb2e8f9f7	1436	switch (Channel)
<>	144:ef7eb2e8f9f7	1437	{
<>	144:ef7eb2e8f9f7	1438	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1439	{
<>	144:ef7eb2e8f9f7	1440	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1441	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1442	}
<>	144:ef7eb2e8f9f7	1443	break;
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1446	{
<>	144:ef7eb2e8f9f7	1447	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1448	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1449	}
<>	144:ef7eb2e8f9f7	1450	break;
<>	144:ef7eb2e8f9f7	1451
<>	144:ef7eb2e8f9f7	1452	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1453	{
<>	144:ef7eb2e8f9f7	1454	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1455	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1456	}
<>	144:ef7eb2e8f9f7	1457	break;
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1460	{
<>	144:ef7eb2e8f9f7	1461	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1462	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1463	}
<>	144:ef7eb2e8f9f7	1464	break;
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	default:
<>	144:ef7eb2e8f9f7	1467	break;
<>	144:ef7eb2e8f9f7	1468	}
<>	144:ef7eb2e8f9f7	1469
<>	144:ef7eb2e8f9f7	1470	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1471	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1472
<>	144:ef7eb2e8f9f7	1473	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1474	{
<>	144:ef7eb2e8f9f7	1475	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	1476	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1477	}
<>	144:ef7eb2e8f9f7	1478
<>	144:ef7eb2e8f9f7	1479	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1480	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1481
<>	144:ef7eb2e8f9f7	1482	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1483	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1484
<>	144:ef7eb2e8f9f7	1485	/* Return function status */
<>	144:ef7eb2e8f9f7	1486	return HAL_OK;
<>	144:ef7eb2e8f9f7	1487	}
<>	144:ef7eb2e8f9f7	1488	/**
<>	144:ef7eb2e8f9f7	1489	* @}
<>	144:ef7eb2e8f9f7	1490	*/
<>	144:ef7eb2e8f9f7	1491
<>	144:ef7eb2e8f9f7	1492	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<>	144:ef7eb2e8f9f7	1493	* @brief Time Input Capture functions
<>	144:ef7eb2e8f9f7	1494	*
<>	144:ef7eb2e8f9f7	1495	@verbatim
<>	144:ef7eb2e8f9f7	1496	==============================================================================
<>	144:ef7eb2e8f9f7	1497	##### Time Input Capture functions #####
<>	144:ef7eb2e8f9f7	1498	==============================================================================
<>	144:ef7eb2e8f9f7	1499	[..]
<>	144:ef7eb2e8f9f7	1500	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1501	(+) Initialize and configure the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1502	(+) De-initialize the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1503	(+) Start the Time Input Capture.
<>	144:ef7eb2e8f9f7	1504	(+) Stop the Time Input Capture.
<>	144:ef7eb2e8f9f7	1505	(+) Start the Time Input Capture and enable interrupt.
<>	144:ef7eb2e8f9f7	1506	(+) Stop the Time Input Capture and disable interrupt.
<>	144:ef7eb2e8f9f7	1507	(+) Start the Time Input Capture and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1508	(+) Stop the Time Input Capture and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1509
<>	144:ef7eb2e8f9f7	1510	@endverbatim
<>	144:ef7eb2e8f9f7	1511	* @{
<>	144:ef7eb2e8f9f7	1512	*/
<>	144:ef7eb2e8f9f7	1513	/**
<>	144:ef7eb2e8f9f7	1514	* @brief Initializes the TIM Input Capture Time base according to the specified
<>	144:ef7eb2e8f9f7	1515	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1516	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1517	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1518	* @retval HAL status
<>	144:ef7eb2e8f9f7	1519	*/
<>	144:ef7eb2e8f9f7	1520	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1521	{
<>	144:ef7eb2e8f9f7	1522	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1523	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1524	{
<>	144:ef7eb2e8f9f7	1525	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1526	}
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1529	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1530	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1531	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	167:e84263d55307	1532	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
AnnaBridge	167:e84263d55307	1533
<>	144:ef7eb2e8f9f7	1534	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1535	{
<>	144:ef7eb2e8f9f7	1536	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1537	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1538	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1539	HAL_TIM_IC_MspInit(htim);
<>	144:ef7eb2e8f9f7	1540	}
<>	144:ef7eb2e8f9f7	1541
<>	144:ef7eb2e8f9f7	1542	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1543	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1544
<>	144:ef7eb2e8f9f7	1545	/* Init the base time for the input capture */
<>	144:ef7eb2e8f9f7	1546	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1547
<>	144:ef7eb2e8f9f7	1548	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1549	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1550
<>	144:ef7eb2e8f9f7	1551	return HAL_OK;
<>	144:ef7eb2e8f9f7	1552	}
<>	144:ef7eb2e8f9f7	1553
<>	144:ef7eb2e8f9f7	1554	/**
<>	144:ef7eb2e8f9f7	1555	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	1556	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1557	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1558	* @retval HAL status
<>	144:ef7eb2e8f9f7	1559	*/
<>	144:ef7eb2e8f9f7	1560	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1561	{
<>	144:ef7eb2e8f9f7	1562	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1563	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1564
<>	144:ef7eb2e8f9f7	1565	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1566
<>	144:ef7eb2e8f9f7	1567	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1568	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1569
<>	144:ef7eb2e8f9f7	1570	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1571	HAL_TIM_IC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1572
<>	144:ef7eb2e8f9f7	1573	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1574	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1575
<>	144:ef7eb2e8f9f7	1576	/* Release Lock */
<>	144:ef7eb2e8f9f7	1577	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1578
<>	144:ef7eb2e8f9f7	1579	return HAL_OK;
<>	144:ef7eb2e8f9f7	1580	}
<>	144:ef7eb2e8f9f7	1581
<>	144:ef7eb2e8f9f7	1582	/**
<>	144:ef7eb2e8f9f7	1583	* @brief Initializes the TIM INput Capture MSP.
<>	144:ef7eb2e8f9f7	1584	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1585	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1586	* @retval None
<>	144:ef7eb2e8f9f7	1587	*/
<>	144:ef7eb2e8f9f7	1588	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1591	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1592	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1593	the HAL_TIM_IC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1594	*/
<>	144:ef7eb2e8f9f7	1595	}
<>	144:ef7eb2e8f9f7	1596
<>	144:ef7eb2e8f9f7	1597	/**
<>	144:ef7eb2e8f9f7	1598	* @brief DeInitializes TIM Input Capture MSP.
<>	144:ef7eb2e8f9f7	1599	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1600	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1601	* @retval None
<>	144:ef7eb2e8f9f7	1602	*/
<>	144:ef7eb2e8f9f7	1603	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1604	{
<>	144:ef7eb2e8f9f7	1605	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1606	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1607	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1608	the HAL_TIM_IC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1609	*/
<>	144:ef7eb2e8f9f7	1610	}
<>	144:ef7eb2e8f9f7	1611
<>	144:ef7eb2e8f9f7	1612	/**
<>	144:ef7eb2e8f9f7	1613	* @brief Starts the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1614	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1615	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1616	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1617	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1618	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1619	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1620	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1621	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1622	* @retval HAL status
<>	144:ef7eb2e8f9f7	1623	*/
<>	144:ef7eb2e8f9f7	1624	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1625	{
<>	144:ef7eb2e8f9f7	1626	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1627	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1628
<>	144:ef7eb2e8f9f7	1629	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1630	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1633	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	/* Return function status */
<>	144:ef7eb2e8f9f7	1636	return HAL_OK;
<>	144:ef7eb2e8f9f7	1637	}
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	/**
<>	144:ef7eb2e8f9f7	1640	* @brief Stops the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1641	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1642	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1643	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1644	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1645	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1646	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1647	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1648	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1649	* @retval HAL status
<>	144:ef7eb2e8f9f7	1650	*/
<>	144:ef7eb2e8f9f7	1651	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1652	{
<>	144:ef7eb2e8f9f7	1653	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1654	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1655
<>	144:ef7eb2e8f9f7	1656	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1657	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1658
<>	144:ef7eb2e8f9f7	1659	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1660	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	/* Return function status */
<>	144:ef7eb2e8f9f7	1663	return HAL_OK;
<>	144:ef7eb2e8f9f7	1664	}
<>	144:ef7eb2e8f9f7	1665
<>	144:ef7eb2e8f9f7	1666	/**
<>	144:ef7eb2e8f9f7	1667	* @brief Starts the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1668	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1669	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1670	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1671	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1672	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1673	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1674	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1675	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1676	* @retval HAL status
<>	144:ef7eb2e8f9f7	1677	*/
<>	144:ef7eb2e8f9f7	1678	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1679	{
<>	144:ef7eb2e8f9f7	1680	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1681	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1682
<>	144:ef7eb2e8f9f7	1683	switch (Channel)
<>	144:ef7eb2e8f9f7	1684	{
<>	144:ef7eb2e8f9f7	1685	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1686	{
<>	144:ef7eb2e8f9f7	1687	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1688	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1689	}
<>	144:ef7eb2e8f9f7	1690	break;
<>	144:ef7eb2e8f9f7	1691
<>	144:ef7eb2e8f9f7	1692	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1693	{
<>	144:ef7eb2e8f9f7	1694	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1695	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1696	}
<>	144:ef7eb2e8f9f7	1697	break;
<>	144:ef7eb2e8f9f7	1698
<>	144:ef7eb2e8f9f7	1699	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1700	{
<>	144:ef7eb2e8f9f7	1701	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1702	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1703	}
<>	144:ef7eb2e8f9f7	1704	break;
<>	144:ef7eb2e8f9f7	1705
<>	144:ef7eb2e8f9f7	1706	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1707	{
<>	144:ef7eb2e8f9f7	1708	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1709	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1710	}
<>	144:ef7eb2e8f9f7	1711	break;
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	default:
<>	144:ef7eb2e8f9f7	1714	break;
<>	144:ef7eb2e8f9f7	1715	}
<>	144:ef7eb2e8f9f7	1716	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1717	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1720	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1721
<>	144:ef7eb2e8f9f7	1722	/* Return function status */
<>	144:ef7eb2e8f9f7	1723	return HAL_OK;
<>	144:ef7eb2e8f9f7	1724	}
<>	144:ef7eb2e8f9f7	1725
<>	144:ef7eb2e8f9f7	1726	/**
<>	144:ef7eb2e8f9f7	1727	* @brief Stops the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1728	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1729	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1730	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1731	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1732	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1733	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1734	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1735	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1736	* @retval HAL status
<>	144:ef7eb2e8f9f7	1737	*/
<>	144:ef7eb2e8f9f7	1738	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1739	{
<>	144:ef7eb2e8f9f7	1740	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1741	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1742
<>	144:ef7eb2e8f9f7	1743	switch (Channel)
<>	144:ef7eb2e8f9f7	1744	{
<>	144:ef7eb2e8f9f7	1745	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1746	{
<>	144:ef7eb2e8f9f7	1747	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1748	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1749	}
<>	144:ef7eb2e8f9f7	1750	break;
<>	144:ef7eb2e8f9f7	1751
<>	144:ef7eb2e8f9f7	1752	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1753	{
<>	144:ef7eb2e8f9f7	1754	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1755	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1756	}
<>	144:ef7eb2e8f9f7	1757	break;
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1760	{
<>	144:ef7eb2e8f9f7	1761	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1762	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1763	}
<>	144:ef7eb2e8f9f7	1764	break;
<>	144:ef7eb2e8f9f7	1765
<>	144:ef7eb2e8f9f7	1766	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1767	{
<>	144:ef7eb2e8f9f7	1768	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1769	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1770	}
<>	144:ef7eb2e8f9f7	1771	break;
<>	144:ef7eb2e8f9f7	1772
<>	144:ef7eb2e8f9f7	1773	default:
<>	144:ef7eb2e8f9f7	1774	break;
<>	144:ef7eb2e8f9f7	1775	}
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1778	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1781	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	/* Return function status */
<>	144:ef7eb2e8f9f7	1784	return HAL_OK;
<>	144:ef7eb2e8f9f7	1785	}
<>	144:ef7eb2e8f9f7	1786
<>	144:ef7eb2e8f9f7	1787	/**
<>	144:ef7eb2e8f9f7	1788	* @brief Starts the TIM Input Capture measurement on in DMA mode.
<>	144:ef7eb2e8f9f7	1789	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1790	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1791	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	1792	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1793	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1794	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1795	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1796	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1797	* @param pData: The destination Buffer address.
<>	144:ef7eb2e8f9f7	1798	* @param Length: The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	1799	* @retval HAL status
<>	144:ef7eb2e8f9f7	1800	*/
<>	144:ef7eb2e8f9f7	1801	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1802	{
<>	144:ef7eb2e8f9f7	1803	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1804	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1805	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1806
<>	144:ef7eb2e8f9f7	1807	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1808	{
<>	144:ef7eb2e8f9f7	1809	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1810	}
<>	144:ef7eb2e8f9f7	1811	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1812	{
AnnaBridge	167:e84263d55307	1813	if((pData == 0U ) && (Length > 0))
<>	144:ef7eb2e8f9f7	1814	{
<>	144:ef7eb2e8f9f7	1815	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1816	}
<>	144:ef7eb2e8f9f7	1817	else
<>	144:ef7eb2e8f9f7	1818	{
<>	144:ef7eb2e8f9f7	1819	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1820	}
<>	144:ef7eb2e8f9f7	1821	}
<>	144:ef7eb2e8f9f7	1822
<>	144:ef7eb2e8f9f7	1823	switch (Channel)
<>	144:ef7eb2e8f9f7	1824	{
<>	144:ef7eb2e8f9f7	1825	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1826	{
<>	144:ef7eb2e8f9f7	1827	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1828	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1829
<>	144:ef7eb2e8f9f7	1830	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1831	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1832
<>	144:ef7eb2e8f9f7	1833	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1834	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1837	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1838	}
<>	144:ef7eb2e8f9f7	1839	break;
<>	144:ef7eb2e8f9f7	1840
<>	144:ef7eb2e8f9f7	1841	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1842	{
<>	144:ef7eb2e8f9f7	1843	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1844	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1845
<>	144:ef7eb2e8f9f7	1846	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1847	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1848
<>	144:ef7eb2e8f9f7	1849	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1850	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1851
<>	144:ef7eb2e8f9f7	1852	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1853	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1854	}
<>	144:ef7eb2e8f9f7	1855	break;
<>	144:ef7eb2e8f9f7	1856
<>	144:ef7eb2e8f9f7	1857	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1858	{
<>	144:ef7eb2e8f9f7	1859	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1860	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1861
<>	144:ef7eb2e8f9f7	1862	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1863	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1864
<>	144:ef7eb2e8f9f7	1865	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1866	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1867
<>	144:ef7eb2e8f9f7	1868	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1869	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1870	}
<>	144:ef7eb2e8f9f7	1871	break;
<>	144:ef7eb2e8f9f7	1872
<>	144:ef7eb2e8f9f7	1873	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1874	{
<>	144:ef7eb2e8f9f7	1875	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1876	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1877
<>	144:ef7eb2e8f9f7	1878	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1879	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1880
<>	144:ef7eb2e8f9f7	1881	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1882	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1883
<>	144:ef7eb2e8f9f7	1884	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1885	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1886	}
<>	144:ef7eb2e8f9f7	1887	break;
<>	144:ef7eb2e8f9f7	1888
<>	144:ef7eb2e8f9f7	1889	default:
<>	144:ef7eb2e8f9f7	1890	break;
<>	144:ef7eb2e8f9f7	1891	}
<>	144:ef7eb2e8f9f7	1892
<>	144:ef7eb2e8f9f7	1893	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1894	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1895
<>	144:ef7eb2e8f9f7	1896	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1897	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	/* Return function status */
<>	144:ef7eb2e8f9f7	1900	return HAL_OK;
<>	144:ef7eb2e8f9f7	1901	}
<>	144:ef7eb2e8f9f7	1902
<>	144:ef7eb2e8f9f7	1903	/**
<>	144:ef7eb2e8f9f7	1904	* @brief Stops the TIM Input Capture measurement on in DMA mode.
<>	144:ef7eb2e8f9f7	1905	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1906	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1907	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	1908	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1909	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1910	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1911	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1912	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1913	* @retval HAL status
<>	144:ef7eb2e8f9f7	1914	*/
<>	144:ef7eb2e8f9f7	1915	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1916	{
<>	144:ef7eb2e8f9f7	1917	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1918	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1919	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1920
<>	144:ef7eb2e8f9f7	1921	switch (Channel)
<>	144:ef7eb2e8f9f7	1922	{
<>	144:ef7eb2e8f9f7	1923	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1924	{
<>	144:ef7eb2e8f9f7	1925	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1926	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1927	}
<>	144:ef7eb2e8f9f7	1928	break;
<>	144:ef7eb2e8f9f7	1929
<>	144:ef7eb2e8f9f7	1930	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1931	{
<>	144:ef7eb2e8f9f7	1932	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1933	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1934	}
<>	144:ef7eb2e8f9f7	1935	break;
<>	144:ef7eb2e8f9f7	1936
<>	144:ef7eb2e8f9f7	1937	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1938	{
<>	144:ef7eb2e8f9f7	1939	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1940	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1941	}
<>	144:ef7eb2e8f9f7	1942	break;
<>	144:ef7eb2e8f9f7	1943
<>	144:ef7eb2e8f9f7	1944	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1945	{
<>	144:ef7eb2e8f9f7	1946	/* Disable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1947	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1948	}
<>	144:ef7eb2e8f9f7	1949	break;
<>	144:ef7eb2e8f9f7	1950
<>	144:ef7eb2e8f9f7	1951	default:
<>	144:ef7eb2e8f9f7	1952	break;
<>	144:ef7eb2e8f9f7	1953	}
<>	144:ef7eb2e8f9f7	1954
<>	144:ef7eb2e8f9f7	1955	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1956	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1957
<>	144:ef7eb2e8f9f7	1958	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1959	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1960
<>	144:ef7eb2e8f9f7	1961	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1962	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1963
<>	144:ef7eb2e8f9f7	1964	/* Return function status */
<>	144:ef7eb2e8f9f7	1965	return HAL_OK;
<>	144:ef7eb2e8f9f7	1966	}
<>	144:ef7eb2e8f9f7	1967	/**
<>	144:ef7eb2e8f9f7	1968	* @}
<>	144:ef7eb2e8f9f7	1969	*/
<>	144:ef7eb2e8f9f7	1970
<>	144:ef7eb2e8f9f7	1971	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<>	144:ef7eb2e8f9f7	1972	* @brief Time One Pulse functions
<>	144:ef7eb2e8f9f7	1973	*
<>	144:ef7eb2e8f9f7	1974	@verbatim
<>	144:ef7eb2e8f9f7	1975	==============================================================================
<>	144:ef7eb2e8f9f7	1976	##### Time One Pulse functions #####
<>	144:ef7eb2e8f9f7	1977	==============================================================================
<>	144:ef7eb2e8f9f7	1978	[..]
<>	144:ef7eb2e8f9f7	1979	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1980	(+) Initialize and configure the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1981	(+) De-initialize the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1982	(+) Start the Time One Pulse.
<>	144:ef7eb2e8f9f7	1983	(+) Stop the Time One Pulse.
<>	144:ef7eb2e8f9f7	1984	(+) Start the Time One Pulse and enable interrupt.
<>	144:ef7eb2e8f9f7	1985	(+) Stop the Time One Pulse and disable interrupt.
<>	144:ef7eb2e8f9f7	1986	(+) Start the Time One Pulse and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1987	(+) Stop the Time One Pulse and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1988
<>	144:ef7eb2e8f9f7	1989	@endverbatim
<>	144:ef7eb2e8f9f7	1990	* @{
<>	144:ef7eb2e8f9f7	1991	*/
<>	144:ef7eb2e8f9f7	1992	/**
<>	144:ef7eb2e8f9f7	1993	* @brief Initializes the TIM One Pulse Time Base according to the specified
<>	144:ef7eb2e8f9f7	1994	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1995	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1996	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	1997	* @param OnePulseMode: Select the One pulse mode.
<>	144:ef7eb2e8f9f7	1998	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1999	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<>	144:ef7eb2e8f9f7	2000	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
<>	144:ef7eb2e8f9f7	2001	* @retval HAL status
<>	144:ef7eb2e8f9f7	2002	*/
<>	144:ef7eb2e8f9f7	2003	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<>	144:ef7eb2e8f9f7	2004	{
<>	144:ef7eb2e8f9f7	2005	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	2006	if(htim == NULL)
<>	144:ef7eb2e8f9f7	2007	{
<>	144:ef7eb2e8f9f7	2008	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2009	}
<>	144:ef7eb2e8f9f7	2010
<>	144:ef7eb2e8f9f7	2011	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2012	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2013	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	2014	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	167:e84263d55307	2015	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	2016	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<>	144:ef7eb2e8f9f7	2017
<>	144:ef7eb2e8f9f7	2018	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	2019	{
<>	144:ef7eb2e8f9f7	2020	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	2021	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	2022	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	2023	HAL_TIM_OnePulse_MspInit(htim);
<>	144:ef7eb2e8f9f7	2024	}
<>	144:ef7eb2e8f9f7	2025
<>	144:ef7eb2e8f9f7	2026	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	2027	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2028
<>	144:ef7eb2e8f9f7	2029	/* Configure the Time base in the One Pulse Mode */
<>	144:ef7eb2e8f9f7	2030	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	2031
<>	144:ef7eb2e8f9f7	2032	/* Reset the OPM Bit */
<>	144:ef7eb2e8f9f7	2033	htim->Instance->CR1 &= ~TIM_CR1_OPM;
<>	144:ef7eb2e8f9f7	2034
<>	144:ef7eb2e8f9f7	2035	/* Configure the OPM Mode */
<>	144:ef7eb2e8f9f7	2036	htim->Instance->CR1 \|= OnePulseMode;
<>	144:ef7eb2e8f9f7	2037
<>	144:ef7eb2e8f9f7	2038	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	2039	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2040
<>	144:ef7eb2e8f9f7	2041	return HAL_OK;
<>	144:ef7eb2e8f9f7	2042	}
<>	144:ef7eb2e8f9f7	2043
<>	144:ef7eb2e8f9f7	2044	/**
<>	144:ef7eb2e8f9f7	2045	* @brief DeInitializes the TIM One Pulse
<>	144:ef7eb2e8f9f7	2046	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2047	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2048	* @retval HAL status
<>	144:ef7eb2e8f9f7	2049	*/
<>	144:ef7eb2e8f9f7	2050	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2051	{
<>	144:ef7eb2e8f9f7	2052	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2053	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2054
<>	144:ef7eb2e8f9f7	2055	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2056
<>	144:ef7eb2e8f9f7	2057	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	2058	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2059
<>	144:ef7eb2e8f9f7	2060	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	2061	HAL_TIM_OnePulse_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	2062
<>	144:ef7eb2e8f9f7	2063	/* Change TIM state */
<>	144:ef7eb2e8f9f7	2064	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	2065
<>	144:ef7eb2e8f9f7	2066	/* Release Lock */
<>	144:ef7eb2e8f9f7	2067	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2068
<>	144:ef7eb2e8f9f7	2069	return HAL_OK;
<>	144:ef7eb2e8f9f7	2070	}
<>	144:ef7eb2e8f9f7	2071
<>	144:ef7eb2e8f9f7	2072	/**
<>	144:ef7eb2e8f9f7	2073	* @brief Initializes the TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	2074	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2075	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2076	* @retval None
<>	144:ef7eb2e8f9f7	2077	*/
<>	144:ef7eb2e8f9f7	2078	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2079	{
<>	144:ef7eb2e8f9f7	2080	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2081	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2082	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2083	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2084	*/
<>	144:ef7eb2e8f9f7	2085	}
<>	144:ef7eb2e8f9f7	2086
<>	144:ef7eb2e8f9f7	2087	/**
<>	144:ef7eb2e8f9f7	2088	* @brief DeInitializes TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	2089	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2090	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2091	* @retval None
<>	144:ef7eb2e8f9f7	2092	*/
<>	144:ef7eb2e8f9f7	2093	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2094	{
<>	144:ef7eb2e8f9f7	2095	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2096	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2097	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2098	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2099	*/
<>	144:ef7eb2e8f9f7	2100	}
<>	144:ef7eb2e8f9f7	2101
<>	144:ef7eb2e8f9f7	2102	/**
<>	144:ef7eb2e8f9f7	2103	* @brief Starts the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2104	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2105	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2106	* @param OutputChannel : TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2107	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2108	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2109	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2110	* @retval HAL status
<>	144:ef7eb2e8f9f7	2111	*/
<>	144:ef7eb2e8f9f7	2112	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2113	{
<>	144:ef7eb2e8f9f7	2114	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2115	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2116	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2117	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2118	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2119
<>	144:ef7eb2e8f9f7	2120	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2121	(the counter starts in response to a stimulus and generate a pulse */
<>	144:ef7eb2e8f9f7	2122
AnnaBridge	167:e84263d55307	2123	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	2124	UNUSED(OutputChannel);
AnnaBridge	167:e84263d55307	2125
<>	144:ef7eb2e8f9f7	2126	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2127	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2128
<>	144:ef7eb2e8f9f7	2129	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2130	{
<>	144:ef7eb2e8f9f7	2131	/* Enable the main output */
<>	144:ef7eb2e8f9f7	2132	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2133	}
<>	144:ef7eb2e8f9f7	2134
<>	144:ef7eb2e8f9f7	2135	/* Return function status */
<>	144:ef7eb2e8f9f7	2136	return HAL_OK;
<>	144:ef7eb2e8f9f7	2137	}
<>	144:ef7eb2e8f9f7	2138
<>	144:ef7eb2e8f9f7	2139	/**
<>	144:ef7eb2e8f9f7	2140	* @brief Stops the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2141	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2142	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2143	* @param OutputChannel : TIM Channels to be disable.
<>	144:ef7eb2e8f9f7	2144	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2145	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2146	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2147	* @retval HAL status
<>	144:ef7eb2e8f9f7	2148	*/
<>	144:ef7eb2e8f9f7	2149	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2150	{
<>	144:ef7eb2e8f9f7	2151	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2152	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2153	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2154	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2155	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
AnnaBridge	167:e84263d55307	2156
AnnaBridge	167:e84263d55307	2157	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	2158	UNUSED(OutputChannel);
AnnaBridge	167:e84263d55307	2159
<>	144:ef7eb2e8f9f7	2160	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2161	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2162
<>	144:ef7eb2e8f9f7	2163	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2164	{
<>	144:ef7eb2e8f9f7	2165	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	2166	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2167	}
<>	144:ef7eb2e8f9f7	2168
<>	144:ef7eb2e8f9f7	2169	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2170	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2171
<>	144:ef7eb2e8f9f7	2172	/* Return function status */
<>	144:ef7eb2e8f9f7	2173	return HAL_OK;
<>	144:ef7eb2e8f9f7	2174	}
<>	144:ef7eb2e8f9f7	2175
<>	144:ef7eb2e8f9f7	2176	/**
<>	144:ef7eb2e8f9f7	2177	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2178	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2179	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2180	* @param OutputChannel : TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2181	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2182	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2183	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2184	* @retval HAL status
<>	144:ef7eb2e8f9f7	2185	*/
<>	144:ef7eb2e8f9f7	2186	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2187	{
<>	144:ef7eb2e8f9f7	2188	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2189	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2190	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2191	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2192	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2193
<>	144:ef7eb2e8f9f7	2194	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2195	(the counter starts in response to a stimulus and generate a pulse */
AnnaBridge	167:e84263d55307	2196
AnnaBridge	167:e84263d55307	2197	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	2198	UNUSED(OutputChannel);
AnnaBridge	167:e84263d55307	2199
<>	144:ef7eb2e8f9f7	2200	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2201	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2202
<>	144:ef7eb2e8f9f7	2203	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2204	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2205
<>	144:ef7eb2e8f9f7	2206	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2207	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2208
<>	144:ef7eb2e8f9f7	2209	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2210	{
<>	144:ef7eb2e8f9f7	2211	/* Enable the main output */
<>	144:ef7eb2e8f9f7	2212	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2213	}
<>	144:ef7eb2e8f9f7	2214
<>	144:ef7eb2e8f9f7	2215	/* Return function status */
<>	144:ef7eb2e8f9f7	2216	return HAL_OK;
<>	144:ef7eb2e8f9f7	2217	}
<>	144:ef7eb2e8f9f7	2218
<>	144:ef7eb2e8f9f7	2219	/**
<>	144:ef7eb2e8f9f7	2220	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2221	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2222	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2223	* @param OutputChannel : TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2224	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2225	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2226	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2227	* @retval HAL status
<>	144:ef7eb2e8f9f7	2228	*/
<>	144:ef7eb2e8f9f7	2229	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2230	{
AnnaBridge	167:e84263d55307	2231	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	2232	UNUSED(OutputChannel);
AnnaBridge	167:e84263d55307	2233
<>	144:ef7eb2e8f9f7	2234	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2235	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2236
<>	144:ef7eb2e8f9f7	2237	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2238	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2239
<>	144:ef7eb2e8f9f7	2240	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2241	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2242	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2243	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2244	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	144:ef7eb2e8f9f7	2245	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2246	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2247
<>	144:ef7eb2e8f9f7	2248	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2249	{
<>	144:ef7eb2e8f9f7	2250	/* Disable the Main Output */
<>	144:ef7eb2e8f9f7	2251	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2252	}
<>	144:ef7eb2e8f9f7	2253
<>	144:ef7eb2e8f9f7	2254	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2255	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2256
<>	144:ef7eb2e8f9f7	2257	/* Return function status */
<>	144:ef7eb2e8f9f7	2258	return HAL_OK;
<>	144:ef7eb2e8f9f7	2259	}
<>	144:ef7eb2e8f9f7	2260	/**
<>	144:ef7eb2e8f9f7	2261	* @}
<>	144:ef7eb2e8f9f7	2262	*/
<>	144:ef7eb2e8f9f7	2263
<>	144:ef7eb2e8f9f7	2264	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<>	144:ef7eb2e8f9f7	2265	* @brief Time Encoder functions
<>	144:ef7eb2e8f9f7	2266	*
<>	144:ef7eb2e8f9f7	2267	@verbatim
<>	144:ef7eb2e8f9f7	2268	==============================================================================
<>	144:ef7eb2e8f9f7	2269	##### Time Encoder functions #####
<>	144:ef7eb2e8f9f7	2270	==============================================================================
<>	144:ef7eb2e8f9f7	2271	[..]
<>	144:ef7eb2e8f9f7	2272	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2273	(+) Initialize and configure the TIM Encoder.
<>	144:ef7eb2e8f9f7	2274	(+) De-initialize the TIM Encoder.
<>	144:ef7eb2e8f9f7	2275	(+) Start the Time Encoder.
<>	144:ef7eb2e8f9f7	2276	(+) Stop the Time Encoder.
<>	144:ef7eb2e8f9f7	2277	(+) Start the Time Encoder and enable interrupt.
<>	144:ef7eb2e8f9f7	2278	(+) Stop the Time Encoder and disable interrupt.
<>	144:ef7eb2e8f9f7	2279	(+) Start the Time Encoder and enable DMA transfer.
<>	144:ef7eb2e8f9f7	2280	(+) Stop the Time Encoder and disable DMA transfer.
<>	144:ef7eb2e8f9f7	2281
<>	144:ef7eb2e8f9f7	2282	@endverbatim
<>	144:ef7eb2e8f9f7	2283	* @{
<>	144:ef7eb2e8f9f7	2284	*/
<>	144:ef7eb2e8f9f7	2285	/**
<>	144:ef7eb2e8f9f7	2286	* @brief Initializes the TIM Encoder Interface and create the associated handle.
<>	144:ef7eb2e8f9f7	2287	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2288	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2289	* @param sConfig: TIM Encoder Interface configuration structure
<>	144:ef7eb2e8f9f7	2290	* @retval HAL status
<>	144:ef7eb2e8f9f7	2291	*/
<>	144:ef7eb2e8f9f7	2292	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
<>	144:ef7eb2e8f9f7	2293	{
<>	144:ef7eb2e8f9f7	2294	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	2295	uint32_t tmpccmr1 = 0U;
<>	144:ef7eb2e8f9f7	2296	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	2297
<>	144:ef7eb2e8f9f7	2298	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	2299	if(htim == NULL)
<>	144:ef7eb2e8f9f7	2300	{
<>	144:ef7eb2e8f9f7	2301	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2302	}
<>	144:ef7eb2e8f9f7	2303
<>	144:ef7eb2e8f9f7	2304	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2305	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
AnnaBridge	167:e84263d55307	2306	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
AnnaBridge	167:e84263d55307	2307	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	167:e84263d55307	2308	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	2309	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<>	144:ef7eb2e8f9f7	2310	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<>	144:ef7eb2e8f9f7	2311	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<>	144:ef7eb2e8f9f7	2312	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<>	144:ef7eb2e8f9f7	2313	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<>	144:ef7eb2e8f9f7	2314	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<>	144:ef7eb2e8f9f7	2315	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<>	144:ef7eb2e8f9f7	2316	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<>	144:ef7eb2e8f9f7	2317	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<>	144:ef7eb2e8f9f7	2318
<>	144:ef7eb2e8f9f7	2319	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	2320	{
<>	144:ef7eb2e8f9f7	2321	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	2322	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	2323	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	2324	HAL_TIM_Encoder_MspInit(htim);
<>	144:ef7eb2e8f9f7	2325	}
<>	144:ef7eb2e8f9f7	2326
<>	144:ef7eb2e8f9f7	2327	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	2328	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2329
<>	144:ef7eb2e8f9f7	2330	/* Reset the SMS bits */
<>	144:ef7eb2e8f9f7	2331	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	2332
<>	144:ef7eb2e8f9f7	2333	/* Configure the Time base in the Encoder Mode */
<>	144:ef7eb2e8f9f7	2334	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	2335
<>	144:ef7eb2e8f9f7	2336	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	2337	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	2338
<>	144:ef7eb2e8f9f7	2339	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	2340	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	2341
<>	144:ef7eb2e8f9f7	2342	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	2343	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	2344
<>	144:ef7eb2e8f9f7	2345	/* Set the encoder Mode */
<>	144:ef7eb2e8f9f7	2346	tmpsmcr \|= sConfig->EncoderMode;
<>	144:ef7eb2e8f9f7	2347
<>	144:ef7eb2e8f9f7	2348	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
<>	144:ef7eb2e8f9f7	2349	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
<>	144:ef7eb2e8f9f7	2350	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8U));
<>	144:ef7eb2e8f9f7	2351
<>	144:ef7eb2e8f9f7	2352	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<>	144:ef7eb2e8f9f7	2353	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
<>	144:ef7eb2e8f9f7	2354	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
<>	144:ef7eb2e8f9f7	2355	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8U);
<>	144:ef7eb2e8f9f7	2356	tmpccmr1 \|= (sConfig->IC1Filter << 4U) \| (sConfig->IC2Filter << 12U);
<>	144:ef7eb2e8f9f7	2357
<>	144:ef7eb2e8f9f7	2358	/* Set the TI1 and the TI2 Polarities */
<>	144:ef7eb2e8f9f7	2359	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
<>	144:ef7eb2e8f9f7	2360	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
<>	144:ef7eb2e8f9f7	2361	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4U);
<>	144:ef7eb2e8f9f7	2362
<>	144:ef7eb2e8f9f7	2363	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	2364	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	2367	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	2368
<>	144:ef7eb2e8f9f7	2369	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	2370	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	2371
<>	144:ef7eb2e8f9f7	2372	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	2373	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2374
<>	144:ef7eb2e8f9f7	2375	return HAL_OK;
<>	144:ef7eb2e8f9f7	2376	}
<>	144:ef7eb2e8f9f7	2377
<>	144:ef7eb2e8f9f7	2378	/**
<>	144:ef7eb2e8f9f7	2379	* @brief DeInitializes the TIM Encoder interface
<>	144:ef7eb2e8f9f7	2380	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2381	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2382	* @retval HAL status
<>	144:ef7eb2e8f9f7	2383	*/
<>	144:ef7eb2e8f9f7	2384	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2385	{
<>	144:ef7eb2e8f9f7	2386	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2387	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2388
<>	144:ef7eb2e8f9f7	2389	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2390
<>	144:ef7eb2e8f9f7	2391	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	2392	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2393
<>	144:ef7eb2e8f9f7	2394	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	2395	HAL_TIM_Encoder_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	2396
<>	144:ef7eb2e8f9f7	2397	/* Change TIM state */
<>	144:ef7eb2e8f9f7	2398	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	2399
<>	144:ef7eb2e8f9f7	2400	/* Release Lock */
<>	144:ef7eb2e8f9f7	2401	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2402
<>	144:ef7eb2e8f9f7	2403	return HAL_OK;
<>	144:ef7eb2e8f9f7	2404	}
<>	144:ef7eb2e8f9f7	2405
<>	144:ef7eb2e8f9f7	2406	/**
<>	144:ef7eb2e8f9f7	2407	* @brief Initializes the TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2408	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2409	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2410	* @retval None
<>	144:ef7eb2e8f9f7	2411	*/
<>	144:ef7eb2e8f9f7	2412	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2413	{
<>	144:ef7eb2e8f9f7	2414	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2415	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2416	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2417	the HAL_TIM_Encoder_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2418	*/
<>	144:ef7eb2e8f9f7	2419	}
<>	144:ef7eb2e8f9f7	2420
<>	144:ef7eb2e8f9f7	2421	/**
<>	144:ef7eb2e8f9f7	2422	* @brief DeInitializes TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2423	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2424	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2425	* @retval None
<>	144:ef7eb2e8f9f7	2426	*/
<>	144:ef7eb2e8f9f7	2427	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2428	{
<>	144:ef7eb2e8f9f7	2429	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2430	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2431	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2432	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2433	*/
<>	144:ef7eb2e8f9f7	2434	}
<>	144:ef7eb2e8f9f7	2435
<>	144:ef7eb2e8f9f7	2436	/**
<>	144:ef7eb2e8f9f7	2437	* @brief Starts the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2438	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2439	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2440	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2441	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2442	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2443	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2444	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2445	* @retval HAL status
<>	144:ef7eb2e8f9f7	2446	*/
<>	144:ef7eb2e8f9f7	2447	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2448	{
<>	144:ef7eb2e8f9f7	2449	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2450	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2451
<>	144:ef7eb2e8f9f7	2452	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2453	switch (Channel)
<>	144:ef7eb2e8f9f7	2454	{
<>	144:ef7eb2e8f9f7	2455	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2456	{
<>	144:ef7eb2e8f9f7	2457	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2458	break;
<>	144:ef7eb2e8f9f7	2459	}
<>	144:ef7eb2e8f9f7	2460	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2461	{
<>	144:ef7eb2e8f9f7	2462	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2463	break;
<>	144:ef7eb2e8f9f7	2464	}
<>	144:ef7eb2e8f9f7	2465	default :
<>	144:ef7eb2e8f9f7	2466	{
<>	144:ef7eb2e8f9f7	2467	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2468	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2469	break;
<>	144:ef7eb2e8f9f7	2470	}
<>	144:ef7eb2e8f9f7	2471	}
<>	144:ef7eb2e8f9f7	2472	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2473	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2474
<>	144:ef7eb2e8f9f7	2475	/* Return function status */
<>	144:ef7eb2e8f9f7	2476	return HAL_OK;
<>	144:ef7eb2e8f9f7	2477	}
<>	144:ef7eb2e8f9f7	2478
<>	144:ef7eb2e8f9f7	2479	/**
<>	144:ef7eb2e8f9f7	2480	* @brief Stops the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2481	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2482	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2483	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	2484	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2485	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2486	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2487	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2488	* @retval HAL status
<>	144:ef7eb2e8f9f7	2489	*/
<>	144:ef7eb2e8f9f7	2490	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2491	{
<>	144:ef7eb2e8f9f7	2492	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2493	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2494
<>	144:ef7eb2e8f9f7	2495	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2496	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2497	switch (Channel)
<>	144:ef7eb2e8f9f7	2498	{
<>	144:ef7eb2e8f9f7	2499	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2500	{
<>	144:ef7eb2e8f9f7	2501	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2502	break;
<>	144:ef7eb2e8f9f7	2503	}
<>	144:ef7eb2e8f9f7	2504	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2505	{
<>	144:ef7eb2e8f9f7	2506	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2507	break;
<>	144:ef7eb2e8f9f7	2508	}
<>	144:ef7eb2e8f9f7	2509	default :
<>	144:ef7eb2e8f9f7	2510	{
<>	144:ef7eb2e8f9f7	2511	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2512	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2513	break;
<>	144:ef7eb2e8f9f7	2514	}
<>	144:ef7eb2e8f9f7	2515	}
<>	144:ef7eb2e8f9f7	2516	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2517	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2518
<>	144:ef7eb2e8f9f7	2519	/* Return function status */
<>	144:ef7eb2e8f9f7	2520	return HAL_OK;
<>	144:ef7eb2e8f9f7	2521	}
<>	144:ef7eb2e8f9f7	2522
<>	144:ef7eb2e8f9f7	2523	/**
<>	144:ef7eb2e8f9f7	2524	* @brief Starts the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2525	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2526	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2527	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2528	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2529	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2530	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2531	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2532	* @retval HAL status
<>	144:ef7eb2e8f9f7	2533	*/
<>	144:ef7eb2e8f9f7	2534	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2535	{
<>	144:ef7eb2e8f9f7	2536	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2537	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2538
<>	144:ef7eb2e8f9f7	2539	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2540	/* Enable the capture compare Interrupts 1 and/or 2 */
<>	144:ef7eb2e8f9f7	2541	switch (Channel)
<>	144:ef7eb2e8f9f7	2542	{
<>	144:ef7eb2e8f9f7	2543	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2544	{
<>	144:ef7eb2e8f9f7	2545	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2546	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2547	break;
<>	144:ef7eb2e8f9f7	2548	}
<>	144:ef7eb2e8f9f7	2549	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2550	{
<>	144:ef7eb2e8f9f7	2551	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2552	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2553	break;
<>	144:ef7eb2e8f9f7	2554	}
<>	144:ef7eb2e8f9f7	2555	default :
<>	144:ef7eb2e8f9f7	2556	{
<>	144:ef7eb2e8f9f7	2557	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2558	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2559	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2560	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2561	break;
<>	144:ef7eb2e8f9f7	2562	}
<>	144:ef7eb2e8f9f7	2563	}
<>	144:ef7eb2e8f9f7	2564
<>	144:ef7eb2e8f9f7	2565	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2566	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2567
<>	144:ef7eb2e8f9f7	2568	/* Return function status */
<>	144:ef7eb2e8f9f7	2569	return HAL_OK;
<>	144:ef7eb2e8f9f7	2570	}
<>	144:ef7eb2e8f9f7	2571
<>	144:ef7eb2e8f9f7	2572	/**
<>	144:ef7eb2e8f9f7	2573	* @brief Stops the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2574	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2575	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2576	* @param Channel: TIM Channels to be disabled.
<>	144:ef7eb2e8f9f7	2577	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2578	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2579	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2580	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2581	* @retval HAL status
<>	144:ef7eb2e8f9f7	2582	*/
<>	144:ef7eb2e8f9f7	2583	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2584	{
<>	144:ef7eb2e8f9f7	2585	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2586	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2587
<>	144:ef7eb2e8f9f7	2588	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2589	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2590	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2591	{
<>	144:ef7eb2e8f9f7	2592	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2593
<>	144:ef7eb2e8f9f7	2594	/* Disable the capture compare Interrupts 1 */
<>	144:ef7eb2e8f9f7	2595	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2596	}
<>	144:ef7eb2e8f9f7	2597	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2598	{
<>	144:ef7eb2e8f9f7	2599	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2600
<>	144:ef7eb2e8f9f7	2601	/* Disable the capture compare Interrupts 2 */
<>	144:ef7eb2e8f9f7	2602	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2603	}
<>	144:ef7eb2e8f9f7	2604	else
<>	144:ef7eb2e8f9f7	2605	{
<>	144:ef7eb2e8f9f7	2606	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2607	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2608
<>	144:ef7eb2e8f9f7	2609	/* Disable the capture compare Interrupts 1 and 2 */
<>	144:ef7eb2e8f9f7	2610	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2611	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2612	}
<>	144:ef7eb2e8f9f7	2613
<>	144:ef7eb2e8f9f7	2614	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2615	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2616
<>	144:ef7eb2e8f9f7	2617	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2618	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2619
<>	144:ef7eb2e8f9f7	2620	/* Return function status */
<>	144:ef7eb2e8f9f7	2621	return HAL_OK;
<>	144:ef7eb2e8f9f7	2622	}
<>	144:ef7eb2e8f9f7	2623
<>	144:ef7eb2e8f9f7	2624	/**
<>	144:ef7eb2e8f9f7	2625	* @brief Starts the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2626	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2627	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2628	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2629	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2630	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2631	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2632	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2633	* @param pData1: The destination Buffer address for IC1.
<>	144:ef7eb2e8f9f7	2634	* @param pData2: The destination Buffer address for IC2.
<>	144:ef7eb2e8f9f7	2635	* @param Length: The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	2636	* @retval HAL status
<>	144:ef7eb2e8f9f7	2637	*/
<>	144:ef7eb2e8f9f7	2638	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
<>	144:ef7eb2e8f9f7	2639	{
<>	144:ef7eb2e8f9f7	2640	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2641	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2642
<>	144:ef7eb2e8f9f7	2643	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	2644	{
<>	144:ef7eb2e8f9f7	2645	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2646	}
<>	144:ef7eb2e8f9f7	2647	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	2648	{
AnnaBridge	167:e84263d55307	2649	if((((pData1 == 0U) \|\| (pData2 == 0U) )) && (Length > 0))
<>	144:ef7eb2e8f9f7	2650	{
<>	144:ef7eb2e8f9f7	2651	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2652	}
<>	144:ef7eb2e8f9f7	2653	else
<>	144:ef7eb2e8f9f7	2654	{
<>	144:ef7eb2e8f9f7	2655	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2656	}
<>	144:ef7eb2e8f9f7	2657	}
<>	144:ef7eb2e8f9f7	2658
<>	144:ef7eb2e8f9f7	2659	switch (Channel)
<>	144:ef7eb2e8f9f7	2660	{
<>	144:ef7eb2e8f9f7	2661	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2662	{
<>	144:ef7eb2e8f9f7	2663	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2664	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2665
<>	144:ef7eb2e8f9f7	2666	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2667	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2668
<>	144:ef7eb2e8f9f7	2669	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2670	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<>	144:ef7eb2e8f9f7	2671
<>	144:ef7eb2e8f9f7	2672	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2673	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2674
<>	144:ef7eb2e8f9f7	2675	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2676	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2677
<>	144:ef7eb2e8f9f7	2678	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2679	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2680	}
<>	144:ef7eb2e8f9f7	2681	break;
<>	144:ef7eb2e8f9f7	2682
<>	144:ef7eb2e8f9f7	2683	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2684	{
<>	144:ef7eb2e8f9f7	2685	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2686	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2687
<>	144:ef7eb2e8f9f7	2688	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2689	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<>	144:ef7eb2e8f9f7	2690	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2691	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2692
<>	144:ef7eb2e8f9f7	2693	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2694	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2695
<>	144:ef7eb2e8f9f7	2696	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2697	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2698
<>	144:ef7eb2e8f9f7	2699	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2700	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2701	}
<>	144:ef7eb2e8f9f7	2702	break;
<>	144:ef7eb2e8f9f7	2703
<>	144:ef7eb2e8f9f7	2704	case TIM_CHANNEL_ALL:
<>	144:ef7eb2e8f9f7	2705	{
<>	144:ef7eb2e8f9f7	2706	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2707	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2708
<>	144:ef7eb2e8f9f7	2709	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2710	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2711
<>	144:ef7eb2e8f9f7	2712	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2713	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<>	144:ef7eb2e8f9f7	2714
<>	144:ef7eb2e8f9f7	2715	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2716	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2717
<>	144:ef7eb2e8f9f7	2718	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2719	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2720
<>	144:ef7eb2e8f9f7	2721	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2722	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2723
<>	144:ef7eb2e8f9f7	2724	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2725	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2726
<>	144:ef7eb2e8f9f7	2727	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2728	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2729	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2730
<>	144:ef7eb2e8f9f7	2731	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2732	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2733	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2734	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2735	}
<>	144:ef7eb2e8f9f7	2736	break;
<>	144:ef7eb2e8f9f7	2737
<>	144:ef7eb2e8f9f7	2738	default:
<>	144:ef7eb2e8f9f7	2739	break;
<>	144:ef7eb2e8f9f7	2740	}
<>	144:ef7eb2e8f9f7	2741	/* Return function status */
<>	144:ef7eb2e8f9f7	2742	return HAL_OK;
<>	144:ef7eb2e8f9f7	2743	}
<>	144:ef7eb2e8f9f7	2744
<>	144:ef7eb2e8f9f7	2745	/**
<>	144:ef7eb2e8f9f7	2746	* @brief Stops the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2747	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2748	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2749	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2750	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2751	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2752	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2753	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2754	* @retval HAL status
<>	144:ef7eb2e8f9f7	2755	*/
<>	144:ef7eb2e8f9f7	2756	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2757	{
<>	144:ef7eb2e8f9f7	2758	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2759	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2760
<>	144:ef7eb2e8f9f7	2761	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2762	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2763	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2764	{
<>	144:ef7eb2e8f9f7	2765	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2766
<>	144:ef7eb2e8f9f7	2767	/* Disable the capture compare DMA Request 1 */
<>	144:ef7eb2e8f9f7	2768	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2769	}
<>	144:ef7eb2e8f9f7	2770	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2771	{
<>	144:ef7eb2e8f9f7	2772	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2773
<>	144:ef7eb2e8f9f7	2774	/* Disable the capture compare DMA Request 2 */
<>	144:ef7eb2e8f9f7	2775	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2776	}
<>	144:ef7eb2e8f9f7	2777	else
<>	144:ef7eb2e8f9f7	2778	{
<>	144:ef7eb2e8f9f7	2779	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2780	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2781
<>	144:ef7eb2e8f9f7	2782	/* Disable the capture compare DMA Request 1 and 2 */
<>	144:ef7eb2e8f9f7	2783	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2784	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2785	}
<>	144:ef7eb2e8f9f7	2786
<>	144:ef7eb2e8f9f7	2787	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2788	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2789
<>	144:ef7eb2e8f9f7	2790	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2791	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2792
<>	144:ef7eb2e8f9f7	2793	/* Return function status */
<>	144:ef7eb2e8f9f7	2794	return HAL_OK;
<>	144:ef7eb2e8f9f7	2795	}
<>	144:ef7eb2e8f9f7	2796	/**
<>	144:ef7eb2e8f9f7	2797	* @}
<>	144:ef7eb2e8f9f7	2798	*/
<>	144:ef7eb2e8f9f7	2799
<>	144:ef7eb2e8f9f7	2800	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<>	144:ef7eb2e8f9f7	2801	* @brief IRQ handler management
<>	144:ef7eb2e8f9f7	2802	*
<>	144:ef7eb2e8f9f7	2803	@verbatim
<>	144:ef7eb2e8f9f7	2804	==============================================================================
<>	144:ef7eb2e8f9f7	2805	##### IRQ handler management #####
<>	144:ef7eb2e8f9f7	2806	==============================================================================
<>	144:ef7eb2e8f9f7	2807	[..]
<>	144:ef7eb2e8f9f7	2808	This section provides Timer IRQ handler function.
<>	144:ef7eb2e8f9f7	2809
<>	144:ef7eb2e8f9f7	2810	@endverbatim
<>	144:ef7eb2e8f9f7	2811	* @{
<>	144:ef7eb2e8f9f7	2812	*/
<>	144:ef7eb2e8f9f7	2813	/**
<>	144:ef7eb2e8f9f7	2814	* @brief This function handles TIM interrupts requests.
<>	144:ef7eb2e8f9f7	2815	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2816	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2817	* @retval None
<>	144:ef7eb2e8f9f7	2818	*/
<>	144:ef7eb2e8f9f7	2819	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2820	{
<>	144:ef7eb2e8f9f7	2821	/* Capture compare 1 event */
<>	144:ef7eb2e8f9f7	2822	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<>	144:ef7eb2e8f9f7	2823	{
<>	144:ef7eb2e8f9f7	2824	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<>	144:ef7eb2e8f9f7	2825	{
<>	144:ef7eb2e8f9f7	2826	{
<>	144:ef7eb2e8f9f7	2827	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2828	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	2829
<>	144:ef7eb2e8f9f7	2830	/* Input capture event */
<>	144:ef7eb2e8f9f7	2831	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
<>	144:ef7eb2e8f9f7	2832	{
<>	144:ef7eb2e8f9f7	2833	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2834	}
<>	144:ef7eb2e8f9f7	2835	/* Output compare event */
<>	144:ef7eb2e8f9f7	2836	else
<>	144:ef7eb2e8f9f7	2837	{
<>	144:ef7eb2e8f9f7	2838	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2839	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2840	}
<>	144:ef7eb2e8f9f7	2841	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2842	}
<>	144:ef7eb2e8f9f7	2843	}
<>	144:ef7eb2e8f9f7	2844	}
<>	144:ef7eb2e8f9f7	2845	/* Capture compare 2 event */
<>	144:ef7eb2e8f9f7	2846	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<>	144:ef7eb2e8f9f7	2847	{
<>	144:ef7eb2e8f9f7	2848	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<>	144:ef7eb2e8f9f7	2849	{
<>	144:ef7eb2e8f9f7	2850	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2851	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	2852	/* Input capture event */
<>	144:ef7eb2e8f9f7	2853	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
<>	144:ef7eb2e8f9f7	2854	{
<>	144:ef7eb2e8f9f7	2855	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2856	}
<>	144:ef7eb2e8f9f7	2857	/* Output compare event */
<>	144:ef7eb2e8f9f7	2858	else
<>	144:ef7eb2e8f9f7	2859	{
<>	144:ef7eb2e8f9f7	2860	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2861	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2862	}
<>	144:ef7eb2e8f9f7	2863	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2864	}
<>	144:ef7eb2e8f9f7	2865	}
<>	144:ef7eb2e8f9f7	2866	/* Capture compare 3 event */
<>	144:ef7eb2e8f9f7	2867	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<>	144:ef7eb2e8f9f7	2868	{
<>	144:ef7eb2e8f9f7	2869	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<>	144:ef7eb2e8f9f7	2870	{
<>	144:ef7eb2e8f9f7	2871	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	2872	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	2873	/* Input capture event */
<>	144:ef7eb2e8f9f7	2874	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
<>	144:ef7eb2e8f9f7	2875	{
<>	144:ef7eb2e8f9f7	2876	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2877	}
<>	144:ef7eb2e8f9f7	2878	/* Output compare event */
<>	144:ef7eb2e8f9f7	2879	else
<>	144:ef7eb2e8f9f7	2880	{
<>	144:ef7eb2e8f9f7	2881	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2882	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2883	}
<>	144:ef7eb2e8f9f7	2884	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2885	}
<>	144:ef7eb2e8f9f7	2886	}
<>	144:ef7eb2e8f9f7	2887	/* Capture compare 4 event */
<>	144:ef7eb2e8f9f7	2888	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<>	144:ef7eb2e8f9f7	2889	{
<>	144:ef7eb2e8f9f7	2890	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<>	144:ef7eb2e8f9f7	2891	{
<>	144:ef7eb2e8f9f7	2892	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	2893	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	2894	/* Input capture event */
<>	144:ef7eb2e8f9f7	2895	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
<>	144:ef7eb2e8f9f7	2896	{
<>	144:ef7eb2e8f9f7	2897	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2898	}
<>	144:ef7eb2e8f9f7	2899	/* Output compare event */
<>	144:ef7eb2e8f9f7	2900	else
<>	144:ef7eb2e8f9f7	2901	{
<>	144:ef7eb2e8f9f7	2902	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2903	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2904	}
<>	144:ef7eb2e8f9f7	2905	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2906	}
<>	144:ef7eb2e8f9f7	2907	}
<>	144:ef7eb2e8f9f7	2908	/* TIM Update event */
<>	144:ef7eb2e8f9f7	2909	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<>	144:ef7eb2e8f9f7	2910	{
<>	144:ef7eb2e8f9f7	2911	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<>	144:ef7eb2e8f9f7	2912	{
<>	144:ef7eb2e8f9f7	2913	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	2914	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2915	}
<>	144:ef7eb2e8f9f7	2916	}
<>	144:ef7eb2e8f9f7	2917	/* TIM Break input event */
<>	144:ef7eb2e8f9f7	2918	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<>	144:ef7eb2e8f9f7	2919	{
<>	144:ef7eb2e8f9f7	2920	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<>	144:ef7eb2e8f9f7	2921	{
<>	144:ef7eb2e8f9f7	2922	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<>	144:ef7eb2e8f9f7	2923	HAL_TIMEx_BreakCallback(htim);
<>	144:ef7eb2e8f9f7	2924	}
<>	144:ef7eb2e8f9f7	2925	}
<>	144:ef7eb2e8f9f7	2926	/* TIM Trigger detection event */
<>	144:ef7eb2e8f9f7	2927	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<>	144:ef7eb2e8f9f7	2928	{
<>	144:ef7eb2e8f9f7	2929	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<>	144:ef7eb2e8f9f7	2930	{
<>	144:ef7eb2e8f9f7	2931	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	2932	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	2933	}
<>	144:ef7eb2e8f9f7	2934	}
<>	144:ef7eb2e8f9f7	2935	/* TIM commutation event */
<>	144:ef7eb2e8f9f7	2936	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<>	144:ef7eb2e8f9f7	2937	{
<>	144:ef7eb2e8f9f7	2938	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<>	144:ef7eb2e8f9f7	2939	{
<>	144:ef7eb2e8f9f7	2940	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<>	144:ef7eb2e8f9f7	2941	HAL_TIMEx_CommutationCallback(htim);
<>	144:ef7eb2e8f9f7	2942	}
<>	144:ef7eb2e8f9f7	2943	}
<>	144:ef7eb2e8f9f7	2944	}
<>	144:ef7eb2e8f9f7	2945	/**
<>	144:ef7eb2e8f9f7	2946	* @}
<>	144:ef7eb2e8f9f7	2947	*/
<>	144:ef7eb2e8f9f7	2948
<>	144:ef7eb2e8f9f7	2949	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<>	144:ef7eb2e8f9f7	2950	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	2951	*
<>	144:ef7eb2e8f9f7	2952	@verbatim
<>	144:ef7eb2e8f9f7	2953	==============================================================================
<>	144:ef7eb2e8f9f7	2954	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	2955	==============================================================================
<>	144:ef7eb2e8f9f7	2956	[..]
<>	144:ef7eb2e8f9f7	2957	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2958	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<>	144:ef7eb2e8f9f7	2959	(+) Configure External Clock source.
<>	144:ef7eb2e8f9f7	2960	(+) Configure Complementary channels, break features and dead time.
<>	144:ef7eb2e8f9f7	2961	(+) Configure Master and the Slave synchronization.
<>	144:ef7eb2e8f9f7	2962	(+) Configure the DMA Burst Mode.
<>	144:ef7eb2e8f9f7	2963
<>	144:ef7eb2e8f9f7	2964	@endverbatim
<>	144:ef7eb2e8f9f7	2965	* @{
<>	144:ef7eb2e8f9f7	2966	*/
<>	144:ef7eb2e8f9f7	2967
<>	144:ef7eb2e8f9f7	2968	/**
<>	144:ef7eb2e8f9f7	2969	* @brief Initializes the TIM Output Compare Channels according to the specified
<>	144:ef7eb2e8f9f7	2970	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2971	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2972	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	2973	* @param sConfig: TIM Output Compare configuration structure
<>	144:ef7eb2e8f9f7	2974	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	2975	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2976	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2977	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2978	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2979	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	2980	* @retval HAL status
<>	144:ef7eb2e8f9f7	2981	*/
<>	144:ef7eb2e8f9f7	2982	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2983	{
<>	144:ef7eb2e8f9f7	2984	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2985	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	2986	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	2987	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	2988
<>	144:ef7eb2e8f9f7	2989	/* Check input state */
<>	144:ef7eb2e8f9f7	2990	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2991
<>	144:ef7eb2e8f9f7	2992	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2993
<>	144:ef7eb2e8f9f7	2994	switch (Channel)
<>	144:ef7eb2e8f9f7	2995	{
<>	144:ef7eb2e8f9f7	2996	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2997	{
<>	144:ef7eb2e8f9f7	2998	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2999	/* Configure the TIM Channel 1 in Output Compare */
<>	144:ef7eb2e8f9f7	3000	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3001	}
<>	144:ef7eb2e8f9f7	3002	break;
<>	144:ef7eb2e8f9f7	3003
<>	144:ef7eb2e8f9f7	3004	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3005	{
<>	144:ef7eb2e8f9f7	3006	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3007	/* Configure the TIM Channel 2 in Output Compare */
<>	144:ef7eb2e8f9f7	3008	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3009	}
<>	144:ef7eb2e8f9f7	3010	break;
<>	144:ef7eb2e8f9f7	3011
<>	144:ef7eb2e8f9f7	3012	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3013	{
<>	144:ef7eb2e8f9f7	3014	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3015	/* Configure the TIM Channel 3 in Output Compare */
<>	144:ef7eb2e8f9f7	3016	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3017	}
<>	144:ef7eb2e8f9f7	3018	break;
<>	144:ef7eb2e8f9f7	3019
<>	144:ef7eb2e8f9f7	3020	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3021	{
<>	144:ef7eb2e8f9f7	3022	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3023	/* Configure the TIM Channel 4 in Output Compare */
<>	144:ef7eb2e8f9f7	3024	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3025	}
<>	144:ef7eb2e8f9f7	3026	break;
<>	144:ef7eb2e8f9f7	3027
<>	144:ef7eb2e8f9f7	3028	default:
<>	144:ef7eb2e8f9f7	3029	break;
<>	144:ef7eb2e8f9f7	3030	}
<>	144:ef7eb2e8f9f7	3031	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3032
<>	144:ef7eb2e8f9f7	3033	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3034
<>	144:ef7eb2e8f9f7	3035	return HAL_OK;
<>	144:ef7eb2e8f9f7	3036	}
<>	144:ef7eb2e8f9f7	3037
<>	144:ef7eb2e8f9f7	3038	/**
<>	144:ef7eb2e8f9f7	3039	* @brief Initializes the TIM Input Capture Channels according to the specified
<>	144:ef7eb2e8f9f7	3040	* parameters in the TIM_IC_InitTypeDef.
<>	144:ef7eb2e8f9f7	3041	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3042	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3043	* @param sConfig: TIM Input Capture configuration structure
<>	144:ef7eb2e8f9f7	3044	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	3045	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3046	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3047	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3048	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	3049	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	3050	* @retval HAL status
<>	144:ef7eb2e8f9f7	3051	*/
<>	144:ef7eb2e8f9f7	3052	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3053	{
<>	144:ef7eb2e8f9f7	3054	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3055	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3056	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<>	144:ef7eb2e8f9f7	3057	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<>	144:ef7eb2e8f9f7	3058	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<>	144:ef7eb2e8f9f7	3059	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<>	144:ef7eb2e8f9f7	3060
<>	144:ef7eb2e8f9f7	3061	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3062
<>	144:ef7eb2e8f9f7	3063	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3064
<>	144:ef7eb2e8f9f7	3065	if (Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	3066	{
<>	144:ef7eb2e8f9f7	3067	/* TI1 Configuration */
<>	144:ef7eb2e8f9f7	3068	TIM_TI1_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3069	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3070	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3071	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3072
<>	144:ef7eb2e8f9f7	3073	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	3074	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	3075
<>	144:ef7eb2e8f9f7	3076	/* Set the IC1PSC value */
<>	144:ef7eb2e8f9f7	3077	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	3078	}
<>	144:ef7eb2e8f9f7	3079	else if (Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	3080	{
<>	144:ef7eb2e8f9f7	3081	/* TI2 Configuration */
<>	144:ef7eb2e8f9f7	3082	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3083
<>	144:ef7eb2e8f9f7	3084	TIM_TI2_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3085	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3086	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3087	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3088
<>	144:ef7eb2e8f9f7	3089	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	3090	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	3091
<>	144:ef7eb2e8f9f7	3092	/* Set the IC2PSC value */
<>	144:ef7eb2e8f9f7	3093	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8U);
<>	144:ef7eb2e8f9f7	3094	}
<>	144:ef7eb2e8f9f7	3095	else if (Channel == TIM_CHANNEL_3)
<>	144:ef7eb2e8f9f7	3096	{
<>	144:ef7eb2e8f9f7	3097	/* TI3 Configuration */
<>	144:ef7eb2e8f9f7	3098	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3099
<>	144:ef7eb2e8f9f7	3100	TIM_TI3_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3101	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3102	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3103	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3104
<>	144:ef7eb2e8f9f7	3105	/* Reset the IC3PSC Bits */
<>	144:ef7eb2e8f9f7	3106	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<>	144:ef7eb2e8f9f7	3107
<>	144:ef7eb2e8f9f7	3108	/* Set the IC3PSC value */
<>	144:ef7eb2e8f9f7	3109	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	3110	}
<>	144:ef7eb2e8f9f7	3111	else
<>	144:ef7eb2e8f9f7	3112	{
<>	144:ef7eb2e8f9f7	3113	/* TI4 Configuration */
<>	144:ef7eb2e8f9f7	3114	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3115
<>	144:ef7eb2e8f9f7	3116	TIM_TI4_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3117	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3118	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3119	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3120
<>	144:ef7eb2e8f9f7	3121	/* Reset the IC4PSC Bits */
<>	144:ef7eb2e8f9f7	3122	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<>	144:ef7eb2e8f9f7	3123
<>	144:ef7eb2e8f9f7	3124	/* Set the IC4PSC value */
<>	144:ef7eb2e8f9f7	3125	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8U);
<>	144:ef7eb2e8f9f7	3126	}
<>	144:ef7eb2e8f9f7	3127
<>	144:ef7eb2e8f9f7	3128	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3129
<>	144:ef7eb2e8f9f7	3130	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3131
<>	144:ef7eb2e8f9f7	3132	return HAL_OK;
<>	144:ef7eb2e8f9f7	3133	}
<>	144:ef7eb2e8f9f7	3134
<>	144:ef7eb2e8f9f7	3135	/**
<>	144:ef7eb2e8f9f7	3136	* @brief Initializes the TIM PWM channels according to the specified
<>	144:ef7eb2e8f9f7	3137	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	3138	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3139	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3140	* @param sConfig: TIM PWM configuration structure
<>	144:ef7eb2e8f9f7	3141	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	3142	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3143	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3144	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3145	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	3146	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	3147	* @retval HAL status
<>	144:ef7eb2e8f9f7	3148	*/
<>	144:ef7eb2e8f9f7	3149	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3150	{
<>	144:ef7eb2e8f9f7	3151	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3152
<>	144:ef7eb2e8f9f7	3153	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3154	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	3155	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	3156	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	3157	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<>	144:ef7eb2e8f9f7	3158
<>	144:ef7eb2e8f9f7	3159	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3160
<>	144:ef7eb2e8f9f7	3161	switch (Channel)
<>	144:ef7eb2e8f9f7	3162	{
<>	144:ef7eb2e8f9f7	3163	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3164	{
<>	144:ef7eb2e8f9f7	3165	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3166	/* Configure the Channel 1 in PWM mode */
<>	144:ef7eb2e8f9f7	3167	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3168
<>	144:ef7eb2e8f9f7	3169	/* Set the Preload enable bit for channel1 */
<>	144:ef7eb2e8f9f7	3170	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
<>	144:ef7eb2e8f9f7	3171
<>	144:ef7eb2e8f9f7	3172	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3173	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<>	144:ef7eb2e8f9f7	3174	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3175	}
<>	144:ef7eb2e8f9f7	3176	break;
<>	144:ef7eb2e8f9f7	3177
<>	144:ef7eb2e8f9f7	3178	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3179	{
<>	144:ef7eb2e8f9f7	3180	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3181	/* Configure the Channel 2 in PWM mode */
<>	144:ef7eb2e8f9f7	3182	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3183
<>	144:ef7eb2e8f9f7	3184	/* Set the Preload enable bit for channel2 */
<>	144:ef7eb2e8f9f7	3185	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
<>	144:ef7eb2e8f9f7	3186
<>	144:ef7eb2e8f9f7	3187	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3188	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<>	144:ef7eb2e8f9f7	3189	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8U;
<>	144:ef7eb2e8f9f7	3190	}
<>	144:ef7eb2e8f9f7	3191	break;
<>	144:ef7eb2e8f9f7	3192
<>	144:ef7eb2e8f9f7	3193	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3194	{
<>	144:ef7eb2e8f9f7	3195	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3196	/* Configure the Channel 3 in PWM mode */
<>	144:ef7eb2e8f9f7	3197	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3198
<>	144:ef7eb2e8f9f7	3199	/* Set the Preload enable bit for channel3 */
<>	144:ef7eb2e8f9f7	3200	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
<>	144:ef7eb2e8f9f7	3201
<>	144:ef7eb2e8f9f7	3202	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3203	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<>	144:ef7eb2e8f9f7	3204	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3205	}
<>	144:ef7eb2e8f9f7	3206	break;
<>	144:ef7eb2e8f9f7	3207
<>	144:ef7eb2e8f9f7	3208	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3209	{
<>	144:ef7eb2e8f9f7	3210	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3211	/* Configure the Channel 4 in PWM mode */
<>	144:ef7eb2e8f9f7	3212	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3213
<>	144:ef7eb2e8f9f7	3214	/* Set the Preload enable bit for channel4 */
<>	144:ef7eb2e8f9f7	3215	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
<>	144:ef7eb2e8f9f7	3216
<>	144:ef7eb2e8f9f7	3217	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3218	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<>	144:ef7eb2e8f9f7	3219	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8U;
<>	144:ef7eb2e8f9f7	3220	}
<>	144:ef7eb2e8f9f7	3221	break;
<>	144:ef7eb2e8f9f7	3222
<>	144:ef7eb2e8f9f7	3223	default:
<>	144:ef7eb2e8f9f7	3224	break;
<>	144:ef7eb2e8f9f7	3225	}
<>	144:ef7eb2e8f9f7	3226
<>	144:ef7eb2e8f9f7	3227	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3228
<>	144:ef7eb2e8f9f7	3229	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3230
<>	144:ef7eb2e8f9f7	3231	return HAL_OK;
<>	144:ef7eb2e8f9f7	3232	}
<>	144:ef7eb2e8f9f7	3233
<>	144:ef7eb2e8f9f7	3234	/**
<>	144:ef7eb2e8f9f7	3235	* @brief Initializes the TIM One Pulse Channels according to the specified
<>	144:ef7eb2e8f9f7	3236	* parameters in the TIM_OnePulse_InitTypeDef.
<>	144:ef7eb2e8f9f7	3237	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3238	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3239	* @param sConfig: TIM One Pulse configuration structure
<>	144:ef7eb2e8f9f7	3240	* @param OutputChannel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	3241	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3242	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3243	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3244	* @param InputChannel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	3245	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3246	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3247	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3248	* @retval HAL status
<>	144:ef7eb2e8f9f7	3249	*/
<>	144:ef7eb2e8f9f7	3250	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<>	144:ef7eb2e8f9f7	3251	{
<>	144:ef7eb2e8f9f7	3252	TIM_OC_InitTypeDef temp1;
<>	144:ef7eb2e8f9f7	3253
<>	144:ef7eb2e8f9f7	3254	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3255	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<>	144:ef7eb2e8f9f7	3256	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<>	144:ef7eb2e8f9f7	3257
<>	144:ef7eb2e8f9f7	3258	if(OutputChannel != InputChannel)
<>	144:ef7eb2e8f9f7	3259	{
<>	144:ef7eb2e8f9f7	3260	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3261
<>	144:ef7eb2e8f9f7	3262	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3263
<>	144:ef7eb2e8f9f7	3264	/* Extract the Output compare configuration from sConfig structure */
<>	144:ef7eb2e8f9f7	3265	temp1.OCMode = sConfig->OCMode;
<>	144:ef7eb2e8f9f7	3266	temp1.Pulse = sConfig->Pulse;
<>	144:ef7eb2e8f9f7	3267	temp1.OCPolarity = sConfig->OCPolarity;
<>	144:ef7eb2e8f9f7	3268	temp1.OCNPolarity = sConfig->OCNPolarity;
<>	144:ef7eb2e8f9f7	3269	temp1.OCIdleState = sConfig->OCIdleState;
<>	144:ef7eb2e8f9f7	3270	temp1.OCNIdleState = sConfig->OCNIdleState;
<>	144:ef7eb2e8f9f7	3271
<>	144:ef7eb2e8f9f7	3272	switch (OutputChannel)
<>	144:ef7eb2e8f9f7	3273	{
<>	144:ef7eb2e8f9f7	3274	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3275	{
<>	144:ef7eb2e8f9f7	3276	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3277
<>	144:ef7eb2e8f9f7	3278	TIM_OC1_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3279	}
<>	144:ef7eb2e8f9f7	3280	break;
<>	144:ef7eb2e8f9f7	3281	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3282	{
<>	144:ef7eb2e8f9f7	3283	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3284
<>	144:ef7eb2e8f9f7	3285	TIM_OC2_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3286	}
<>	144:ef7eb2e8f9f7	3287	break;
<>	144:ef7eb2e8f9f7	3288	default:
<>	144:ef7eb2e8f9f7	3289	break;
<>	144:ef7eb2e8f9f7	3290	}
<>	144:ef7eb2e8f9f7	3291	switch (InputChannel)
<>	144:ef7eb2e8f9f7	3292	{
<>	144:ef7eb2e8f9f7	3293	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3294	{
<>	144:ef7eb2e8f9f7	3295	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3296
<>	144:ef7eb2e8f9f7	3297	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3298	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3299
<>	144:ef7eb2e8f9f7	3300	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	3301	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	3302
<>	144:ef7eb2e8f9f7	3303	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3304	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3305	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
<>	144:ef7eb2e8f9f7	3306
<>	144:ef7eb2e8f9f7	3307	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3308	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3309	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3310	}
<>	144:ef7eb2e8f9f7	3311	break;
<>	144:ef7eb2e8f9f7	3312	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3313	{
<>	144:ef7eb2e8f9f7	3314	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3315
<>	144:ef7eb2e8f9f7	3316	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3317	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3318
<>	144:ef7eb2e8f9f7	3319	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	3320	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	3321
<>	144:ef7eb2e8f9f7	3322	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3323	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3324	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
<>	144:ef7eb2e8f9f7	3325
<>	144:ef7eb2e8f9f7	3326	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3327	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3328	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3329	}
<>	144:ef7eb2e8f9f7	3330	break;
<>	144:ef7eb2e8f9f7	3331
<>	144:ef7eb2e8f9f7	3332	default:
<>	144:ef7eb2e8f9f7	3333	break;
<>	144:ef7eb2e8f9f7	3334	}
<>	144:ef7eb2e8f9f7	3335
<>	144:ef7eb2e8f9f7	3336	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3337
<>	144:ef7eb2e8f9f7	3338	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3339
<>	144:ef7eb2e8f9f7	3340	return HAL_OK;
<>	144:ef7eb2e8f9f7	3341	}
<>	144:ef7eb2e8f9f7	3342	else
<>	144:ef7eb2e8f9f7	3343	{
<>	144:ef7eb2e8f9f7	3344	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3345	}
<>	144:ef7eb2e8f9f7	3346	}
<>	144:ef7eb2e8f9f7	3347
<>	144:ef7eb2e8f9f7	3348	/**
<>	144:ef7eb2e8f9f7	3349	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<>	144:ef7eb2e8f9f7	3350	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3351	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3352	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
<>	144:ef7eb2e8f9f7	3353	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3354	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3355	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3356	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3357	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3358	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3359	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3360	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3361	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3362	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3363	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3364	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3365	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3366	* @arg TIM_DMABASE_RCR
<>	144:ef7eb2e8f9f7	3367	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3368	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3369	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3370	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3371	* @arg TIM_DMABASE_BDTR
<>	144:ef7eb2e8f9f7	3372	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3373	* @param BurstRequestSrc: TIM DMA Request sources.
<>	144:ef7eb2e8f9f7	3374	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3375	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3376	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3377	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3378	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3379	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3380	* @arg TIM_DMA_COM: TIM Commutation DMA source
<>	144:ef7eb2e8f9f7	3381	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3382	* @param BurstBuffer: The Buffer address.
<>	144:ef7eb2e8f9f7	3383	* @param BurstLength: DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3384	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	144:ef7eb2e8f9f7	3385	* @retval HAL status
<>	144:ef7eb2e8f9f7	3386	*/
<>	144:ef7eb2e8f9f7	3387	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3388	uint32_t* BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3389	{
<>	144:ef7eb2e8f9f7	3390	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3391	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3392	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3393	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3394	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3395
<>	144:ef7eb2e8f9f7	3396	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3397	{
<>	144:ef7eb2e8f9f7	3398	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3399	}
<>	144:ef7eb2e8f9f7	3400	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3401	{
<>	144:ef7eb2e8f9f7	3402	if((BurstBuffer == 0U ) && (BurstLength > 0U))
<>	144:ef7eb2e8f9f7	3403	{
<>	144:ef7eb2e8f9f7	3404	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3405	}
<>	144:ef7eb2e8f9f7	3406	else
<>	144:ef7eb2e8f9f7	3407	{
<>	144:ef7eb2e8f9f7	3408	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3409	}
<>	144:ef7eb2e8f9f7	3410	}
<>	144:ef7eb2e8f9f7	3411	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3412	{
<>	144:ef7eb2e8f9f7	3413	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3414	{
<>	144:ef7eb2e8f9f7	3415	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3416	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3417
<>	144:ef7eb2e8f9f7	3418	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3419	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3420
<>	144:ef7eb2e8f9f7	3421	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3422	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3423	}
<>	144:ef7eb2e8f9f7	3424	break;
<>	144:ef7eb2e8f9f7	3425	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3426	{
<>	144:ef7eb2e8f9f7	3427	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3428	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3429
<>	144:ef7eb2e8f9f7	3430	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3431	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3432
<>	144:ef7eb2e8f9f7	3433	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3434	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3435	}
<>	144:ef7eb2e8f9f7	3436	break;
<>	144:ef7eb2e8f9f7	3437	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3438	{
<>	144:ef7eb2e8f9f7	3439	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3440	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3441
<>	144:ef7eb2e8f9f7	3442	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3443	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3444
<>	144:ef7eb2e8f9f7	3445	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3446	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3447	}
<>	144:ef7eb2e8f9f7	3448	break;
<>	144:ef7eb2e8f9f7	3449	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3450	{
<>	144:ef7eb2e8f9f7	3451	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3452	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3453
<>	144:ef7eb2e8f9f7	3454	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3455	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3456
<>	144:ef7eb2e8f9f7	3457	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3458	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3459	}
<>	144:ef7eb2e8f9f7	3460	break;
<>	144:ef7eb2e8f9f7	3461	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3462	{
<>	144:ef7eb2e8f9f7	3463	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3464	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3465
<>	144:ef7eb2e8f9f7	3466	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3467	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3468
<>	144:ef7eb2e8f9f7	3469	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3470	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3471	}
<>	144:ef7eb2e8f9f7	3472	break;
<>	144:ef7eb2e8f9f7	3473	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3474	{
<>	144:ef7eb2e8f9f7	3475	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3476	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<>	144:ef7eb2e8f9f7	3477
<>	144:ef7eb2e8f9f7	3478	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3479	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3480
<>	144:ef7eb2e8f9f7	3481	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3482	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3483	}
<>	144:ef7eb2e8f9f7	3484	break;
<>	144:ef7eb2e8f9f7	3485	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3486	{
<>	144:ef7eb2e8f9f7	3487	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3488	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3489
<>	144:ef7eb2e8f9f7	3490	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3491	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3492
<>	144:ef7eb2e8f9f7	3493	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3494	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3495	}
<>	144:ef7eb2e8f9f7	3496	break;
<>	144:ef7eb2e8f9f7	3497	default:
<>	144:ef7eb2e8f9f7	3498	break;
<>	144:ef7eb2e8f9f7	3499	}
<>	144:ef7eb2e8f9f7	3500	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3501	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3502
<>	144:ef7eb2e8f9f7	3503	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3504	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3505
<>	144:ef7eb2e8f9f7	3506	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3507
<>	144:ef7eb2e8f9f7	3508	/* Return function status */
<>	144:ef7eb2e8f9f7	3509	return HAL_OK;
<>	144:ef7eb2e8f9f7	3510	}
<>	144:ef7eb2e8f9f7	3511
<>	144:ef7eb2e8f9f7	3512	/**
<>	144:ef7eb2e8f9f7	3513	* @brief Stops the TIM DMA Burst mode
<>	144:ef7eb2e8f9f7	3514	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3515	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3516	* @param BurstRequestSrc: TIM DMA Request sources to disable
<>	144:ef7eb2e8f9f7	3517	* @retval HAL status
<>	144:ef7eb2e8f9f7	3518	*/
<>	144:ef7eb2e8f9f7	3519	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3520	{
<>	144:ef7eb2e8f9f7	3521	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3522	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3523
<>	144:ef7eb2e8f9f7	3524	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3525	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3526	{
<>	144:ef7eb2e8f9f7	3527	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3528	{
<>	144:ef7eb2e8f9f7	3529	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3530	}
<>	144:ef7eb2e8f9f7	3531	break;
<>	144:ef7eb2e8f9f7	3532	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3533	{
<>	144:ef7eb2e8f9f7	3534	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3535	}
<>	144:ef7eb2e8f9f7	3536	break;
<>	144:ef7eb2e8f9f7	3537	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3538	{
<>	144:ef7eb2e8f9f7	3539	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3540	}
<>	144:ef7eb2e8f9f7	3541	break;
<>	144:ef7eb2e8f9f7	3542	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3543	{
<>	144:ef7eb2e8f9f7	3544	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3545	}
<>	144:ef7eb2e8f9f7	3546	break;
<>	144:ef7eb2e8f9f7	3547	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3548	{
<>	144:ef7eb2e8f9f7	3549	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3550	}
<>	144:ef7eb2e8f9f7	3551	break;
<>	144:ef7eb2e8f9f7	3552	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3553	{
<>	144:ef7eb2e8f9f7	3554	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<>	144:ef7eb2e8f9f7	3555	}
<>	144:ef7eb2e8f9f7	3556	break;
<>	144:ef7eb2e8f9f7	3557	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3558	{
<>	144:ef7eb2e8f9f7	3559	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3560	}
<>	144:ef7eb2e8f9f7	3561	break;
<>	144:ef7eb2e8f9f7	3562	default:
<>	144:ef7eb2e8f9f7	3563	break;
<>	144:ef7eb2e8f9f7	3564	}
<>	144:ef7eb2e8f9f7	3565
<>	144:ef7eb2e8f9f7	3566	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3567	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3568
<>	144:ef7eb2e8f9f7	3569	/* Return function status */
<>	144:ef7eb2e8f9f7	3570	return HAL_OK;
<>	144:ef7eb2e8f9f7	3571	}
<>	144:ef7eb2e8f9f7	3572
<>	144:ef7eb2e8f9f7	3573	/**
<>	144:ef7eb2e8f9f7	3574	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<>	144:ef7eb2e8f9f7	3575	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3576	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3577	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
<>	144:ef7eb2e8f9f7	3578	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3579	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3580	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3581	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3582	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3583	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3584	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3585	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3586	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3587	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3588	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3589	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3590	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3591	* @arg TIM_DMABASE_RCR
<>	144:ef7eb2e8f9f7	3592	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3593	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3594	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3595	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3596	* @arg TIM_DMABASE_BDTR
<>	144:ef7eb2e8f9f7	3597	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3598	* @param BurstRequestSrc: TIM DMA Request sources.
<>	144:ef7eb2e8f9f7	3599	* This parameters can be on of the following values:
<>	144:ef7eb2e8f9f7	3600	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3601	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3602	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3603	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3604	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3605	* @arg TIM_DMA_COM: TIM Commutation DMA source
<>	144:ef7eb2e8f9f7	3606	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3607	* @param BurstBuffer: The Buffer address.
<>	144:ef7eb2e8f9f7	3608	* @param BurstLength: DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3609	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	144:ef7eb2e8f9f7	3610	* @retval HAL status
<>	144:ef7eb2e8f9f7	3611	*/
<>	144:ef7eb2e8f9f7	3612	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3613	uint32_t *BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3614	{
<>	144:ef7eb2e8f9f7	3615	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3616	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3617	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3618	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3619	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3620
<>	144:ef7eb2e8f9f7	3621	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3622	{
<>	144:ef7eb2e8f9f7	3623	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3624	}
<>	144:ef7eb2e8f9f7	3625	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3626	{
AnnaBridge	167:e84263d55307	3627	if((BurstBuffer == 0U ) && (BurstLength > 0U))
<>	144:ef7eb2e8f9f7	3628	{
<>	144:ef7eb2e8f9f7	3629	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3630	}
<>	144:ef7eb2e8f9f7	3631	else
<>	144:ef7eb2e8f9f7	3632	{
<>	144:ef7eb2e8f9f7	3633	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3634	}
<>	144:ef7eb2e8f9f7	3635	}
<>	144:ef7eb2e8f9f7	3636	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3637	{
<>	144:ef7eb2e8f9f7	3638	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3639	{
<>	144:ef7eb2e8f9f7	3640	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3641	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3642
<>	144:ef7eb2e8f9f7	3643	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3644	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3645
<>	144:ef7eb2e8f9f7	3646	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3647	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3648	}
<>	144:ef7eb2e8f9f7	3649	break;
<>	144:ef7eb2e8f9f7	3650	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3651	{
<>	144:ef7eb2e8f9f7	3652	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3653	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3654
<>	144:ef7eb2e8f9f7	3655	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3656	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3657
<>	144:ef7eb2e8f9f7	3658	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3659	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3660	}
<>	144:ef7eb2e8f9f7	3661	break;
<>	144:ef7eb2e8f9f7	3662	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3663	{
<>	144:ef7eb2e8f9f7	3664	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3665	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3666
<>	144:ef7eb2e8f9f7	3667	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3668	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3669
<>	144:ef7eb2e8f9f7	3670	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3671	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3672	}
<>	144:ef7eb2e8f9f7	3673	break;
<>	144:ef7eb2e8f9f7	3674	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3675	{
<>	144:ef7eb2e8f9f7	3676	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3677	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3678
<>	144:ef7eb2e8f9f7	3679	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3680	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3681
<>	144:ef7eb2e8f9f7	3682	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3683	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3684	}
<>	144:ef7eb2e8f9f7	3685	break;
<>	144:ef7eb2e8f9f7	3686	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3687	{
<>	144:ef7eb2e8f9f7	3688	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3689	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3690
<>	144:ef7eb2e8f9f7	3691	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3692	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3693
<>	144:ef7eb2e8f9f7	3694	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3695	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3696	}
<>	144:ef7eb2e8f9f7	3697	break;
<>	144:ef7eb2e8f9f7	3698	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3699	{
<>	144:ef7eb2e8f9f7	3700	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3701	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<>	144:ef7eb2e8f9f7	3702
<>	144:ef7eb2e8f9f7	3703	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3704	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3705
<>	144:ef7eb2e8f9f7	3706	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3707	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3708	}
<>	144:ef7eb2e8f9f7	3709	break;
<>	144:ef7eb2e8f9f7	3710	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3711	{
<>	144:ef7eb2e8f9f7	3712	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3713	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3714
<>	144:ef7eb2e8f9f7	3715	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3716	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3717
<>	144:ef7eb2e8f9f7	3718	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3719	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3720	}
<>	144:ef7eb2e8f9f7	3721	break;
<>	144:ef7eb2e8f9f7	3722	default:
<>	144:ef7eb2e8f9f7	3723	break;
<>	144:ef7eb2e8f9f7	3724	}
<>	144:ef7eb2e8f9f7	3725
<>	144:ef7eb2e8f9f7	3726	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3727	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3728
<>	144:ef7eb2e8f9f7	3729	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3730	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3731
<>	144:ef7eb2e8f9f7	3732	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3733
<>	144:ef7eb2e8f9f7	3734	/* Return function status */
<>	144:ef7eb2e8f9f7	3735	return HAL_OK;
<>	144:ef7eb2e8f9f7	3736	}
<>	144:ef7eb2e8f9f7	3737
<>	144:ef7eb2e8f9f7	3738	/**
<>	144:ef7eb2e8f9f7	3739	* @brief Stop the DMA burst reading
<>	144:ef7eb2e8f9f7	3740	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3741	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3742	* @param BurstRequestSrc: TIM DMA Request sources to disable.
<>	144:ef7eb2e8f9f7	3743	* @retval HAL status
<>	144:ef7eb2e8f9f7	3744	*/
<>	144:ef7eb2e8f9f7	3745	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3746	{
<>	144:ef7eb2e8f9f7	3747	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3748	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3749
<>	144:ef7eb2e8f9f7	3750	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3751	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3752	{
<>	144:ef7eb2e8f9f7	3753	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3754	{
<>	144:ef7eb2e8f9f7	3755	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3756	}
<>	144:ef7eb2e8f9f7	3757	break;
<>	144:ef7eb2e8f9f7	3758	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3759	{
<>	144:ef7eb2e8f9f7	3760	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3761	}
<>	144:ef7eb2e8f9f7	3762	break;
<>	144:ef7eb2e8f9f7	3763	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3764	{
<>	144:ef7eb2e8f9f7	3765	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3766	}
<>	144:ef7eb2e8f9f7	3767	break;
<>	144:ef7eb2e8f9f7	3768	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3769	{
<>	144:ef7eb2e8f9f7	3770	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3771	}
<>	144:ef7eb2e8f9f7	3772	break;
<>	144:ef7eb2e8f9f7	3773	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3774	{
<>	144:ef7eb2e8f9f7	3775	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3776	}
<>	144:ef7eb2e8f9f7	3777	break;
<>	144:ef7eb2e8f9f7	3778	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3779	{
<>	144:ef7eb2e8f9f7	3780	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<>	144:ef7eb2e8f9f7	3781	}
<>	144:ef7eb2e8f9f7	3782	break;
<>	144:ef7eb2e8f9f7	3783	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3784	{
<>	144:ef7eb2e8f9f7	3785	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3786	}
<>	144:ef7eb2e8f9f7	3787	break;
<>	144:ef7eb2e8f9f7	3788	default:
<>	144:ef7eb2e8f9f7	3789	break;
<>	144:ef7eb2e8f9f7	3790	}
<>	144:ef7eb2e8f9f7	3791
<>	144:ef7eb2e8f9f7	3792	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3793	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3794
<>	144:ef7eb2e8f9f7	3795	/* Return function status */
<>	144:ef7eb2e8f9f7	3796	return HAL_OK;
<>	144:ef7eb2e8f9f7	3797	}
<>	144:ef7eb2e8f9f7	3798
<>	144:ef7eb2e8f9f7	3799	/**
<>	144:ef7eb2e8f9f7	3800	* @brief Generate a software event
<>	144:ef7eb2e8f9f7	3801	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3802	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3803	* @param EventSource: specifies the event source.
<>	144:ef7eb2e8f9f7	3804	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3805	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<>	144:ef7eb2e8f9f7	3806	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<>	144:ef7eb2e8f9f7	3807	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<>	144:ef7eb2e8f9f7	3808	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<>	144:ef7eb2e8f9f7	3809	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<>	144:ef7eb2e8f9f7	3810	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
<>	144:ef7eb2e8f9f7	3811	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<>	144:ef7eb2e8f9f7	3812	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<>	144:ef7eb2e8f9f7	3813	* @note TIM6 and TIM7 can only generate an update event.
<>	144:ef7eb2e8f9f7	3814	* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
<>	144:ef7eb2e8f9f7	3815	* @retval HAL status
<>	144:ef7eb2e8f9f7	3816	*/
<>	144:ef7eb2e8f9f7	3817
<>	144:ef7eb2e8f9f7	3818	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<>	144:ef7eb2e8f9f7	3819	{
<>	144:ef7eb2e8f9f7	3820	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3821	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3822	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<>	144:ef7eb2e8f9f7	3823
<>	144:ef7eb2e8f9f7	3824	/* Process Locked */
<>	144:ef7eb2e8f9f7	3825	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3826
<>	144:ef7eb2e8f9f7	3827	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3828	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3829
<>	144:ef7eb2e8f9f7	3830	/* Set the event sources */
<>	144:ef7eb2e8f9f7	3831	htim->Instance->EGR = EventSource;
<>	144:ef7eb2e8f9f7	3832
<>	144:ef7eb2e8f9f7	3833	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3834	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3835
<>	144:ef7eb2e8f9f7	3836	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3837
<>	144:ef7eb2e8f9f7	3838	/* Return function status */
<>	144:ef7eb2e8f9f7	3839	return HAL_OK;
<>	144:ef7eb2e8f9f7	3840	}
<>	144:ef7eb2e8f9f7	3841
<>	144:ef7eb2e8f9f7	3842	/**
<>	144:ef7eb2e8f9f7	3843	* @brief Configures the OCRef clear feature
<>	144:ef7eb2e8f9f7	3844	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3845	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3846	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3847	* contains the OCREF clear feature and parameters for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3848	* @param Channel: specifies the TIM Channel.
<>	144:ef7eb2e8f9f7	3849	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3850	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3851	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3852	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	3853	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	3854	* @retval HAL status
<>	144:ef7eb2e8f9f7	3855	*/
<>	144:ef7eb2e8f9f7	3856	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3857	{
<>	144:ef7eb2e8f9f7	3858	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3859	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3860	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	3861	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<>	144:ef7eb2e8f9f7	3862	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<>	144:ef7eb2e8f9f7	3863	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<>	144:ef7eb2e8f9f7	3864	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<>	144:ef7eb2e8f9f7	3865
<>	144:ef7eb2e8f9f7	3866	/* Process Locked */
<>	144:ef7eb2e8f9f7	3867	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3868
<>	144:ef7eb2e8f9f7	3869	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3870
<>	144:ef7eb2e8f9f7	3871	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
<>	144:ef7eb2e8f9f7	3872	{
<>	144:ef7eb2e8f9f7	3873	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3874	sClearInputConfig->ClearInputPrescaler,
<>	144:ef7eb2e8f9f7	3875	sClearInputConfig->ClearInputPolarity,
<>	144:ef7eb2e8f9f7	3876	sClearInputConfig->ClearInputFilter);
<>	144:ef7eb2e8f9f7	3877	}
<>	144:ef7eb2e8f9f7	3878
<>	144:ef7eb2e8f9f7	3879	switch (Channel)
<>	144:ef7eb2e8f9f7	3880	{
<>	144:ef7eb2e8f9f7	3881	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3882	{
<>	144:ef7eb2e8f9f7	3883	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3884	{
<>	144:ef7eb2e8f9f7	3885	/* Enable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3886	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3887	}
<>	144:ef7eb2e8f9f7	3888	else
<>	144:ef7eb2e8f9f7	3889	{
<>	144:ef7eb2e8f9f7	3890	/* Disable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3891	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3892	}
<>	144:ef7eb2e8f9f7	3893	}
<>	144:ef7eb2e8f9f7	3894	break;
<>	144:ef7eb2e8f9f7	3895	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3896	{
<>	144:ef7eb2e8f9f7	3897	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3898	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3899	{
<>	144:ef7eb2e8f9f7	3900	/* Enable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3901	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3902	}
<>	144:ef7eb2e8f9f7	3903	else
<>	144:ef7eb2e8f9f7	3904	{
<>	144:ef7eb2e8f9f7	3905	/* Disable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3906	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3907	}
<>	144:ef7eb2e8f9f7	3908	}
<>	144:ef7eb2e8f9f7	3909	break;
<>	144:ef7eb2e8f9f7	3910	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3911	{
<>	144:ef7eb2e8f9f7	3912	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3913	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3914	{
<>	144:ef7eb2e8f9f7	3915	/* Enable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3916	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3917	}
<>	144:ef7eb2e8f9f7	3918	else
<>	144:ef7eb2e8f9f7	3919	{
<>	144:ef7eb2e8f9f7	3920	/* Disable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3921	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3922	}
<>	144:ef7eb2e8f9f7	3923	}
<>	144:ef7eb2e8f9f7	3924	break;
<>	144:ef7eb2e8f9f7	3925	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3926	{
<>	144:ef7eb2e8f9f7	3927	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3928	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3929	{
<>	144:ef7eb2e8f9f7	3930	/* Enable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3931	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3932	}
<>	144:ef7eb2e8f9f7	3933	else
<>	144:ef7eb2e8f9f7	3934	{
<>	144:ef7eb2e8f9f7	3935	/* Disable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3936	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3937	}
<>	144:ef7eb2e8f9f7	3938	}
<>	144:ef7eb2e8f9f7	3939	break;
<>	144:ef7eb2e8f9f7	3940	default:
<>	144:ef7eb2e8f9f7	3941	break;
<>	144:ef7eb2e8f9f7	3942	}
<>	144:ef7eb2e8f9f7	3943
<>	144:ef7eb2e8f9f7	3944	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3945
<>	144:ef7eb2e8f9f7	3946	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3947
<>	144:ef7eb2e8f9f7	3948	return HAL_OK;
<>	144:ef7eb2e8f9f7	3949	}
<>	144:ef7eb2e8f9f7	3950
<>	144:ef7eb2e8f9f7	3951	/**
<>	144:ef7eb2e8f9f7	3952	* @brief Configures the clock source to be used
<>	144:ef7eb2e8f9f7	3953	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3954	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	3955	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3956	* contains the clock source information for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3957	* @retval HAL status
<>	144:ef7eb2e8f9f7	3958	*/
<>	144:ef7eb2e8f9f7	3959	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
<>	144:ef7eb2e8f9f7	3960	{
<>	144:ef7eb2e8f9f7	3961	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	3962
<>	144:ef7eb2e8f9f7	3963	/* Process Locked */
<>	144:ef7eb2e8f9f7	3964	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3965
<>	144:ef7eb2e8f9f7	3966	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3967
<>	144:ef7eb2e8f9f7	3968	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3969	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<>	144:ef7eb2e8f9f7	3970
<>	144:ef7eb2e8f9f7	3971	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<>	144:ef7eb2e8f9f7	3972	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3973	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	3974	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	3975	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3976
<>	144:ef7eb2e8f9f7	3977	switch (sClockSourceConfig->ClockSource)
<>	144:ef7eb2e8f9f7	3978	{
<>	144:ef7eb2e8f9f7	3979	case TIM_CLOCKSOURCE_INTERNAL:
<>	144:ef7eb2e8f9f7	3980	{
<>	144:ef7eb2e8f9f7	3981	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3982
<>	144:ef7eb2e8f9f7	3983	/* Disable slave mode to clock the prescaler directly with the internal clock */
<>	144:ef7eb2e8f9f7	3984	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3985	}
<>	144:ef7eb2e8f9f7	3986	break;
<>	144:ef7eb2e8f9f7	3987
<>	144:ef7eb2e8f9f7	3988	case TIM_CLOCKSOURCE_ETRMODE1:
<>	144:ef7eb2e8f9f7	3989	{
<>	144:ef7eb2e8f9f7	3990	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3991
<>	144:ef7eb2e8f9f7	3992	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3993	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	3994	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3995
<>	144:ef7eb2e8f9f7	3996	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	3997	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3998	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	3999	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4000	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4001	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	4002	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	4003	/* Reset the SMS and TS Bits */
<>	144:ef7eb2e8f9f7	4004	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	4005	/* Select the External clock mode1 and the ETRF trigger */
<>	144:ef7eb2e8f9f7	4006	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
<>	144:ef7eb2e8f9f7	4007	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	4008	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	4009	}
<>	144:ef7eb2e8f9f7	4010	break;
<>	144:ef7eb2e8f9f7	4011
<>	144:ef7eb2e8f9f7	4012	case TIM_CLOCKSOURCE_ETRMODE2:
<>	144:ef7eb2e8f9f7	4013	{
<>	144:ef7eb2e8f9f7	4014	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4015
<>	144:ef7eb2e8f9f7	4016	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4017	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	4018	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4019
<>	144:ef7eb2e8f9f7	4020	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	4021	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	4022	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	4023	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4024	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4025	/* Enable the External clock mode2 */
<>	144:ef7eb2e8f9f7	4026	htim->Instance->SMCR \|= TIM_SMCR_ECE;
<>	144:ef7eb2e8f9f7	4027	}
<>	144:ef7eb2e8f9f7	4028	break;
<>	144:ef7eb2e8f9f7	4029
<>	144:ef7eb2e8f9f7	4030	case TIM_CLOCKSOURCE_TI1:
<>	144:ef7eb2e8f9f7	4031	{
<>	144:ef7eb2e8f9f7	4032	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4033
<>	144:ef7eb2e8f9f7	4034	/* Check TI1 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	4035	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4036	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4037
<>	144:ef7eb2e8f9f7	4038	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4039	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4040	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4041	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<>	144:ef7eb2e8f9f7	4042	}
<>	144:ef7eb2e8f9f7	4043	break;
<>	144:ef7eb2e8f9f7	4044	case TIM_CLOCKSOURCE_TI2:
<>	144:ef7eb2e8f9f7	4045	{
<>	144:ef7eb2e8f9f7	4046	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4047
<>	144:ef7eb2e8f9f7	4048	/* Check TI1 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	4049	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4050	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4051
<>	144:ef7eb2e8f9f7	4052	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4053	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4054	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4055	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<>	144:ef7eb2e8f9f7	4056	}
<>	144:ef7eb2e8f9f7	4057	break;
<>	144:ef7eb2e8f9f7	4058	case TIM_CLOCKSOURCE_TI1ED:
<>	144:ef7eb2e8f9f7	4059	{
<>	144:ef7eb2e8f9f7	4060	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4061
<>	144:ef7eb2e8f9f7	4062	/* Check TI1 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	4063	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4064	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4065
<>	144:ef7eb2e8f9f7	4066	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4067	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4068	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4069	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<>	144:ef7eb2e8f9f7	4070	}
<>	144:ef7eb2e8f9f7	4071	break;
<>	144:ef7eb2e8f9f7	4072	case TIM_CLOCKSOURCE_ITR0:
<>	144:ef7eb2e8f9f7	4073	{
<>	144:ef7eb2e8f9f7	4074	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4075	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<>	144:ef7eb2e8f9f7	4076	}
<>	144:ef7eb2e8f9f7	4077	break;
<>	144:ef7eb2e8f9f7	4078	case TIM_CLOCKSOURCE_ITR1:
<>	144:ef7eb2e8f9f7	4079	{
<>	144:ef7eb2e8f9f7	4080	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4081	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<>	144:ef7eb2e8f9f7	4082	}
<>	144:ef7eb2e8f9f7	4083	break;
<>	144:ef7eb2e8f9f7	4084	case TIM_CLOCKSOURCE_ITR2:
<>	144:ef7eb2e8f9f7	4085	{
<>	144:ef7eb2e8f9f7	4086	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4087	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<>	144:ef7eb2e8f9f7	4088	}
<>	144:ef7eb2e8f9f7	4089	break;
<>	144:ef7eb2e8f9f7	4090	case TIM_CLOCKSOURCE_ITR3:
<>	144:ef7eb2e8f9f7	4091	{
<>	144:ef7eb2e8f9f7	4092	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4093	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<>	144:ef7eb2e8f9f7	4094	}
<>	144:ef7eb2e8f9f7	4095	break;
<>	144:ef7eb2e8f9f7	4096
<>	144:ef7eb2e8f9f7	4097	default:
<>	144:ef7eb2e8f9f7	4098	break;
<>	144:ef7eb2e8f9f7	4099	}
<>	144:ef7eb2e8f9f7	4100	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4101
<>	144:ef7eb2e8f9f7	4102	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4103
<>	144:ef7eb2e8f9f7	4104	return HAL_OK;
<>	144:ef7eb2e8f9f7	4105	}
<>	144:ef7eb2e8f9f7	4106
<>	144:ef7eb2e8f9f7	4107	/**
<>	144:ef7eb2e8f9f7	4108	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
<>	144:ef7eb2e8f9f7	4109	* or a XOR combination between CH1_input, CH2_input & CH3_input
<>	144:ef7eb2e8f9f7	4110	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4111	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4112	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
<>	144:ef7eb2e8f9f7	4113	* output of a XOR gate.
<>	144:ef7eb2e8f9f7	4114	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4115	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<>	144:ef7eb2e8f9f7	4116	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<>	144:ef7eb2e8f9f7	4117	* pins are connected to the TI1 input (XOR combination)
<>	144:ef7eb2e8f9f7	4118	* @retval HAL status
<>	144:ef7eb2e8f9f7	4119	*/
<>	144:ef7eb2e8f9f7	4120	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<>	144:ef7eb2e8f9f7	4121	{
<>	144:ef7eb2e8f9f7	4122	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4123
<>	144:ef7eb2e8f9f7	4124	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4125	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4126	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<>	144:ef7eb2e8f9f7	4127
<>	144:ef7eb2e8f9f7	4128	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4129	tmpcr2 = htim->Instance->CR2;
<>	144:ef7eb2e8f9f7	4130
<>	144:ef7eb2e8f9f7	4131	/* Reset the TI1 selection */
<>	144:ef7eb2e8f9f7	4132	tmpcr2 &= ~TIM_CR2_TI1S;
<>	144:ef7eb2e8f9f7	4133
<>	144:ef7eb2e8f9f7	4134	/* Set the TI1 selection */
<>	144:ef7eb2e8f9f7	4135	tmpcr2 \|= TI1_Selection;
<>	144:ef7eb2e8f9f7	4136
<>	144:ef7eb2e8f9f7	4137	/* Write to TIMxCR2 */
<>	144:ef7eb2e8f9f7	4138	htim->Instance->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4139
<>	144:ef7eb2e8f9f7	4140	return HAL_OK;
<>	144:ef7eb2e8f9f7	4141	}
<>	144:ef7eb2e8f9f7	4142
<>	144:ef7eb2e8f9f7	4143	/**
<>	144:ef7eb2e8f9f7	4144	* @brief Configures the TIM in Slave mode
<>	144:ef7eb2e8f9f7	4145	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4146	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4147	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	4148	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	4149	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	4150	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	4151	* @retval HAL status
<>	144:ef7eb2e8f9f7	4152	*/
<>	144:ef7eb2e8f9f7	4153	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
<>	144:ef7eb2e8f9f7	4154	{
<>	144:ef7eb2e8f9f7	4155	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4156	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4157	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	4158	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	4159
<>	144:ef7eb2e8f9f7	4160	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4161
<>	144:ef7eb2e8f9f7	4162	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	4163
<>	144:ef7eb2e8f9f7	4164	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	4165
<>	144:ef7eb2e8f9f7	4166	/* Disable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	4167	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	4168
<>	144:ef7eb2e8f9f7	4169	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	4170	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	4171
<>	144:ef7eb2e8f9f7	4172	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4173
<>	144:ef7eb2e8f9f7	4174	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4175
<>	144:ef7eb2e8f9f7	4176	return HAL_OK;
<>	144:ef7eb2e8f9f7	4177	}
<>	144:ef7eb2e8f9f7	4178
<>	144:ef7eb2e8f9f7	4179	/**
<>	144:ef7eb2e8f9f7	4180	* @brief Configures the TIM in Slave mode in interrupt mode
<>	144:ef7eb2e8f9f7	4181	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	4182	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	4183	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	4184	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	4185	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	4186	* @retval HAL status
<>	144:ef7eb2e8f9f7	4187	*/
<>	144:ef7eb2e8f9f7	4188	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	4189	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	4190	{
<>	144:ef7eb2e8f9f7	4191	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4192	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4193	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	4194	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	4195
<>	144:ef7eb2e8f9f7	4196	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4197
<>	144:ef7eb2e8f9f7	4198	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	4199
<>	144:ef7eb2e8f9f7	4200	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	4201
<>	144:ef7eb2e8f9f7	4202	/* Enable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	4203	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	4204
<>	144:ef7eb2e8f9f7	4205	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	4206	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	4207
<>	144:ef7eb2e8f9f7	4208	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4209
<>	144:ef7eb2e8f9f7	4210	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4211
<>	144:ef7eb2e8f9f7	4212	return HAL_OK;
<>	144:ef7eb2e8f9f7	4213	}
<>	144:ef7eb2e8f9f7	4214
<>	144:ef7eb2e8f9f7	4215	/**
<>	144:ef7eb2e8f9f7	4216	* @brief Read the captured value from Capture Compare unit
<>	144:ef7eb2e8f9f7	4217	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4218	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4219	* @param Channel: TIM Channels to be enabled.
<>	144:ef7eb2e8f9f7	4220	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4221	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	4222	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	4223	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	4224	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	4225	* @retval Captured value
<>	144:ef7eb2e8f9f7	4226	*/
<>	144:ef7eb2e8f9f7	4227	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	4228	{
<>	144:ef7eb2e8f9f7	4229	uint32_t tmpreg = 0U;
<>	144:ef7eb2e8f9f7	4230
<>	144:ef7eb2e8f9f7	4231	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4232
<>	144:ef7eb2e8f9f7	4233	switch (Channel)
<>	144:ef7eb2e8f9f7	4234	{
<>	144:ef7eb2e8f9f7	4235	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	4236	{
<>	144:ef7eb2e8f9f7	4237	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4238	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4239
<>	144:ef7eb2e8f9f7	4240	/* Return the capture 1 value */
<>	144:ef7eb2e8f9f7	4241	tmpreg = htim->Instance->CCR1;
<>	144:ef7eb2e8f9f7	4242
<>	144:ef7eb2e8f9f7	4243	break;
<>	144:ef7eb2e8f9f7	4244	}
<>	144:ef7eb2e8f9f7	4245	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	4246	{
<>	144:ef7eb2e8f9f7	4247	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4248	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4249
<>	144:ef7eb2e8f9f7	4250	/* Return the capture 2 value */
<>	144:ef7eb2e8f9f7	4251	tmpreg = htim->Instance->CCR2;
<>	144:ef7eb2e8f9f7	4252
<>	144:ef7eb2e8f9f7	4253	break;
<>	144:ef7eb2e8f9f7	4254	}
<>	144:ef7eb2e8f9f7	4255
<>	144:ef7eb2e8f9f7	4256	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	4257	{
<>	144:ef7eb2e8f9f7	4258	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4259	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4260
<>	144:ef7eb2e8f9f7	4261	/* Return the capture 3 value */
<>	144:ef7eb2e8f9f7	4262	tmpreg = htim->Instance->CCR3;
<>	144:ef7eb2e8f9f7	4263
<>	144:ef7eb2e8f9f7	4264	break;
<>	144:ef7eb2e8f9f7	4265	}
<>	144:ef7eb2e8f9f7	4266
<>	144:ef7eb2e8f9f7	4267	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	4268	{
<>	144:ef7eb2e8f9f7	4269	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4270	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4271
<>	144:ef7eb2e8f9f7	4272	/* Return the capture 4 value */
<>	144:ef7eb2e8f9f7	4273	tmpreg = htim->Instance->CCR4;
<>	144:ef7eb2e8f9f7	4274
<>	144:ef7eb2e8f9f7	4275	break;
<>	144:ef7eb2e8f9f7	4276	}
<>	144:ef7eb2e8f9f7	4277
<>	144:ef7eb2e8f9f7	4278	default:
<>	144:ef7eb2e8f9f7	4279	break;
<>	144:ef7eb2e8f9f7	4280	}
<>	144:ef7eb2e8f9f7	4281
<>	144:ef7eb2e8f9f7	4282	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4283	return tmpreg;
<>	144:ef7eb2e8f9f7	4284	}
<>	144:ef7eb2e8f9f7	4285	/**
<>	144:ef7eb2e8f9f7	4286	* @}
<>	144:ef7eb2e8f9f7	4287	*/
<>	144:ef7eb2e8f9f7	4288
<>	144:ef7eb2e8f9f7	4289	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<>	144:ef7eb2e8f9f7	4290	* @brief TIM Callbacks functions
<>	144:ef7eb2e8f9f7	4291	*
<>	144:ef7eb2e8f9f7	4292	@verbatim
<>	144:ef7eb2e8f9f7	4293	==============================================================================
<>	144:ef7eb2e8f9f7	4294	##### TIM Callbacks functions #####
<>	144:ef7eb2e8f9f7	4295	==============================================================================
<>	144:ef7eb2e8f9f7	4296	[..]
<>	144:ef7eb2e8f9f7	4297	This section provides TIM callback functions:
<>	144:ef7eb2e8f9f7	4298	(+) Timer Period elapsed callback
<>	144:ef7eb2e8f9f7	4299	(+) Timer Output Compare callback
<>	144:ef7eb2e8f9f7	4300	(+) Timer Input capture callback
<>	144:ef7eb2e8f9f7	4301	(+) Timer Trigger callback
<>	144:ef7eb2e8f9f7	4302	(+) Timer Error callback
<>	144:ef7eb2e8f9f7	4303
<>	144:ef7eb2e8f9f7	4304	@endverbatim
<>	144:ef7eb2e8f9f7	4305	* @{
<>	144:ef7eb2e8f9f7	4306	*/
<>	144:ef7eb2e8f9f7	4307
<>	144:ef7eb2e8f9f7	4308	/**
<>	144:ef7eb2e8f9f7	4309	* @brief Period elapsed callback in non blocking mode
<>	144:ef7eb2e8f9f7	4310	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4311	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4312	* @retval None
<>	144:ef7eb2e8f9f7	4313	*/
<>	144:ef7eb2e8f9f7	4314	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4315	{
<>	144:ef7eb2e8f9f7	4316	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4317	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4318	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4319	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4320	*/
<>	144:ef7eb2e8f9f7	4321	}
<>	144:ef7eb2e8f9f7	4322
<>	144:ef7eb2e8f9f7	4323	/**
<>	144:ef7eb2e8f9f7	4324	* @brief Output Compare callback in non blocking mode
<>	144:ef7eb2e8f9f7	4325	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4326	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4327	* @retval None
<>	144:ef7eb2e8f9f7	4328	*/
<>	144:ef7eb2e8f9f7	4329	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4330	{
<>	144:ef7eb2e8f9f7	4331	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4332	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4333	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4334	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4335	*/
<>	144:ef7eb2e8f9f7	4336	}
<>	144:ef7eb2e8f9f7	4337
<>	144:ef7eb2e8f9f7	4338	/**
<>	144:ef7eb2e8f9f7	4339	* @brief Input Capture callback in non blocking mode
<>	144:ef7eb2e8f9f7	4340	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4341	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4342	* @retval None
<>	144:ef7eb2e8f9f7	4343	*/
<>	144:ef7eb2e8f9f7	4344	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4345	{
<>	144:ef7eb2e8f9f7	4346	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4347	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4348	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4349	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4350	*/
<>	144:ef7eb2e8f9f7	4351	}
<>	144:ef7eb2e8f9f7	4352
<>	144:ef7eb2e8f9f7	4353	/**
<>	144:ef7eb2e8f9f7	4354	* @brief PWM Pulse finished callback in non blocking mode
<>	144:ef7eb2e8f9f7	4355	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4356	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4357	* @retval None
<>	144:ef7eb2e8f9f7	4358	*/
<>	144:ef7eb2e8f9f7	4359	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4360	{
<>	144:ef7eb2e8f9f7	4361	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4362	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4363	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4364	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4365	*/
<>	144:ef7eb2e8f9f7	4366	}
<>	144:ef7eb2e8f9f7	4367
<>	144:ef7eb2e8f9f7	4368	/**
<>	144:ef7eb2e8f9f7	4369	* @brief Hall Trigger detection callback in non blocking mode
<>	144:ef7eb2e8f9f7	4370	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4371	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4372	* @retval None
<>	144:ef7eb2e8f9f7	4373	*/
<>	144:ef7eb2e8f9f7	4374	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4375	{
<>	144:ef7eb2e8f9f7	4376	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4377	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4378	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4379	the HAL_TIM_TriggerCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4380	*/
<>	144:ef7eb2e8f9f7	4381	}
<>	144:ef7eb2e8f9f7	4382
<>	144:ef7eb2e8f9f7	4383	/**
<>	144:ef7eb2e8f9f7	4384	* @brief Timer error callback in non blocking mode
<>	144:ef7eb2e8f9f7	4385	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4386	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4387	* @retval None
<>	144:ef7eb2e8f9f7	4388	*/
<>	144:ef7eb2e8f9f7	4389	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4390	{
<>	144:ef7eb2e8f9f7	4391	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4392	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4393	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4394	the HAL_TIM_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4395	*/
<>	144:ef7eb2e8f9f7	4396	}
<>	144:ef7eb2e8f9f7	4397	/**
<>	144:ef7eb2e8f9f7	4398	* @}
<>	144:ef7eb2e8f9f7	4399	*/
<>	144:ef7eb2e8f9f7	4400
<>	144:ef7eb2e8f9f7	4401	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<>	144:ef7eb2e8f9f7	4402	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	4403	*
<>	144:ef7eb2e8f9f7	4404	@verbatim
<>	144:ef7eb2e8f9f7	4405	==============================================================================
<>	144:ef7eb2e8f9f7	4406	##### Peripheral State functions #####
<>	144:ef7eb2e8f9f7	4407	==============================================================================
<>	144:ef7eb2e8f9f7	4408	[..]
<>	144:ef7eb2e8f9f7	4409	This subsection permits to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	4410	and the data flow.
<>	144:ef7eb2e8f9f7	4411
<>	144:ef7eb2e8f9f7	4412	@endverbatim
<>	144:ef7eb2e8f9f7	4413	* @{
<>	144:ef7eb2e8f9f7	4414	*/
<>	144:ef7eb2e8f9f7	4415
<>	144:ef7eb2e8f9f7	4416	/**
<>	144:ef7eb2e8f9f7	4417	* @brief Return the TIM Base state
<>	144:ef7eb2e8f9f7	4418	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4419	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4420	* @retval HAL state
<>	144:ef7eb2e8f9f7	4421	*/
<>	144:ef7eb2e8f9f7	4422	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4423	{
<>	144:ef7eb2e8f9f7	4424	return htim->State;
<>	144:ef7eb2e8f9f7	4425	}
<>	144:ef7eb2e8f9f7	4426
<>	144:ef7eb2e8f9f7	4427	/**
<>	144:ef7eb2e8f9f7	4428	* @brief Return the TIM OC state
<>	144:ef7eb2e8f9f7	4429	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4430	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4431	* @retval HAL state
<>	144:ef7eb2e8f9f7	4432	*/
<>	144:ef7eb2e8f9f7	4433	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4434	{
<>	144:ef7eb2e8f9f7	4435	return htim->State;
<>	144:ef7eb2e8f9f7	4436	}
<>	144:ef7eb2e8f9f7	4437
<>	144:ef7eb2e8f9f7	4438	/**
<>	144:ef7eb2e8f9f7	4439	* @brief Return the TIM PWM state
<>	144:ef7eb2e8f9f7	4440	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4441	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4442	* @retval HAL state
<>	144:ef7eb2e8f9f7	4443	*/
<>	144:ef7eb2e8f9f7	4444	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4445	{
<>	144:ef7eb2e8f9f7	4446	return htim->State;
<>	144:ef7eb2e8f9f7	4447	}
<>	144:ef7eb2e8f9f7	4448
<>	144:ef7eb2e8f9f7	4449	/**
<>	144:ef7eb2e8f9f7	4450	* @brief Return the TIM Input Capture state
<>	144:ef7eb2e8f9f7	4451	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4452	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4453	* @retval HAL state
<>	144:ef7eb2e8f9f7	4454	*/
<>	144:ef7eb2e8f9f7	4455	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4456	{
<>	144:ef7eb2e8f9f7	4457	return htim->State;
<>	144:ef7eb2e8f9f7	4458	}
<>	144:ef7eb2e8f9f7	4459
<>	144:ef7eb2e8f9f7	4460	/**
<>	144:ef7eb2e8f9f7	4461	* @brief Return the TIM One Pulse Mode state
<>	144:ef7eb2e8f9f7	4462	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4463	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4464	* @retval HAL state
<>	144:ef7eb2e8f9f7	4465	*/
<>	144:ef7eb2e8f9f7	4466	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4467	{
<>	144:ef7eb2e8f9f7	4468	return htim->State;
<>	144:ef7eb2e8f9f7	4469	}
<>	144:ef7eb2e8f9f7	4470
<>	144:ef7eb2e8f9f7	4471	/**
<>	144:ef7eb2e8f9f7	4472	* @brief Return the TIM Encoder Mode state
<>	144:ef7eb2e8f9f7	4473	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4474	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4475	* @retval HAL state
<>	144:ef7eb2e8f9f7	4476	*/
<>	144:ef7eb2e8f9f7	4477	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4478	{
<>	144:ef7eb2e8f9f7	4479	return htim->State;
<>	144:ef7eb2e8f9f7	4480	}
<>	144:ef7eb2e8f9f7	4481	/**
<>	144:ef7eb2e8f9f7	4482	* @}
<>	144:ef7eb2e8f9f7	4483	*/
<>	144:ef7eb2e8f9f7	4484
<>	144:ef7eb2e8f9f7	4485	/**
<>	144:ef7eb2e8f9f7	4486	* @brief Time Base configuration
<>	144:ef7eb2e8f9f7	4487	* @param TIMx: TIM peripheral
<>	144:ef7eb2e8f9f7	4488	* @param Structure: pointer on TIM Time Base required parameters
<>	144:ef7eb2e8f9f7	4489	* @retval None
<>	144:ef7eb2e8f9f7	4490	*/
<>	144:ef7eb2e8f9f7	4491	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
<>	144:ef7eb2e8f9f7	4492	{
<>	144:ef7eb2e8f9f7	4493	uint32_t tmpcr1 = 0U;
<>	144:ef7eb2e8f9f7	4494	tmpcr1 = TIMx->CR1;
<>	144:ef7eb2e8f9f7	4495
<>	144:ef7eb2e8f9f7	4496	/* Set TIM Time Base Unit parameters ---------------------------------------*/
<>	144:ef7eb2e8f9f7	4497	if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4498	{
<>	144:ef7eb2e8f9f7	4499	/* Select the Counter Mode */
<>	144:ef7eb2e8f9f7	4500	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
<>	144:ef7eb2e8f9f7	4501	tmpcr1 \|= Structure->CounterMode;
<>	144:ef7eb2e8f9f7	4502	}
<>	144:ef7eb2e8f9f7	4503
<>	144:ef7eb2e8f9f7	4504	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4505	{
<>	144:ef7eb2e8f9f7	4506	/* Set the clock division */
<>	144:ef7eb2e8f9f7	4507	tmpcr1 &= ~TIM_CR1_CKD;
<>	144:ef7eb2e8f9f7	4508	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
<>	144:ef7eb2e8f9f7	4509	}
<>	144:ef7eb2e8f9f7	4510
AnnaBridge	167:e84263d55307	4511	/* Set the auto-reload preload */
AnnaBridge	167:e84263d55307	4512	tmpcr1 &= ~TIM_CR1_ARPE;
AnnaBridge	167:e84263d55307	4513	tmpcr1 \|= (uint32_t)Structure->AutoReloadPreload;
AnnaBridge	167:e84263d55307	4514
<>	144:ef7eb2e8f9f7	4515	TIMx->CR1 = tmpcr1;
<>	144:ef7eb2e8f9f7	4516
<>	144:ef7eb2e8f9f7	4517	/* Set the Auto-reload value */
<>	144:ef7eb2e8f9f7	4518	TIMx->ARR = (uint32_t)Structure->Period ;
<>	144:ef7eb2e8f9f7	4519
<>	144:ef7eb2e8f9f7	4520	/* Set the Prescaler value */
<>	144:ef7eb2e8f9f7	4521	TIMx->PSC = (uint32_t)Structure->Prescaler;
<>	144:ef7eb2e8f9f7	4522
<>	144:ef7eb2e8f9f7	4523	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4524	{
<>	144:ef7eb2e8f9f7	4525	/* Set the Repetition Counter value */
<>	144:ef7eb2e8f9f7	4526	TIMx->RCR = Structure->RepetitionCounter;
<>	144:ef7eb2e8f9f7	4527	}
<>	144:ef7eb2e8f9f7	4528
<>	144:ef7eb2e8f9f7	4529	/* Generate an update event to reload the Prescaler
<>	144:ef7eb2e8f9f7	4530	and the repetition counter(only for TIM1 and TIM8) value immediately */
<>	144:ef7eb2e8f9f7	4531	TIMx->EGR = TIM_EGR_UG;
<>	144:ef7eb2e8f9f7	4532	}
<>	144:ef7eb2e8f9f7	4533
<>	144:ef7eb2e8f9f7	4534	/**
<>	144:ef7eb2e8f9f7	4535	* @brief Configure the TI1 as Input.
<>	144:ef7eb2e8f9f7	4536	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	4537	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	4538	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4539	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	4540	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	4541	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	4542	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	4543	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4544	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	4545	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	4546	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	4547	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	4548	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	4549	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<>	144:ef7eb2e8f9f7	4550	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<>	144:ef7eb2e8f9f7	4551	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	4552	* @retval None
<>	144:ef7eb2e8f9f7	4553	*/
<>	144:ef7eb2e8f9f7	4554	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	4555	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	4556	{
<>	144:ef7eb2e8f9f7	4557	uint32_t tmpccmr1 = 0U;
<>	144:ef7eb2e8f9f7	4558	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4559
<>	144:ef7eb2e8f9f7	4560	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4561	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4562	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4563	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4564
<>	144:ef7eb2e8f9f7	4565	/* Select the Input */
<>	144:ef7eb2e8f9f7	4566	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4567	{
<>	144:ef7eb2e8f9f7	4568	tmpccmr1 &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4569	tmpccmr1 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	4570	}
<>	144:ef7eb2e8f9f7	4571	else
<>	144:ef7eb2e8f9f7	4572	{
<>	144:ef7eb2e8f9f7	4573	tmpccmr1 &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4574	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
<>	144:ef7eb2e8f9f7	4575	}
<>	144:ef7eb2e8f9f7	4576
<>	144:ef7eb2e8f9f7	4577	/* Set the filter */
<>	144:ef7eb2e8f9f7	4578	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	144:ef7eb2e8f9f7	4579	tmpccmr1 \|= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
<>	144:ef7eb2e8f9f7	4580
<>	144:ef7eb2e8f9f7	4581	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	4582	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	4583	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
<>	144:ef7eb2e8f9f7	4584
<>	144:ef7eb2e8f9f7	4585	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	4586	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	4587	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4588	}
<>	144:ef7eb2e8f9f7	4589
<>	144:ef7eb2e8f9f7	4590	/**
<>	144:ef7eb2e8f9f7	4591	* @brief Time Output Compare 2 configuration
<>	144:ef7eb2e8f9f7	4592	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4593	* @param OC_Config: The output configuration structure
<>	144:ef7eb2e8f9f7	4594	* @retval None
<>	144:ef7eb2e8f9f7	4595	*/
<>	144:ef7eb2e8f9f7	4596	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4597	{
<>	144:ef7eb2e8f9f7	4598	uint32_t tmpccmrx = 0U;
<>	144:ef7eb2e8f9f7	4599	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4600	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4601
<>	144:ef7eb2e8f9f7	4602	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4603	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	4604
<>	144:ef7eb2e8f9f7	4605	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4606	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4607	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4608	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4609
<>	144:ef7eb2e8f9f7	4610	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4611	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4612
<>	144:ef7eb2e8f9f7	4613	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4614	tmpccmrx &= ~TIM_CCMR1_OC2M;
<>	144:ef7eb2e8f9f7	4615	tmpccmrx &= ~TIM_CCMR1_CC2S;
<>	144:ef7eb2e8f9f7	4616
<>	144:ef7eb2e8f9f7	4617	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4618	tmpccmrx \|= (OC_Config->OCMode << 8U);
<>	144:ef7eb2e8f9f7	4619
<>	144:ef7eb2e8f9f7	4620	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4621	tmpccer &= ~TIM_CCER_CC2P;
<>	144:ef7eb2e8f9f7	4622	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4623	tmpccer \|= (OC_Config->OCPolarity << 4U);
<>	144:ef7eb2e8f9f7	4624
<>	144:ef7eb2e8f9f7	4625	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4626	{
<>	144:ef7eb2e8f9f7	4627	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4628
<>	144:ef7eb2e8f9f7	4629	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4630	tmpccer &= ~TIM_CCER_CC2NP;
<>	144:ef7eb2e8f9f7	4631	/* Set the Output N Polarity */
<>	144:ef7eb2e8f9f7	4632	tmpccer \|= (OC_Config->OCNPolarity << 4U);
<>	144:ef7eb2e8f9f7	4633	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4634	tmpccer &= ~TIM_CCER_CC2NE;
<>	144:ef7eb2e8f9f7	4635
<>	144:ef7eb2e8f9f7	4636	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4637	tmpcr2 &= ~TIM_CR2_OIS2;
<>	144:ef7eb2e8f9f7	4638	tmpcr2 &= ~TIM_CR2_OIS2N;
<>	144:ef7eb2e8f9f7	4639	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4640	tmpcr2 \|= (OC_Config->OCIdleState << 2U);
<>	144:ef7eb2e8f9f7	4641	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4642	tmpcr2 \|= (OC_Config->OCNIdleState << 2U);
<>	144:ef7eb2e8f9f7	4643	}
<>	144:ef7eb2e8f9f7	4644	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4645	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4646
<>	144:ef7eb2e8f9f7	4647	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4648	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4649
<>	144:ef7eb2e8f9f7	4650	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4651	TIMx->CCR2 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4652
<>	144:ef7eb2e8f9f7	4653	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4654	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4655	}
<>	144:ef7eb2e8f9f7	4656
<>	144:ef7eb2e8f9f7	4657	/**
<>	144:ef7eb2e8f9f7	4658	* @brief TIM DMA Delay Pulse complete callback.
<>	144:ef7eb2e8f9f7	4659	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4660	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4661	* @retval None
<>	144:ef7eb2e8f9f7	4662	*/
<>	144:ef7eb2e8f9f7	4663	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4664	{
<>	144:ef7eb2e8f9f7	4665	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4666
<>	144:ef7eb2e8f9f7	4667	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4668
<>	144:ef7eb2e8f9f7	4669	if(hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4670	{
<>	144:ef7eb2e8f9f7	4671	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4672	}
<>	144:ef7eb2e8f9f7	4673	else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4674	{
<>	144:ef7eb2e8f9f7	4675	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4676	}
<>	144:ef7eb2e8f9f7	4677	else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4678	{
<>	144:ef7eb2e8f9f7	4679	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4680	}
<>	144:ef7eb2e8f9f7	4681	else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4682	{
<>	144:ef7eb2e8f9f7	4683	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4684	}
<>	144:ef7eb2e8f9f7	4685
<>	144:ef7eb2e8f9f7	4686	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	4687
<>	144:ef7eb2e8f9f7	4688	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4689	}
<>	144:ef7eb2e8f9f7	4690
<>	144:ef7eb2e8f9f7	4691	/**
<>	144:ef7eb2e8f9f7	4692	* @brief TIM DMA error callback
<>	144:ef7eb2e8f9f7	4693	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4694	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4695	* @retval None
<>	144:ef7eb2e8f9f7	4696	*/
<>	144:ef7eb2e8f9f7	4697	void TIM_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4698	{
<>	144:ef7eb2e8f9f7	4699	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4700
<>	144:ef7eb2e8f9f7	4701	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4702
<>	144:ef7eb2e8f9f7	4703	HAL_TIM_ErrorCallback(htim);
<>	144:ef7eb2e8f9f7	4704	}
<>	144:ef7eb2e8f9f7	4705
<>	144:ef7eb2e8f9f7	4706	/**
<>	144:ef7eb2e8f9f7	4707	* @brief TIM DMA Capture complete callback.
<>	144:ef7eb2e8f9f7	4708	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4709	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4710	* @retval None
<>	144:ef7eb2e8f9f7	4711	*/
<>	144:ef7eb2e8f9f7	4712	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4713	{
<>	144:ef7eb2e8f9f7	4714	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4715
<>	144:ef7eb2e8f9f7	4716	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4717
<>	144:ef7eb2e8f9f7	4718	if(hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4719	{
<>	144:ef7eb2e8f9f7	4720	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4721	}
<>	144:ef7eb2e8f9f7	4722	else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4723	{
<>	144:ef7eb2e8f9f7	4724	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4725	}
<>	144:ef7eb2e8f9f7	4726	else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4727	{
<>	144:ef7eb2e8f9f7	4728	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4729	}
<>	144:ef7eb2e8f9f7	4730	else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4731	{
<>	144:ef7eb2e8f9f7	4732	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4733	}
<>	144:ef7eb2e8f9f7	4734
<>	144:ef7eb2e8f9f7	4735	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	4736
<>	144:ef7eb2e8f9f7	4737	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4738	}
<>	144:ef7eb2e8f9f7	4739
<>	144:ef7eb2e8f9f7	4740	/**
<>	144:ef7eb2e8f9f7	4741	* @brief Enables or disables the TIM Capture Compare Channel x.
<>	144:ef7eb2e8f9f7	4742	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4743	* @param Channel: specifies the TIM Channel
<>	144:ef7eb2e8f9f7	4744	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4745	* @arg TIM_Channel_1: TIM Channel 1
<>	144:ef7eb2e8f9f7	4746	* @arg TIM_Channel_2: TIM Channel 2
<>	144:ef7eb2e8f9f7	4747	* @arg TIM_Channel_3: TIM Channel 3
<>	144:ef7eb2e8f9f7	4748	* @arg TIM_Channel_4: TIM Channel 4
<>	144:ef7eb2e8f9f7	4749	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
<>	144:ef7eb2e8f9f7	4750	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<>	144:ef7eb2e8f9f7	4751	* @retval None
<>	144:ef7eb2e8f9f7	4752	*/
<>	144:ef7eb2e8f9f7	4753	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<>	144:ef7eb2e8f9f7	4754	{
<>	144:ef7eb2e8f9f7	4755	uint32_t tmp = 0;
<>	144:ef7eb2e8f9f7	4756
<>	144:ef7eb2e8f9f7	4757	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4758	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	144:ef7eb2e8f9f7	4759	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	4760
<>	144:ef7eb2e8f9f7	4761	tmp = TIM_CCER_CC1E << Channel;
<>	144:ef7eb2e8f9f7	4762
<>	144:ef7eb2e8f9f7	4763	/* Reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	4764	TIMx->CCER &= ~tmp;
<>	144:ef7eb2e8f9f7	4765
<>	144:ef7eb2e8f9f7	4766	/* Set or reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	4767	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
<>	144:ef7eb2e8f9f7	4768	}
<>	144:ef7eb2e8f9f7	4769
<>	144:ef7eb2e8f9f7	4770	/**
<>	144:ef7eb2e8f9f7	4771	* @brief TIM DMA Period Elapse complete callback.
<>	144:ef7eb2e8f9f7	4772	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4773	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4774	* @retval None
<>	144:ef7eb2e8f9f7	4775	*/
<>	144:ef7eb2e8f9f7	4776	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4777	{
<>	144:ef7eb2e8f9f7	4778	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4779
<>	144:ef7eb2e8f9f7	4780	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4781
<>	144:ef7eb2e8f9f7	4782	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	4783	}
<>	144:ef7eb2e8f9f7	4784
<>	144:ef7eb2e8f9f7	4785	/**
<>	144:ef7eb2e8f9f7	4786	* @brief TIM DMA Trigger callback.
<>	144:ef7eb2e8f9f7	4787	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4788	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	4789	* @retval None
<>	144:ef7eb2e8f9f7	4790	*/
<>	144:ef7eb2e8f9f7	4791	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4792	{
<>	144:ef7eb2e8f9f7	4793	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4794
<>	144:ef7eb2e8f9f7	4795	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4796
<>	144:ef7eb2e8f9f7	4797	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	4798	}
<>	144:ef7eb2e8f9f7	4799
<>	144:ef7eb2e8f9f7	4800	/**
<>	144:ef7eb2e8f9f7	4801	* @brief Time Output Compare 1 configuration
<>	144:ef7eb2e8f9f7	4802	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4803	* @param OC_Config: The output configuration structure
<>	144:ef7eb2e8f9f7	4804	* @retval None
<>	144:ef7eb2e8f9f7	4805	*/
<>	144:ef7eb2e8f9f7	4806	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4807	{
<>	144:ef7eb2e8f9f7	4808	uint32_t tmpccmrx = 0U;
<>	144:ef7eb2e8f9f7	4809	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4810	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4811
<>	144:ef7eb2e8f9f7	4812	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4813	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4814
<>	144:ef7eb2e8f9f7	4815	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4816	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4817	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4818	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4819
<>	144:ef7eb2e8f9f7	4820	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4821	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4822
<>	144:ef7eb2e8f9f7	4823	/* Reset the Output Compare Mode Bits */
<>	144:ef7eb2e8f9f7	4824	tmpccmrx &= ~TIM_CCMR1_OC1M;
<>	144:ef7eb2e8f9f7	4825	tmpccmrx &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4826	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4827	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4828
<>	144:ef7eb2e8f9f7	4829	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4830	tmpccer &= ~TIM_CCER_CC1P;
<>	144:ef7eb2e8f9f7	4831	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4832	tmpccer \|= OC_Config->OCPolarity;
<>	144:ef7eb2e8f9f7	4833
<>	144:ef7eb2e8f9f7	4834
<>	144:ef7eb2e8f9f7	4835	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4836	{
<>	144:ef7eb2e8f9f7	4837	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4838	tmpccer &= ~TIM_CCER_CC1NP;
<>	144:ef7eb2e8f9f7	4839	/* Set the Output N Polarity */
<>	144:ef7eb2e8f9f7	4840	tmpccer \|= OC_Config->OCNPolarity;
<>	144:ef7eb2e8f9f7	4841	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4842	tmpccer &= ~TIM_CCER_CC1NE;
<>	144:ef7eb2e8f9f7	4843
<>	144:ef7eb2e8f9f7	4844	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4845	tmpcr2 &= ~TIM_CR2_OIS1;
<>	144:ef7eb2e8f9f7	4846	tmpcr2 &= ~TIM_CR2_OIS1N;
<>	144:ef7eb2e8f9f7	4847	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4848	tmpcr2 \|= OC_Config->OCIdleState;
<>	144:ef7eb2e8f9f7	4849	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4850	tmpcr2 \|= OC_Config->OCNIdleState;
<>	144:ef7eb2e8f9f7	4851	}
<>	144:ef7eb2e8f9f7	4852	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4853	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4854
<>	144:ef7eb2e8f9f7	4855	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4856	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4857
<>	144:ef7eb2e8f9f7	4858	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4859	TIMx->CCR1 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4860
<>	144:ef7eb2e8f9f7	4861	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4862	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4863	}
<>	144:ef7eb2e8f9f7	4864
<>	144:ef7eb2e8f9f7	4865	/**
<>	144:ef7eb2e8f9f7	4866	* @brief Time Output Compare 3 configuration
<>	144:ef7eb2e8f9f7	4867	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4868	* @param OC_Config: The output configuration structure
<>	144:ef7eb2e8f9f7	4869	* @retval None
<>	144:ef7eb2e8f9f7	4870	*/
<>	144:ef7eb2e8f9f7	4871	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4872	{
<>	144:ef7eb2e8f9f7	4873	uint32_t tmpccmrx = 0U;
<>	144:ef7eb2e8f9f7	4874	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4875	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4876
<>	144:ef7eb2e8f9f7	4877	/* Disable the Channel 3: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4878	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	4879
<>	144:ef7eb2e8f9f7	4880	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4881	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4882	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4883	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4884
<>	144:ef7eb2e8f9f7	4885	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4886	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4887
<>	144:ef7eb2e8f9f7	4888	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4889	tmpccmrx &= ~TIM_CCMR2_OC3M;
<>	144:ef7eb2e8f9f7	4890	tmpccmrx &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	4891	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4892	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4893
<>	144:ef7eb2e8f9f7	4894	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4895	tmpccer &= ~TIM_CCER_CC3P;
<>	144:ef7eb2e8f9f7	4896	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4897	tmpccer \|= (OC_Config->OCPolarity << 8U);
<>	144:ef7eb2e8f9f7	4898
<>	144:ef7eb2e8f9f7	4899	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4900	{
<>	144:ef7eb2e8f9f7	4901	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4902	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<>	144:ef7eb2e8f9f7	4903	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4904
<>	144:ef7eb2e8f9f7	4905	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4906	tmpccer &= ~TIM_CCER_CC3NP;
<>	144:ef7eb2e8f9f7	4907	/* Set the Output N Polarity */
<>	144:ef7eb2e8f9f7	4908	tmpccer \|= (OC_Config->OCNPolarity << 8U);
<>	144:ef7eb2e8f9f7	4909	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4910	tmpccer &= ~TIM_CCER_CC3NE;
<>	144:ef7eb2e8f9f7	4911
<>	144:ef7eb2e8f9f7	4912	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4913	tmpcr2 &= ~TIM_CR2_OIS3;
<>	144:ef7eb2e8f9f7	4914	tmpcr2 &= ~TIM_CR2_OIS3N;
<>	144:ef7eb2e8f9f7	4915	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4916	tmpcr2 \|= (OC_Config->OCIdleState << 4U);
<>	144:ef7eb2e8f9f7	4917	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4918	tmpcr2 \|= (OC_Config->OCNIdleState << 4U);
<>	144:ef7eb2e8f9f7	4919	}
<>	144:ef7eb2e8f9f7	4920	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4921	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4922
<>	144:ef7eb2e8f9f7	4923	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4924	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4925
<>	144:ef7eb2e8f9f7	4926	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4927	TIMx->CCR3 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4928
<>	144:ef7eb2e8f9f7	4929	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4930	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4931	}
<>	144:ef7eb2e8f9f7	4932
<>	144:ef7eb2e8f9f7	4933	/**
<>	144:ef7eb2e8f9f7	4934	* @brief Time Output Compare 4 configuration
<>	144:ef7eb2e8f9f7	4935	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4936	* @param OC_Config: The output configuration structure
<>	144:ef7eb2e8f9f7	4937	* @retval None
<>	144:ef7eb2e8f9f7	4938	*/
<>	144:ef7eb2e8f9f7	4939	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4940	{
<>	144:ef7eb2e8f9f7	4941	uint32_t tmpccmrx = 0U;
<>	144:ef7eb2e8f9f7	4942	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4943	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4944
<>	144:ef7eb2e8f9f7	4945	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	4946	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	4947
<>	144:ef7eb2e8f9f7	4948	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4949	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4950	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4951	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4952
<>	144:ef7eb2e8f9f7	4953	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4954	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4955
<>	144:ef7eb2e8f9f7	4956	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4957	tmpccmrx &= ~TIM_CCMR2_OC4M;
<>	144:ef7eb2e8f9f7	4958	tmpccmrx &= ~TIM_CCMR2_CC4S;
<>	144:ef7eb2e8f9f7	4959
<>	144:ef7eb2e8f9f7	4960	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4961	tmpccmrx \|= (OC_Config->OCMode << 8U);
<>	144:ef7eb2e8f9f7	4962
<>	144:ef7eb2e8f9f7	4963	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4964	tmpccer &= ~TIM_CCER_CC4P;
<>	144:ef7eb2e8f9f7	4965	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4966	tmpccer \|= (OC_Config->OCPolarity << 12U);
<>	144:ef7eb2e8f9f7	4967
<>	144:ef7eb2e8f9f7	4968	/if((TIMx == TIM1) \|\| (TIMx == TIM8))/
<>	144:ef7eb2e8f9f7	4969	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	4970	{
<>	144:ef7eb2e8f9f7	4971	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4972	/* Reset the Output Compare IDLE State */
<>	144:ef7eb2e8f9f7	4973	tmpcr2 &= ~TIM_CR2_OIS4;
<>	144:ef7eb2e8f9f7	4974	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4975	tmpcr2 \|= (OC_Config->OCIdleState << 6U);
<>	144:ef7eb2e8f9f7	4976	}
<>	144:ef7eb2e8f9f7	4977	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4978	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4979
<>	144:ef7eb2e8f9f7	4980	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4981	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4982
<>	144:ef7eb2e8f9f7	4983	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4984	TIMx->CCR4 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4985
<>	144:ef7eb2e8f9f7	4986	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4987	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4988	}
<>	144:ef7eb2e8f9f7	4989
<>	144:ef7eb2e8f9f7	4990	/**
<>	144:ef7eb2e8f9f7	4991	* @brief Time Output Compare 4 configuration
<>	144:ef7eb2e8f9f7	4992	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4993	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4994	* @param sSlaveConfig: The slave configuration structure
<>	144:ef7eb2e8f9f7	4995	* @retval None
<>	144:ef7eb2e8f9f7	4996	*/
<>	144:ef7eb2e8f9f7	4997	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	4998	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	4999	{
<>	144:ef7eb2e8f9f7	5000	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	5001	uint32_t tmpccmr1 = 0U;
<>	144:ef7eb2e8f9f7	5002	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5003
<>	144:ef7eb2e8f9f7	5004	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	5005	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	5006
<>	144:ef7eb2e8f9f7	5007	/* Reset the Trigger Selection Bits */
<>	144:ef7eb2e8f9f7	5008	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	5009	/* Set the Input Trigger source */
<>	144:ef7eb2e8f9f7	5010	tmpsmcr \|= sSlaveConfig->InputTrigger;
<>	144:ef7eb2e8f9f7	5011
<>	144:ef7eb2e8f9f7	5012	/* Reset the slave mode Bits */
<>	144:ef7eb2e8f9f7	5013	tmpsmcr &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	5014	/* Set the slave mode */
<>	144:ef7eb2e8f9f7	5015	tmpsmcr \|= sSlaveConfig->SlaveMode;
<>	144:ef7eb2e8f9f7	5016
<>	144:ef7eb2e8f9f7	5017	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	5018	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	5019
<>	144:ef7eb2e8f9f7	5020	/* Configure the trigger prescaler, filter, and polarity */
<>	144:ef7eb2e8f9f7	5021	switch (sSlaveConfig->InputTrigger)
<>	144:ef7eb2e8f9f7	5022	{
<>	144:ef7eb2e8f9f7	5023	case TIM_TS_ETRF:
<>	144:ef7eb2e8f9f7	5024	{
<>	144:ef7eb2e8f9f7	5025	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5026	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5027	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<>	144:ef7eb2e8f9f7	5028	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	5029	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	5030	/* Configure the ETR Trigger source */
<>	144:ef7eb2e8f9f7	5031	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	5032	sSlaveConfig->TriggerPrescaler,
<>	144:ef7eb2e8f9f7	5033	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	5034	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	5035	}
<>	144:ef7eb2e8f9f7	5036	break;
<>	144:ef7eb2e8f9f7	5037
<>	144:ef7eb2e8f9f7	5038	case TIM_TS_TI1F_ED:
<>	144:ef7eb2e8f9f7	5039	{
<>	144:ef7eb2e8f9f7	5040	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5041	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5042	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	5043
<>	144:ef7eb2e8f9f7	5044	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	5045	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	5046	htim->Instance->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	5047	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	5048
<>	144:ef7eb2e8f9f7	5049	/* Set the filter */
<>	144:ef7eb2e8f9f7	5050	tmpccmr1 &= ~TIM_CCMR1_IC1F;
AnnaBridge	167:e84263d55307	5051	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4U);
<>	144:ef7eb2e8f9f7	5052
<>	144:ef7eb2e8f9f7	5053	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5054	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	5055	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5056
<>	144:ef7eb2e8f9f7	5057	}
<>	144:ef7eb2e8f9f7	5058	break;
<>	144:ef7eb2e8f9f7	5059
<>	144:ef7eb2e8f9f7	5060	case TIM_TS_TI1FP1:
<>	144:ef7eb2e8f9f7	5061	{
<>	144:ef7eb2e8f9f7	5062	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5063	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5064	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	5065	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	5066
<>	144:ef7eb2e8f9f7	5067	/* Configure TI1 Filter and Polarity */
<>	144:ef7eb2e8f9f7	5068	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	5069	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	5070	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	5071	}
<>	144:ef7eb2e8f9f7	5072	break;
<>	144:ef7eb2e8f9f7	5073
<>	144:ef7eb2e8f9f7	5074	case TIM_TS_TI2FP2:
<>	144:ef7eb2e8f9f7	5075	{
<>	144:ef7eb2e8f9f7	5076	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5077	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5078	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	5079	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	5080
<>	144:ef7eb2e8f9f7	5081	/* Configure TI2 Filter and Polarity */
<>	144:ef7eb2e8f9f7	5082	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	5083	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	5084	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	5085	}
<>	144:ef7eb2e8f9f7	5086	break;
<>	144:ef7eb2e8f9f7	5087
<>	144:ef7eb2e8f9f7	5088	case TIM_TS_ITR0:
<>	144:ef7eb2e8f9f7	5089	{
<>	144:ef7eb2e8f9f7	5090	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5091	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5092	}
<>	144:ef7eb2e8f9f7	5093	break;
<>	144:ef7eb2e8f9f7	5094
<>	144:ef7eb2e8f9f7	5095	case TIM_TS_ITR1:
<>	144:ef7eb2e8f9f7	5096	{
<>	144:ef7eb2e8f9f7	5097	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5098	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5099	}
<>	144:ef7eb2e8f9f7	5100	break;
<>	144:ef7eb2e8f9f7	5101
<>	144:ef7eb2e8f9f7	5102	case TIM_TS_ITR2:
<>	144:ef7eb2e8f9f7	5103	{
<>	144:ef7eb2e8f9f7	5104	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5105	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5106	}
<>	144:ef7eb2e8f9f7	5107	break;
<>	144:ef7eb2e8f9f7	5108
<>	144:ef7eb2e8f9f7	5109	case TIM_TS_ITR3:
<>	144:ef7eb2e8f9f7	5110	{
<>	144:ef7eb2e8f9f7	5111	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5112	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5113	}
<>	144:ef7eb2e8f9f7	5114	break;
<>	144:ef7eb2e8f9f7	5115
<>	144:ef7eb2e8f9f7	5116	default:
<>	144:ef7eb2e8f9f7	5117	break;
<>	144:ef7eb2e8f9f7	5118	}
<>	144:ef7eb2e8f9f7	5119	}
<>	144:ef7eb2e8f9f7	5120
<>	144:ef7eb2e8f9f7	5121
<>	144:ef7eb2e8f9f7	5122	/**
<>	144:ef7eb2e8f9f7	5123	* @brief Configure the Polarity and Filter for TI1.
<>	144:ef7eb2e8f9f7	5124	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5125	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5126	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5127	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	5128	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	5129	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	5130	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5131	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5132	* @retval None
<>	144:ef7eb2e8f9f7	5133	*/
<>	144:ef7eb2e8f9f7	5134	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5135	{
<>	144:ef7eb2e8f9f7	5136	uint32_t tmpccmr1 = 0U;
<>	144:ef7eb2e8f9f7	5137	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5138
<>	144:ef7eb2e8f9f7	5139	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	5140	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5141	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	5142	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5143
<>	144:ef7eb2e8f9f7	5144	/* Set the filter */
<>	144:ef7eb2e8f9f7	5145	tmpccmr1 &= ~TIM_CCMR1_IC1F;
<>	144:ef7eb2e8f9f7	5146	tmpccmr1 \|= (TIM_ICFilter << 4U);
<>	144:ef7eb2e8f9f7	5147
<>	144:ef7eb2e8f9f7	5148	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	5149	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	5150	tmpccer \|= TIM_ICPolarity;
<>	144:ef7eb2e8f9f7	5151
<>	144:ef7eb2e8f9f7	5152	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5153	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	5154	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5155	}
<>	144:ef7eb2e8f9f7	5156
<>	144:ef7eb2e8f9f7	5157	/**
<>	144:ef7eb2e8f9f7	5158	* @brief Configure the TI2 as Input.
<>	144:ef7eb2e8f9f7	5159	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5160	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5161	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5162	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	5163	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	5164	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	5165	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	5166	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5167	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	5168	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	5169	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5170	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5171	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5172	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<>	144:ef7eb2e8f9f7	5173	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<>	144:ef7eb2e8f9f7	5174	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5175	* @retval None
<>	144:ef7eb2e8f9f7	5176	*/
<>	144:ef7eb2e8f9f7	5177	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5178	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5179	{
<>	144:ef7eb2e8f9f7	5180	uint32_t tmpccmr1 = 0U;
<>	144:ef7eb2e8f9f7	5181	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5182
<>	144:ef7eb2e8f9f7	5183	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	5184	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	5185	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5186	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5187
<>	144:ef7eb2e8f9f7	5188	/* Select the Input */
<>	144:ef7eb2e8f9f7	5189	tmpccmr1 &= ~TIM_CCMR1_CC2S;
<>	144:ef7eb2e8f9f7	5190	tmpccmr1 \|= (TIM_ICSelection << 8U);
<>	144:ef7eb2e8f9f7	5191
<>	144:ef7eb2e8f9f7	5192	/* Set the filter */
<>	144:ef7eb2e8f9f7	5193	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	144:ef7eb2e8f9f7	5194	tmpccmr1 \|= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
<>	144:ef7eb2e8f9f7	5195
<>	144:ef7eb2e8f9f7	5196	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	5197	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	144:ef7eb2e8f9f7	5198	tmpccer \|= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
<>	144:ef7eb2e8f9f7	5199
<>	144:ef7eb2e8f9f7	5200	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5201	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	5202	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5203	}
<>	144:ef7eb2e8f9f7	5204
<>	144:ef7eb2e8f9f7	5205	/**
<>	144:ef7eb2e8f9f7	5206	* @brief Configure the Polarity and Filter for TI2.
<>	144:ef7eb2e8f9f7	5207	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5208	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5209	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5210	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	5211	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	5212	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	5213	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5214	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5215	* @retval None
<>	144:ef7eb2e8f9f7	5216	*/
<>	144:ef7eb2e8f9f7	5217	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5218	{
<>	144:ef7eb2e8f9f7	5219	uint32_t tmpccmr1 = 0U;
<>	144:ef7eb2e8f9f7	5220	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5221
<>	144:ef7eb2e8f9f7	5222	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	5223	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	5224	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5225	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5226
<>	144:ef7eb2e8f9f7	5227	/* Set the filter */
<>	144:ef7eb2e8f9f7	5228	tmpccmr1 &= ~TIM_CCMR1_IC2F;
<>	144:ef7eb2e8f9f7	5229	tmpccmr1 \|= (TIM_ICFilter << 12U);
<>	144:ef7eb2e8f9f7	5230
<>	144:ef7eb2e8f9f7	5231	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	5232	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	144:ef7eb2e8f9f7	5233	tmpccer \|= (TIM_ICPolarity << 4U);
<>	144:ef7eb2e8f9f7	5234
<>	144:ef7eb2e8f9f7	5235	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5236	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	5237	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5238	}
<>	144:ef7eb2e8f9f7	5239
<>	144:ef7eb2e8f9f7	5240	/**
<>	144:ef7eb2e8f9f7	5241	* @brief Configure the TI3 as Input.
<>	144:ef7eb2e8f9f7	5242	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5243	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5244	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5245	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	5246	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	5247	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	5248	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	5249	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5250	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	5251	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	5252	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5253	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5254	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5255	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<>	144:ef7eb2e8f9f7	5256	* (on channel4 path) is used as the input signal. Therefore CCMR2 must be
<>	144:ef7eb2e8f9f7	5257	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5258	* @retval None
<>	144:ef7eb2e8f9f7	5259	*/
<>	144:ef7eb2e8f9f7	5260	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5261	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5262	{
<>	144:ef7eb2e8f9f7	5263	uint32_t tmpccmr2 = 0U;
<>	144:ef7eb2e8f9f7	5264	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5265
<>	144:ef7eb2e8f9f7	5266	/* Disable the Channel 3: Reset the CC3E Bit */
<>	144:ef7eb2e8f9f7	5267	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	5268	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	5269	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5270
<>	144:ef7eb2e8f9f7	5271	/* Select the Input */
<>	144:ef7eb2e8f9f7	5272	tmpccmr2 &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	5273	tmpccmr2 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	5274
<>	144:ef7eb2e8f9f7	5275	/* Set the filter */
<>	144:ef7eb2e8f9f7	5276	tmpccmr2 &= ~TIM_CCMR2_IC3F;
<>	144:ef7eb2e8f9f7	5277	tmpccmr2 \|= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
<>	144:ef7eb2e8f9f7	5278
<>	144:ef7eb2e8f9f7	5279	/* Select the Polarity and set the CC3E Bit */
<>	144:ef7eb2e8f9f7	5280	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
<>	144:ef7eb2e8f9f7	5281	tmpccer \|= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
<>	144:ef7eb2e8f9f7	5282
<>	144:ef7eb2e8f9f7	5283	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	5284	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	5285	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5286	}
<>	144:ef7eb2e8f9f7	5287
<>	144:ef7eb2e8f9f7	5288	/**
<>	144:ef7eb2e8f9f7	5289	* @brief Configure the TI4 as Input.
<>	144:ef7eb2e8f9f7	5290	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5291	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5292	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5293	* @arg TIM_ICPolarity_Rising
<>	144:ef7eb2e8f9f7	5294	* @arg TIM_ICPolarity_Falling
<>	144:ef7eb2e8f9f7	5295	* @arg TIM_ICPolarity_BothEdge
<>	144:ef7eb2e8f9f7	5296	* @param TIM_ICSelection: specifies the input to be used.
<>	144:ef7eb2e8f9f7	5297	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5298	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	5299	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	5300	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5301	* @param TIM_ICFilter: Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5302	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5303	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<>	144:ef7eb2e8f9f7	5304	* (on channel3 path) is used as the input signal. Therefore CCMR2 must be
<>	144:ef7eb2e8f9f7	5305	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5306	* @retval None
<>	144:ef7eb2e8f9f7	5307	*/
<>	144:ef7eb2e8f9f7	5308	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5309	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5310	{
<>	144:ef7eb2e8f9f7	5311	uint32_t tmpccmr2 = 0U;
<>	144:ef7eb2e8f9f7	5312	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5313
<>	144:ef7eb2e8f9f7	5314	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	5315	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	5316	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	5317	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5318
<>	144:ef7eb2e8f9f7	5319	/* Select the Input */
<>	144:ef7eb2e8f9f7	5320	tmpccmr2 &= ~TIM_CCMR2_CC4S;
<>	144:ef7eb2e8f9f7	5321	tmpccmr2 \|= (TIM_ICSelection << 8U);
<>	144:ef7eb2e8f9f7	5322
<>	144:ef7eb2e8f9f7	5323	/* Set the filter */
<>	144:ef7eb2e8f9f7	5324	tmpccmr2 &= ~TIM_CCMR2_IC4F;
<>	144:ef7eb2e8f9f7	5325	tmpccmr2 \|= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
<>	144:ef7eb2e8f9f7	5326
<>	144:ef7eb2e8f9f7	5327	/* Select the Polarity and set the CC4E Bit */
<>	144:ef7eb2e8f9f7	5328	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
<>	144:ef7eb2e8f9f7	5329	tmpccer \|= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
<>	144:ef7eb2e8f9f7	5330
<>	144:ef7eb2e8f9f7	5331	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	5332	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	5333	TIMx->CCER = tmpccer ;
<>	144:ef7eb2e8f9f7	5334	}
<>	144:ef7eb2e8f9f7	5335
<>	144:ef7eb2e8f9f7	5336	/**
<>	144:ef7eb2e8f9f7	5337	* @brief Selects the Input Trigger source
<>	144:ef7eb2e8f9f7	5338	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5339	* @param TIM_ITRx: The Input Trigger source.
<>	144:ef7eb2e8f9f7	5340	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5341	* @arg TIM_TS_ITR0: Internal Trigger 0
<>	144:ef7eb2e8f9f7	5342	* @arg TIM_TS_ITR1: Internal Trigger 1
<>	144:ef7eb2e8f9f7	5343	* @arg TIM_TS_ITR2: Internal Trigger 2
<>	144:ef7eb2e8f9f7	5344	* @arg TIM_TS_ITR3: Internal Trigger 3
<>	144:ef7eb2e8f9f7	5345	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
<>	144:ef7eb2e8f9f7	5346	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
<>	144:ef7eb2e8f9f7	5347	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
<>	144:ef7eb2e8f9f7	5348	* @arg TIM_TS_ETRF: External Trigger input
<>	144:ef7eb2e8f9f7	5349	* @retval None
<>	144:ef7eb2e8f9f7	5350	*/
<>	144:ef7eb2e8f9f7	5351	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
<>	144:ef7eb2e8f9f7	5352	{
<>	144:ef7eb2e8f9f7	5353	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	5354
<>	144:ef7eb2e8f9f7	5355	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	5356	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	5357	/* Reset the TS Bits */
<>	144:ef7eb2e8f9f7	5358	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	5359	/* Set the Input Trigger source and the slave mode*/
<>	144:ef7eb2e8f9f7	5360	tmpsmcr \|= TIM_ITRx \| TIM_SLAVEMODE_EXTERNAL1;
<>	144:ef7eb2e8f9f7	5361	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	5362	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	5363	}
<>	144:ef7eb2e8f9f7	5364
<>	144:ef7eb2e8f9f7	5365	/**
<>	144:ef7eb2e8f9f7	5366	* @brief Configures the TIMx External Trigger (ETR).
<>	144:ef7eb2e8f9f7	5367	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5368	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
<>	144:ef7eb2e8f9f7	5369	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5370	* @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
<>	144:ef7eb2e8f9f7	5371	* @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
<>	144:ef7eb2e8f9f7	5372	* @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
<>	144:ef7eb2e8f9f7	5373	* @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
<>	144:ef7eb2e8f9f7	5374	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
<>	144:ef7eb2e8f9f7	5375	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5376	* @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
<>	144:ef7eb2e8f9f7	5377	* @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
<>	144:ef7eb2e8f9f7	5378	* @param ExtTRGFilter: External Trigger Filter.
<>	144:ef7eb2e8f9f7	5379	* This parameter must be a value between 0x00 and 0x0F
<>	144:ef7eb2e8f9f7	5380	* @retval None
<>	144:ef7eb2e8f9f7	5381	*/
<>	144:ef7eb2e8f9f7	5382	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<>	144:ef7eb2e8f9f7	5383	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<>	144:ef7eb2e8f9f7	5384	{
<>	144:ef7eb2e8f9f7	5385	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	5386
<>	144:ef7eb2e8f9f7	5387	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	5388
<>	144:ef7eb2e8f9f7	5389	/* Reset the ETR Bits */
<>	144:ef7eb2e8f9f7	5390	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	5391
<>	144:ef7eb2e8f9f7	5392	/* Set the Prescaler, the Filter value and the Polarity */
<>	144:ef7eb2e8f9f7	5393	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8U)));
<>	144:ef7eb2e8f9f7	5394
<>	144:ef7eb2e8f9f7	5395	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	5396	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	5397	}
<>	144:ef7eb2e8f9f7	5398
<>	144:ef7eb2e8f9f7	5399	/**
<>	144:ef7eb2e8f9f7	5400	* @}
<>	144:ef7eb2e8f9f7	5401	*/
<>	144:ef7eb2e8f9f7	5402
<>	144:ef7eb2e8f9f7	5403	#endif /* HAL_TIM_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5404	/**
<>	144:ef7eb2e8f9f7	5405	* @}
<>	144:ef7eb2e8f9f7	5406	*/
<>	144:ef7eb2e8f9f7	5407
<>	144:ef7eb2e8f9f7	5408	/**
<>	144:ef7eb2e8f9f7	5409	* @}
<>	144:ef7eb2e8f9f7	5410	*/
<>	144:ef7eb2e8f9f7	5411	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/