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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_sram.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_sram.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief SRAM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive SRAM memories
<> 144:ef7eb2e8f9f7 9 * mounted as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control SRAM memories. It uses the FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with SRAM devices.
<> 144:ef7eb2e8f9f7 19 The following sequence should be followed to configure the FSMC to interface
<> 144:ef7eb2e8f9f7 20 with SRAM/PSRAM memories:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SRAM_HandleTypeDef hsram; and:
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
<> 144:ef7eb2e8f9f7 26 values of the structure member.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
<> 144:ef7eb2e8f9f7 29 base register instance for NOR or SRAM device
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
<> 144:ef7eb2e8f9f7 32 base register instance for NOR or SRAM extended mode
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
<> 144:ef7eb2e8f9f7 35 mode timings; for example:
<> 144:ef7eb2e8f9f7 36 FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
<> 144:ef7eb2e8f9f7 37 and fill its fields with the allowed values of the structure member.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
<> 144:ef7eb2e8f9f7 40 performs the following sequence:
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
<> 144:ef7eb2e8f9f7 43 (##) Control register configuration using the FSMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 44 FSMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 45 (##) Timing register configuration using the FSMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 46 FSMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 47 (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 48 FSMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 49 (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) At this stage you can perform read/write accesses from/to the memory connected
<> 144:ef7eb2e8f9f7 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
<> 144:ef7eb2e8f9f7 53 following APIs:
<> 144:ef7eb2e8f9f7 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
<> 144:ef7eb2e8f9f7 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
<> 144:ef7eb2e8f9f7 61 HAL_SRAM_GetState()
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 @endverbatim
<> 144:ef7eb2e8f9f7 64 ******************************************************************************
<> 144:ef7eb2e8f9f7 65 * @attention
<> 144:ef7eb2e8f9f7 66 *
AnnaBridge 167:e84263d55307 67 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 70 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 71 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 72 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 74 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 75 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 77 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 78 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 90 *
<> 144:ef7eb2e8f9f7 91 ******************************************************************************
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup SRAM SRAM
<> 144:ef7eb2e8f9f7 102 * @brief SRAM driver modules
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 #ifdef HAL_SRAM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 108 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 109 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 111 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 118 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 119 *
<> 144:ef7eb2e8f9f7 120 @verbatim
<> 144:ef7eb2e8f9f7 121 ==============================================================================
<> 144:ef7eb2e8f9f7 122 ##### SRAM Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 123 ==============================================================================
<> 144:ef7eb2e8f9f7 124 [..] This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 125 the SRAM memory
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 @endverbatim
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief Performs the SRAM device initialization sequence
<> 144:ef7eb2e8f9f7 133 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 134 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 135 * @param Timing: Pointer to SRAM control timing structure
<> 144:ef7eb2e8f9f7 136 * @param ExtTiming: Pointer to SRAM extended mode timing structure
<> 144:ef7eb2e8f9f7 137 * @retval HAL status
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 /* Check the SRAM handle parameter */
<> 144:ef7eb2e8f9f7 142 if(hsram == NULL)
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 if(hsram->State == HAL_SRAM_STATE_RESET)
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 150 hsram->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 151 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 152 HAL_SRAM_MspInit(hsram);
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Initialize SRAM control Interface */
<> 144:ef7eb2e8f9f7 156 FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Initialize SRAM timing Interface */
<> 144:ef7eb2e8f9f7 159 FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* Initialize SRAM extended mode timing Interface */
<> 144:ef7eb2e8f9f7 162 FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Enable the NORSRAM device */
<> 144:ef7eb2e8f9f7 165 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 return HAL_OK;
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @brief Performs the SRAM device De-initialization sequence.
<> 144:ef7eb2e8f9f7 172 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 173 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 174 * @retval HAL status
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 /* De-Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 179 HAL_SRAM_MspDeInit(hsram);
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Configure the SRAM registers with their reset values */
<> 144:ef7eb2e8f9f7 182 FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 hsram->State = HAL_SRAM_STATE_RESET;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Release Lock */
<> 144:ef7eb2e8f9f7 187 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 return HAL_OK;
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @brief SRAM MSP Init.
<> 144:ef7eb2e8f9f7 194 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 195 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 196 * @retval None
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 201 UNUSED(hsram);
<> 144:ef7eb2e8f9f7 202 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 203 the HAL_SRAM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief SRAM MSP DeInit.
<> 144:ef7eb2e8f9f7 209 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 210 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 211 * @retval None
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 216 UNUSED(hsram);
<> 144:ef7eb2e8f9f7 217 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 218 the HAL_SRAM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 224 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 225 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 226 * @retval None
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 231 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 232 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 233 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief DMA transfer complete error callback.
<> 144:ef7eb2e8f9f7 239 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 240 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 241 * @retval None
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 246 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 247 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 248 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @}
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 257 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 @verbatim
<> 144:ef7eb2e8f9f7 260 ==============================================================================
<> 144:ef7eb2e8f9f7 261 ##### SRAM Input and Output functions #####
<> 144:ef7eb2e8f9f7 262 ==============================================================================
<> 144:ef7eb2e8f9f7 263 [..]
<> 144:ef7eb2e8f9f7 264 This section provides functions allowing to use and control the SRAM memory
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 @endverbatim
<> 144:ef7eb2e8f9f7 267 * @{
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @brief Reads 8-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 272 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 273 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 274 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 275 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 276 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 277 * @retval HAL status
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Process Locked */
<> 144:ef7eb2e8f9f7 284 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 287 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Read data from memory */
<> 144:ef7eb2e8f9f7 290 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
<> 144:ef7eb2e8f9f7 293 pDstBuffer++;
<> 144:ef7eb2e8f9f7 294 pSramAddress++;
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 298 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Process unlocked */
<> 144:ef7eb2e8f9f7 301 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 return HAL_OK;
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @brief Writes 8-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 308 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 309 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 310 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 311 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 312 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 313 * @retval HAL status
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 320 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Process Locked */
<> 144:ef7eb2e8f9f7 326 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 329 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Write data to memory */
<> 144:ef7eb2e8f9f7 332 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 335 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 336 pSramAddress++;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 340 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Process unlocked */
<> 144:ef7eb2e8f9f7 343 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 return HAL_OK;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @brief Reads 16-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 350 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 351 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 352 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 353 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 354 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 355 * @retval HAL status
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Process Locked */
<> 144:ef7eb2e8f9f7 362 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 365 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Read data from memory */
<> 144:ef7eb2e8f9f7 368 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
<> 144:ef7eb2e8f9f7 371 pDstBuffer++;
<> 144:ef7eb2e8f9f7 372 pSramAddress++;
<> 144:ef7eb2e8f9f7 373 }
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 376 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Process unlocked */
<> 144:ef7eb2e8f9f7 379 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 return HAL_OK;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief Writes 16-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 386 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 387 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 388 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 389 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 390 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 391 * @retval HAL status
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 398 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Process Locked */
<> 144:ef7eb2e8f9f7 404 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 407 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Write data to memory */
<> 144:ef7eb2e8f9f7 410 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 413 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 414 pSramAddress++;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 418 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Process unlocked */
<> 144:ef7eb2e8f9f7 421 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 return HAL_OK;
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @brief Reads 32-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 428 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 429 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 430 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 431 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 432 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 433 * @retval HAL status
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 /* Process Locked */
<> 144:ef7eb2e8f9f7 438 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 441 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Read data from memory */
<> 144:ef7eb2e8f9f7 444 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 *pDstBuffer = *(__IO uint32_t *)pAddress;
<> 144:ef7eb2e8f9f7 447 pDstBuffer++;
<> 144:ef7eb2e8f9f7 448 pAddress++;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 452 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Process unlocked */
<> 144:ef7eb2e8f9f7 455 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 return HAL_OK;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @brief Writes 32-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 462 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 463 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 464 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 465 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 466 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 467 * @retval HAL status
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 472 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Process Locked */
<> 144:ef7eb2e8f9f7 478 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 481 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Write data to memory */
<> 144:ef7eb2e8f9f7 484 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 *(__IO uint32_t *)pAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 487 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 488 pAddress++;
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 492 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Process unlocked */
<> 144:ef7eb2e8f9f7 495 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 return HAL_OK;
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /**
<> 144:ef7eb2e8f9f7 501 * @brief Reads a Words data from the SRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 502 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 503 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 504 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 505 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 506 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 507 * @retval HAL status
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 /* Process Locked */
<> 144:ef7eb2e8f9f7 512 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 515 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 518 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 519 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 522 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 525 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Process unlocked */
<> 144:ef7eb2e8f9f7 528 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 return HAL_OK;
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 535 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 536 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 537 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 538 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 539 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 540 * @retval HAL status
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 545 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Process Locked */
<> 144:ef7eb2e8f9f7 551 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 554 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 557 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 558 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 561 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 564 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Process unlocked */
<> 144:ef7eb2e8f9f7 567 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 return HAL_OK;
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /**
<> 144:ef7eb2e8f9f7 573 * @}
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
<> 144:ef7eb2e8f9f7 577 * @brief management functions
<> 144:ef7eb2e8f9f7 578 *
<> 144:ef7eb2e8f9f7 579 @verbatim
<> 144:ef7eb2e8f9f7 580 ==============================================================================
<> 144:ef7eb2e8f9f7 581 ##### SRAM Control functions #####
<> 144:ef7eb2e8f9f7 582 ==============================================================================
<> 144:ef7eb2e8f9f7 583 [..]
<> 144:ef7eb2e8f9f7 584 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 585 the SRAM interface.
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 @endverbatim
<> 144:ef7eb2e8f9f7 588 * @{
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /**
<> 144:ef7eb2e8f9f7 592 * @brief Enables dynamically SRAM write operation.
<> 144:ef7eb2e8f9f7 593 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 594 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 595 * @retval HAL status
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 /* Process Locked */
<> 144:ef7eb2e8f9f7 600 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Enable write operation */
<> 144:ef7eb2e8f9f7 603 FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 606 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Process unlocked */
<> 144:ef7eb2e8f9f7 609 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 return HAL_OK;
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @brief Disables dynamically SRAM write operation.
<> 144:ef7eb2e8f9f7 616 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 617 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 618 * @retval HAL status
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 /* Process Locked */
<> 144:ef7eb2e8f9f7 623 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 626 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Disable write operation */
<> 144:ef7eb2e8f9f7 629 FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 632 hsram->State = HAL_SRAM_STATE_PROTECTED;
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Process unlocked */
<> 144:ef7eb2e8f9f7 635 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 return HAL_OK;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /**
<> 144:ef7eb2e8f9f7 641 * @}
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /** @defgroup SRAM_Exported_Functions_Group4 State functions
<> 144:ef7eb2e8f9f7 645 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 646 *
<> 144:ef7eb2e8f9f7 647 @verbatim
<> 144:ef7eb2e8f9f7 648 ==============================================================================
<> 144:ef7eb2e8f9f7 649 ##### SRAM State functions #####
<> 144:ef7eb2e8f9f7 650 ==============================================================================
<> 144:ef7eb2e8f9f7 651 [..]
<> 144:ef7eb2e8f9f7 652 This subsection permits to get in run-time the status of the SRAM controller
<> 144:ef7eb2e8f9f7 653 and the data flow.
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 @endverbatim
<> 144:ef7eb2e8f9f7 656 * @{
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /**
<> 144:ef7eb2e8f9f7 660 * @brief Returns the SRAM controller state
<> 144:ef7eb2e8f9f7 661 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 662 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 663 * @retval HAL state
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 return hsram->State;
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @}
<> 144:ef7eb2e8f9f7 672 */
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /**
<> 144:ef7eb2e8f9f7 675 * @}
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677 #endif /* HAL_SRAM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 678 /**
<> 144:ef7eb2e8f9f7 679 * @}
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @}
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/