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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_spi.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SPI HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup SPI_Exported_Types SPI Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief SPI Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref SPI_Mode */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref SPI_Direction */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t DataSize; /*!< Specifies the SPI data size.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref SPI_Data_Size */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref SPI_Clock_Polarity */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref SPI_Clock_Phase */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
<> 144:ef7eb2e8f9f7 83 hardware (NSS pin) or by software using the SSI bit.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref SPI_Slave_Select_management */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
<> 144:ef7eb2e8f9f7 87 used to configure the transmit and receive SCK clock.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 144:ef7eb2e8f9f7 89 @note The communication clock is derived from the master
<> 144:ef7eb2e8f9f7 90 clock. The slave clock does not need to be set */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref SPI_TI_mode */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref SPI_CRC_Calculation */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
<> 144:ef7eb2e8f9f7 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
<> 144:ef7eb2e8f9f7 103 }SPI_InitTypeDef;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @brief HAL SPI State structure definition
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 typedef enum
<> 144:ef7eb2e8f9f7 109 {
<> 144:ef7eb2e8f9f7 110 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
<> 144:ef7eb2e8f9f7 111 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 112 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
<> 144:ef7eb2e8f9f7 113 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 114 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 115 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
<> 144:ef7eb2e8f9f7 116 HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
<> 144:ef7eb2e8f9f7 117 }HAL_SPI_StateTypeDef;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /**
<> 144:ef7eb2e8f9f7 120 * @brief SPI handle Structure definition
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 typedef struct __SPI_HandleTypeDef
<> 144:ef7eb2e8f9f7 123 {
<> 144:ef7eb2e8f9f7 124 SPI_TypeDef *Instance; /* SPI registers base address */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 SPI_InitTypeDef Init; /* SPI communication parameters */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 uint16_t TxXferSize; /* SPI Tx transfer size */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 uint16_t RxXferSize; /* SPI Rx transfer size */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 HAL_LockTypeDef Lock; /* SPI locking object */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 __IO uint32_t ErrorCode; /* SPI Error code */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 }SPI_HandleTypeDef;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 161 /** @defgroup SPI_Exported_Constants SPI Exported Constants
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @defgroup SPI_Error_Code SPI Error Code
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
AnnaBridge 167:e84263d55307 168 #define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 167:e84263d55307 169 #define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
AnnaBridge 167:e84263d55307 170 #define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
AnnaBridge 167:e84263d55307 171 #define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
AnnaBridge 167:e84263d55307 172 #define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
AnnaBridge 167:e84263d55307 173 #define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
AnnaBridge 167:e84263d55307 174 #define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup SPI_Mode SPI Mode
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
AnnaBridge 167:e84263d55307 182 #define SPI_MODE_SLAVE 0x00000000U
<> 144:ef7eb2e8f9f7 183 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @}
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /** @defgroup SPI_Direction SPI Direction Mode
<> 144:ef7eb2e8f9f7 189 * @{
<> 144:ef7eb2e8f9f7 190 */
AnnaBridge 167:e84263d55307 191 #define SPI_DIRECTION_2LINES 0x00000000U
<> 144:ef7eb2e8f9f7 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
<> 144:ef7eb2e8f9f7 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @}
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @defgroup SPI_Data_Size SPI Data Size
<> 144:ef7eb2e8f9f7 199 * @{
<> 144:ef7eb2e8f9f7 200 */
AnnaBridge 167:e84263d55307 201 #define SPI_DATASIZE_8BIT 0x00000000U
<> 144:ef7eb2e8f9f7 202 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @}
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
<> 144:ef7eb2e8f9f7 208 * @{
<> 144:ef7eb2e8f9f7 209 */
AnnaBridge 167:e84263d55307 210 #define SPI_POLARITY_LOW 0x00000000U
<> 144:ef7eb2e8f9f7 211 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup SPI_Clock_Phase SPI Clock Phase
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
AnnaBridge 167:e84263d55307 219 #define SPI_PHASE_1EDGE 0x00000000U
<> 144:ef7eb2e8f9f7 220 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @}
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 #define SPI_NSS_SOFT SPI_CR1_SSM
AnnaBridge 167:e84263d55307 229 #define SPI_NSS_HARD_INPUT 0x00000000U
AnnaBridge 167:e84263d55307 230 #define SPI_NSS_HARD_OUTPUT 0x00040000U
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @}
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
<> 144:ef7eb2e8f9f7 236 * @{
<> 144:ef7eb2e8f9f7 237 */
AnnaBridge 167:e84263d55307 238 #define SPI_BAUDRATEPRESCALER_2 0x00000000U
AnnaBridge 167:e84263d55307 239 #define SPI_BAUDRATEPRESCALER_4 0x00000008U
AnnaBridge 167:e84263d55307 240 #define SPI_BAUDRATEPRESCALER_8 0x00000010U
AnnaBridge 167:e84263d55307 241 #define SPI_BAUDRATEPRESCALER_16 0x00000018U
AnnaBridge 167:e84263d55307 242 #define SPI_BAUDRATEPRESCALER_32 0x00000020U
AnnaBridge 167:e84263d55307 243 #define SPI_BAUDRATEPRESCALER_64 0x00000028U
AnnaBridge 167:e84263d55307 244 #define SPI_BAUDRATEPRESCALER_128 0x00000030U
AnnaBridge 167:e84263d55307 245 #define SPI_BAUDRATEPRESCALER_256 0x00000038U
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @}
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
<> 144:ef7eb2e8f9f7 251 * @{
<> 144:ef7eb2e8f9f7 252 */
AnnaBridge 167:e84263d55307 253 #define SPI_FIRSTBIT_MSB 0x00000000U
<> 144:ef7eb2e8f9f7 254 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @defgroup SPI_TI_mode SPI TI Mode
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
AnnaBridge 167:e84263d55307 262 #define SPI_TIMODE_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 263 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
<> 144:ef7eb2e8f9f7 269 * @{
<> 144:ef7eb2e8f9f7 270 */
AnnaBridge 167:e84263d55307 271 #define SPI_CRCCALCULATION_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 272 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @}
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
<> 144:ef7eb2e8f9f7 278 * @{
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 #define SPI_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 281 #define SPI_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 282 #define SPI_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /** @defgroup SPI_Flags_definition SPI Flags Definition
<> 144:ef7eb2e8f9f7 288 * @{
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
<> 144:ef7eb2e8f9f7 291 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
<> 144:ef7eb2e8f9f7 292 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
<> 144:ef7eb2e8f9f7 293 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
<> 144:ef7eb2e8f9f7 294 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
<> 144:ef7eb2e8f9f7 295 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
<> 144:ef7eb2e8f9f7 296 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @}
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 306 /** @defgroup SPI_Exported_Macros SPI Exported Macros
<> 144:ef7eb2e8f9f7 307 * @{
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /** @brief Reset SPI handle state.
<> 144:ef7eb2e8f9f7 311 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 312 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 313 * @retval None
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** @brief Enable or disable the specified SPI interrupts.
<> 144:ef7eb2e8f9f7 318 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 319 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 320 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 144:ef7eb2e8f9f7 321 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 322 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 323 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 324 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 325 * @retval None
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 328 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @brief Check whether the specified SPI interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 331 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 332 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 333 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
<> 144:ef7eb2e8f9f7 334 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 335 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 336 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 337 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 338 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /** @brief Check whether the specified SPI flag is set or not.
<> 144:ef7eb2e8f9f7 343 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 344 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 345 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 346 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 347 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 348 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 349 * @arg SPI_FLAG_CRCERR: CRC error flag
<> 144:ef7eb2e8f9f7 350 * @arg SPI_FLAG_MODF: Mode fault flag
<> 144:ef7eb2e8f9f7 351 * @arg SPI_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 352 * @arg SPI_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 353 * @arg SPI_FLAG_FRE: Frame format error flag
<> 144:ef7eb2e8f9f7 354 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /** @brief Clear the SPI CRCERR pending flag.
<> 144:ef7eb2e8f9f7 359 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 360 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 361 * @retval None
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @brief Clear the SPI MODF pending flag.
<> 144:ef7eb2e8f9f7 366 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 367 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 371 do{ \
<> 144:ef7eb2e8f9f7 372 __IO uint32_t tmpreg_modf = 0x00U; \
<> 144:ef7eb2e8f9f7 373 tmpreg_modf = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 374 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
<> 144:ef7eb2e8f9f7 375 UNUSED(tmpreg_modf); \
<> 144:ef7eb2e8f9f7 376 } while(0)
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /** @brief Clear the SPI OVR pending flag.
<> 144:ef7eb2e8f9f7 379 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 380 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 381 * @retval None
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 384 do{ \
<> 144:ef7eb2e8f9f7 385 __IO uint32_t tmpreg_ovr = 0x00U; \
<> 144:ef7eb2e8f9f7 386 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
<> 144:ef7eb2e8f9f7 387 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 388 UNUSED(tmpreg_ovr); \
<> 144:ef7eb2e8f9f7 389 } while(0)
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /** @brief Clear the SPI FRE pending flag.
<> 144:ef7eb2e8f9f7 392 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 393 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 394 * @retval None
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 397 do{ \
<> 144:ef7eb2e8f9f7 398 __IO uint32_t tmpreg_fre = 0x00U; \
<> 144:ef7eb2e8f9f7 399 tmpreg_fre = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 400 UNUSED(tmpreg_fre); \
<> 144:ef7eb2e8f9f7 401 }while(0)
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /** @brief Enable the SPI peripheral.
<> 144:ef7eb2e8f9f7 404 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 405 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 406 * @retval None
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /** @brief Disable the SPI peripheral.
<> 144:ef7eb2e8f9f7 411 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 412 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 413 * @retval None
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 420 /** @addtogroup SPI_Exported_Functions
<> 144:ef7eb2e8f9f7 421 * @{
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /** @addtogroup SPI_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 425 * @{
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 428 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 429 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 430 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 431 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 432 /**
<> 144:ef7eb2e8f9f7 433 * @}
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /** @addtogroup SPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 437 * @{
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 440 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 441 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 442 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 443 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 444 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 445 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 446 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 447 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 448 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 449 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 450 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 451 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 454 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 455 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 456 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 457 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 458 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 459 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 460 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 461 /**
<> 144:ef7eb2e8f9f7 462 * @}
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /** @addtogroup SPI_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 466 * @{
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 /* Peripheral State and Error functions **************************************/
<> 144:ef7eb2e8f9f7 469 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 470 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @}
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 481 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 482 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 485 /** @defgroup SPI_Private_Macros SPI Private Macros
<> 144:ef7eb2e8f9f7 486 * @{
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /** @brief Set the SPI transmit-only mode.
<> 144:ef7eb2e8f9f7 490 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 491 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 492 * @retval None
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /** @brief Set the SPI receive-only mode.
<> 144:ef7eb2e8f9f7 497 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 498 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 499 * @retval None
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /** @brief Reset the CRC calculation of the SPI.
<> 144:ef7eb2e8f9f7 504 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 505 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 506 * @retval None
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
<> 144:ef7eb2e8f9f7 509 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
<> 144:ef7eb2e8f9f7 512 ((MODE) == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 144:ef7eb2e8f9f7 515 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
<> 144:ef7eb2e8f9f7 516 ((MODE) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 144:ef7eb2e8f9f7 521 ((MODE) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
<> 144:ef7eb2e8f9f7 524 ((DATASIZE) == SPI_DATASIZE_8BIT))
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 527 ((CPOL) == SPI_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
<> 144:ef7eb2e8f9f7 530 ((CPHA) == SPI_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
<> 144:ef7eb2e8f9f7 533 ((NSS) == SPI_NSS_HARD_INPUT) || \
<> 144:ef7eb2e8f9f7 534 ((NSS) == SPI_NSS_HARD_OUTPUT))
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
<> 144:ef7eb2e8f9f7 537 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
<> 144:ef7eb2e8f9f7 538 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
<> 144:ef7eb2e8f9f7 539 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
<> 144:ef7eb2e8f9f7 540 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
<> 144:ef7eb2e8f9f7 541 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
<> 144:ef7eb2e8f9f7 542 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
<> 144:ef7eb2e8f9f7 543 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
<> 144:ef7eb2e8f9f7 546 ((BIT) == SPI_FIRSTBIT_LSB))
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 549 ((MODE) == SPI_TIMODE_ENABLE))
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
<> 144:ef7eb2e8f9f7 552 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /**
<> 144:ef7eb2e8f9f7 557 * @}
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 561 /** @defgroup SPI_Private_Functions SPI Private Functions
<> 144:ef7eb2e8f9f7 562 * @{
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /**
<> 144:ef7eb2e8f9f7 566 * @}
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @}
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @}
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 #endif
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 #endif /* __STM32F2xx_HAL_SPI_H */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/