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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_sd.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_sd.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SD HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_SD_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_SD_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_ll_sdmmc.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup SD SD
<> 144:ef7eb2e8f9f7 54 * @brief SD HAL module driver
<> 144:ef7eb2e8f9f7 55 * @{
AnnaBridge 167:e84263d55307 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup SD_Exported_Types SD Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
AnnaBridge 167:e84263d55307 63 /** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
AnnaBridge 167:e84263d55307 64 * @{
AnnaBridge 167:e84263d55307 65 */
AnnaBridge 167:e84263d55307 66 typedef enum
AnnaBridge 167:e84263d55307 67 {
AnnaBridge 167:e84263d55307 68 HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
AnnaBridge 167:e84263d55307 69 HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
AnnaBridge 167:e84263d55307 70 HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
AnnaBridge 167:e84263d55307 71 HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
AnnaBridge 167:e84263d55307 72 HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
AnnaBridge 167:e84263d55307 73 HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
AnnaBridge 167:e84263d55307 74 HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
AnnaBridge 167:e84263d55307 75 HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
AnnaBridge 167:e84263d55307 76 }HAL_SD_StateTypeDef;
AnnaBridge 167:e84263d55307 77 /**
AnnaBridge 167:e84263d55307 78 * @}
AnnaBridge 167:e84263d55307 79 */
AnnaBridge 167:e84263d55307 80
AnnaBridge 167:e84263d55307 81 /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
AnnaBridge 167:e84263d55307 82 * @{
AnnaBridge 167:e84263d55307 83 */
AnnaBridge 167:e84263d55307 84 typedef enum
AnnaBridge 167:e84263d55307 85 {
AnnaBridge 167:e84263d55307 86 HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
AnnaBridge 167:e84263d55307 87 HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
AnnaBridge 167:e84263d55307 88 HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
AnnaBridge 167:e84263d55307 89 HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
AnnaBridge 167:e84263d55307 90 HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
AnnaBridge 167:e84263d55307 91 HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
AnnaBridge 167:e84263d55307 92 HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
AnnaBridge 167:e84263d55307 93 HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
AnnaBridge 167:e84263d55307 94 HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
AnnaBridge 167:e84263d55307 95 }HAL_SD_CardStateTypeDef;
AnnaBridge 167:e84263d55307 96 /**
AnnaBridge 167:e84263d55307 97 * @}
AnnaBridge 167:e84263d55307 98 */
AnnaBridge 167:e84263d55307 99
AnnaBridge 167:e84263d55307 100 /** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
<> 144:ef7eb2e8f9f7 101 * @{
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 #define SD_InitTypeDef SDIO_InitTypeDef
<> 144:ef7eb2e8f9f7 104 #define SD_TypeDef SDIO_TypeDef
<> 144:ef7eb2e8f9f7 105
AnnaBridge 167:e84263d55307 106 /**
AnnaBridge 167:e84263d55307 107 * @brief SD Card Information Structure definition
AnnaBridge 167:e84263d55307 108 */
AnnaBridge 167:e84263d55307 109 typedef struct
AnnaBridge 167:e84263d55307 110 {
AnnaBridge 167:e84263d55307 111 uint32_t CardType; /*!< Specifies the card Type */
AnnaBridge 167:e84263d55307 112
AnnaBridge 167:e84263d55307 113 uint32_t CardVersion; /*!< Specifies the card version */
AnnaBridge 167:e84263d55307 114
AnnaBridge 167:e84263d55307 115 uint32_t Class; /*!< Specifies the class of the card class */
AnnaBridge 167:e84263d55307 116
AnnaBridge 167:e84263d55307 117 uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
AnnaBridge 167:e84263d55307 118
AnnaBridge 167:e84263d55307 119 uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
AnnaBridge 167:e84263d55307 120
AnnaBridge 167:e84263d55307 121 uint32_t BlockSize; /*!< Specifies one block size in bytes */
AnnaBridge 167:e84263d55307 122
AnnaBridge 167:e84263d55307 123 uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
AnnaBridge 167:e84263d55307 124
AnnaBridge 167:e84263d55307 125 uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
AnnaBridge 167:e84263d55307 126
AnnaBridge 167:e84263d55307 127 }HAL_SD_CardInfoTypeDef;
AnnaBridge 167:e84263d55307 128
AnnaBridge 167:e84263d55307 129 /**
AnnaBridge 167:e84263d55307 130 * @brief SD handle Structure definition
AnnaBridge 167:e84263d55307 131 */
<> 144:ef7eb2e8f9f7 132 typedef struct
<> 144:ef7eb2e8f9f7 133 {
AnnaBridge 167:e84263d55307 134 SD_TypeDef *Instance; /*!< SD registers base address */
<> 144:ef7eb2e8f9f7 135
AnnaBridge 167:e84263d55307 136 SD_InitTypeDef Init; /*!< SD required parameters */
<> 144:ef7eb2e8f9f7 137
AnnaBridge 167:e84263d55307 138 HAL_LockTypeDef Lock; /*!< SD locking object */
<> 144:ef7eb2e8f9f7 139
AnnaBridge 167:e84263d55307 140 uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
AnnaBridge 167:e84263d55307 141
AnnaBridge 167:e84263d55307 142 uint32_t TxXferSize; /*!< SD Tx Transfer size */
AnnaBridge 167:e84263d55307 143
AnnaBridge 167:e84263d55307 144 uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
AnnaBridge 167:e84263d55307 145
AnnaBridge 167:e84263d55307 146 uint32_t RxXferSize; /*!< SD Rx Transfer size */
<> 144:ef7eb2e8f9f7 147
AnnaBridge 167:e84263d55307 148 __IO uint32_t Context; /*!< SD transfer context */
AnnaBridge 167:e84263d55307 149
AnnaBridge 167:e84263d55307 150 __IO HAL_SD_StateTypeDef State; /*!< SD card State */
<> 144:ef7eb2e8f9f7 151
AnnaBridge 167:e84263d55307 152 __IO uint32_t ErrorCode; /*!< SD Card Error codes */
AnnaBridge 167:e84263d55307 153
AnnaBridge 167:e84263d55307 154 DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 155
AnnaBridge 167:e84263d55307 156 DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 157
AnnaBridge 167:e84263d55307 158 HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
<> 144:ef7eb2e8f9f7 159
AnnaBridge 167:e84263d55307 160 uint32_t CSD[4]; /*!< SD card specific data table */
<> 144:ef7eb2e8f9f7 161
AnnaBridge 167:e84263d55307 162 uint32_t CID[4]; /*!< SD card identification number table */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 }SD_HandleTypeDef;
AnnaBridge 167:e84263d55307 165
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
AnnaBridge 167:e84263d55307 170 /** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
<> 144:ef7eb2e8f9f7 171 * @{
AnnaBridge 167:e84263d55307 172 */
<> 144:ef7eb2e8f9f7 173 typedef struct
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 __IO uint8_t CSDStruct; /*!< CSD structure */
<> 144:ef7eb2e8f9f7 176 __IO uint8_t SysSpecVersion; /*!< System specification version */
<> 144:ef7eb2e8f9f7 177 __IO uint8_t Reserved1; /*!< Reserved */
<> 144:ef7eb2e8f9f7 178 __IO uint8_t TAAC; /*!< Data read access time 1 */
<> 144:ef7eb2e8f9f7 179 __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
<> 144:ef7eb2e8f9f7 180 __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
<> 144:ef7eb2e8f9f7 181 __IO uint16_t CardComdClasses; /*!< Card command classes */
<> 144:ef7eb2e8f9f7 182 __IO uint8_t RdBlockLen; /*!< Max. read data block length */
<> 144:ef7eb2e8f9f7 183 __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
<> 144:ef7eb2e8f9f7 184 __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
<> 144:ef7eb2e8f9f7 185 __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
<> 144:ef7eb2e8f9f7 186 __IO uint8_t DSRImpl; /*!< DSR implemented */
<> 144:ef7eb2e8f9f7 187 __IO uint8_t Reserved2; /*!< Reserved */
<> 144:ef7eb2e8f9f7 188 __IO uint32_t DeviceSize; /*!< Device Size */
<> 144:ef7eb2e8f9f7 189 __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
<> 144:ef7eb2e8f9f7 190 __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
<> 144:ef7eb2e8f9f7 191 __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
<> 144:ef7eb2e8f9f7 192 __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
<> 144:ef7eb2e8f9f7 193 __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
<> 144:ef7eb2e8f9f7 194 __IO uint8_t EraseGrSize; /*!< Erase group size */
<> 144:ef7eb2e8f9f7 195 __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
<> 144:ef7eb2e8f9f7 196 __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
<> 144:ef7eb2e8f9f7 197 __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
<> 144:ef7eb2e8f9f7 198 __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
<> 144:ef7eb2e8f9f7 199 __IO uint8_t WrSpeedFact; /*!< Write speed factor */
<> 144:ef7eb2e8f9f7 200 __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
<> 144:ef7eb2e8f9f7 201 __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
<> 144:ef7eb2e8f9f7 202 __IO uint8_t Reserved3; /*!< Reserved */
<> 144:ef7eb2e8f9f7 203 __IO uint8_t ContentProtectAppli; /*!< Content protection application */
<> 144:ef7eb2e8f9f7 204 __IO uint8_t FileFormatGrouop; /*!< File format group */
<> 144:ef7eb2e8f9f7 205 __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
<> 144:ef7eb2e8f9f7 206 __IO uint8_t PermWrProtect; /*!< Permanent write protection */
<> 144:ef7eb2e8f9f7 207 __IO uint8_t TempWrProtect; /*!< Temporary write protection */
<> 144:ef7eb2e8f9f7 208 __IO uint8_t FileFormat; /*!< File format */
<> 144:ef7eb2e8f9f7 209 __IO uint8_t ECC; /*!< ECC code */
<> 144:ef7eb2e8f9f7 210 __IO uint8_t CSD_CRC; /*!< CSD CRC */
<> 144:ef7eb2e8f9f7 211 __IO uint8_t Reserved4; /*!< Always 1 */
AnnaBridge 167:e84263d55307 212
AnnaBridge 167:e84263d55307 213 }HAL_SD_CardCSDTypeDef;
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @}
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
AnnaBridge 167:e84263d55307 218 /** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
<> 144:ef7eb2e8f9f7 219 * @{
AnnaBridge 167:e84263d55307 220 */
<> 144:ef7eb2e8f9f7 221 typedef struct
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
<> 144:ef7eb2e8f9f7 224 __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t ProdName1; /*!< Product Name part1 */
<> 144:ef7eb2e8f9f7 226 __IO uint8_t ProdName2; /*!< Product Name part2 */
<> 144:ef7eb2e8f9f7 227 __IO uint8_t ProdRev; /*!< Product Revision */
<> 144:ef7eb2e8f9f7 228 __IO uint32_t ProdSN; /*!< Product Serial Number */
<> 144:ef7eb2e8f9f7 229 __IO uint8_t Reserved1; /*!< Reserved1 */
<> 144:ef7eb2e8f9f7 230 __IO uint16_t ManufactDate; /*!< Manufacturing Date */
<> 144:ef7eb2e8f9f7 231 __IO uint8_t CID_CRC; /*!< CID CRC */
<> 144:ef7eb2e8f9f7 232 __IO uint8_t Reserved2; /*!< Always 1 */
<> 144:ef7eb2e8f9f7 233
AnnaBridge 167:e84263d55307 234 }HAL_SD_CardCIDTypeDef;
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
AnnaBridge 167:e84263d55307 239 /** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
<> 144:ef7eb2e8f9f7 240 * @{
AnnaBridge 167:e84263d55307 241 */
<> 144:ef7eb2e8f9f7 242 typedef struct
<> 144:ef7eb2e8f9f7 243 {
AnnaBridge 167:e84263d55307 244 __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
AnnaBridge 167:e84263d55307 245 __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
AnnaBridge 167:e84263d55307 246 __IO uint16_t CardType; /*!< Carries information about card type */
AnnaBridge 167:e84263d55307 247 __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
AnnaBridge 167:e84263d55307 248 __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
AnnaBridge 167:e84263d55307 249 __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
AnnaBridge 167:e84263d55307 250 __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
AnnaBridge 167:e84263d55307 251 __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
AnnaBridge 167:e84263d55307 252 __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
AnnaBridge 167:e84263d55307 253 __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
<> 144:ef7eb2e8f9f7 254
AnnaBridge 167:e84263d55307 255 }HAL_SD_CardStatusTypeDef;
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
AnnaBridge 167:e84263d55307 264 /* Exported constants --------------------------------------------------------*/
AnnaBridge 167:e84263d55307 265 /** @defgroup SD_Exported_Constants Exported Constants
AnnaBridge 167:e84263d55307 266 * @{
AnnaBridge 167:e84263d55307 267 */
AnnaBridge 167:e84263d55307 268
AnnaBridge 167:e84263d55307 269 #define BLOCKSIZE 512U /*!< Block size is 512 bytes */
AnnaBridge 167:e84263d55307 270
AnnaBridge 167:e84263d55307 271 /** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
<> 144:ef7eb2e8f9f7 272 * @{
AnnaBridge 167:e84263d55307 273 */
AnnaBridge 167:e84263d55307 274 #define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
AnnaBridge 167:e84263d55307 275 #define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
AnnaBridge 167:e84263d55307 276 #define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
AnnaBridge 167:e84263d55307 277 #define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
AnnaBridge 167:e84263d55307 278 #define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
AnnaBridge 167:e84263d55307 279 #define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
AnnaBridge 167:e84263d55307 280 #define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
AnnaBridge 167:e84263d55307 281 #define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
AnnaBridge 167:e84263d55307 282 #define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
AnnaBridge 167:e84263d55307 283 number of transferred bytes does not match the block length */
AnnaBridge 167:e84263d55307 284 #define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
AnnaBridge 167:e84263d55307 285 #define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
AnnaBridge 167:e84263d55307 286 #define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
AnnaBridge 167:e84263d55307 287 #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
AnnaBridge 167:e84263d55307 288 command or if there was an attempt to access a locked card */
AnnaBridge 167:e84263d55307 289 #define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
AnnaBridge 167:e84263d55307 290 #define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
AnnaBridge 167:e84263d55307 291 #define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
AnnaBridge 167:e84263d55307 292 #define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
AnnaBridge 167:e84263d55307 293 #define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
AnnaBridge 167:e84263d55307 294 #define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
AnnaBridge 167:e84263d55307 295 #define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
AnnaBridge 167:e84263d55307 296 #define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
AnnaBridge 167:e84263d55307 297 #define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
AnnaBridge 167:e84263d55307 298 #define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
AnnaBridge 167:e84263d55307 299 #define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
AnnaBridge 167:e84263d55307 300 of erase sequence command was received */
AnnaBridge 167:e84263d55307 301 #define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
AnnaBridge 167:e84263d55307 302 #define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
AnnaBridge 167:e84263d55307 303 #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
AnnaBridge 167:e84263d55307 304 #define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
AnnaBridge 167:e84263d55307 305 #define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
AnnaBridge 167:e84263d55307 306 #define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
AnnaBridge 167:e84263d55307 307 #define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
AnnaBridge 167:e84263d55307 308 #define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
AnnaBridge 167:e84263d55307 309 #define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
AnnaBridge 167:e84263d55307 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
AnnaBridge 167:e84263d55307 314
AnnaBridge 167:e84263d55307 315 /** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
AnnaBridge 167:e84263d55307 318 #define SD_CONTEXT_NONE 0x00000000U /*!< None */
AnnaBridge 167:e84263d55307 319 #define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
AnnaBridge 167:e84263d55307 320 #define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
AnnaBridge 167:e84263d55307 321 #define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
AnnaBridge 167:e84263d55307 322 #define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
AnnaBridge 167:e84263d55307 323 #define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
AnnaBridge 167:e84263d55307 324 #define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
AnnaBridge 167:e84263d55307 330 /** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
AnnaBridge 167:e84263d55307 333 #define CARD_SDSC 0x00000000U
AnnaBridge 167:e84263d55307 334 #define CARD_SDHC_SDXC 0x00000001U
AnnaBridge 167:e84263d55307 335 #define CARD_SECURED 0x00000003U
AnnaBridge 167:e84263d55307 336
AnnaBridge 167:e84263d55307 337 /**
AnnaBridge 167:e84263d55307 338 * @}
AnnaBridge 167:e84263d55307 339 */
<> 144:ef7eb2e8f9f7 340
AnnaBridge 167:e84263d55307 341 /** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
AnnaBridge 167:e84263d55307 342 * @{
<> 144:ef7eb2e8f9f7 343 */
AnnaBridge 167:e84263d55307 344 #define CARD_V1_X 0x00000000U
AnnaBridge 167:e84263d55307 345 #define CARD_V2_X 0x00000001U
AnnaBridge 167:e84263d55307 346 /**
AnnaBridge 167:e84263d55307 347 * @}
<> 144:ef7eb2e8f9f7 348 */
AnnaBridge 167:e84263d55307 349
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 355 /** @defgroup SD_Exported_macros SD Exported Macros
AnnaBridge 167:e84263d55307 356 * @brief macros to handle interrupts and specific clock configurations
AnnaBridge 167:e84263d55307 357 * @{
AnnaBridge 167:e84263d55307 358 */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @brief Enable the SD device.
<> 144:ef7eb2e8f9f7 362 * @retval None
<> 144:ef7eb2e8f9f7 363 */
AnnaBridge 167:e84263d55307 364 #define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @brief Disable the SD device.
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
AnnaBridge 167:e84263d55307 370 #define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /**
AnnaBridge 167:e84263d55307 373 * @brief Enable the SDMMC DMA transfer.
<> 144:ef7eb2e8f9f7 374 * @retval None
<> 144:ef7eb2e8f9f7 375 */
AnnaBridge 167:e84263d55307 376 #define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
AnnaBridge 167:e84263d55307 379 * @brief Disable the SDMMC DMA transfer.
<> 144:ef7eb2e8f9f7 380 * @retval None
<> 144:ef7eb2e8f9f7 381 */
AnnaBridge 167:e84263d55307 382 #define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief Enable the SD device interrupt.
<> 144:ef7eb2e8f9f7 386 * @param __HANDLE__: SD Handle
AnnaBridge 167:e84263d55307 387 * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 388 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 389 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 390 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 391 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 392 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 393 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 394 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 395 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 396 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 397 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 398 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 399 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 400 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 401 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 402 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 403 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 404 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 405 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 406 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 407 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 408 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 409 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 410 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 411 * @retval None
<> 144:ef7eb2e8f9f7 412 */
AnnaBridge 167:e84263d55307 413 #define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief Disable the SD device interrupt.
<> 144:ef7eb2e8f9f7 417 * @param __HANDLE__: SD Handle
AnnaBridge 167:e84263d55307 418 * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 419 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 420 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 421 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 422 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 423 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 424 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 425 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 426 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 427 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 428 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 429 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 430 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 431 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 432 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 433 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 434 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 435 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 436 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 437 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 438 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 439 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 440 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge 167:e84263d55307 441 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 442 * @retval None
<> 144:ef7eb2e8f9f7 443 */
AnnaBridge 167:e84263d55307 444 #define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @brief Check whether the specified SD flag is set or not.
<> 144:ef7eb2e8f9f7 448 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 449 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 450 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 451 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 452 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 453 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 454 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 455 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 456 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 457 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 458 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 459 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 460 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 461 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
<> 144:ef7eb2e8f9f7 462 * @arg SDIO_FLAG_TXACT: Data transmit in progress
<> 144:ef7eb2e8f9f7 463 * @arg SDIO_FLAG_RXACT: Data receive in progress
<> 144:ef7eb2e8f9f7 464 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<> 144:ef7eb2e8f9f7 465 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
<> 144:ef7eb2e8f9f7 466 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
<> 144:ef7eb2e8f9f7 467 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
<> 144:ef7eb2e8f9f7 468 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
<> 144:ef7eb2e8f9f7 469 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
<> 144:ef7eb2e8f9f7 470 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
<> 144:ef7eb2e8f9f7 471 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
<> 144:ef7eb2e8f9f7 472 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 473 * @retval The new state of SD FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 474 */
AnnaBridge 167:e84263d55307 475 #define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Clear the SD's pending flags.
<> 144:ef7eb2e8f9f7 479 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 480 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 481 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 482 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 483 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 484 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 485 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 486 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 487 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 488 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 489 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 490 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 491 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 492 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 493 * @retval None
<> 144:ef7eb2e8f9f7 494 */
AnnaBridge 167:e84263d55307 495 #define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /**
<> 144:ef7eb2e8f9f7 498 * @brief Check whether the specified SD interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 499 * @param __HANDLE__: SD Handle
AnnaBridge 167:e84263d55307 500 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
<> 144:ef7eb2e8f9f7 501 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 502 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 503 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 504 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 505 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 506 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 507 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 508 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 509 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 510 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 511 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 512 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 513 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 514 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 515 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 516 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 517 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 518 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 519 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 520 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 521 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 522 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 523 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 524 * @retval The new state of SD IT (SET or RESET).
<> 144:ef7eb2e8f9f7 525 */
AnnaBridge 167:e84263d55307 526 #define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /**
<> 144:ef7eb2e8f9f7 529 * @brief Clear the SD's interrupt pending bits.
AnnaBridge 167:e84263d55307 530 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 531 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 532 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 533 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 534 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 535 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 536 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 537 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 538 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 539 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 540 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge 167:e84263d55307 541 * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 542 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 543 * @retval None
<> 144:ef7eb2e8f9f7 544 */
AnnaBridge 167:e84263d55307 545 #define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
AnnaBridge 167:e84263d55307 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @}
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 552 /** @defgroup SD_Exported_Functions SD Exported Functions
<> 144:ef7eb2e8f9f7 553 * @{
<> 144:ef7eb2e8f9f7 554 */
AnnaBridge 167:e84263d55307 555
<> 144:ef7eb2e8f9f7 556 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 557 * @{
<> 144:ef7eb2e8f9f7 558 */
AnnaBridge 167:e84263d55307 559 HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 560 HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 561 HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 562 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 563 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 564 /**
<> 144:ef7eb2e8f9f7 565 * @}
<> 144:ef7eb2e8f9f7 566 */
AnnaBridge 167:e84263d55307 567
AnnaBridge 167:e84263d55307 568 /** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 569 * @{
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 /* Blocking mode: Polling */
AnnaBridge 167:e84263d55307 572 HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
AnnaBridge 167:e84263d55307 573 HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
AnnaBridge 167:e84263d55307 574 HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
AnnaBridge 167:e84263d55307 575 /* Non-Blocking mode: IT */
AnnaBridge 167:e84263d55307 576 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
AnnaBridge 167:e84263d55307 577 HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
AnnaBridge 167:e84263d55307 578 /* Non-Blocking mode: DMA */
AnnaBridge 167:e84263d55307 579 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
AnnaBridge 167:e84263d55307 580 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Callback in non blocking modes (DMA) */
AnnaBridge 167:e84263d55307 585 void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 586 void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 587 void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 588 void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 589 /**
AnnaBridge 167:e84263d55307 590 * @}
AnnaBridge 167:e84263d55307 591 */
AnnaBridge 167:e84263d55307 592
AnnaBridge 167:e84263d55307 593 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge 167:e84263d55307 594 * @{
AnnaBridge 167:e84263d55307 595 */
AnnaBridge 167:e84263d55307 596 HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
<> 144:ef7eb2e8f9f7 597 /**
<> 144:ef7eb2e8f9f7 598 * @}
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600
AnnaBridge 167:e84263d55307 601 /** @defgroup SD_Exported_Functions_Group4 SD card related functions
<> 144:ef7eb2e8f9f7 602 * @{
<> 144:ef7eb2e8f9f7 603 */
AnnaBridge 167:e84263d55307 604 HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
AnnaBridge 167:e84263d55307 605 HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 606 HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
AnnaBridge 167:e84263d55307 607 HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
AnnaBridge 167:e84263d55307 608 HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
AnnaBridge 167:e84263d55307 609 HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
<> 144:ef7eb2e8f9f7 610 /**
<> 144:ef7eb2e8f9f7 611 * @}
<> 144:ef7eb2e8f9f7 612 */
AnnaBridge 167:e84263d55307 613
AnnaBridge 167:e84263d55307 614 /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 615 * @{
<> 144:ef7eb2e8f9f7 616 */
AnnaBridge 167:e84263d55307 617 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 618 uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 619 /**
<> 144:ef7eb2e8f9f7 620 * @}
<> 144:ef7eb2e8f9f7 621 */
AnnaBridge 167:e84263d55307 622
AnnaBridge 167:e84263d55307 623 /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
AnnaBridge 167:e84263d55307 624 * @{
AnnaBridge 167:e84263d55307 625 */
AnnaBridge 167:e84263d55307 626 HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
AnnaBridge 167:e84263d55307 627 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @}
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 633 /** @defgroup SD_Private_Types SD Private Types
<> 144:ef7eb2e8f9f7 634 * @{
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @}
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 642 /** @defgroup SD_Private_Defines SD Private Defines
<> 144:ef7eb2e8f9f7 643 * @{
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /**
<> 144:ef7eb2e8f9f7 647 * @}
<> 144:ef7eb2e8f9f7 648 */
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 651 /** @defgroup SD_Private_Variables SD Private Variables
<> 144:ef7eb2e8f9f7 652 * @{
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @}
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 660 /** @defgroup SD_Private_Constants SD Private Constants
<> 144:ef7eb2e8f9f7 661 * @{
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @}
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 669 /** @defgroup SD_Private_Macros SD Private Macros
<> 144:ef7eb2e8f9f7 670 * @{
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @}
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Private functions prototypes ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 678 /** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
<> 144:ef7eb2e8f9f7 679 * @{
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @}
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 687 /** @defgroup SD_Private_Functions SD Private Functions
<> 144:ef7eb2e8f9f7 688 * @{
<> 144:ef7eb2e8f9f7 689 */
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @}
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694
AnnaBridge 167:e84263d55307 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @}
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @}
<> 144:ef7eb2e8f9f7 702 */
AnnaBridge 167:e84263d55307 703 /**
AnnaBridge 167:e84263d55307 704 * @}
AnnaBridge 167:e84263d55307 705 */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 #endif
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 #endif /* __STM32F2xx_HAL_SD_H */
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/