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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_rcc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Extension RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities RCC extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 ******************************************************************************
<> 144:ef7eb2e8f9f7 13 * @attention
<> 144:ef7eb2e8f9f7 14 *
AnnaBridge 167:e84263d55307 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 ******************************************************************************
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 43 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @defgroup RCCEx RCCEx
<> 144:ef7eb2e8f9f7 50 * @brief RCCEx HAL module driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @addtogroup RCCEx_Private_Constants
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @}
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 65 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 66 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 67 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 68 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<> 144:ef7eb2e8f9f7 69 * @{
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 73 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 @verbatim
<> 144:ef7eb2e8f9f7 76 ===============================================================================
<> 144:ef7eb2e8f9f7 77 ##### Extended Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 78 ===============================================================================
<> 144:ef7eb2e8f9f7 79 [..]
<> 144:ef7eb2e8f9f7 80 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 81 frequencies.
<> 144:ef7eb2e8f9f7 82 [..]
<> 144:ef7eb2e8f9f7 83 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<> 144:ef7eb2e8f9f7 84 select the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 85 order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 86 the backup registers) and RCC_BDCR register are set to their reset values.
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 @endverbatim
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
<> 144:ef7eb2e8f9f7 94 * RCC_PeriphCLKInitTypeDef.
<> 144:ef7eb2e8f9f7 95 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 96 * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
<> 144:ef7eb2e8f9f7 99 * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
<> 144:ef7eb2e8f9f7 100 * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 * @retval HAL status
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 105 {
<> 144:ef7eb2e8f9f7 106 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 107 uint32_t tmpreg1 = 0U;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Check the parameters */
<> 144:ef7eb2e8f9f7 110 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*---------------------------- I2S configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 113 if(((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))|| \
<> 144:ef7eb2e8f9f7 114 (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
<> 144:ef7eb2e8f9f7 115 {
<> 144:ef7eb2e8f9f7 116 /* check for Parameters */
<> 144:ef7eb2e8f9f7 117 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
<> 144:ef7eb2e8f9f7 118 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Disable the PLLI2S */
<> 144:ef7eb2e8f9f7 121 __HAL_RCC_PLLI2S_DISABLE();
<> 144:ef7eb2e8f9f7 122 /* Get tick */
<> 144:ef7eb2e8f9f7 123 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 124 /* Wait till PLLI2S is disabled */
<> 144:ef7eb2e8f9f7 125 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 /* return in case of Timeout detected */
<> 144:ef7eb2e8f9f7 130 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133 /* Configure the PLLI2S division factors */
<> 144:ef7eb2e8f9f7 134 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
<> 144:ef7eb2e8f9f7 135 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
<> 144:ef7eb2e8f9f7 136 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Enable the PLLI2S */
<> 144:ef7eb2e8f9f7 139 __HAL_RCC_PLLI2S_ENABLE();
<> 144:ef7eb2e8f9f7 140 /* Get tick */
<> 144:ef7eb2e8f9f7 141 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 142 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 143 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 /* return in case of Timeout detected */
<> 144:ef7eb2e8f9f7 148 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152 /*--------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /*---------------------------- RTC configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 155 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 /* Check for RTC Parameters used to output RTCCLK */
<> 144:ef7eb2e8f9f7 158 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Enable Power Clock*/
<> 144:ef7eb2e8f9f7 161 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 164 PWR->CR |= PWR_CR_DBP;
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Get tick */
<> 144:ef7eb2e8f9f7 167 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 while((PWR->CR & PWR_CR_DBP) == RESET)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
<> 144:ef7eb2e8f9f7 177 tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
<> 144:ef7eb2e8f9f7 178 if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 /* Store the content of BDCR register before the reset of Backup Domain */
<> 144:ef7eb2e8f9f7 181 tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<> 144:ef7eb2e8f9f7 182 /* RTC Clock selection can be changed only if the Backup Domain is reset */
<> 144:ef7eb2e8f9f7 183 __HAL_RCC_BACKUPRESET_FORCE();
<> 144:ef7eb2e8f9f7 184 __HAL_RCC_BACKUPRESET_RELEASE();
<> 144:ef7eb2e8f9f7 185 /* Restore the Content of BDCR register */
<> 144:ef7eb2e8f9f7 186 RCC->BDCR = tmpreg1;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
<> 144:ef7eb2e8f9f7 189 if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 /* Get tick */
<> 144:ef7eb2e8f9f7 192 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 195 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206 /*--------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 return HAL_OK;
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 213 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 214 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 215 * will be configured.
<> 144:ef7eb2e8f9f7 216 * @retval None
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 uint32_t tempreg;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Set all possible values for the extended clock type parameter------------*/
<> 144:ef7eb2e8f9f7 223 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /* Get the PLLI2S Clock configuration --------------------------------------*/
<> 144:ef7eb2e8f9f7 226 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
<> 144:ef7eb2e8f9f7 227 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Get the RTC Clock configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 230 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
<> 144:ef7eb2e8f9f7 231 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @}
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/