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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_pwr.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of PWR HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup PWR
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup PWR_Exported_Types PWR Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief PWR PVD configuration structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
<> 144:ef7eb2e8f9f7 69 This parameter can be a value of @ref PWR_PVD_detection_level */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref PWR_PVD_Mode */
<> 144:ef7eb2e8f9f7 73 }PWR_PVDTypeDef;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /**
<> 144:ef7eb2e8f9f7 76 * @}
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /** @defgroup PWR_Exported_Constants PWR Exported Constants
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
<> 144:ef7eb2e8f9f7 85 * @{
<> 144:ef7eb2e8f9f7 86 */
AnnaBridge 167:e84263d55307 87 #define PWR_WAKEUP_PIN1 0x00000100U
<> 144:ef7eb2e8f9f7 88 /**
<> 144:ef7eb2e8f9f7 89 * @}
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
<> 144:ef7eb2e8f9f7 93 * @{
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
<> 144:ef7eb2e8f9f7 96 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
<> 144:ef7eb2e8f9f7 97 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
<> 144:ef7eb2e8f9f7 98 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
<> 144:ef7eb2e8f9f7 99 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
<> 144:ef7eb2e8f9f7 100 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
<> 144:ef7eb2e8f9f7 101 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
<> 144:ef7eb2e8f9f7 102 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
<> 144:ef7eb2e8f9f7 103 (Compare internally to VREFINT) */
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @}
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @defgroup PWR_PVD_Mode PWR PVD Mode
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
AnnaBridge 167:e84263d55307 111 #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
AnnaBridge 167:e84263d55307 112 #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
AnnaBridge 167:e84263d55307 113 #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
AnnaBridge 167:e84263d55307 114 #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
AnnaBridge 167:e84263d55307 115 #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
AnnaBridge 167:e84263d55307 116 #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
AnnaBridge 167:e84263d55307 117 #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @}
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
AnnaBridge 167:e84263d55307 126 #define PWR_MAINREGULATOR_ON 0x00000000U
<> 144:ef7eb2e8f9f7 127 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
<> 144:ef7eb2e8f9f7 128 /**
<> 144:ef7eb2e8f9f7 129 * @}
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
<> 144:ef7eb2e8f9f7 133 * @{
<> 144:ef7eb2e8f9f7 134 */
AnnaBridge 167:e84263d55307 135 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
AnnaBridge 167:e84263d55307 136 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @}
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
<> 144:ef7eb2e8f9f7 142 * @{
<> 144:ef7eb2e8f9f7 143 */
AnnaBridge 167:e84263d55307 144 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
AnnaBridge 167:e84263d55307 145 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @}
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @defgroup PWR_Flag PWR Flag
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 154 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 155 #define PWR_FLAG_PVDO PWR_CSR_PVDO
<> 144:ef7eb2e8f9f7 156 #define PWR_FLAG_BRR PWR_CSR_BRR
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @}
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 166 /** @defgroup PWR_Exported_Macro PWR Exported Macro
<> 144:ef7eb2e8f9f7 167 * @{
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /** @brief Check PWR flag is set or not.
<> 144:ef7eb2e8f9f7 171 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 172 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 173 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
<> 144:ef7eb2e8f9f7 174 * was received from the WKUP pin or from the RTC alarm (Alarm A
<> 144:ef7eb2e8f9f7 175 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
<> 144:ef7eb2e8f9f7 176 * An additional wakeup event is detected if the WKUP pin is enabled
<> 144:ef7eb2e8f9f7 177 * (by setting the EWUP bit) when the WKUP pin level is already high.
<> 144:ef7eb2e8f9f7 178 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
<> 144:ef7eb2e8f9f7 179 * resumed from StandBy mode.
<> 144:ef7eb2e8f9f7 180 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
<> 144:ef7eb2e8f9f7 181 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
<> 144:ef7eb2e8f9f7 182 * For this reason, this bit is equal to 0 after Standby or reset
<> 144:ef7eb2e8f9f7 183 * until the PVDE bit is set.
<> 144:ef7eb2e8f9f7 184 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
<> 144:ef7eb2e8f9f7 185 * when the device wakes up from Standby mode or by a system reset
<> 144:ef7eb2e8f9f7 186 * or power reset.
<> 144:ef7eb2e8f9f7 187 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /** @brief Clear the PWR's pending flags.
<> 144:ef7eb2e8f9f7 192 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 193 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 194 * @arg PWR_FLAG_WU: Wake Up flag
<> 144:ef7eb2e8f9f7 195 * @arg PWR_FLAG_SB: StandBy flag
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @brief Enable the PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 201 * @retval None.
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief Disable the PVD EXTI Line 16.
<> 144:ef7eb2e8f9f7 207 * @retval None.
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @brief Enable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 213 * @retval None.
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief Disable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 219 * @retval None.
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Enable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 225 * @retval None.
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /**
<> 144:ef7eb2e8f9f7 230 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 231 * @retval None.
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @brief Enable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 237 * @retval None.
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 244 * @retval None.
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
<> 144:ef7eb2e8f9f7 251 * @retval None.
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
<> 144:ef7eb2e8f9f7 254 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
<> 144:ef7eb2e8f9f7 255 }while(0)
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 259 * This parameter can be:
<> 144:ef7eb2e8f9f7 260 * @retval None.
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
<> 144:ef7eb2e8f9f7 263 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
<> 144:ef7eb2e8f9f7 264 }while(0)
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 268 * @retval EXTI PVD Line Status.
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief Clear the PVD Exti flag.
<> 144:ef7eb2e8f9f7 274 * @retval None.
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief Generates a Software interrupt on PVD EXTI line.
<> 144:ef7eb2e8f9f7 280 * @retval None
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Include PWR HAL Extension module */
<> 144:ef7eb2e8f9f7 289 #include "stm32f2xx_hal_pwr_ex.h"
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 292 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 297 * @{
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 300 void HAL_PWR_DeInit(void);
<> 144:ef7eb2e8f9f7 301 void HAL_PWR_EnableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 302 void HAL_PWR_DisableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 311 /* PVD configuration */
<> 144:ef7eb2e8f9f7 312 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 144:ef7eb2e8f9f7 313 void HAL_PWR_EnablePVD(void);
<> 144:ef7eb2e8f9f7 314 void HAL_PWR_DisablePVD(void);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* WakeUp pins configuration */
<> 144:ef7eb2e8f9f7 317 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
<> 144:ef7eb2e8f9f7 318 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Low Power modes entry */
<> 144:ef7eb2e8f9f7 321 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
<> 144:ef7eb2e8f9f7 322 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
<> 144:ef7eb2e8f9f7 323 void HAL_PWR_EnterSTANDBYMode(void);
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Power PVD IRQ Handler */
<> 144:ef7eb2e8f9f7 326 void HAL_PWR_PVD_IRQHandler(void);
<> 144:ef7eb2e8f9f7 327 void HAL_PWR_PVDCallback(void);
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Cortex System Control functions *******************************************/
<> 144:ef7eb2e8f9f7 330 void HAL_PWR_EnableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 331 void HAL_PWR_DisableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 332 void HAL_PWR_EnableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 333 void HAL_PWR_DisableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 334 /**
<> 144:ef7eb2e8f9f7 335 * @}
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 343 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 344 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 345 /** @defgroup PWR_Private_Constants PWR Private Constants
<> 144:ef7eb2e8f9f7 346 * @{
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
<> 144:ef7eb2e8f9f7 350 * @{
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** @defgroup PWR_register_alias_address PWR Register alias address
<> 144:ef7eb2e8f9f7 358 * @{
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 /* ------------- PWR registers bit address in the alias region ---------------*/
<> 144:ef7eb2e8f9f7 361 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
<> 144:ef7eb2e8f9f7 362 #define PWR_CR_OFFSET 0x00U
<> 144:ef7eb2e8f9f7 363 #define PWR_CSR_OFFSET 0x04U
<> 144:ef7eb2e8f9f7 364 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
<> 144:ef7eb2e8f9f7 365 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @}
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
<> 144:ef7eb2e8f9f7 371 * @{
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373 /* --- CR Register ---*/
<> 144:ef7eb2e8f9f7 374 /* Alias word address of DBP bit */
<> 144:ef7eb2e8f9f7 375 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
<> 144:ef7eb2e8f9f7 376 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Alias word address of PVDE bit */
<> 144:ef7eb2e8f9f7 379 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
<> 144:ef7eb2e8f9f7 380 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
<> 144:ef7eb2e8f9f7 386 * @{
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 /* --- CSR Register ---*/
<> 144:ef7eb2e8f9f7 389 /* Alias word address of EWUP bit */
<> 144:ef7eb2e8f9f7 390 #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
<> 144:ef7eb2e8f9f7 391 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
<> 144:ef7eb2e8f9f7 392 /**
<> 144:ef7eb2e8f9f7 393 * @}
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /**
<> 144:ef7eb2e8f9f7 397 * @}
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 400 /** @defgroup PWR_Private_Macros PWR Private Macros
<> 144:ef7eb2e8f9f7 401 * @{
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
<> 144:ef7eb2e8f9f7 405 * @{
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
<> 144:ef7eb2e8f9f7 408 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 144:ef7eb2e8f9f7 409 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 144:ef7eb2e8f9f7 410 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 144:ef7eb2e8f9f7 411 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 144:ef7eb2e8f9f7 412 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 144:ef7eb2e8f9f7 413 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 144:ef7eb2e8f9f7 414 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 144:ef7eb2e8f9f7 415 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 144:ef7eb2e8f9f7 416 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
<> 144:ef7eb2e8f9f7 417 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<> 144:ef7eb2e8f9f7 418 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<> 144:ef7eb2e8f9f7 419 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @}
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @}
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @}
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /**
<> 144:ef7eb2e8f9f7 433 * @}
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438 #endif
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #endif /* __STM32F2xx_HAL_PWR_H */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/