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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nor.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_nor.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief NOR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive NOR memories mounted
<> 144:ef7eb2e8f9f7 9 * as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control NOR flash memories. It uses the FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with NOR devices. This driver is used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
<> 144:ef7eb2e8f9f7 21 with control and timing parameters for both normal and extended mode.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
<> 144:ef7eb2e8f9f7 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
<> 144:ef7eb2e8f9f7 25 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (+) Access NOR flash memory by read/write data unit operations using the functions
<> 144:ef7eb2e8f9f7 28 HAL_NOR_Read(), HAL_NOR_Program().
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (+) Perform NOR flash erase block/chip operations using the functions
<> 144:ef7eb2e8f9f7 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
<> 144:ef7eb2e8f9f7 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
<> 144:ef7eb2e8f9f7 35 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) You can monitor the NOR device HAL state by calling the function
<> 144:ef7eb2e8f9f7 41 HAL_NOR_GetState()
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
<> 144:ef7eb2e8f9f7 44 If a NOR flash device contains different operations and/or implementations,
<> 144:ef7eb2e8f9f7 45 it should be implemented separately.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 *** NOR HAL driver macros list ***
<> 144:ef7eb2e8f9f7 48 =============================================
<> 144:ef7eb2e8f9f7 49 [..]
<> 144:ef7eb2e8f9f7 50 Below the list of most used macros in NOR HAL driver.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (+) NOR_WRITE : NOR memory write data to specified address
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 @endverbatim
<> 144:ef7eb2e8f9f7 55 ******************************************************************************
<> 144:ef7eb2e8f9f7 56 * @attention
<> 144:ef7eb2e8f9f7 57 *
AnnaBridge 167:e84263d55307 58 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 61 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 62 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 65 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 66 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 68 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 69 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 ******************************************************************************
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /** @defgroup NOR NOR
<> 144:ef7eb2e8f9f7 93 * @brief NOR driver modules
<> 144:ef7eb2e8f9f7 94 * @{
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 #ifdef HAL_NOR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup NOR_Private_Defines NOR Private Defines
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Constants to define address to set to write a command */
AnnaBridge 167:e84263d55307 106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
AnnaBridge 167:e84263d55307 107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
AnnaBridge 167:e84263d55307 108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
AnnaBridge 167:e84263d55307 109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
AnnaBridge 167:e84263d55307 110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
AnnaBridge 167:e84263d55307 111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
AnnaBridge 167:e84263d55307 112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Constants to define data to program a command */
AnnaBridge 167:e84263d55307 115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
AnnaBridge 167:e84263d55307 116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
AnnaBridge 167:e84263d55307 117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
AnnaBridge 167:e84263d55307 118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
AnnaBridge 167:e84263d55307 119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
AnnaBridge 167:e84263d55307 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
AnnaBridge 167:e84263d55307 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
AnnaBridge 167:e84263d55307 122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
AnnaBridge 167:e84263d55307 123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
AnnaBridge 167:e84263d55307 124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
<> 144:ef7eb2e8f9f7 125
AnnaBridge 167:e84263d55307 126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
AnnaBridge 167:e84263d55307 127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
AnnaBridge 167:e84263d55307 128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Mask on NOR STATUS REGISTER */
AnnaBridge 167:e84263d55307 131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
AnnaBridge 167:e84263d55307 132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /** @defgroup NOR_Private_Variables NOR Private Variables
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @}
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 151 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 152 /** @defgroup NOR_Exported_Functions NOR Exported Functions
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 157 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 158 *
<> 144:ef7eb2e8f9f7 159 @verbatim
<> 144:ef7eb2e8f9f7 160 ==============================================================================
<> 144:ef7eb2e8f9f7 161 ##### NOR Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 162 ==============================================================================
<> 144:ef7eb2e8f9f7 163 [..]
<> 144:ef7eb2e8f9f7 164 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 165 the NOR memory
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 @endverbatim
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @brief Perform the NOR memory Initialization sequence
<> 144:ef7eb2e8f9f7 173 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 174 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 175 * @param Timing: pointer to NOR control timing structure
<> 144:ef7eb2e8f9f7 176 * @param ExtTiming: pointer to NOR extended mode timing structure
<> 144:ef7eb2e8f9f7 177 * @retval HAL status
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 /* Check the NOR handle parameter */
<> 144:ef7eb2e8f9f7 182 if(hnor == NULL)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 if(hnor->State == HAL_NOR_STATE_RESET)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 190 hnor->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 191 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 192 HAL_NOR_MspInit(hnor);
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Initialize NOR control Interface */
<> 144:ef7eb2e8f9f7 196 FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Initialize NOR timing Interface */
<> 144:ef7eb2e8f9f7 199 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Initialize NOR extended mode timing Interface */
<> 144:ef7eb2e8f9f7 202 FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Enable the NORSRAM device */
<> 144:ef7eb2e8f9f7 205 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Initialize NOR Memory Data Width*/
<> 144:ef7eb2e8f9f7 208 if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212 else
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 uwNORMemoryDataWidth = NOR_MEMORY_16B;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 218 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 return HAL_OK;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Perform NOR memory De-Initialization sequence
<> 144:ef7eb2e8f9f7 225 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 226 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 227 * @retval HAL status
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 /* De-Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 232 HAL_NOR_MspDeInit(hnor);
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Configure the NOR registers with their reset values */
<> 144:ef7eb2e8f9f7 235 FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 238 hnor->State = HAL_NOR_STATE_RESET;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Release Lock */
<> 144:ef7eb2e8f9f7 241 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 return HAL_OK;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @brief NOR MSP Init
<> 144:ef7eb2e8f9f7 248 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 249 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 250 * @retval None
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 255 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 258 the HAL_NOR_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief NOR MSP DeInit
<> 144:ef7eb2e8f9f7 264 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 265 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 266 * @retval None
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 271 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 274 the HAL_NOR_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief NOR MSP Wait for Ready/Busy signal
<> 144:ef7eb2e8f9f7 280 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 281 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 282 * @param Timeout: Maximum timeout value
<> 144:ef7eb2e8f9f7 283 * @retval None
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 288 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 289 UNUSED(Timeout);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 292 the HAL_NOR_MspWait could be implemented in the user file
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 301 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 302 *
<> 144:ef7eb2e8f9f7 303 @verbatim
<> 144:ef7eb2e8f9f7 304 ==============================================================================
<> 144:ef7eb2e8f9f7 305 ##### NOR Input and Output functions #####
<> 144:ef7eb2e8f9f7 306 ==============================================================================
<> 144:ef7eb2e8f9f7 307 [..]
<> 144:ef7eb2e8f9f7 308 This section provides functions allowing to use and control the NOR memory
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 @endverbatim
<> 144:ef7eb2e8f9f7 311 * @{
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Read NOR flash IDs
<> 144:ef7eb2e8f9f7 316 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 317 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 318 * @param pNOR_ID : pointer to NOR ID structure
<> 144:ef7eb2e8f9f7 319 * @retval HAL status
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Process Locked */
<> 144:ef7eb2e8f9f7 326 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 329 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 335 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 348 {
<> 144:ef7eb2e8f9f7 349 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 353 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Send read ID command */
<> 144:ef7eb2e8f9f7 356 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 357 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 358 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Read the NOR IDs */
<> 144:ef7eb2e8f9f7 361 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
<> 144:ef7eb2e8f9f7 362 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
<> 144:ef7eb2e8f9f7 363 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
<> 144:ef7eb2e8f9f7 364 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 367 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Process unlocked */
<> 144:ef7eb2e8f9f7 370 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 return HAL_OK;
<> 144:ef7eb2e8f9f7 373 }
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /**
<> 144:ef7eb2e8f9f7 376 * @brief Returns the NOR memory to Read mode.
<> 144:ef7eb2e8f9f7 377 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 378 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 379 * @retval HAL status
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Process Locked */
<> 144:ef7eb2e8f9f7 386 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 389 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 395 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 415 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Process unlocked */
<> 144:ef7eb2e8f9f7 418 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 return HAL_OK;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @brief Read data from NOR memory
<> 144:ef7eb2e8f9f7 425 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 426 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 427 * @param pAddress: pointer to Device address
<> 144:ef7eb2e8f9f7 428 * @param pData : pointer to read data
<> 144:ef7eb2e8f9f7 429 * @retval HAL status
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Process Locked */
<> 144:ef7eb2e8f9f7 436 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 439 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 445 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 463 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Send read data command */
<> 144:ef7eb2e8f9f7 466 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 467 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 468 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Read the data */
<> 144:ef7eb2e8f9f7 471 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 474 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Process unlocked */
<> 144:ef7eb2e8f9f7 477 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 return HAL_OK;
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @brief Program data to NOR memory
<> 144:ef7eb2e8f9f7 484 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 485 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 486 * @param pAddress: Device address
<> 144:ef7eb2e8f9f7 487 * @param pData : pointer to the data to write
<> 144:ef7eb2e8f9f7 488 * @retval HAL status
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Process Locked */
<> 144:ef7eb2e8f9f7 495 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 498 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 504 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 522 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Send program data command */
<> 144:ef7eb2e8f9f7 525 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 526 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 527 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Write the data */
<> 144:ef7eb2e8f9f7 530 NOR_WRITE(pAddress, *pData);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 533 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Process unlocked */
<> 144:ef7eb2e8f9f7 536 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 return HAL_OK;
<> 144:ef7eb2e8f9f7 539 }
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @brief Reads a half-word buffer from the NOR memory.
<> 144:ef7eb2e8f9f7 543 * @param hnor: pointer to the NOR handle
<> 144:ef7eb2e8f9f7 544 * @param uwAddress: NOR memory internal address to read from.
<> 144:ef7eb2e8f9f7 545 * @param pData: pointer to the buffer that receives the data read from the
<> 144:ef7eb2e8f9f7 546 * NOR memory.
<> 144:ef7eb2e8f9f7 547 * @param uwBufferSize : number of Half word to read.
<> 144:ef7eb2e8f9f7 548 * @retval HAL status
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Process Locked */
<> 144:ef7eb2e8f9f7 555 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 558 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 564 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 582 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Send read data command */
<> 144:ef7eb2e8f9f7 585 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 586 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 587 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Read buffer */
<> 144:ef7eb2e8f9f7 590 while( uwBufferSize > 0U)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 *pData++ = *(__IO uint16_t *)uwAddress;
<> 144:ef7eb2e8f9f7 593 uwAddress += 2U;
<> 144:ef7eb2e8f9f7 594 uwBufferSize--;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 598 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Process unlocked */
<> 144:ef7eb2e8f9f7 601 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 return HAL_OK;
<> 144:ef7eb2e8f9f7 604 }
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @brief Writes a half-word buffer to the NOR memory. This function must be used
<> 144:ef7eb2e8f9f7 608 only with S29GL128P NOR memory.
<> 144:ef7eb2e8f9f7 609 * @param hnor: pointer to the NOR handle
<> 144:ef7eb2e8f9f7 610 * @param uwAddress: NOR memory internal start write address
<> 144:ef7eb2e8f9f7 611 * @param pData: pointer to source data buffer.
<> 144:ef7eb2e8f9f7 612 * @param uwBufferSize: Size of the buffer to write
<> 144:ef7eb2e8f9f7 613 * @retval HAL status
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 616 {
<> 144:ef7eb2e8f9f7 617 uint16_t * p_currentaddress = (uint16_t *)NULL;
<> 144:ef7eb2e8f9f7 618 uint16_t * p_endaddress = (uint16_t *)NULL;
<> 144:ef7eb2e8f9f7 619 uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Process Locked */
<> 144:ef7eb2e8f9f7 622 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 625 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 631 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 649 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Initialize variables */
<> 144:ef7eb2e8f9f7 652 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
<> 144:ef7eb2e8f9f7 653 p_endaddress = p_currentaddress + (uwBufferSize-1U);
<> 144:ef7eb2e8f9f7 654 lastloadedaddress = (uint32_t)(uwAddress);
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Issue unlock command sequence */
<> 144:ef7eb2e8f9f7 657 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 658 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Write Buffer Load Command */
<> 144:ef7eb2e8f9f7 661 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
AnnaBridge 167:e84263d55307 662 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U));
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Load Data into NOR Buffer */
<> 144:ef7eb2e8f9f7 665 while(p_currentaddress <= p_endaddress)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 /* Store last loaded address & data value (for polling) */
<> 144:ef7eb2e8f9f7 668 lastloadedaddress = (uint32_t)p_currentaddress;
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 NOR_WRITE(p_currentaddress, *pData++);
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 p_currentaddress ++;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 678 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Process unlocked */
<> 144:ef7eb2e8f9f7 681 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 return HAL_OK;
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @brief Erase the specified block of the NOR memory
<> 144:ef7eb2e8f9f7 689 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 690 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 691 * @param BlockAddress : Block to erase address
<> 144:ef7eb2e8f9f7 692 * @param Address: Device address
<> 144:ef7eb2e8f9f7 693 * @retval HAL status
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Process Locked */
<> 144:ef7eb2e8f9f7 700 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 703 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 709 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 727 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* Send block erase command sequence */
<> 144:ef7eb2e8f9f7 730 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 731 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 732 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 733 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 734 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 735 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 738 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Process unlocked */
<> 144:ef7eb2e8f9f7 741 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 return HAL_OK;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 }
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @brief Erase the entire NOR chip.
<> 144:ef7eb2e8f9f7 749 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 750 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 751 * @param Address : Device address
<> 144:ef7eb2e8f9f7 752 * @retval HAL status
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 uint32_t deviceaddress = 0U;
AnnaBridge 167:e84263d55307 757
AnnaBridge 167:e84263d55307 758 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 759 UNUSED(Address);
AnnaBridge 167:e84263d55307 760
<> 144:ef7eb2e8f9f7 761 /* Process Locked */
<> 144:ef7eb2e8f9f7 762 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 765 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 771 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 784 {
<> 144:ef7eb2e8f9f7 785 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 789 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Send NOR chip erase command sequence */
<> 144:ef7eb2e8f9f7 792 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 793 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 794 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 795 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 796 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 797 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 800 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Process unlocked */
<> 144:ef7eb2e8f9f7 803 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 return HAL_OK;
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /**
<> 144:ef7eb2e8f9f7 809 * @brief Read NOR flash CFI IDs
<> 144:ef7eb2e8f9f7 810 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 811 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 812 * @param pNOR_CFI : pointer to NOR CFI IDs structure
<> 144:ef7eb2e8f9f7 813 * @retval HAL status
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /* Process Locked */
<> 144:ef7eb2e8f9f7 820 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 823 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 829 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 847 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /* Send read CFI query command */
<> 144:ef7eb2e8f9f7 850 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* read the NOR CFI information */
<> 144:ef7eb2e8f9f7 853 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
<> 144:ef7eb2e8f9f7 854 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
<> 144:ef7eb2e8f9f7 855 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
<> 144:ef7eb2e8f9f7 856 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 859 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Process unlocked */
<> 144:ef7eb2e8f9f7 862 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 return HAL_OK;
<> 144:ef7eb2e8f9f7 865 }
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /**
<> 144:ef7eb2e8f9f7 868 * @}
<> 144:ef7eb2e8f9f7 869 */
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
<> 144:ef7eb2e8f9f7 872 * @brief management functions
<> 144:ef7eb2e8f9f7 873 *
<> 144:ef7eb2e8f9f7 874 @verbatim
<> 144:ef7eb2e8f9f7 875 ==============================================================================
<> 144:ef7eb2e8f9f7 876 ##### NOR Control functions #####
<> 144:ef7eb2e8f9f7 877 ==============================================================================
<> 144:ef7eb2e8f9f7 878 [..]
<> 144:ef7eb2e8f9f7 879 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 880 the NOR interface.
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 @endverbatim
<> 144:ef7eb2e8f9f7 883 * @{
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /**
<> 144:ef7eb2e8f9f7 887 * @brief Enables dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 888 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 889 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 890 * @retval HAL status
<> 144:ef7eb2e8f9f7 891 */
<> 144:ef7eb2e8f9f7 892 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 /* Process Locked */
<> 144:ef7eb2e8f9f7 895 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Enable write operation */
<> 144:ef7eb2e8f9f7 898 FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 901 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /* Process unlocked */
<> 144:ef7eb2e8f9f7 904 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 return HAL_OK;
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /**
<> 144:ef7eb2e8f9f7 910 * @brief Disables dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 911 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 912 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 913 * @retval HAL status
<> 144:ef7eb2e8f9f7 914 */
<> 144:ef7eb2e8f9f7 915 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 /* Process Locked */
<> 144:ef7eb2e8f9f7 918 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 921 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 /* Disable write operation */
<> 144:ef7eb2e8f9f7 924 FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 927 hnor->State = HAL_NOR_STATE_PROTECTED;
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Process unlocked */
<> 144:ef7eb2e8f9f7 930 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 return HAL_OK;
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /**
<> 144:ef7eb2e8f9f7 936 * @}
<> 144:ef7eb2e8f9f7 937 */
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
<> 144:ef7eb2e8f9f7 940 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 941 *
<> 144:ef7eb2e8f9f7 942 @verbatim
<> 144:ef7eb2e8f9f7 943 ==============================================================================
<> 144:ef7eb2e8f9f7 944 ##### NOR State functions #####
<> 144:ef7eb2e8f9f7 945 ==============================================================================
<> 144:ef7eb2e8f9f7 946 [..]
<> 144:ef7eb2e8f9f7 947 This subsection permits to get in run-time the status of the NOR controller
<> 144:ef7eb2e8f9f7 948 and the data flow.
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 @endverbatim
<> 144:ef7eb2e8f9f7 951 * @{
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
<> 144:ef7eb2e8f9f7 955 * @brief return the NOR controller state
<> 144:ef7eb2e8f9f7 956 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 957 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 958 * @retval NOR controller state
<> 144:ef7eb2e8f9f7 959 */
<> 144:ef7eb2e8f9f7 960 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 return hnor->State;
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /**
<> 144:ef7eb2e8f9f7 966 * @brief Returns the NOR operation status.
<> 144:ef7eb2e8f9f7 967 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 968 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 969 * @param Address: Device address
<> 144:ef7eb2e8f9f7 970 * @param Timeout: NOR programming Timeout
<> 144:ef7eb2e8f9f7 971 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
<> 144:ef7eb2e8f9f7 972 * or HAL_NOR_STATUS_TIMEOUT
<> 144:ef7eb2e8f9f7 973 */
<> 144:ef7eb2e8f9f7 974 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 977 uint16_t tmpSR1 = 0U, tmpSR2 = 0U;
<> 144:ef7eb2e8f9f7 978 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
<> 144:ef7eb2e8f9f7 981 HAL_NOR_MspWait(hnor, Timeout);
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /* Get the NOR memory operation status -------------------------------------*/
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Get tick */
<> 144:ef7eb2e8f9f7 986 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 987 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 990 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 status = HAL_NOR_STATUS_TIMEOUT;
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* Read NOR status register (DQ6 and DQ5) */
<> 144:ef7eb2e8f9f7 999 tmpSR1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1000 tmpSR2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
<> 144:ef7eb2e8f9f7 1003 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 return HAL_NOR_STATUS_SUCCESS ;
<> 144:ef7eb2e8f9f7 1006 }
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1009 {
<> 144:ef7eb2e8f9f7 1010 status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 tmpSR1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1014 tmpSR2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
<> 144:ef7eb2e8f9f7 1017 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1018 {
<> 144:ef7eb2e8f9f7 1019 return HAL_NOR_STATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 1020 }
<> 144:ef7eb2e8f9f7 1021 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 return HAL_NOR_STATUS_ERROR;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Return the operation status */
<> 144:ef7eb2e8f9f7 1028 return status;
<> 144:ef7eb2e8f9f7 1029 }
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /**
<> 144:ef7eb2e8f9f7 1032 * @}
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /**
<> 144:ef7eb2e8f9f7 1036 * @}
<> 144:ef7eb2e8f9f7 1037 */
<> 144:ef7eb2e8f9f7 1038 #endif /* HAL_NOR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1039 /**
<> 144:ef7eb2e8f9f7 1040 * @}
<> 144:ef7eb2e8f9f7 1041 */
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /**
<> 144:ef7eb2e8f9f7 1044 * @}
<> 144:ef7eb2e8f9f7 1045 */
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/