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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nand.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 167:e84263d55307

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_nand.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief NAND HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides a generic firmware to drive NAND memories mounted
<>	144:ef7eb2e8f9f7	9	* as external device.
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	@verbatim
<>	144:ef7eb2e8f9f7	12	==============================================================================
<>	144:ef7eb2e8f9f7	13	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	14	==============================================================================
<>	144:ef7eb2e8f9f7	15	[..]
<>	144:ef7eb2e8f9f7	16	This driver is a generic layered driver which contains a set of APIs used to
<>	144:ef7eb2e8f9f7	17	control NAND flash memories. It uses the FSMC layer functions to interface
<>	144:ef7eb2e8f9f7	18	with NAND devices. This driver is used as follows:
<>	144:ef7eb2e8f9f7	19
<>	144:ef7eb2e8f9f7	20	(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
<>	144:ef7eb2e8f9f7	21	with control and timing parameters for both common and attribute spaces.
<>	144:ef7eb2e8f9f7	22
<>	144:ef7eb2e8f9f7	23	(+) Read NAND flash memory maker and device IDs using the function
<>	144:ef7eb2e8f9f7	24	HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
<>	144:ef7eb2e8f9f7	25	structure declared by the function caller.
<>	144:ef7eb2e8f9f7	26
<>	144:ef7eb2e8f9f7	27	(+) Access NAND flash memory by read/write operations using the functions
AnnaBridge	167:e84263d55307	28	HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
AnnaBridge	167:e84263d55307	29	HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
AnnaBridge	167:e84263d55307	30	HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
AnnaBridge	167:e84263d55307	31	HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
<>	144:ef7eb2e8f9f7	32	to read/write page(s)/spare area(s). These functions use specific device
<>	144:ef7eb2e8f9f7	33	information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
<>	144:ef7eb2e8f9f7	34	structure. The read/write address information is contained by the Nand_Address_Typedef
<>	144:ef7eb2e8f9f7	35	structure passed as parameter.
<>	144:ef7eb2e8f9f7	36
<>	144:ef7eb2e8f9f7	37	(+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	(+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
<>	144:ef7eb2e8f9f7	40	The erase block address information is contained in the Nand_Address_Typedef
<>	144:ef7eb2e8f9f7	41	structure passed as parameter.
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43	(+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	(+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
<>	144:ef7eb2e8f9f7	46	HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
<>	144:ef7eb2e8f9f7	47	feature or the function HAL_NAND_GetECC() to get the ECC correction code.
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(+) You can monitor the NAND device HAL state by calling the function
<>	144:ef7eb2e8f9f7	50	HAL_NAND_GetState()
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	[..]
<>	144:ef7eb2e8f9f7	53	(@) This driver is a set of generic APIs which handle standard NAND flash operations.
<>	144:ef7eb2e8f9f7	54	If a NAND flash device contains different operations and/or implementations,
<>	144:ef7eb2e8f9f7	55	it should be implemented separately.
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	@endverbatim
<>	144:ef7eb2e8f9f7	58	******************************************************************************
<>	144:ef7eb2e8f9f7	59	* @attention
<>	144:ef7eb2e8f9f7	60	*
AnnaBridge	167:e84263d55307	61	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	62	*
<>	144:ef7eb2e8f9f7	63	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	64	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	65	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	66	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	67	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	68	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	69	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	70	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	71	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	72	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	73	*
<>	144:ef7eb2e8f9f7	74	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	75	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	76	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	77	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	78	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	79	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	80	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	81	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	82	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	83	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	84	*
<>	144:ef7eb2e8f9f7	85	******************************************************************************
<>	144:ef7eb2e8f9f7	86	*/
<>	144:ef7eb2e8f9f7	87
<>	144:ef7eb2e8f9f7	88	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	89	#include "stm32f2xx_hal.h"
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	92	* @{
<>	144:ef7eb2e8f9f7	93	*/
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95
<>	144:ef7eb2e8f9f7	96	#ifdef HAL_NAND_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	/** @defgroup NAND NAND
<>	144:ef7eb2e8f9f7	100	* @brief NAND HAL module driver
<>	144:ef7eb2e8f9f7	101	* @{
<>	144:ef7eb2e8f9f7	102	*/
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	105	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	106	/** @defgroup NAND_Private_Constants NAND Private Constants
<>	144:ef7eb2e8f9f7	107	* @{
<>	144:ef7eb2e8f9f7	108	*/
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	/**
<>	144:ef7eb2e8f9f7	111	* @}
<>	144:ef7eb2e8f9f7	112	*/
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	115	/** @defgroup NAND_Private_Macros NAND Private Macros
<>	144:ef7eb2e8f9f7	116	* @{
<>	144:ef7eb2e8f9f7	117	*/
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	/**
<>	144:ef7eb2e8f9f7	120	* @}
<>	144:ef7eb2e8f9f7	121	*/
<>	144:ef7eb2e8f9f7	122	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	123	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	124	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	125	/** @defgroup NAND_Exported_Functions NAND Exported Functions
<>	144:ef7eb2e8f9f7	126	* @{
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	130	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	131	*
<>	144:ef7eb2e8f9f7	132	@verbatim
<>	144:ef7eb2e8f9f7	133	==============================================================================
<>	144:ef7eb2e8f9f7	134	##### NAND Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	135	==============================================================================
<>	144:ef7eb2e8f9f7	136	[..]
<>	144:ef7eb2e8f9f7	137	This section provides functions allowing to initialize/de-initialize
<>	144:ef7eb2e8f9f7	138	the NAND memory
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	@endverbatim
<>	144:ef7eb2e8f9f7	141	* @{
<>	144:ef7eb2e8f9f7	142	*/
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144	/**
<>	144:ef7eb2e8f9f7	145	* @brief Perform NAND memory Initialization sequence
<>	144:ef7eb2e8f9f7	146	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	147	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	148	* @param ComSpace_Timing: pointer to Common space timing structure
<>	144:ef7eb2e8f9f7	149	* @param AttSpace_Timing: pointer to Attribute space timing structure
<>	144:ef7eb2e8f9f7	150	* @retval HAL status
<>	144:ef7eb2e8f9f7	151	*/
<>	144:ef7eb2e8f9f7	152	HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef hnand, FSMC_NAND_PCC_TimingTypeDef ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
<>	144:ef7eb2e8f9f7	153	{
<>	144:ef7eb2e8f9f7	154	/* Check the NAND handle state */
<>	144:ef7eb2e8f9f7	155	if(hnand == NULL)
<>	144:ef7eb2e8f9f7	156	{
<>	144:ef7eb2e8f9f7	157	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	158	}
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	if(hnand->State == HAL_NAND_STATE_RESET)
<>	144:ef7eb2e8f9f7	161	{
<>	144:ef7eb2e8f9f7	162	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	163	hnand->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	164	/* Initialize the low level hardware (MSP) */
<>	144:ef7eb2e8f9f7	165	HAL_NAND_MspInit(hnand);
<>	144:ef7eb2e8f9f7	166	}
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	/* Initialize NAND control Interface */
<>	144:ef7eb2e8f9f7	169	FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	/* Initialize NAND common space timing Interface */
<>	144:ef7eb2e8f9f7	172	FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	/* Initialize NAND attribute space timing Interface */
<>	144:ef7eb2e8f9f7	175	FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	176
<>	144:ef7eb2e8f9f7	177	/* Enable the NAND device */
<>	144:ef7eb2e8f9f7	178	__FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	181	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	return HAL_OK;
<>	144:ef7eb2e8f9f7	184	}
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186	/**
<>	144:ef7eb2e8f9f7	187	* @brief Perform NAND memory De-Initialization sequence
<>	144:ef7eb2e8f9f7	188	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	189	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	190	* @retval HAL status
<>	144:ef7eb2e8f9f7	191	*/
<>	144:ef7eb2e8f9f7	192	HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	193	{
<>	144:ef7eb2e8f9f7	194	/* Initialize the low level hardware (MSP) */
<>	144:ef7eb2e8f9f7	195	HAL_NAND_MspDeInit(hnand);
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	/* Configure the NAND registers with their reset values */
<>	144:ef7eb2e8f9f7	198	FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200	/* Reset the NAND controller state */
<>	144:ef7eb2e8f9f7	201	hnand->State = HAL_NAND_STATE_RESET;
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	/* Release Lock */
<>	144:ef7eb2e8f9f7	204	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	return HAL_OK;
<>	144:ef7eb2e8f9f7	207	}
<>	144:ef7eb2e8f9f7	208
<>	144:ef7eb2e8f9f7	209	/**
<>	144:ef7eb2e8f9f7	210	* @brief NAND MSP Init
<>	144:ef7eb2e8f9f7	211	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	212	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	213	* @retval None
<>	144:ef7eb2e8f9f7	214	*/
<>	144:ef7eb2e8f9f7	215	__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	216	{
<>	144:ef7eb2e8f9f7	217	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	218	UNUSED(hnand);
<>	144:ef7eb2e8f9f7	219	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	220	the HAL_NAND_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	221	*/
<>	144:ef7eb2e8f9f7	222	}
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	/**
<>	144:ef7eb2e8f9f7	225	* @brief NAND MSP DeInit
<>	144:ef7eb2e8f9f7	226	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	227	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	228	* @retval None
<>	144:ef7eb2e8f9f7	229	*/
<>	144:ef7eb2e8f9f7	230	__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	231	{
<>	144:ef7eb2e8f9f7	232	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	233	UNUSED(hnand);
<>	144:ef7eb2e8f9f7	234	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	235	the HAL_NAND_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	236	*/
<>	144:ef7eb2e8f9f7	237	}
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239
<>	144:ef7eb2e8f9f7	240	/**
<>	144:ef7eb2e8f9f7	241	* @brief This function handles NAND device interrupt request.
<>	144:ef7eb2e8f9f7	242	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	243	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	244	* @retval HAL status
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246	void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	247	{
<>	144:ef7eb2e8f9f7	248	/* Check NAND interrupt Rising edge flag */
<>	144:ef7eb2e8f9f7	249	if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
<>	144:ef7eb2e8f9f7	250	{
<>	144:ef7eb2e8f9f7	251	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	252	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/* Clear NAND interrupt Rising edge pending bit */
<>	144:ef7eb2e8f9f7	255	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
<>	144:ef7eb2e8f9f7	256	}
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/* Check NAND interrupt Level flag */
<>	144:ef7eb2e8f9f7	259	if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
<>	144:ef7eb2e8f9f7	260	{
<>	144:ef7eb2e8f9f7	261	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	262	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/* Clear NAND interrupt Level pending bit */
<>	144:ef7eb2e8f9f7	265	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
<>	144:ef7eb2e8f9f7	266	}
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	/* Check NAND interrupt Falling edge flag */
<>	144:ef7eb2e8f9f7	269	if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
<>	144:ef7eb2e8f9f7	270	{
<>	144:ef7eb2e8f9f7	271	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	272	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/* Clear NAND interrupt Falling edge pending bit */
<>	144:ef7eb2e8f9f7	275	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
<>	144:ef7eb2e8f9f7	276	}
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278	/* Check NAND interrupt FIFO empty flag */
<>	144:ef7eb2e8f9f7	279	if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
<>	144:ef7eb2e8f9f7	280	{
<>	144:ef7eb2e8f9f7	281	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	282	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	/* Clear NAND interrupt FIFO empty pending bit */
<>	144:ef7eb2e8f9f7	285	__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
<>	144:ef7eb2e8f9f7	286	}
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	}
<>	144:ef7eb2e8f9f7	289
<>	144:ef7eb2e8f9f7	290	/**
<>	144:ef7eb2e8f9f7	291	* @brief NAND interrupt feature callback
<>	144:ef7eb2e8f9f7	292	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	293	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	294	* @retval None
<>	144:ef7eb2e8f9f7	295	*/
<>	144:ef7eb2e8f9f7	296	__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	297	{
<>	144:ef7eb2e8f9f7	298	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	299	UNUSED(hnand);
<>	144:ef7eb2e8f9f7	300	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	301	the HAL_NAND_ITCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	302	*/
<>	144:ef7eb2e8f9f7	303	}
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	/**
<>	144:ef7eb2e8f9f7	306	* @}
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
<>	144:ef7eb2e8f9f7	310	* @brief Input Output and memory control functions
<>	144:ef7eb2e8f9f7	311	*
<>	144:ef7eb2e8f9f7	312	@verbatim
<>	144:ef7eb2e8f9f7	313	==============================================================================
<>	144:ef7eb2e8f9f7	314	##### NAND Input and Output functions #####
<>	144:ef7eb2e8f9f7	315	==============================================================================
<>	144:ef7eb2e8f9f7	316	[..]
<>	144:ef7eb2e8f9f7	317	This section provides functions allowing to use and control the NAND
<>	144:ef7eb2e8f9f7	318	memory
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	@endverbatim
<>	144:ef7eb2e8f9f7	321	* @{
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/**
<>	144:ef7eb2e8f9f7	325	* @brief Read the NAND memory electronic signature
<>	144:ef7eb2e8f9f7	326	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	327	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	328	* @param pNAND_ID: NAND ID structure
<>	144:ef7eb2e8f9f7	329	* @retval HAL status
<>	144:ef7eb2e8f9f7	330	*/
<>	144:ef7eb2e8f9f7	331	HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef hnand, NAND_IDTypeDef pNAND_ID)
<>	144:ef7eb2e8f9f7	332	{
<>	144:ef7eb2e8f9f7	333	__IO uint32_t data = 0U;
AnnaBridge	167:e84263d55307	334	__IO uint32_t data1 = 0U;
<>	144:ef7eb2e8f9f7	335	uint32_t deviceaddress = 0U;
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/* Process Locked */
<>	144:ef7eb2e8f9f7	338	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	341	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	342	{
<>	144:ef7eb2e8f9f7	343	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	344	}
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/* Identify the device address */
<>	144:ef7eb2e8f9f7	347	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	348	{
<>	144:ef7eb2e8f9f7	349	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	350	}
<>	144:ef7eb2e8f9f7	351	else
<>	144:ef7eb2e8f9f7	352	{
<>	144:ef7eb2e8f9f7	353	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	354	}
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	357	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	/* Send Read ID command sequence */
<>	144:ef7eb2e8f9f7	360	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_READID;
AnnaBridge	167:e84263d55307	361	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	362
AnnaBridge	167:e84263d55307	363	/* Read the electronic signature from NAND flash */
AnnaBridge	167:e84263d55307	364	if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
AnnaBridge	167:e84263d55307	365	{
AnnaBridge	167:e84263d55307	366	data = (__IO uint32_t )deviceaddress;
<>	144:ef7eb2e8f9f7	367
AnnaBridge	167:e84263d55307	368	/* Return the data read */
AnnaBridge	167:e84263d55307	369	pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
AnnaBridge	167:e84263d55307	370	pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
AnnaBridge	167:e84263d55307	371	pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
AnnaBridge	167:e84263d55307	372	pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
AnnaBridge	167:e84263d55307	373	}
AnnaBridge	167:e84263d55307	374	else
AnnaBridge	167:e84263d55307	375	{
AnnaBridge	167:e84263d55307	376	data = (__IO uint32_t )deviceaddress;
AnnaBridge	167:e84263d55307	377	data1 = ((__IO uint32_t )deviceaddress + 4U);
AnnaBridge	167:e84263d55307	378
AnnaBridge	167:e84263d55307	379	/* Return the data read */
AnnaBridge	167:e84263d55307	380	pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
AnnaBridge	167:e84263d55307	381	pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
AnnaBridge	167:e84263d55307	382	pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
AnnaBridge	167:e84263d55307	383	pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
AnnaBridge	167:e84263d55307	384	}
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	387	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/* Process unlocked */
<>	144:ef7eb2e8f9f7	390	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	return HAL_OK;
<>	144:ef7eb2e8f9f7	393	}
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	/**
<>	144:ef7eb2e8f9f7	396	* @brief NAND memory reset
<>	144:ef7eb2e8f9f7	397	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	398	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	399	* @retval HAL status
<>	144:ef7eb2e8f9f7	400	*/
<>	144:ef7eb2e8f9f7	401	HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	402	{
<>	144:ef7eb2e8f9f7	403	uint32_t deviceaddress = 0U;
<>	144:ef7eb2e8f9f7	404
<>	144:ef7eb2e8f9f7	405	/* Process Locked */
<>	144:ef7eb2e8f9f7	406	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	409	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	410	{
<>	144:ef7eb2e8f9f7	411	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	412	}
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	/* Identify the device address */
<>	144:ef7eb2e8f9f7	415	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	416	{
<>	144:ef7eb2e8f9f7	417	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	418	}
<>	144:ef7eb2e8f9f7	419	else
<>	144:ef7eb2e8f9f7	420	{
<>	144:ef7eb2e8f9f7	421	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	422	}
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	425	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	/* Send NAND reset command */
AnnaBridge	167:e84263d55307	428	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = 0xFF;
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	432	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	433
<>	144:ef7eb2e8f9f7	434	/* Process unlocked */
<>	144:ef7eb2e8f9f7	435	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	436
<>	144:ef7eb2e8f9f7	437	return HAL_OK;
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	}
AnnaBridge	167:e84263d55307	440
AnnaBridge	167:e84263d55307	441	/**
AnnaBridge	167:e84263d55307	442	* @brief Configure the device: Enter the physical parameters of the device
AnnaBridge	167:e84263d55307	443	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	444	* the configuration information for NAND module.
AnnaBridge	167:e84263d55307	445	* @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
AnnaBridge	167:e84263d55307	446	* @retval HAL status
AnnaBridge	167:e84263d55307	447	*/
AnnaBridge	167:e84263d55307	448	HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef hnand, NAND_DeviceConfigTypeDef pDeviceConfig)
AnnaBridge	167:e84263d55307	449	{
AnnaBridge	167:e84263d55307	450	hnand->Config.PageSize = pDeviceConfig->PageSize;
AnnaBridge	167:e84263d55307	451	hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
AnnaBridge	167:e84263d55307	452	hnand->Config.BlockSize = pDeviceConfig->BlockSize;
AnnaBridge	167:e84263d55307	453	hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
AnnaBridge	167:e84263d55307	454	hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
AnnaBridge	167:e84263d55307	455	hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
AnnaBridge	167:e84263d55307	456	hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
AnnaBridge	167:e84263d55307	457
AnnaBridge	167:e84263d55307	458	return HAL_OK;
AnnaBridge	167:e84263d55307	459	}
<>	144:ef7eb2e8f9f7	460
<>	144:ef7eb2e8f9f7	461	/**
AnnaBridge	167:e84263d55307	462	* @brief Read Page(s) from NAND memory block (8-bits addressing)
<>	144:ef7eb2e8f9f7	463	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	464	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	465	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	466	* @param pBuffer : pointer to destination read buffer
<>	144:ef7eb2e8f9f7	467	* @param NumPageToRead : number of pages to read from block
<>	144:ef7eb2e8f9f7	468	* @retval HAL status
<>	144:ef7eb2e8f9f7	469	*/
AnnaBridge	167:e84263d55307	470	HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
<>	144:ef7eb2e8f9f7	471	{
<>	144:ef7eb2e8f9f7	472	__IO uint32_t index = 0U;
AnnaBridge	167:e84263d55307	473	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	474	uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/* Process Locked */
<>	144:ef7eb2e8f9f7	477	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	478
<>	144:ef7eb2e8f9f7	479	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	480	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	481	{
<>	144:ef7eb2e8f9f7	482	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	483	}
<>	144:ef7eb2e8f9f7	484
<>	144:ef7eb2e8f9f7	485	/* Identify the device address */
<>	144:ef7eb2e8f9f7	486	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	487	{
<>	144:ef7eb2e8f9f7	488	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	489	}
<>	144:ef7eb2e8f9f7	490	else
<>	144:ef7eb2e8f9f7	491	{
<>	144:ef7eb2e8f9f7	492	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	493	}
<>	144:ef7eb2e8f9f7	494
<>	144:ef7eb2e8f9f7	495	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	496	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	497
AnnaBridge	167:e84263d55307	498	/* NAND raw address calculation */
AnnaBridge	167:e84263d55307	499	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
<>	144:ef7eb2e8f9f7	500
<>	144:ef7eb2e8f9f7	501	/* Page(s) read loop */
AnnaBridge	167:e84263d55307	502	while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
AnnaBridge	167:e84263d55307	503	{
<>	144:ef7eb2e8f9f7	504	/* update the buffer size */
AnnaBridge	167:e84263d55307	505	size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/* Send read page command sequence */
<>	144:ef7eb2e8f9f7	508	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	144:ef7eb2e8f9f7	509
AnnaBridge	167:e84263d55307	510	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	511	if((hnand->Config.PageSize) <= 512U)
<>	144:ef7eb2e8f9f7	512	{
AnnaBridge	167:e84263d55307	513	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	514	{
AnnaBridge	167:e84263d55307	515	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	516	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	517	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	518	}
AnnaBridge	167:e84263d55307	519	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	520	{
AnnaBridge	167:e84263d55307	521	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	522	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	523	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	524	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	525	}
AnnaBridge	167:e84263d55307	526	}
AnnaBridge	167:e84263d55307	527	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	528	{
AnnaBridge	167:e84263d55307	529	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	530	{
AnnaBridge	167:e84263d55307	531	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	532	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	533	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	534	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	535	}
AnnaBridge	167:e84263d55307	536	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	537	{
AnnaBridge	167:e84263d55307	538	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	539	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	540	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	541	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	542	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	543	}
<>	144:ef7eb2e8f9f7	544	}
<>	144:ef7eb2e8f9f7	545
<>	144:ef7eb2e8f9f7	546	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<>	144:ef7eb2e8f9f7	547
AnnaBridge	167:e84263d55307	548	/* Check if an extra command is needed for reading pages */
AnnaBridge	167:e84263d55307	549	if(hnand->Config.ExtraCommandEnable == ENABLE)
AnnaBridge	167:e84263d55307	550	{
AnnaBridge	167:e84263d55307	551	/* Get tick */
AnnaBridge	167:e84263d55307	552	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	553
AnnaBridge	167:e84263d55307	554	/* Read status until NAND is ready */
AnnaBridge	167:e84263d55307	555	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
AnnaBridge	167:e84263d55307	556	{
AnnaBridge	167:e84263d55307	557	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
AnnaBridge	167:e84263d55307	558	{
AnnaBridge	167:e84263d55307	559	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	560	}
AnnaBridge	167:e84263d55307	561	}
AnnaBridge	167:e84263d55307	562
AnnaBridge	167:e84263d55307	563	/* Go back to read mode */
AnnaBridge	167:e84263d55307	564	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = ((uint8_t)0x00);
AnnaBridge	167:e84263d55307	565	__DSB();
AnnaBridge	167:e84263d55307	566	}
AnnaBridge	167:e84263d55307	567
<>	144:ef7eb2e8f9f7	568	/* Get Data into Buffer */
<>	144:ef7eb2e8f9f7	569	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	570	{
<>	144:ef7eb2e8f9f7	571	(uint8_t )pBuffer++ = (uint8_t )deviceaddress;
<>	144:ef7eb2e8f9f7	572	}
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/* Increment read pages number */
AnnaBridge	167:e84263d55307	575	numPagesRead++;
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	/* Decrement pages to read */
<>	144:ef7eb2e8f9f7	578	NumPageToRead--;
<>	144:ef7eb2e8f9f7	579
<>	144:ef7eb2e8f9f7	580	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	581	nandaddress = (uint32_t)(nandaddress + 1U);
<>	144:ef7eb2e8f9f7	582	}
<>	144:ef7eb2e8f9f7	583
<>	144:ef7eb2e8f9f7	584	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	585	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	586
<>	144:ef7eb2e8f9f7	587	/* Process unlocked */
<>	144:ef7eb2e8f9f7	588	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	589
<>	144:ef7eb2e8f9f7	590	return HAL_OK;
<>	144:ef7eb2e8f9f7	591	}
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	/**
AnnaBridge	167:e84263d55307	594	* @brief Read Page(s) from NAND memory block (16-bits addressing)
AnnaBridge	167:e84263d55307	595	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	596	* the configuration information for NAND module.
AnnaBridge	167:e84263d55307	597	* @param pAddress : pointer to NAND address structure
AnnaBridge	167:e84263d55307	598	* @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
AnnaBridge	167:e84263d55307	599	* @param NumPageToRead : number of pages to read from block
AnnaBridge	167:e84263d55307	600	* @retval HAL status
AnnaBridge	167:e84263d55307	601	*/
AnnaBridge	167:e84263d55307	602	HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
AnnaBridge	167:e84263d55307	603	{
AnnaBridge	167:e84263d55307	604	__IO uint32_t index = 0U;
AnnaBridge	167:e84263d55307	605	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	606	uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
AnnaBridge	167:e84263d55307	607
AnnaBridge	167:e84263d55307	608	/* Process Locked */
AnnaBridge	167:e84263d55307	609	__HAL_LOCK(hnand);
AnnaBridge	167:e84263d55307	610
AnnaBridge	167:e84263d55307	611	/* Check the NAND controller state */
AnnaBridge	167:e84263d55307	612	if(hnand->State == HAL_NAND_STATE_BUSY)
AnnaBridge	167:e84263d55307	613	{
AnnaBridge	167:e84263d55307	614	return HAL_BUSY;
AnnaBridge	167:e84263d55307	615	}
AnnaBridge	167:e84263d55307	616
AnnaBridge	167:e84263d55307	617	/* Identify the device address */
AnnaBridge	167:e84263d55307	618	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
AnnaBridge	167:e84263d55307	619	{
AnnaBridge	167:e84263d55307	620	deviceaddress = NAND_DEVICE1;
AnnaBridge	167:e84263d55307	621	}
AnnaBridge	167:e84263d55307	622	else
AnnaBridge	167:e84263d55307	623	{
AnnaBridge	167:e84263d55307	624	deviceaddress = NAND_DEVICE2;
AnnaBridge	167:e84263d55307	625	}
AnnaBridge	167:e84263d55307	626
AnnaBridge	167:e84263d55307	627	/* Update the NAND controller state */
AnnaBridge	167:e84263d55307	628	hnand->State = HAL_NAND_STATE_BUSY;
AnnaBridge	167:e84263d55307	629
AnnaBridge	167:e84263d55307	630	/* NAND raw address calculation */
AnnaBridge	167:e84263d55307	631	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
AnnaBridge	167:e84263d55307	632
AnnaBridge	167:e84263d55307	633	/* Page(s) read loop */
AnnaBridge	167:e84263d55307	634	while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
AnnaBridge	167:e84263d55307	635	{
AnnaBridge	167:e84263d55307	636	/* update the buffer size */
AnnaBridge	167:e84263d55307	637	size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
AnnaBridge	167:e84263d55307	638
AnnaBridge	167:e84263d55307	639	/* Send read page command sequence */
AnnaBridge	167:e84263d55307	640	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
AnnaBridge	167:e84263d55307	641	__DSB();
AnnaBridge	167:e84263d55307	642
AnnaBridge	167:e84263d55307	643	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	644	if((hnand->Config.PageSize) <= 512U)
AnnaBridge	167:e84263d55307	645	{
AnnaBridge	167:e84263d55307	646	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	647	{
AnnaBridge	167:e84263d55307	648	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	649	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	650	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	651	}
AnnaBridge	167:e84263d55307	652	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	653	{
AnnaBridge	167:e84263d55307	654	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	655	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	656	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	657	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	658	}
AnnaBridge	167:e84263d55307	659	}
AnnaBridge	167:e84263d55307	660	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	661	{
AnnaBridge	167:e84263d55307	662	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	663	{
AnnaBridge	167:e84263d55307	664	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	665	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	666	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	667	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	668	}
AnnaBridge	167:e84263d55307	669	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	670	{
AnnaBridge	167:e84263d55307	671	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	672	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	673	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	674	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	675	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	676	}
AnnaBridge	167:e84263d55307	677	}
AnnaBridge	167:e84263d55307	678
AnnaBridge	167:e84263d55307	679	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
AnnaBridge	167:e84263d55307	680
AnnaBridge	167:e84263d55307	681	if(hnand->Config.ExtraCommandEnable == ENABLE)
AnnaBridge	167:e84263d55307	682	{
AnnaBridge	167:e84263d55307	683	/* Get tick */
AnnaBridge	167:e84263d55307	684	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	685
AnnaBridge	167:e84263d55307	686	/* Read status until NAND is ready */
AnnaBridge	167:e84263d55307	687	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
AnnaBridge	167:e84263d55307	688	{
AnnaBridge	167:e84263d55307	689	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
AnnaBridge	167:e84263d55307	690	{
AnnaBridge	167:e84263d55307	691	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	692	}
AnnaBridge	167:e84263d55307	693	}
AnnaBridge	167:e84263d55307	694
AnnaBridge	167:e84263d55307	695	/* Go back to read mode */
AnnaBridge	167:e84263d55307	696	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = ((uint8_t)0x00);
AnnaBridge	167:e84263d55307	697	}
AnnaBridge	167:e84263d55307	698
AnnaBridge	167:e84263d55307	699	/* Get Data into Buffer */
AnnaBridge	167:e84263d55307	700	for(; index < size; index++)
AnnaBridge	167:e84263d55307	701	{
AnnaBridge	167:e84263d55307	702	(uint16_t )pBuffer++ = (uint16_t )deviceaddress;
AnnaBridge	167:e84263d55307	703	}
AnnaBridge	167:e84263d55307	704
AnnaBridge	167:e84263d55307	705	/* Increment read pages number */
AnnaBridge	167:e84263d55307	706	numPagesRead++;
AnnaBridge	167:e84263d55307	707
AnnaBridge	167:e84263d55307	708	/* Decrement pages to read */
AnnaBridge	167:e84263d55307	709	NumPageToRead--;
AnnaBridge	167:e84263d55307	710
AnnaBridge	167:e84263d55307	711	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	712	nandaddress = (uint32_t)(nandaddress + 1U);
AnnaBridge	167:e84263d55307	713	}
AnnaBridge	167:e84263d55307	714
AnnaBridge	167:e84263d55307	715	/* Update the NAND controller state */
AnnaBridge	167:e84263d55307	716	hnand->State = HAL_NAND_STATE_READY;
AnnaBridge	167:e84263d55307	717
AnnaBridge	167:e84263d55307	718	/* Process unlocked */
AnnaBridge	167:e84263d55307	719	__HAL_UNLOCK(hnand);
AnnaBridge	167:e84263d55307	720
AnnaBridge	167:e84263d55307	721	return HAL_OK;
AnnaBridge	167:e84263d55307	722	}
AnnaBridge	167:e84263d55307	723
AnnaBridge	167:e84263d55307	724	/**
AnnaBridge	167:e84263d55307	725	* @brief Write Page(s) to NAND memory block (8-bits addressing)
<>	144:ef7eb2e8f9f7	726	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	727	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	728	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	729	* @param pBuffer : pointer to source buffer to write
<>	144:ef7eb2e8f9f7	730	* @param NumPageToWrite : number of pages to write to block
<>	144:ef7eb2e8f9f7	731	* @retval HAL status
<>	144:ef7eb2e8f9f7	732	*/
AnnaBridge	167:e84263d55307	733	HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
<>	144:ef7eb2e8f9f7	734	{
AnnaBridge	167:e84263d55307	735	__IO uint32_t index = 0U;
<>	144:ef7eb2e8f9f7	736	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	737	uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
AnnaBridge	167:e84263d55307	738
AnnaBridge	167:e84263d55307	739	/* Process Locked */
AnnaBridge	167:e84263d55307	740	__HAL_LOCK(hnand);
AnnaBridge	167:e84263d55307	741
AnnaBridge	167:e84263d55307	742	/* Check the NAND controller state */
AnnaBridge	167:e84263d55307	743	if(hnand->State == HAL_NAND_STATE_BUSY)
AnnaBridge	167:e84263d55307	744	{
AnnaBridge	167:e84263d55307	745	return HAL_BUSY;
AnnaBridge	167:e84263d55307	746	}
AnnaBridge	167:e84263d55307	747
AnnaBridge	167:e84263d55307	748	/* Identify the device address */
AnnaBridge	167:e84263d55307	749	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
AnnaBridge	167:e84263d55307	750	{
AnnaBridge	167:e84263d55307	751	deviceaddress = NAND_DEVICE1;
AnnaBridge	167:e84263d55307	752	}
AnnaBridge	167:e84263d55307	753	else
AnnaBridge	167:e84263d55307	754	{
AnnaBridge	167:e84263d55307	755	deviceaddress = NAND_DEVICE2;
AnnaBridge	167:e84263d55307	756	}
AnnaBridge	167:e84263d55307	757
AnnaBridge	167:e84263d55307	758	/* Update the NAND controller state */
AnnaBridge	167:e84263d55307	759	hnand->State = HAL_NAND_STATE_BUSY;
AnnaBridge	167:e84263d55307	760
AnnaBridge	167:e84263d55307	761	/* NAND raw address calculation */
AnnaBridge	167:e84263d55307	762	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
AnnaBridge	167:e84263d55307	763
AnnaBridge	167:e84263d55307	764	/* Page(s) write loop */
AnnaBridge	167:e84263d55307	765	while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
AnnaBridge	167:e84263d55307	766	{
AnnaBridge	167:e84263d55307	767	/* update the buffer size */
AnnaBridge	167:e84263d55307	768	size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
AnnaBridge	167:e84263d55307	769
AnnaBridge	167:e84263d55307	770	/* Send write page command sequence */
AnnaBridge	167:e84263d55307	771	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
AnnaBridge	167:e84263d55307	772	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE0;
AnnaBridge	167:e84263d55307	773
AnnaBridge	167:e84263d55307	774	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	775	if((hnand->Config.PageSize) <= 512U)
AnnaBridge	167:e84263d55307	776	{
AnnaBridge	167:e84263d55307	777	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	778	{
AnnaBridge	167:e84263d55307	779	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	780	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	781	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	782	}
AnnaBridge	167:e84263d55307	783	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	784	{
AnnaBridge	167:e84263d55307	785	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	786	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	787	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	788	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	789	}
AnnaBridge	167:e84263d55307	790	}
AnnaBridge	167:e84263d55307	791	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	792	{
AnnaBridge	167:e84263d55307	793	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	794	{
AnnaBridge	167:e84263d55307	795	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	796	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	797	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	798	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	799	}
AnnaBridge	167:e84263d55307	800	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	801	{
AnnaBridge	167:e84263d55307	802	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	803	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	804	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	805	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	806	__DSB();
AnnaBridge	167:e84263d55307	807	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	808	__DSB();
AnnaBridge	167:e84263d55307	809	}
AnnaBridge	167:e84263d55307	810	}
AnnaBridge	167:e84263d55307	811
AnnaBridge	167:e84263d55307	812
AnnaBridge	167:e84263d55307	813	/* Write data to memory */
AnnaBridge	167:e84263d55307	814	for(; index < size; index++)
AnnaBridge	167:e84263d55307	815	{
AnnaBridge	167:e84263d55307	816	(__IO uint8_t )deviceaddress = (uint8_t )pBuffer++;
AnnaBridge	167:e84263d55307	817	}
AnnaBridge	167:e84263d55307	818
AnnaBridge	167:e84263d55307	819	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
AnnaBridge	167:e84263d55307	820
AnnaBridge	167:e84263d55307	821	/* Read status until NAND is ready */
AnnaBridge	167:e84263d55307	822	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
AnnaBridge	167:e84263d55307	823	{
AnnaBridge	167:e84263d55307	824	/* Get tick */
AnnaBridge	167:e84263d55307	825	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	826
AnnaBridge	167:e84263d55307	827	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
AnnaBridge	167:e84263d55307	828	{
AnnaBridge	167:e84263d55307	829	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	830	}
AnnaBridge	167:e84263d55307	831	}
AnnaBridge	167:e84263d55307	832
AnnaBridge	167:e84263d55307	833	/* Increment written pages number */
AnnaBridge	167:e84263d55307	834	numPagesWritten++;
AnnaBridge	167:e84263d55307	835
AnnaBridge	167:e84263d55307	836	/* Decrement pages to write */
AnnaBridge	167:e84263d55307	837	NumPageToWrite--;
AnnaBridge	167:e84263d55307	838
AnnaBridge	167:e84263d55307	839	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	840	nandaddress = (uint32_t)(nandaddress + 1U);
AnnaBridge	167:e84263d55307	841	}
AnnaBridge	167:e84263d55307	842
AnnaBridge	167:e84263d55307	843	/* Update the NAND controller state */
AnnaBridge	167:e84263d55307	844	hnand->State = HAL_NAND_STATE_READY;
AnnaBridge	167:e84263d55307	845
AnnaBridge	167:e84263d55307	846	/* Process unlocked */
AnnaBridge	167:e84263d55307	847	__HAL_UNLOCK(hnand);
AnnaBridge	167:e84263d55307	848
AnnaBridge	167:e84263d55307	849	return HAL_OK;
AnnaBridge	167:e84263d55307	850	}
AnnaBridge	167:e84263d55307	851
AnnaBridge	167:e84263d55307	852	/**
AnnaBridge	167:e84263d55307	853	* @brief Write Page(s) to NAND memory block (16-bits addressing)
AnnaBridge	167:e84263d55307	854	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	855	* the configuration information for NAND module.
AnnaBridge	167:e84263d55307	856	* @param pAddress : pointer to NAND address structure
AnnaBridge	167:e84263d55307	857	* @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
AnnaBridge	167:e84263d55307	858	* @param NumPageToWrite : number of pages to write to block
AnnaBridge	167:e84263d55307	859	* @retval HAL status
AnnaBridge	167:e84263d55307	860	*/
AnnaBridge	167:e84263d55307	861	HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
AnnaBridge	167:e84263d55307	862	{
AnnaBridge	167:e84263d55307	863	__IO uint32_t index = 0U;
AnnaBridge	167:e84263d55307	864	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	865	uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	/* Process Locked */
<>	144:ef7eb2e8f9f7	868	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	871	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	872	{
<>	144:ef7eb2e8f9f7	873	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	874	}
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/* Identify the device address */
<>	144:ef7eb2e8f9f7	877	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	878	{
<>	144:ef7eb2e8f9f7	879	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	880	}
<>	144:ef7eb2e8f9f7	881	else
<>	144:ef7eb2e8f9f7	882	{
<>	144:ef7eb2e8f9f7	883	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	884	}
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	887	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	888
AnnaBridge	167:e84263d55307	889	/* NAND raw address calculation */
AnnaBridge	167:e84263d55307	890	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
AnnaBridge	167:e84263d55307	891
<>	144:ef7eb2e8f9f7	892	/* Page(s) write loop */
AnnaBridge	167:e84263d55307	893	while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	894	{
<>	144:ef7eb2e8f9f7	895	/* update the buffer size */
AnnaBridge	167:e84263d55307	896	size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
AnnaBridge	167:e84263d55307	897
<>	144:ef7eb2e8f9f7	898	/* Send write page command sequence */
<>	144:ef7eb2e8f9f7	899	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
AnnaBridge	167:e84263d55307	900	__DSB();
<>	144:ef7eb2e8f9f7	901	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE0;
AnnaBridge	167:e84263d55307	902	__DSB();
<>	144:ef7eb2e8f9f7	903
AnnaBridge	167:e84263d55307	904	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	905	if((hnand->Config.PageSize) <= 512U)
<>	144:ef7eb2e8f9f7	906	{
AnnaBridge	167:e84263d55307	907	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	908	{
AnnaBridge	167:e84263d55307	909	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	910	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	911	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	912	}
AnnaBridge	167:e84263d55307	913	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	914	{
AnnaBridge	167:e84263d55307	915	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	916	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	917	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	918	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	919	}
AnnaBridge	167:e84263d55307	920	}
AnnaBridge	167:e84263d55307	921	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	922	{
AnnaBridge	167:e84263d55307	923	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	924	{
AnnaBridge	167:e84263d55307	925	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	926	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	927	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	928	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	929	}
AnnaBridge	167:e84263d55307	930	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	931	{
AnnaBridge	167:e84263d55307	932	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	933	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	934	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	935	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	936	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	937	}
<>	144:ef7eb2e8f9f7	938	}
<>	144:ef7eb2e8f9f7	939
<>	144:ef7eb2e8f9f7	940	/* Write data to memory */
<>	144:ef7eb2e8f9f7	941	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	942	{
AnnaBridge	167:e84263d55307	943	(__IO uint16_t )deviceaddress = (uint16_t )pBuffer++;
<>	144:ef7eb2e8f9f7	944	}
<>	144:ef7eb2e8f9f7	945
<>	144:ef7eb2e8f9f7	946	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	/* Read status until NAND is ready */
<>	144:ef7eb2e8f9f7	949	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	950	{
AnnaBridge	167:e84263d55307	951	/* Get tick */
AnnaBridge	167:e84263d55307	952	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	953
<>	144:ef7eb2e8f9f7	954	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	144:ef7eb2e8f9f7	955	{
<>	144:ef7eb2e8f9f7	956	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	957	}
AnnaBridge	167:e84263d55307	958	}
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	/* Increment written pages number */
AnnaBridge	167:e84263d55307	961	numPagesWritten++;
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	/* Decrement pages to write */
<>	144:ef7eb2e8f9f7	964	NumPageToWrite--;
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	967	nandaddress = (uint32_t)(nandaddress + 1U);
<>	144:ef7eb2e8f9f7	968	}
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	971	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	972
<>	144:ef7eb2e8f9f7	973	/* Process unlocked */
AnnaBridge	167:e84263d55307	974	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	return HAL_OK;
<>	144:ef7eb2e8f9f7	977	}
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/**
<>	144:ef7eb2e8f9f7	980	* @brief Read Spare area(s) from NAND memory
<>	144:ef7eb2e8f9f7	981	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	982	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	983	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	984	* @param pBuffer: pointer to source buffer to write
<>	144:ef7eb2e8f9f7	985	* @param NumSpareAreaToRead: Number of spare area to read
<>	144:ef7eb2e8f9f7	986	* @retval HAL status
<>	144:ef7eb2e8f9f7	987	*/
AnnaBridge	167:e84263d55307	988	HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
<>	144:ef7eb2e8f9f7	989	{
AnnaBridge	167:e84263d55307	990	__IO uint32_t index = 0U;
AnnaBridge	167:e84263d55307	991	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	992	uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
<>	144:ef7eb2e8f9f7	993
<>	144:ef7eb2e8f9f7	994	/* Process Locked */
<>	144:ef7eb2e8f9f7	995	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	998	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	999	{
<>	144:ef7eb2e8f9f7	1000	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1001	}
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1004	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	1005	{
<>	144:ef7eb2e8f9f7	1006	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	1007	}
<>	144:ef7eb2e8f9f7	1008	else
<>	144:ef7eb2e8f9f7	1009	{
<>	144:ef7eb2e8f9f7	1010	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	1011	}
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1014	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1015
AnnaBridge	167:e84263d55307	1016	/* NAND raw address calculation */
AnnaBridge	167:e84263d55307	1017	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
AnnaBridge	167:e84263d55307	1018
AnnaBridge	167:e84263d55307	1019	/* Column in page address */
AnnaBridge	167:e84263d55307	1020	columnaddress = COLUMN_ADDRESS(hnand);
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	/* Spare area(s) read loop */
AnnaBridge	167:e84263d55307	1023	while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	1024	{
<>	144:ef7eb2e8f9f7	1025	/* update the buffer size */
AnnaBridge	167:e84263d55307	1026	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
<>	144:ef7eb2e8f9f7	1027
AnnaBridge	167:e84263d55307	1028	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	1029	if((hnand->Config.PageSize) <= 512U)
<>	144:ef7eb2e8f9f7	1030	{
AnnaBridge	167:e84263d55307	1031	/* Send read spare area command sequence */
AnnaBridge	167:e84263d55307	1032	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_C;
AnnaBridge	167:e84263d55307	1033
AnnaBridge	167:e84263d55307	1034	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1035	{
AnnaBridge	167:e84263d55307	1036	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1037	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1038	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1039	}
AnnaBridge	167:e84263d55307	1040	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1041	{
AnnaBridge	167:e84263d55307	1042	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1043	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1044	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1045	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1046	}
AnnaBridge	167:e84263d55307	1047	}
AnnaBridge	167:e84263d55307	1048	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	1049	{
AnnaBridge	167:e84263d55307	1050	/* Send read spare area command sequence */
AnnaBridge	167:e84263d55307	1051	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
AnnaBridge	167:e84263d55307	1052
AnnaBridge	167:e84263d55307	1053	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1054	{
AnnaBridge	167:e84263d55307	1055	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1056	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1057	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1058	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1059	}
AnnaBridge	167:e84263d55307	1060	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1061	{
AnnaBridge	167:e84263d55307	1062	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1063	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1064	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1065	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1066	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1067	}
AnnaBridge	167:e84263d55307	1068	}
<>	144:ef7eb2e8f9f7	1069
<>	144:ef7eb2e8f9f7	1070	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<>	144:ef7eb2e8f9f7	1071
AnnaBridge	167:e84263d55307	1072	if(hnand->Config.ExtraCommandEnable == ENABLE)
AnnaBridge	167:e84263d55307	1073	{
AnnaBridge	167:e84263d55307	1074	/* Get tick */
AnnaBridge	167:e84263d55307	1075	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	1076
AnnaBridge	167:e84263d55307	1077	/* Read status until NAND is ready */
AnnaBridge	167:e84263d55307	1078	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
AnnaBridge	167:e84263d55307	1079	{
AnnaBridge	167:e84263d55307	1080	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
AnnaBridge	167:e84263d55307	1081	{
AnnaBridge	167:e84263d55307	1082	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	1083	}
AnnaBridge	167:e84263d55307	1084	}
AnnaBridge	167:e84263d55307	1085
AnnaBridge	167:e84263d55307	1086	/* Go back to read mode */
AnnaBridge	167:e84263d55307	1087	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = ((uint8_t)0x00);
AnnaBridge	167:e84263d55307	1088	}
AnnaBridge	167:e84263d55307	1089
<>	144:ef7eb2e8f9f7	1090	/* Get Data into Buffer */
<>	144:ef7eb2e8f9f7	1091	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	1092	{
<>	144:ef7eb2e8f9f7	1093	(uint8_t )pBuffer++ = (uint8_t )deviceaddress;
<>	144:ef7eb2e8f9f7	1094	}
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	/* Increment read spare areas number */
AnnaBridge	167:e84263d55307	1097	numSpareAreaRead++;
<>	144:ef7eb2e8f9f7	1098
<>	144:ef7eb2e8f9f7	1099	/* Decrement spare areas to read */
<>	144:ef7eb2e8f9f7	1100	NumSpareAreaToRead--;
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	1103	nandaddress = (uint32_t)(nandaddress + 1U);
<>	144:ef7eb2e8f9f7	1104	}
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1107	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1110	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	return HAL_OK;
<>	144:ef7eb2e8f9f7	1113	}
<>	144:ef7eb2e8f9f7	1114
<>	144:ef7eb2e8f9f7	1115	/**
AnnaBridge	167:e84263d55307	1116	* @brief Read Spare area(s) from NAND memory (16-bits addressing)
AnnaBridge	167:e84263d55307	1117	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1118	* the configuration information for NAND module.
AnnaBridge	167:e84263d55307	1119	* @param pAddress : pointer to NAND address structure
AnnaBridge	167:e84263d55307	1120	* @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
AnnaBridge	167:e84263d55307	1121	* @param NumSpareAreaToRead: Number of spare area to read
AnnaBridge	167:e84263d55307	1122	* @retval HAL status
AnnaBridge	167:e84263d55307	1123	*/
AnnaBridge	167:e84263d55307	1124	HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
AnnaBridge	167:e84263d55307	1125	{
AnnaBridge	167:e84263d55307	1126	__IO uint32_t index = 0U;
AnnaBridge	167:e84263d55307	1127	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	1128	uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
AnnaBridge	167:e84263d55307	1129
AnnaBridge	167:e84263d55307	1130	/* Process Locked */
AnnaBridge	167:e84263d55307	1131	__HAL_LOCK(hnand);
AnnaBridge	167:e84263d55307	1132
AnnaBridge	167:e84263d55307	1133	/* Check the NAND controller state */
AnnaBridge	167:e84263d55307	1134	if(hnand->State == HAL_NAND_STATE_BUSY)
AnnaBridge	167:e84263d55307	1135	{
AnnaBridge	167:e84263d55307	1136	return HAL_BUSY;
AnnaBridge	167:e84263d55307	1137	}
AnnaBridge	167:e84263d55307	1138
AnnaBridge	167:e84263d55307	1139	/* Identify the device address */
AnnaBridge	167:e84263d55307	1140	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
AnnaBridge	167:e84263d55307	1141	{
AnnaBridge	167:e84263d55307	1142	deviceaddress = NAND_DEVICE1;
AnnaBridge	167:e84263d55307	1143	}
AnnaBridge	167:e84263d55307	1144	else
AnnaBridge	167:e84263d55307	1145	{
AnnaBridge	167:e84263d55307	1146	deviceaddress = NAND_DEVICE2;
AnnaBridge	167:e84263d55307	1147	}
AnnaBridge	167:e84263d55307	1148
AnnaBridge	167:e84263d55307	1149	/* Update the NAND controller state */
AnnaBridge	167:e84263d55307	1150	hnand->State = HAL_NAND_STATE_BUSY;
AnnaBridge	167:e84263d55307	1151
AnnaBridge	167:e84263d55307	1152	/* NAND raw address calculation */
AnnaBridge	167:e84263d55307	1153	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
AnnaBridge	167:e84263d55307	1154
AnnaBridge	167:e84263d55307	1155	/* Column in page address */
AnnaBridge	167:e84263d55307	1156	columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
AnnaBridge	167:e84263d55307	1157
AnnaBridge	167:e84263d55307	1158	/* Spare area(s) read loop */
AnnaBridge	167:e84263d55307	1159	while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
AnnaBridge	167:e84263d55307	1160	{
AnnaBridge	167:e84263d55307	1161	/* update the buffer size */
AnnaBridge	167:e84263d55307	1162	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
AnnaBridge	167:e84263d55307	1163
AnnaBridge	167:e84263d55307	1164	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	1165	if((hnand->Config.PageSize) <= 512U)
AnnaBridge	167:e84263d55307	1166	{
AnnaBridge	167:e84263d55307	1167	/* Send read spare area command sequence */
AnnaBridge	167:e84263d55307	1168	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_C;
AnnaBridge	167:e84263d55307	1169
AnnaBridge	167:e84263d55307	1170	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1171	{
AnnaBridge	167:e84263d55307	1172	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1173	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1174	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1175	}
AnnaBridge	167:e84263d55307	1176	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1177	{
AnnaBridge	167:e84263d55307	1178	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1179	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1180	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1181	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1182	}
AnnaBridge	167:e84263d55307	1183	}
AnnaBridge	167:e84263d55307	1184	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	1185	{
AnnaBridge	167:e84263d55307	1186	/* Send read spare area command sequence */
AnnaBridge	167:e84263d55307	1187	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
AnnaBridge	167:e84263d55307	1188
AnnaBridge	167:e84263d55307	1189	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1190	{
AnnaBridge	167:e84263d55307	1191	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1192	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1193	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1194	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1195	}
AnnaBridge	167:e84263d55307	1196	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1197	{
AnnaBridge	167:e84263d55307	1198	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1199	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1200	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1201	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1202	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1203	}
AnnaBridge	167:e84263d55307	1204	}
AnnaBridge	167:e84263d55307	1205
AnnaBridge	167:e84263d55307	1206	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
AnnaBridge	167:e84263d55307	1207
AnnaBridge	167:e84263d55307	1208	if(hnand->Config.ExtraCommandEnable == ENABLE)
AnnaBridge	167:e84263d55307	1209	{
AnnaBridge	167:e84263d55307	1210	/* Get tick */
AnnaBridge	167:e84263d55307	1211	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	1212
AnnaBridge	167:e84263d55307	1213	/* Read status until NAND is ready */
AnnaBridge	167:e84263d55307	1214	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
AnnaBridge	167:e84263d55307	1215	{
AnnaBridge	167:e84263d55307	1216	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
AnnaBridge	167:e84263d55307	1217	{
AnnaBridge	167:e84263d55307	1218	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	1219	}
AnnaBridge	167:e84263d55307	1220	}
AnnaBridge	167:e84263d55307	1221
AnnaBridge	167:e84263d55307	1222	/* Go back to read mode */
AnnaBridge	167:e84263d55307	1223	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = ((uint8_t)0x00);
AnnaBridge	167:e84263d55307	1224	}
AnnaBridge	167:e84263d55307	1225
AnnaBridge	167:e84263d55307	1226	/* Get Data into Buffer */
AnnaBridge	167:e84263d55307	1227	for(; index < size; index++)
AnnaBridge	167:e84263d55307	1228	{
AnnaBridge	167:e84263d55307	1229	(uint16_t )pBuffer++ = (uint16_t )deviceaddress;
AnnaBridge	167:e84263d55307	1230	}
AnnaBridge	167:e84263d55307	1231
AnnaBridge	167:e84263d55307	1232	/* Increment read spare areas number */
AnnaBridge	167:e84263d55307	1233	numSpareAreaRead++;
AnnaBridge	167:e84263d55307	1234
AnnaBridge	167:e84263d55307	1235	/* Decrement spare areas to read */
AnnaBridge	167:e84263d55307	1236	NumSpareAreaToRead--;
AnnaBridge	167:e84263d55307	1237
AnnaBridge	167:e84263d55307	1238	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	1239	nandaddress = (uint32_t)(nandaddress + 1U);
AnnaBridge	167:e84263d55307	1240	}
AnnaBridge	167:e84263d55307	1241
AnnaBridge	167:e84263d55307	1242	/* Update the NAND controller state */
AnnaBridge	167:e84263d55307	1243	hnand->State = HAL_NAND_STATE_READY;
AnnaBridge	167:e84263d55307	1244
AnnaBridge	167:e84263d55307	1245	/* Process unlocked */
AnnaBridge	167:e84263d55307	1246	__HAL_UNLOCK(hnand);
AnnaBridge	167:e84263d55307	1247
AnnaBridge	167:e84263d55307	1248	return HAL_OK;
AnnaBridge	167:e84263d55307	1249	}
AnnaBridge	167:e84263d55307	1250
AnnaBridge	167:e84263d55307	1251	/**
<>	144:ef7eb2e8f9f7	1252	* @brief Write Spare area(s) to NAND memory
<>	144:ef7eb2e8f9f7	1253	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1254	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1255	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	1256	* @param pBuffer : pointer to source buffer to write
<>	144:ef7eb2e8f9f7	1257	* @param NumSpareAreaTowrite : number of spare areas to write to block
<>	144:ef7eb2e8f9f7	1258	* @retval HAL status
<>	144:ef7eb2e8f9f7	1259	*/
AnnaBridge	167:e84263d55307	1260	HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
<>	144:ef7eb2e8f9f7	1261	{
<>	144:ef7eb2e8f9f7	1262	__IO uint32_t index = 0U;
<>	144:ef7eb2e8f9f7	1263	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	1264	uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
<>	144:ef7eb2e8f9f7	1265
<>	144:ef7eb2e8f9f7	1266	/* Process Locked */
<>	144:ef7eb2e8f9f7	1267	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	1268
<>	144:ef7eb2e8f9f7	1269	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1270	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1271	{
<>	144:ef7eb2e8f9f7	1272	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1273	}
<>	144:ef7eb2e8f9f7	1274
<>	144:ef7eb2e8f9f7	1275	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1276	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	1277	{
<>	144:ef7eb2e8f9f7	1278	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	1279	}
<>	144:ef7eb2e8f9f7	1280	else
<>	144:ef7eb2e8f9f7	1281	{
<>	144:ef7eb2e8f9f7	1282	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	1283	}
<>	144:ef7eb2e8f9f7	1284
<>	144:ef7eb2e8f9f7	1285	/* Update the FSMC_NAND controller state */
<>	144:ef7eb2e8f9f7	1286	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1287
AnnaBridge	167:e84263d55307	1288	/* Page address calculation */
AnnaBridge	167:e84263d55307	1289	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
AnnaBridge	167:e84263d55307	1290
AnnaBridge	167:e84263d55307	1291	/* Column in page address */
AnnaBridge	167:e84263d55307	1292	columnaddress = COLUMN_ADDRESS(hnand);
<>	144:ef7eb2e8f9f7	1293
<>	144:ef7eb2e8f9f7	1294	/* Spare area(s) write loop */
AnnaBridge	167:e84263d55307	1295	while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	1296	{
<>	144:ef7eb2e8f9f7	1297	/* update the buffer size */
AnnaBridge	167:e84263d55307	1298	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
<>	144:ef7eb2e8f9f7	1299
AnnaBridge	167:e84263d55307	1300	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	1301	if((hnand->Config.PageSize) <= 512U)
<>	144:ef7eb2e8f9f7	1302	{
AnnaBridge	167:e84263d55307	1303	/* Send write Spare area command sequence */
AnnaBridge	167:e84263d55307	1304	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_C;
AnnaBridge	167:e84263d55307	1305	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE0;
AnnaBridge	167:e84263d55307	1306
AnnaBridge	167:e84263d55307	1307	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1308	{
AnnaBridge	167:e84263d55307	1309	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1310	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1311	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1312	}
AnnaBridge	167:e84263d55307	1313	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1314	{
AnnaBridge	167:e84263d55307	1315	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1316	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1317	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1318	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1319	}
AnnaBridge	167:e84263d55307	1320	}
AnnaBridge	167:e84263d55307	1321	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	1322	{
AnnaBridge	167:e84263d55307	1323	/* Send write Spare area command sequence */
AnnaBridge	167:e84263d55307	1324	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
AnnaBridge	167:e84263d55307	1325	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE0;
AnnaBridge	167:e84263d55307	1326
AnnaBridge	167:e84263d55307	1327	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1328	{
AnnaBridge	167:e84263d55307	1329	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1330	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1331	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1332	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1333	}
AnnaBridge	167:e84263d55307	1334	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1335	{
AnnaBridge	167:e84263d55307	1336	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1337	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1338	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1339	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1340	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1341	}
<>	144:ef7eb2e8f9f7	1342	}
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/* Write data to memory */
<>	144:ef7eb2e8f9f7	1345	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	1346	{
<>	144:ef7eb2e8f9f7	1347	(__IO uint8_t )deviceaddress = (uint8_t )pBuffer++;
<>	144:ef7eb2e8f9f7	1348	}
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<>	144:ef7eb2e8f9f7	1351
<>	144:ef7eb2e8f9f7	1352	/* Get tick */
<>	144:ef7eb2e8f9f7	1353	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	/* Read status until NAND is ready */
<>	144:ef7eb2e8f9f7	1356	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	1357	{
<>	144:ef7eb2e8f9f7	1358	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	144:ef7eb2e8f9f7	1359	{
<>	144:ef7eb2e8f9f7	1360	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1361	}
<>	144:ef7eb2e8f9f7	1362	}
<>	144:ef7eb2e8f9f7	1363
<>	144:ef7eb2e8f9f7	1364	/* Increment written spare areas number */
AnnaBridge	167:e84263d55307	1365	numSpareAreaWritten++;
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	/* Decrement spare areas to write */
<>	144:ef7eb2e8f9f7	1368	NumSpareAreaTowrite--;
<>	144:ef7eb2e8f9f7	1369
<>	144:ef7eb2e8f9f7	1370	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	1371	nandaddress = (uint32_t)(nandaddress + 1U);
<>	144:ef7eb2e8f9f7	1372	}
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1375	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1378	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	return HAL_OK;
<>	144:ef7eb2e8f9f7	1381	}
<>	144:ef7eb2e8f9f7	1382
<>	144:ef7eb2e8f9f7	1383	/**
AnnaBridge	167:e84263d55307	1384	* @brief Write Spare area(s) to NAND memory (16-bits addressing)
AnnaBridge	167:e84263d55307	1385	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1386	* the configuration information for NAND module.
AnnaBridge	167:e84263d55307	1387	* @param pAddress : pointer to NAND address structure
AnnaBridge	167:e84263d55307	1388	* @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
AnnaBridge	167:e84263d55307	1389	* @param NumSpareAreaTowrite : number of spare areas to write to block
AnnaBridge	167:e84263d55307	1390	* @retval HAL status
AnnaBridge	167:e84263d55307	1391	*/
AnnaBridge	167:e84263d55307	1392	HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
AnnaBridge	167:e84263d55307	1393	{
AnnaBridge	167:e84263d55307	1394	__IO uint32_t index = 0U;
AnnaBridge	167:e84263d55307	1395	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	1396	uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
AnnaBridge	167:e84263d55307	1397
AnnaBridge	167:e84263d55307	1398	/* Process Locked */
AnnaBridge	167:e84263d55307	1399	__HAL_LOCK(hnand);
AnnaBridge	167:e84263d55307	1400
AnnaBridge	167:e84263d55307	1401	/* Check the NAND controller state */
AnnaBridge	167:e84263d55307	1402	if(hnand->State == HAL_NAND_STATE_BUSY)
AnnaBridge	167:e84263d55307	1403	{
AnnaBridge	167:e84263d55307	1404	return HAL_BUSY;
AnnaBridge	167:e84263d55307	1405	}
AnnaBridge	167:e84263d55307	1406
AnnaBridge	167:e84263d55307	1407	/* Identify the device address */
AnnaBridge	167:e84263d55307	1408	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
AnnaBridge	167:e84263d55307	1409	{
AnnaBridge	167:e84263d55307	1410	deviceaddress = NAND_DEVICE1;
AnnaBridge	167:e84263d55307	1411	}
AnnaBridge	167:e84263d55307	1412	else
AnnaBridge	167:e84263d55307	1413	{
AnnaBridge	167:e84263d55307	1414	deviceaddress = NAND_DEVICE2;
AnnaBridge	167:e84263d55307	1415	}
AnnaBridge	167:e84263d55307	1416
AnnaBridge	167:e84263d55307	1417	/* Update the FSMC_NAND controller state */
AnnaBridge	167:e84263d55307	1418	hnand->State = HAL_NAND_STATE_BUSY;
AnnaBridge	167:e84263d55307	1419
AnnaBridge	167:e84263d55307	1420	/* NAND raw address calculation */
AnnaBridge	167:e84263d55307	1421	nandaddress = ARRAY_ADDRESS(pAddress, hnand);
AnnaBridge	167:e84263d55307	1422
AnnaBridge	167:e84263d55307	1423	/* Column in page address */
AnnaBridge	167:e84263d55307	1424	columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
AnnaBridge	167:e84263d55307	1425
AnnaBridge	167:e84263d55307	1426	/* Spare area(s) write loop */
AnnaBridge	167:e84263d55307	1427	while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
AnnaBridge	167:e84263d55307	1428	{
AnnaBridge	167:e84263d55307	1429	/* update the buffer size */
AnnaBridge	167:e84263d55307	1430	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
AnnaBridge	167:e84263d55307	1431
AnnaBridge	167:e84263d55307	1432	/* Cards with page size <= 512 bytes */
AnnaBridge	167:e84263d55307	1433	if((hnand->Config.PageSize) <= 512U)
AnnaBridge	167:e84263d55307	1434	{
AnnaBridge	167:e84263d55307	1435	/* Send write Spare area command sequence */
AnnaBridge	167:e84263d55307	1436	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_C;
AnnaBridge	167:e84263d55307	1437	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE0;
AnnaBridge	167:e84263d55307	1438
AnnaBridge	167:e84263d55307	1439	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1440	{
AnnaBridge	167:e84263d55307	1441	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1442	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1443	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1444	}
AnnaBridge	167:e84263d55307	1445	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1446	{
AnnaBridge	167:e84263d55307	1447	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = 0x00;
AnnaBridge	167:e84263d55307	1448	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1449	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1450	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1451	}
AnnaBridge	167:e84263d55307	1452	}
AnnaBridge	167:e84263d55307	1453	else /* (hnand->Config.PageSize) > 512 */
AnnaBridge	167:e84263d55307	1454	{
AnnaBridge	167:e84263d55307	1455	/* Send write Spare area command sequence */
AnnaBridge	167:e84263d55307	1456	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_AREA_A;
AnnaBridge	167:e84263d55307	1457	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE0;
AnnaBridge	167:e84263d55307	1458
AnnaBridge	167:e84263d55307	1459	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
AnnaBridge	167:e84263d55307	1460	{
AnnaBridge	167:e84263d55307	1461	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1462	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1463	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1464	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1465	}
AnnaBridge	167:e84263d55307	1466	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
AnnaBridge	167:e84263d55307	1467	{
AnnaBridge	167:e84263d55307	1468	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1469	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
AnnaBridge	167:e84263d55307	1470	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1471	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1472	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
AnnaBridge	167:e84263d55307	1473	}
AnnaBridge	167:e84263d55307	1474	}
AnnaBridge	167:e84263d55307	1475
AnnaBridge	167:e84263d55307	1476	/* Write data to memory */
AnnaBridge	167:e84263d55307	1477	for(; index < size; index++)
AnnaBridge	167:e84263d55307	1478	{
AnnaBridge	167:e84263d55307	1479	(__IO uint16_t )deviceaddress = (uint16_t )pBuffer++;
AnnaBridge	167:e84263d55307	1480	}
AnnaBridge	167:e84263d55307	1481
AnnaBridge	167:e84263d55307	1482	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
AnnaBridge	167:e84263d55307	1483
AnnaBridge	167:e84263d55307	1484	/* Read status until NAND is ready */
AnnaBridge	167:e84263d55307	1485	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
AnnaBridge	167:e84263d55307	1486	{
AnnaBridge	167:e84263d55307	1487	/* Get tick */
AnnaBridge	167:e84263d55307	1488	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	1489
AnnaBridge	167:e84263d55307	1490	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
AnnaBridge	167:e84263d55307	1491	{
AnnaBridge	167:e84263d55307	1492	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	1493	}
AnnaBridge	167:e84263d55307	1494	}
AnnaBridge	167:e84263d55307	1495
AnnaBridge	167:e84263d55307	1496	/* Increment written spare areas number */
AnnaBridge	167:e84263d55307	1497	numSpareAreaWritten++;
AnnaBridge	167:e84263d55307	1498
AnnaBridge	167:e84263d55307	1499	/* Decrement spare areas to write */
AnnaBridge	167:e84263d55307	1500	NumSpareAreaTowrite--;
AnnaBridge	167:e84263d55307	1501
AnnaBridge	167:e84263d55307	1502	/* Increment the NAND address */
AnnaBridge	167:e84263d55307	1503	nandaddress = (uint32_t)(nandaddress + 1U);
AnnaBridge	167:e84263d55307	1504	}
AnnaBridge	167:e84263d55307	1505
AnnaBridge	167:e84263d55307	1506	/* Update the NAND controller state */
AnnaBridge	167:e84263d55307	1507	hnand->State = HAL_NAND_STATE_READY;
AnnaBridge	167:e84263d55307	1508
AnnaBridge	167:e84263d55307	1509	/* Process unlocked */
AnnaBridge	167:e84263d55307	1510	__HAL_UNLOCK(hnand);
AnnaBridge	167:e84263d55307	1511
AnnaBridge	167:e84263d55307	1512	return HAL_OK;
AnnaBridge	167:e84263d55307	1513	}
AnnaBridge	167:e84263d55307	1514
AnnaBridge	167:e84263d55307	1515	/**
<>	144:ef7eb2e8f9f7	1516	* @brief NAND memory Block erase
<>	144:ef7eb2e8f9f7	1517	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1518	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1519	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	1520	* @retval HAL status
<>	144:ef7eb2e8f9f7	1521	*/
<>	144:ef7eb2e8f9f7	1522	HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress)
<>	144:ef7eb2e8f9f7	1523	{
<>	144:ef7eb2e8f9f7	1524	uint32_t deviceaddress = 0U;
<>	144:ef7eb2e8f9f7	1525	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/* Process Locked */
<>	144:ef7eb2e8f9f7	1528	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1531	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1532	{
<>	144:ef7eb2e8f9f7	1533	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1534	}
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1537	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	1538	{
<>	144:ef7eb2e8f9f7	1539	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	1540	}
<>	144:ef7eb2e8f9f7	1541	else
<>	144:ef7eb2e8f9f7	1542	{
<>	144:ef7eb2e8f9f7	1543	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	1544	}
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1547	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	/* Send Erase block command sequence */
<>	144:ef7eb2e8f9f7	1550	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_ERASE0;
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<>	144:ef7eb2e8f9f7	1553	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<>	144:ef7eb2e8f9f7	1554	(__IO uint8_t )((uint32_t)(deviceaddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<>	144:ef7eb2e8f9f7	1555
<>	144:ef7eb2e8f9f7	1556	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_ERASE1;
<>	144:ef7eb2e8f9f7	1557
<>	144:ef7eb2e8f9f7	1558	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1559	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	/* Get tick */
<>	144:ef7eb2e8f9f7	1562	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	/* Read status until NAND is ready */
<>	144:ef7eb2e8f9f7	1565	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	1566	{
<>	144:ef7eb2e8f9f7	1567	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	144:ef7eb2e8f9f7	1568	{
<>	144:ef7eb2e8f9f7	1569	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1570	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1573	}
<>	144:ef7eb2e8f9f7	1574	}
<>	144:ef7eb2e8f9f7	1575
<>	144:ef7eb2e8f9f7	1576	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1577	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1578
<>	144:ef7eb2e8f9f7	1579	return HAL_OK;
<>	144:ef7eb2e8f9f7	1580	}
<>	144:ef7eb2e8f9f7	1581
<>	144:ef7eb2e8f9f7	1582	/**
<>	144:ef7eb2e8f9f7	1583	* @brief NAND memory read status
<>	144:ef7eb2e8f9f7	1584	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1585	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1586	* @retval NAND status
<>	144:ef7eb2e8f9f7	1587	*/
<>	144:ef7eb2e8f9f7	1588	uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	uint32_t data = 0U;
<>	144:ef7eb2e8f9f7	1591	uint32_t deviceaddress = 0U;
<>	144:ef7eb2e8f9f7	1592
<>	144:ef7eb2e8f9f7	1593	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1594	if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<>	144:ef7eb2e8f9f7	1595	{
<>	144:ef7eb2e8f9f7	1596	deviceaddress = NAND_DEVICE1;
<>	144:ef7eb2e8f9f7	1597	}
<>	144:ef7eb2e8f9f7	1598	else
<>	144:ef7eb2e8f9f7	1599	{
<>	144:ef7eb2e8f9f7	1600	deviceaddress = NAND_DEVICE2;
<>	144:ef7eb2e8f9f7	1601	}
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	/* Send Read status operation command */
<>	144:ef7eb2e8f9f7	1604	(__IO uint8_t )((uint32_t)(deviceaddress \| CMD_AREA)) = NAND_CMD_STATUS;
<>	144:ef7eb2e8f9f7	1605
<>	144:ef7eb2e8f9f7	1606	/* Read status register data */
<>	144:ef7eb2e8f9f7	1607	data = (__IO uint8_t )deviceaddress;
<>	144:ef7eb2e8f9f7	1608
<>	144:ef7eb2e8f9f7	1609	/* Return the status */
<>	144:ef7eb2e8f9f7	1610	if((data & NAND_ERROR) == NAND_ERROR)
<>	144:ef7eb2e8f9f7	1611	{
<>	144:ef7eb2e8f9f7	1612	return NAND_ERROR;
<>	144:ef7eb2e8f9f7	1613	}
<>	144:ef7eb2e8f9f7	1614	else if((data & NAND_READY) == NAND_READY)
<>	144:ef7eb2e8f9f7	1615	{
<>	144:ef7eb2e8f9f7	1616	return NAND_READY;
<>	144:ef7eb2e8f9f7	1617	}
<>	144:ef7eb2e8f9f7	1618
<>	144:ef7eb2e8f9f7	1619	return NAND_BUSY;
<>	144:ef7eb2e8f9f7	1620	}
<>	144:ef7eb2e8f9f7	1621
<>	144:ef7eb2e8f9f7	1622	/**
<>	144:ef7eb2e8f9f7	1623	* @brief Increment the NAND memory address
<>	144:ef7eb2e8f9f7	1624	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1625	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1626	* @param pAddress: pointer to NAND address structure
<>	144:ef7eb2e8f9f7	1627	* @retval The new status of the increment address operation. It can be:
<>	144:ef7eb2e8f9f7	1628	* - NAND_VALID_ADDRESS: When the new address is valid address
<>	144:ef7eb2e8f9f7	1629	* - NAND_INVALID_ADDRESS: When the new address is invalid address
<>	144:ef7eb2e8f9f7	1630	*/
<>	144:ef7eb2e8f9f7	1631	uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress)
<>	144:ef7eb2e8f9f7	1632	{
<>	144:ef7eb2e8f9f7	1633	uint32_t status = NAND_VALID_ADDRESS;
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	/* Increment page address */
<>	144:ef7eb2e8f9f7	1636	pAddress->Page++;
<>	144:ef7eb2e8f9f7	1637
<>	144:ef7eb2e8f9f7	1638	/* Check NAND address is valid */
AnnaBridge	167:e84263d55307	1639	if(pAddress->Page == hnand->Config.BlockSize)
<>	144:ef7eb2e8f9f7	1640	{
<>	144:ef7eb2e8f9f7	1641	pAddress->Page = 0U;
<>	144:ef7eb2e8f9f7	1642	pAddress->Block++;
<>	144:ef7eb2e8f9f7	1643
AnnaBridge	167:e84263d55307	1644	if(pAddress->Block == hnand->Config.PlaneSize)
<>	144:ef7eb2e8f9f7	1645	{
<>	144:ef7eb2e8f9f7	1646	pAddress->Block = 0U;
AnnaBridge	167:e84263d55307	1647	pAddress->Plane++;
<>	144:ef7eb2e8f9f7	1648
AnnaBridge	167:e84263d55307	1649	if(pAddress->Plane == (hnand->Config.PlaneSize/ hnand->Config.BlockNbr))
<>	144:ef7eb2e8f9f7	1650	{
<>	144:ef7eb2e8f9f7	1651	status = NAND_INVALID_ADDRESS;
<>	144:ef7eb2e8f9f7	1652	}
<>	144:ef7eb2e8f9f7	1653	}
<>	144:ef7eb2e8f9f7	1654	}
<>	144:ef7eb2e8f9f7	1655
<>	144:ef7eb2e8f9f7	1656	return (status);
<>	144:ef7eb2e8f9f7	1657	}
<>	144:ef7eb2e8f9f7	1658	/**
<>	144:ef7eb2e8f9f7	1659	* @}
<>	144:ef7eb2e8f9f7	1660	*/
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1663	* @brief management functions
<>	144:ef7eb2e8f9f7	1664	*
<>	144:ef7eb2e8f9f7	1665	@verbatim
<>	144:ef7eb2e8f9f7	1666	==============================================================================
<>	144:ef7eb2e8f9f7	1667	##### NAND Control functions #####
<>	144:ef7eb2e8f9f7	1668	==============================================================================
<>	144:ef7eb2e8f9f7	1669	[..]
<>	144:ef7eb2e8f9f7	1670	This subsection provides a set of functions allowing to control dynamically
<>	144:ef7eb2e8f9f7	1671	the NAND interface.
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673	@endverbatim
<>	144:ef7eb2e8f9f7	1674	* @{
<>	144:ef7eb2e8f9f7	1675	*/
<>	144:ef7eb2e8f9f7	1676
<>	144:ef7eb2e8f9f7	1677
<>	144:ef7eb2e8f9f7	1678	/**
<>	144:ef7eb2e8f9f7	1679	* @brief Enables dynamically NAND ECC feature.
<>	144:ef7eb2e8f9f7	1680	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1681	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1682	* @retval HAL status
<>	144:ef7eb2e8f9f7	1683	*/
<>	144:ef7eb2e8f9f7	1684	HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	1685	{
<>	144:ef7eb2e8f9f7	1686	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1687	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1688	{
<>	144:ef7eb2e8f9f7	1689	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1690	}
<>	144:ef7eb2e8f9f7	1691
<>	144:ef7eb2e8f9f7	1692	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1693	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/* Enable ECC feature */
<>	144:ef7eb2e8f9f7	1696	FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1699	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1700
<>	144:ef7eb2e8f9f7	1701	return HAL_OK;
<>	144:ef7eb2e8f9f7	1702	}
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	/**
<>	144:ef7eb2e8f9f7	1705	* @brief Disables dynamically FSMC_NAND ECC feature.
<>	144:ef7eb2e8f9f7	1706	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1707	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1708	* @retval HAL status
<>	144:ef7eb2e8f9f7	1709	*/
<>	144:ef7eb2e8f9f7	1710	HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	1711	{
<>	144:ef7eb2e8f9f7	1712	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1713	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1714	{
<>	144:ef7eb2e8f9f7	1715	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1716	}
<>	144:ef7eb2e8f9f7	1717
<>	144:ef7eb2e8f9f7	1718	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1719	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1720
<>	144:ef7eb2e8f9f7	1721	/* Disable ECC feature */
<>	144:ef7eb2e8f9f7	1722	FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1725	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1726
<>	144:ef7eb2e8f9f7	1727	return HAL_OK;
<>	144:ef7eb2e8f9f7	1728	}
<>	144:ef7eb2e8f9f7	1729
<>	144:ef7eb2e8f9f7	1730	/**
<>	144:ef7eb2e8f9f7	1731	* @brief Disables dynamically NAND ECC feature.
<>	144:ef7eb2e8f9f7	1732	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1733	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1734	* @param ECCval: pointer to ECC value
<>	144:ef7eb2e8f9f7	1735	* @param Timeout: maximum timeout to wait
<>	144:ef7eb2e8f9f7	1736	* @retval HAL status
<>	144:ef7eb2e8f9f7	1737	*/
<>	144:ef7eb2e8f9f7	1738	HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef hnand, uint32_t ECCval, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1739	{
<>	144:ef7eb2e8f9f7	1740	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1741
<>	144:ef7eb2e8f9f7	1742	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1743	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1744	{
<>	144:ef7eb2e8f9f7	1745	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1746	}
<>	144:ef7eb2e8f9f7	1747
<>	144:ef7eb2e8f9f7	1748	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1749	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1750
<>	144:ef7eb2e8f9f7	1751	/* Get NAND ECC value */
<>	144:ef7eb2e8f9f7	1752	status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
<>	144:ef7eb2e8f9f7	1753
<>	144:ef7eb2e8f9f7	1754	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1755	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1756
<>	144:ef7eb2e8f9f7	1757	return status;
<>	144:ef7eb2e8f9f7	1758	}
<>	144:ef7eb2e8f9f7	1759
<>	144:ef7eb2e8f9f7	1760	/**
<>	144:ef7eb2e8f9f7	1761	* @}
<>	144:ef7eb2e8f9f7	1762	*/
<>	144:ef7eb2e8f9f7	1763
<>	144:ef7eb2e8f9f7	1764
<>	144:ef7eb2e8f9f7	1765	/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
<>	144:ef7eb2e8f9f7	1766	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	1767	*
<>	144:ef7eb2e8f9f7	1768	@verbatim
<>	144:ef7eb2e8f9f7	1769	==============================================================================
<>	144:ef7eb2e8f9f7	1770	##### NAND State functions #####
<>	144:ef7eb2e8f9f7	1771	==============================================================================
<>	144:ef7eb2e8f9f7	1772	[..]
<>	144:ef7eb2e8f9f7	1773	This subsection permits to get in run-time the status of the NAND controller
<>	144:ef7eb2e8f9f7	1774	and the data flow.
<>	144:ef7eb2e8f9f7	1775
<>	144:ef7eb2e8f9f7	1776	@endverbatim
<>	144:ef7eb2e8f9f7	1777	* @{
<>	144:ef7eb2e8f9f7	1778	*/
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780	/**
<>	144:ef7eb2e8f9f7	1781	* @brief return the NAND state
<>	144:ef7eb2e8f9f7	1782	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1783	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1784	* @retval HAL state
<>	144:ef7eb2e8f9f7	1785	*/
<>	144:ef7eb2e8f9f7	1786	HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	1787	{
<>	144:ef7eb2e8f9f7	1788	return hnand->State;
<>	144:ef7eb2e8f9f7	1789	}
<>	144:ef7eb2e8f9f7	1790
<>	144:ef7eb2e8f9f7	1791	/**
<>	144:ef7eb2e8f9f7	1792	* @}
<>	144:ef7eb2e8f9f7	1793	*/
<>	144:ef7eb2e8f9f7	1794
<>	144:ef7eb2e8f9f7	1795	/**
<>	144:ef7eb2e8f9f7	1796	* @}
<>	144:ef7eb2e8f9f7	1797	*/
<>	144:ef7eb2e8f9f7	1798
<>	144:ef7eb2e8f9f7	1799	/**
<>	144:ef7eb2e8f9f7	1800	* @}
<>	144:ef7eb2e8f9f7	1801	*/
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	#endif /* HAL_NAND_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	1804
<>	144:ef7eb2e8f9f7	1805	/**
<>	144:ef7eb2e8f9f7	1806	* @}
<>	144:ef7eb2e8f9f7	1807	*/
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/