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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_irda.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_irda.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief IRDA HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the IrDA SIR ENDEC block (IrDA):
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization methods
<> 144:ef7eb2e8f9f7 11 * + IO operation methods
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control methods
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 The IRDA HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (#) Declare a IRDA_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 22 (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
<> 144:ef7eb2e8f9f7 23 (##) Enable the USARTx interface clock.
<> 144:ef7eb2e8f9f7 24 (##) IRDA pins configuration:
<> 144:ef7eb2e8f9f7 25 (+++) Enable the clock for the IRDA GPIOs.
<> 144:ef7eb2e8f9f7 26 (+++) Configure these IRDA pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 27 (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 28 and HAL_IRDA_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 29 (+++) Configure the USARTx interrupt priority.
<> 144:ef7eb2e8f9f7 30 (+++) Enable the NVIC USART IRQ handle.
<> 144:ef7eb2e8f9f7 31 (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 32 and HAL_IRDA_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 33 (+++) Declare a DMA handle structure for the Tx/Rx stream.
<> 144:ef7eb2e8f9f7 34 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 37 (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 38 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
<> 144:ef7eb2e8f9f7 41 and Mode(Receiver/Transmitter) in the hirda Init structure.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
<> 144:ef7eb2e8f9f7 44 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 45 by calling the customized HAL_IRDA_MspInit() API.
<> 144:ef7eb2e8f9f7 46 -@@- The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 47 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 48 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 53 =================================
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 56 (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 59 ===================================
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61 (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 62 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 63 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 64 (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 65 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 68 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 71 =============================
<> 144:ef7eb2e8f9f7 72 [..]
<> 144:ef7eb2e8f9f7 73 (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 74 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 75 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 76 (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 77 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 78 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 79 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 *** IRDA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 83 ===================================
<> 144:ef7eb2e8f9f7 84 [..]
<> 144:ef7eb2e8f9f7 85 Below the list of most used macros in IRDA HAL driver.
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
<> 144:ef7eb2e8f9f7 88 (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
<> 144:ef7eb2e8f9f7 89 (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
<> 144:ef7eb2e8f9f7 90 (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
<> 144:ef7eb2e8f9f7 91 (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 92 (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
AnnaBridge 167:e84263d55307 93
AnnaBridge 167:e84263d55307 94 [..]
<> 144:ef7eb2e8f9f7 95 (@) You can refer to the IRDA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
AnnaBridge 167:e84263d55307 101 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup IRDA IRDA
<> 144:ef7eb2e8f9f7 136 * @brief HAL IRDA module driver
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #ifdef HAL_IRDA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /** @addtogroup IRDA_Private_Constants
<> 144:ef7eb2e8f9f7 145 * @{
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @}
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 151 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 152 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 153 /** @addtogroup IRDA_Private_Functions
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 157 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 158 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 159 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 160 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 161 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 163 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 164 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 165 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 166 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 167 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 168 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 169 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 170 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
<> 144:ef7eb2e8f9f7 171 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 172 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 173 /**
<> 144:ef7eb2e8f9f7 174 * @}
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 177 /** @defgroup IRDA_Exported_Functions IrDA Exported Functions
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 182 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 183 *
<> 144:ef7eb2e8f9f7 184 @verbatim
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 ===============================================================================
<> 144:ef7eb2e8f9f7 187 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 188 ===============================================================================
<> 144:ef7eb2e8f9f7 189 [..]
<> 144:ef7eb2e8f9f7 190 This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<> 144:ef7eb2e8f9f7 191 in IrDA mode.
<> 144:ef7eb2e8f9f7 192 (+) For the asynchronous mode only these parameters can be configured:
<> 144:ef7eb2e8f9f7 193 (++) BaudRate
<> 144:ef7eb2e8f9f7 194 (++) WordLength
<> 144:ef7eb2e8f9f7 195 (++) Parity: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 196 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 197 Depending on the frame length defined by the M bit (8-bits or 9-bits),
<> 144:ef7eb2e8f9f7 198 please refer to Reference manual for possible IRDA frame formats.
<> 144:ef7eb2e8f9f7 199 (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
<> 144:ef7eb2e8f9f7 200 not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
<> 144:ef7eb2e8f9f7 201 specification specifies a minimum of 10 ms delay between transmission and
<> 144:ef7eb2e8f9f7 202 reception (IrDA is a half duplex protocol).
<> 144:ef7eb2e8f9f7 203 (++) Mode: Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 204 (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
<> 144:ef7eb2e8f9f7 205 [..]
<> 144:ef7eb2e8f9f7 206 The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
<> 144:ef7eb2e8f9f7 207 are available in reference manual).
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 @endverbatim
<> 144:ef7eb2e8f9f7 210 * @{
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @brief Initializes the IRDA mode according to the specified
<> 144:ef7eb2e8f9f7 215 * parameters in the IRDA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 216 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 217 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 218 * @retval HAL status
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 223 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Check the IRDA instance parameters */
<> 144:ef7eb2e8f9f7 229 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 230 /* Check the IRDA mode parameter in the IRDA handle */
<> 144:ef7eb2e8f9f7 231 assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 if(hirda->gState == HAL_IRDA_STATE_RESET)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 236 hirda->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 237 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 238 HAL_IRDA_MspInit(hirda);
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Disable the IRDA peripheral */
<> 144:ef7eb2e8f9f7 244 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Set the IRDA communication parameters */
<> 144:ef7eb2e8f9f7 247 IRDA_SetConfig(hirda);
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* In IrDA mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 250 - LINEN, STOP and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 251 - SCEN and HDSEL bits in the USART_CR3 register.*/
<> 144:ef7eb2e8f9f7 252 CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 253 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Enable the IRDA peripheral */
<> 144:ef7eb2e8f9f7 256 __HAL_IRDA_ENABLE(hirda);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Set the prescaler */
<> 144:ef7eb2e8f9f7 259 MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Configure the IrDA mode */
<> 144:ef7eb2e8f9f7 262 MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
<> 144:ef7eb2e8f9f7 265 SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Initialize the IRDA state*/
<> 144:ef7eb2e8f9f7 268 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 269 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 270 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 return HAL_OK;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /**
<> 144:ef7eb2e8f9f7 276 * @brief DeInitializes the IRDA peripheral
<> 144:ef7eb2e8f9f7 277 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 278 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 279 * @retval HAL status
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 284 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Check the parameters */
<> 144:ef7eb2e8f9f7 290 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 295 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 298 HAL_IRDA_MspDeInit(hirda);
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 hirda->gState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 303 hirda->RxState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Release Lock */
<> 144:ef7eb2e8f9f7 306 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 return HAL_OK;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @brief IRDA MSP Init.
<> 144:ef7eb2e8f9f7 313 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 314 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 315 * @retval None
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 320 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 321 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 322 the HAL_IRDA_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @brief IRDA MSP DeInit.
<> 144:ef7eb2e8f9f7 328 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 329 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 330 * @retval None
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 335 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 336 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 337 the HAL_IRDA_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @}
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 346 * @brief IRDA Transmit/Receive functions
<> 144:ef7eb2e8f9f7 347 *
<> 144:ef7eb2e8f9f7 348 @verbatim
<> 144:ef7eb2e8f9f7 349 ===============================================================================
<> 144:ef7eb2e8f9f7 350 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 351 ===============================================================================
<> 144:ef7eb2e8f9f7 352 This subsection provides a set of functions allowing to manage the IRDA data transfers.
<> 144:ef7eb2e8f9f7 353 [..]
<> 144:ef7eb2e8f9f7 354 IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
<> 144:ef7eb2e8f9f7 355 on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
<> 144:ef7eb2e8f9f7 356 is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
<> 144:ef7eb2e8f9f7 357 While receiving data, transmission should be avoided as the data to be transmitted
<> 144:ef7eb2e8f9f7 358 could be corrupted.
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 361 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 362 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 363 after finishing transfer.
<> 144:ef7eb2e8f9f7 364 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 365 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 366 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 367 dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 368 using DMA mode.
<> 144:ef7eb2e8f9f7 369 The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 370 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 371 The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 (#) Blocking mode API's are :
<> 144:ef7eb2e8f9f7 374 (++) HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 375 (++) HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 (#) Non Blocking mode APIs with Interrupt are :
<> 144:ef7eb2e8f9f7 378 (++) HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 379 (++) HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 380 (++) HAL_IRDA_IRQHandler()
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 (#) Non Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 383 (++) HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 384 (++) HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 387 (++) HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 388 (++) HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 389 (++) HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 @endverbatim
<> 144:ef7eb2e8f9f7 392 * @{
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @brief Sends an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 397 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 398 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 399 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 400 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 401 * @param Timeout: Specify timeout value
<> 144:ef7eb2e8f9f7 402 * @retval HAL status
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 407 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 410 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 411 {
AnnaBridge 167:e84263d55307 412 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Process Locked */
<> 144:ef7eb2e8f9f7 418 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 421 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Init tickstart for timeout managment*/
<> 144:ef7eb2e8f9f7 424 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 427 hirda->TxXferCount = Size;
AnnaBridge 167:e84263d55307 428 while(hirda->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 431 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437 tmp = (uint16_t*) pData;
AnnaBridge 167:e84263d55307 438 hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
<> 144:ef7eb2e8f9f7 439 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 440 {
AnnaBridge 167:e84263d55307 441 pData +=2;
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443 else
<> 144:ef7eb2e8f9f7 444 {
AnnaBridge 167:e84263d55307 445 pData +=1;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 else
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 453 }
AnnaBridge 167:e84263d55307 454 hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 464 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 467 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 return HAL_OK;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471 else
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 479 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 480 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 481 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 482 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 483 * @param Timeout: Specify timeout value
<> 144:ef7eb2e8f9f7 484 * @retval HAL status
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 489 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 492 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 493 {
AnnaBridge 167:e84263d55307 494 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /* Process Locked */
<> 144:ef7eb2e8f9f7 500 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 503 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Init tickstart for timeout managment*/
<> 144:ef7eb2e8f9f7 506 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 509 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 510 /* Check the remain data to be received */
AnnaBridge 167:e84263d55307 511 while(hirda->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 hirda->RxXferCount--;
<> 144:ef7eb2e8f9f7 514 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 521 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 522 {
AnnaBridge 167:e84263d55307 523 *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
AnnaBridge 167:e84263d55307 524 pData +=2;
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526 else
<> 144:ef7eb2e8f9f7 527 {
AnnaBridge 167:e84263d55307 528 *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
AnnaBridge 167:e84263d55307 529 pData +=1;
<> 144:ef7eb2e8f9f7 530 }
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532 else
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 539 {
AnnaBridge 167:e84263d55307 540 *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 else
<> 144:ef7eb2e8f9f7 543 {
AnnaBridge 167:e84263d55307 544 *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 550 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 553 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 return HAL_OK;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 else
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @brief Send an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 565 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 566 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 567 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 568 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 569 * @retval HAL status
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 574 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 575 {
AnnaBridge 167:e84263d55307 576 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 /* Process Locked */
<> 144:ef7eb2e8f9f7 581 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 584 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 585 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 586 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 587 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 590 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Enable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 593 SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 return HAL_OK;
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597 else
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 605 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 606 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 607 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 608 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 609 * @retval HAL status
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 614 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 615 {
AnnaBridge 167:e84263d55307 616 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Process Locked */
<> 144:ef7eb2e8f9f7 622 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 625 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 626 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 627 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 628 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 631 __HAL_UNLOCK(hirda);
AnnaBridge 167:e84263d55307 632
<> 144:ef7eb2e8f9f7 633 /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
<> 144:ef7eb2e8f9f7 634 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 637 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
AnnaBridge 167:e84263d55307 638
<> 144:ef7eb2e8f9f7 639 return HAL_OK;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641 else
<> 144:ef7eb2e8f9f7 642 {
<> 144:ef7eb2e8f9f7 643 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 644 }
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /**
<> 144:ef7eb2e8f9f7 648 * @brief Sends an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 649 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 650 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 651 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 652 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 653 * @retval HAL status
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 660 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 661 {
AnnaBridge 167:e84263d55307 662 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Process Locked */
<> 144:ef7eb2e8f9f7 668 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 671 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 672 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 673 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 674 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 677 hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 680 hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 683 hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /* Set the DMA abort callback */
<> 144:ef7eb2e8f9f7 686 hirda->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Enable the IRDA transmit DMA Stream */
<> 144:ef7eb2e8f9f7 689 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 690 HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Clear the TC flag in the SR register by writing 0 to it */
<> 144:ef7eb2e8f9f7 693 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 696 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 699 in the USART CR3 register */
<> 144:ef7eb2e8f9f7 700 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 return HAL_OK;
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 else
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /**
<> 144:ef7eb2e8f9f7 711 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 712 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 713 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 714 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 715 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 716 * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
<> 144:ef7eb2e8f9f7 717 * @retval HAL status
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 720 {
<> 144:ef7eb2e8f9f7 721 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 724 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 725 {
AnnaBridge 167:e84263d55307 726 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Process Locked */
<> 144:ef7eb2e8f9f7 732 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 735 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 736 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 737 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 740 hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 743 hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 746 hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Set the DMA abort callback */
<> 144:ef7eb2e8f9f7 749 hirda->hdmarx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 752 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 753 HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
AnnaBridge 167:e84263d55307 754
AnnaBridge 167:e84263d55307 755 /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
AnnaBridge 167:e84263d55307 756 __HAL_IRDA_CLEAR_OREFLAG(hirda);
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 759 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Enable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 762 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 765 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 768 in the USART CR3 register */
<> 144:ef7eb2e8f9f7 769 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 return HAL_OK;
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773 else
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /**
<> 144:ef7eb2e8f9f7 780 * @brief Pauses the DMA Transfer.
<> 144:ef7eb2e8f9f7 781 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 782 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 783 * @retval HAL status
<> 144:ef7eb2e8f9f7 784 */
<> 144:ef7eb2e8f9f7 785 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Process Locked */
<> 144:ef7eb2e8f9f7 790 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 793 if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 /* Disable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 796 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 800 if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 803 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 804 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Disable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 807 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 811 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 return HAL_OK;
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /**
<> 144:ef7eb2e8f9f7 817 * @brief Resumes the DMA Transfer.
<> 144:ef7eb2e8f9f7 818 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 819 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 820 * @retval HAL status
<> 144:ef7eb2e8f9f7 821 */
<> 144:ef7eb2e8f9f7 822 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 /* Process Locked */
<> 144:ef7eb2e8f9f7 825 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 /* Enable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 830 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 /* Clear the Overrun flag before resuming the Rx transfer */
<> 144:ef7eb2e8f9f7 835 __HAL_IRDA_CLEAR_OREFLAG(hirda);
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 838 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 839 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Enable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 842 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 846 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 return HAL_OK;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /**
<> 144:ef7eb2e8f9f7 852 * @brief Stops the DMA Transfer.
<> 144:ef7eb2e8f9f7 853 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 854 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 855 * @retval HAL status
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 860 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 861 to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
<> 144:ef7eb2e8f9f7 862 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 863 and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 864 */
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Stop IRDA DMA Tx request if ongoing */
<> 144:ef7eb2e8f9f7 867 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 868 if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* Abort the IRDA DMA Tx channel */
<> 144:ef7eb2e8f9f7 873 if(hirda->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 HAL_DMA_Abort(hirda->hdmatx);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877 IRDA_EndTxTransfer(hirda);
<> 144:ef7eb2e8f9f7 878 }
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /* Stop IRDA DMA Rx request if ongoing */
<> 144:ef7eb2e8f9f7 881 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 882 if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Abort the IRDA DMA Rx channel */
<> 144:ef7eb2e8f9f7 887 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 888 {
<> 144:ef7eb2e8f9f7 889 HAL_DMA_Abort(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893 return HAL_OK;
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /**
AnnaBridge 167:e84263d55307 897 * @brief Abort ongoing transfers (blocking mode).
AnnaBridge 167:e84263d55307 898 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 899 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 900 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 901 * - Disable PPP Interrupts
AnnaBridge 167:e84263d55307 902 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 903 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 904 * - Set handle State to READY
AnnaBridge 167:e84263d55307 905 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge 167:e84263d55307 906 * @retval HAL status
AnnaBridge 167:e84263d55307 907 */
AnnaBridge 167:e84263d55307 908 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 909 {
AnnaBridge 167:e84263d55307 910 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge 167:e84263d55307 911 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
AnnaBridge 167:e84263d55307 912 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
AnnaBridge 167:e84263d55307 913
AnnaBridge 167:e84263d55307 914 /* Disable the IRDA DMA Tx request if enabled */
AnnaBridge 167:e84263d55307 915 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
AnnaBridge 167:e84263d55307 916 {
AnnaBridge 167:e84263d55307 917 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
AnnaBridge 167:e84263d55307 918
AnnaBridge 167:e84263d55307 919 /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 920 if(hirda->hdmatx != NULL)
AnnaBridge 167:e84263d55307 921 {
AnnaBridge 167:e84263d55307 922 /* Set the IRDA DMA Abort callback to Null.
AnnaBridge 167:e84263d55307 923 No call back execution at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 924 hirda->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 925
AnnaBridge 167:e84263d55307 926 HAL_DMA_Abort(hirda->hdmatx);
AnnaBridge 167:e84263d55307 927 }
AnnaBridge 167:e84263d55307 928 }
AnnaBridge 167:e84263d55307 929
AnnaBridge 167:e84263d55307 930 /* Disable the IRDA DMA Rx request if enabled */
AnnaBridge 167:e84263d55307 931 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
AnnaBridge 167:e84263d55307 932 {
AnnaBridge 167:e84263d55307 933 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
AnnaBridge 167:e84263d55307 934
AnnaBridge 167:e84263d55307 935 /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 936 if(hirda->hdmarx != NULL)
AnnaBridge 167:e84263d55307 937 {
AnnaBridge 167:e84263d55307 938 /* Set the IRDA DMA Abort callback to Null.
AnnaBridge 167:e84263d55307 939 No call back execution at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 940 hirda->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 941
AnnaBridge 167:e84263d55307 942 HAL_DMA_Abort(hirda->hdmarx);
AnnaBridge 167:e84263d55307 943 }
AnnaBridge 167:e84263d55307 944 }
AnnaBridge 167:e84263d55307 945
AnnaBridge 167:e84263d55307 946 /* Reset Tx and Rx transfer counters */
AnnaBridge 167:e84263d55307 947 hirda->TxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 948 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 949
AnnaBridge 167:e84263d55307 950 /* Reset ErrorCode */
AnnaBridge 167:e84263d55307 951 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
AnnaBridge 167:e84263d55307 952
AnnaBridge 167:e84263d55307 953 /* Restore hirda->RxState and hirda->gState to Ready */
AnnaBridge 167:e84263d55307 954 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 955 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 956
AnnaBridge 167:e84263d55307 957 return HAL_OK;
AnnaBridge 167:e84263d55307 958 }
AnnaBridge 167:e84263d55307 959
AnnaBridge 167:e84263d55307 960 /**
AnnaBridge 167:e84263d55307 961 * @brief Abort ongoing Transmit transfer (blocking mode).
AnnaBridge 167:e84263d55307 962 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 963 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 964 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 965 * - Disable PPP Interrupts
AnnaBridge 167:e84263d55307 966 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 967 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 968 * - Set handle State to READY
AnnaBridge 167:e84263d55307 969 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge 167:e84263d55307 970 * @retval HAL status
AnnaBridge 167:e84263d55307 971 */
AnnaBridge 167:e84263d55307 972 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 973 {
AnnaBridge 167:e84263d55307 974 /* Disable TXEIE and TCIE interrupts */
AnnaBridge 167:e84263d55307 975 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
AnnaBridge 167:e84263d55307 976
AnnaBridge 167:e84263d55307 977 /* Disable the IRDA DMA Tx request if enabled */
AnnaBridge 167:e84263d55307 978 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
AnnaBridge 167:e84263d55307 979 {
AnnaBridge 167:e84263d55307 980 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
AnnaBridge 167:e84263d55307 981
AnnaBridge 167:e84263d55307 982 /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 983 if(hirda->hdmatx != NULL)
AnnaBridge 167:e84263d55307 984 {
AnnaBridge 167:e84263d55307 985 /* Set the IRDA DMA Abort callback to Null.
AnnaBridge 167:e84263d55307 986 No call back execution at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 987 hirda->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 988
AnnaBridge 167:e84263d55307 989 HAL_DMA_Abort(hirda->hdmatx);
AnnaBridge 167:e84263d55307 990 }
AnnaBridge 167:e84263d55307 991 }
AnnaBridge 167:e84263d55307 992
AnnaBridge 167:e84263d55307 993 /* Reset Tx transfer counter */
AnnaBridge 167:e84263d55307 994 hirda->TxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 995
AnnaBridge 167:e84263d55307 996 /* Restore hirda->gState to Ready */
AnnaBridge 167:e84263d55307 997 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 998
AnnaBridge 167:e84263d55307 999 return HAL_OK;
AnnaBridge 167:e84263d55307 1000 }
AnnaBridge 167:e84263d55307 1001
AnnaBridge 167:e84263d55307 1002 /**
AnnaBridge 167:e84263d55307 1003 * @brief Abort ongoing Receive transfer (blocking mode).
AnnaBridge 167:e84263d55307 1004 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 1005 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 1006 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 1007 * - Disable PPP Interrupts
AnnaBridge 167:e84263d55307 1008 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 1009 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 1010 * - Set handle State to READY
AnnaBridge 167:e84263d55307 1011 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge 167:e84263d55307 1012 * @retval HAL status
AnnaBridge 167:e84263d55307 1013 */
AnnaBridge 167:e84263d55307 1014 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 1015 {
AnnaBridge 167:e84263d55307 1016 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge 167:e84263d55307 1017 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
AnnaBridge 167:e84263d55307 1018 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
AnnaBridge 167:e84263d55307 1019
AnnaBridge 167:e84263d55307 1020 /* Disable the IRDA DMA Rx request if enabled */
AnnaBridge 167:e84263d55307 1021 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
AnnaBridge 167:e84263d55307 1022 {
AnnaBridge 167:e84263d55307 1023 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
AnnaBridge 167:e84263d55307 1024
AnnaBridge 167:e84263d55307 1025 /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 1026 if(hirda->hdmarx != NULL)
AnnaBridge 167:e84263d55307 1027 {
AnnaBridge 167:e84263d55307 1028 /* Set the IRDA DMA Abort callback to Null.
AnnaBridge 167:e84263d55307 1029 No call back execution at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 1030 hirda->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1031
AnnaBridge 167:e84263d55307 1032 HAL_DMA_Abort(hirda->hdmarx);
AnnaBridge 167:e84263d55307 1033 }
AnnaBridge 167:e84263d55307 1034 }
AnnaBridge 167:e84263d55307 1035
AnnaBridge 167:e84263d55307 1036 /* Reset Rx transfer counter */
AnnaBridge 167:e84263d55307 1037 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1038
AnnaBridge 167:e84263d55307 1039 /* Restore hirda->RxState to Ready */
AnnaBridge 167:e84263d55307 1040 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1041
AnnaBridge 167:e84263d55307 1042 return HAL_OK;
AnnaBridge 167:e84263d55307 1043 }
AnnaBridge 167:e84263d55307 1044
AnnaBridge 167:e84263d55307 1045 /**
AnnaBridge 167:e84263d55307 1046 * @brief Abort ongoing transfers (Interrupt mode).
AnnaBridge 167:e84263d55307 1047 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 1048 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 1049 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 1050 * - Disable PPP Interrupts
AnnaBridge 167:e84263d55307 1051 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 1052 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 1053 * - Set handle State to READY
AnnaBridge 167:e84263d55307 1054 * - At abort completion, call user abort complete callback
AnnaBridge 167:e84263d55307 1055 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge 167:e84263d55307 1056 * considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge 167:e84263d55307 1057 * @retval HAL status
AnnaBridge 167:e84263d55307 1058 */
AnnaBridge 167:e84263d55307 1059 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 1060 {
AnnaBridge 167:e84263d55307 1061 uint32_t AbortCplt = 1U;
AnnaBridge 167:e84263d55307 1062
AnnaBridge 167:e84263d55307 1063 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge 167:e84263d55307 1064 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
AnnaBridge 167:e84263d55307 1065 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
AnnaBridge 167:e84263d55307 1066
AnnaBridge 167:e84263d55307 1067 /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
AnnaBridge 167:e84263d55307 1068 before any call to DMA Abort functions */
AnnaBridge 167:e84263d55307 1069 /* DMA Tx Handle is valid */
AnnaBridge 167:e84263d55307 1070 if(hirda->hdmatx != NULL)
AnnaBridge 167:e84263d55307 1071 {
AnnaBridge 167:e84263d55307 1072 /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
AnnaBridge 167:e84263d55307 1073 Otherwise, set it to NULL */
AnnaBridge 167:e84263d55307 1074 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
AnnaBridge 167:e84263d55307 1075 {
AnnaBridge 167:e84263d55307 1076 hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
AnnaBridge 167:e84263d55307 1077 }
AnnaBridge 167:e84263d55307 1078 else
AnnaBridge 167:e84263d55307 1079 {
AnnaBridge 167:e84263d55307 1080 hirda->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1081 }
AnnaBridge 167:e84263d55307 1082 }
AnnaBridge 167:e84263d55307 1083 /* DMA Rx Handle is valid */
AnnaBridge 167:e84263d55307 1084 if(hirda->hdmarx != NULL)
AnnaBridge 167:e84263d55307 1085 {
AnnaBridge 167:e84263d55307 1086 /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
AnnaBridge 167:e84263d55307 1087 Otherwise, set it to NULL */
AnnaBridge 167:e84263d55307 1088 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
AnnaBridge 167:e84263d55307 1089 {
AnnaBridge 167:e84263d55307 1090 hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
AnnaBridge 167:e84263d55307 1091 }
AnnaBridge 167:e84263d55307 1092 else
AnnaBridge 167:e84263d55307 1093 {
AnnaBridge 167:e84263d55307 1094 hirda->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1095 }
AnnaBridge 167:e84263d55307 1096 }
AnnaBridge 167:e84263d55307 1097
AnnaBridge 167:e84263d55307 1098 /* Disable the IRDA DMA Tx request if enabled */
AnnaBridge 167:e84263d55307 1099 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
AnnaBridge 167:e84263d55307 1100 {
AnnaBridge 167:e84263d55307 1101 /* Disable DMA Tx at IRDA level */
AnnaBridge 167:e84263d55307 1102 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
AnnaBridge 167:e84263d55307 1103
AnnaBridge 167:e84263d55307 1104 /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
AnnaBridge 167:e84263d55307 1105 if(hirda->hdmatx != NULL)
AnnaBridge 167:e84263d55307 1106 {
AnnaBridge 167:e84263d55307 1107 /* IRDA Tx DMA Abort callback has already been initialised :
AnnaBridge 167:e84263d55307 1108 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 1109
AnnaBridge 167:e84263d55307 1110 /* Abort DMA TX */
AnnaBridge 167:e84263d55307 1111 if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
AnnaBridge 167:e84263d55307 1112 {
AnnaBridge 167:e84263d55307 1113 hirda->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1114 }
AnnaBridge 167:e84263d55307 1115 else
AnnaBridge 167:e84263d55307 1116 {
AnnaBridge 167:e84263d55307 1117 AbortCplt = 0x00U;
AnnaBridge 167:e84263d55307 1118 }
AnnaBridge 167:e84263d55307 1119 }
AnnaBridge 167:e84263d55307 1120 }
AnnaBridge 167:e84263d55307 1121
AnnaBridge 167:e84263d55307 1122 /* Disable the IRDA DMA Rx request if enabled */
AnnaBridge 167:e84263d55307 1123 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
AnnaBridge 167:e84263d55307 1124 {
AnnaBridge 167:e84263d55307 1125 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
AnnaBridge 167:e84263d55307 1126
AnnaBridge 167:e84263d55307 1127 /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
AnnaBridge 167:e84263d55307 1128 if(hirda->hdmarx != NULL)
AnnaBridge 167:e84263d55307 1129 {
AnnaBridge 167:e84263d55307 1130 /* IRDA Rx DMA Abort callback has already been initialised :
AnnaBridge 167:e84263d55307 1131 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 1132
AnnaBridge 167:e84263d55307 1133 /* Abort DMA RX */
AnnaBridge 167:e84263d55307 1134 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
AnnaBridge 167:e84263d55307 1135 {
AnnaBridge 167:e84263d55307 1136 hirda->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1137 AbortCplt = 0x01U;
AnnaBridge 167:e84263d55307 1138 }
AnnaBridge 167:e84263d55307 1139 else
AnnaBridge 167:e84263d55307 1140 {
AnnaBridge 167:e84263d55307 1141 AbortCplt = 0x00U;
AnnaBridge 167:e84263d55307 1142 }
AnnaBridge 167:e84263d55307 1143 }
AnnaBridge 167:e84263d55307 1144 }
AnnaBridge 167:e84263d55307 1145
AnnaBridge 167:e84263d55307 1146 /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
AnnaBridge 167:e84263d55307 1147 if(AbortCplt == 0x01U)
AnnaBridge 167:e84263d55307 1148 {
AnnaBridge 167:e84263d55307 1149 /* Reset Tx and Rx transfer counters */
AnnaBridge 167:e84263d55307 1150 hirda->TxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1151 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1152
AnnaBridge 167:e84263d55307 1153 /* Reset ErrorCode */
AnnaBridge 167:e84263d55307 1154 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
AnnaBridge 167:e84263d55307 1155
AnnaBridge 167:e84263d55307 1156 /* Restore hirda->gState and hirda->RxState to Ready */
AnnaBridge 167:e84263d55307 1157 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1158 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1159
AnnaBridge 167:e84263d55307 1160 /* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge 167:e84263d55307 1161 HAL_IRDA_AbortCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1162 }
AnnaBridge 167:e84263d55307 1163
AnnaBridge 167:e84263d55307 1164 return HAL_OK;
AnnaBridge 167:e84263d55307 1165 }
AnnaBridge 167:e84263d55307 1166
AnnaBridge 167:e84263d55307 1167 /**
AnnaBridge 167:e84263d55307 1168 * @brief Abort ongoing Transmit transfer (Interrupt mode).
AnnaBridge 167:e84263d55307 1169 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 1170 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 1171 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 1172 * - Disable PPP Interrupts
AnnaBridge 167:e84263d55307 1173 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 1174 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 1175 * - Set handle State to READY
AnnaBridge 167:e84263d55307 1176 * - At abort completion, call user abort complete callback
AnnaBridge 167:e84263d55307 1177 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge 167:e84263d55307 1178 * considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge 167:e84263d55307 1179 * @retval HAL status
AnnaBridge 167:e84263d55307 1180 */
AnnaBridge 167:e84263d55307 1181 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 1182 {
AnnaBridge 167:e84263d55307 1183 /* Disable TXEIE and TCIE interrupts */
AnnaBridge 167:e84263d55307 1184 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
AnnaBridge 167:e84263d55307 1185
AnnaBridge 167:e84263d55307 1186 /* Disable the IRDA DMA Tx request if enabled */
AnnaBridge 167:e84263d55307 1187 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
AnnaBridge 167:e84263d55307 1188 {
AnnaBridge 167:e84263d55307 1189 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
AnnaBridge 167:e84263d55307 1190
AnnaBridge 167:e84263d55307 1191 /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 1192 if(hirda->hdmatx != NULL)
AnnaBridge 167:e84263d55307 1193 {
AnnaBridge 167:e84263d55307 1194 /* Set the IRDA DMA Abort callback :
AnnaBridge 167:e84263d55307 1195 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 1196 hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
AnnaBridge 167:e84263d55307 1197
AnnaBridge 167:e84263d55307 1198 /* Abort DMA TX */
AnnaBridge 167:e84263d55307 1199 if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
AnnaBridge 167:e84263d55307 1200 {
AnnaBridge 167:e84263d55307 1201 /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
AnnaBridge 167:e84263d55307 1202 hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
AnnaBridge 167:e84263d55307 1203 }
AnnaBridge 167:e84263d55307 1204 }
AnnaBridge 167:e84263d55307 1205 else
AnnaBridge 167:e84263d55307 1206 {
AnnaBridge 167:e84263d55307 1207 /* Reset Tx transfer counter */
AnnaBridge 167:e84263d55307 1208 hirda->TxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1209
AnnaBridge 167:e84263d55307 1210 /* Restore hirda->gState to Ready */
AnnaBridge 167:e84263d55307 1211 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1212
AnnaBridge 167:e84263d55307 1213 /* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge 167:e84263d55307 1214 HAL_IRDA_AbortTransmitCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1215 }
AnnaBridge 167:e84263d55307 1216 }
AnnaBridge 167:e84263d55307 1217 else
AnnaBridge 167:e84263d55307 1218 {
AnnaBridge 167:e84263d55307 1219 /* Reset Tx transfer counter */
AnnaBridge 167:e84263d55307 1220 hirda->TxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1221
AnnaBridge 167:e84263d55307 1222 /* Restore hirda->gState to Ready */
AnnaBridge 167:e84263d55307 1223 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1224
AnnaBridge 167:e84263d55307 1225 /* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge 167:e84263d55307 1226 HAL_IRDA_AbortTransmitCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1227 }
AnnaBridge 167:e84263d55307 1228
AnnaBridge 167:e84263d55307 1229 return HAL_OK;
AnnaBridge 167:e84263d55307 1230 }
AnnaBridge 167:e84263d55307 1231
AnnaBridge 167:e84263d55307 1232 /**
AnnaBridge 167:e84263d55307 1233 * @brief Abort ongoing Receive transfer (Interrupt mode).
AnnaBridge 167:e84263d55307 1234 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 1235 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 1236 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 1237 * - Disable PPP Interrupts
AnnaBridge 167:e84263d55307 1238 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 1239 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 1240 * - Set handle State to READY
AnnaBridge 167:e84263d55307 1241 * - At abort completion, call user abort complete callback
AnnaBridge 167:e84263d55307 1242 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge 167:e84263d55307 1243 * considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge 167:e84263d55307 1244 * @retval HAL status
AnnaBridge 167:e84263d55307 1245 */
AnnaBridge 167:e84263d55307 1246 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 1247 {
AnnaBridge 167:e84263d55307 1248 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
AnnaBridge 167:e84263d55307 1249 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
AnnaBridge 167:e84263d55307 1250 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
AnnaBridge 167:e84263d55307 1251
AnnaBridge 167:e84263d55307 1252 /* Disable the IRDA DMA Rx request if enabled */
AnnaBridge 167:e84263d55307 1253 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
AnnaBridge 167:e84263d55307 1254 {
AnnaBridge 167:e84263d55307 1255 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
AnnaBridge 167:e84263d55307 1256
AnnaBridge 167:e84263d55307 1257 /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 1258 if(hirda->hdmarx != NULL)
AnnaBridge 167:e84263d55307 1259 {
AnnaBridge 167:e84263d55307 1260 /* Set the IRDA DMA Abort callback :
AnnaBridge 167:e84263d55307 1261 will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 1262 hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
AnnaBridge 167:e84263d55307 1263
AnnaBridge 167:e84263d55307 1264 /* Abort DMA RX */
AnnaBridge 167:e84263d55307 1265 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
AnnaBridge 167:e84263d55307 1266 {
AnnaBridge 167:e84263d55307 1267 /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
AnnaBridge 167:e84263d55307 1268 hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
AnnaBridge 167:e84263d55307 1269 }
AnnaBridge 167:e84263d55307 1270 }
AnnaBridge 167:e84263d55307 1271 else
AnnaBridge 167:e84263d55307 1272 {
AnnaBridge 167:e84263d55307 1273 /* Reset Rx transfer counter */
AnnaBridge 167:e84263d55307 1274 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1275
AnnaBridge 167:e84263d55307 1276 /* Restore hirda->RxState to Ready */
AnnaBridge 167:e84263d55307 1277 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1278
AnnaBridge 167:e84263d55307 1279 /* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge 167:e84263d55307 1280 HAL_IRDA_AbortReceiveCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1281 }
AnnaBridge 167:e84263d55307 1282 }
AnnaBridge 167:e84263d55307 1283 else
AnnaBridge 167:e84263d55307 1284 {
AnnaBridge 167:e84263d55307 1285 /* Reset Rx transfer counter */
AnnaBridge 167:e84263d55307 1286 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1287
AnnaBridge 167:e84263d55307 1288 /* Restore hirda->RxState to Ready */
AnnaBridge 167:e84263d55307 1289 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1290
AnnaBridge 167:e84263d55307 1291 /* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge 167:e84263d55307 1292 HAL_IRDA_AbortReceiveCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1293 }
AnnaBridge 167:e84263d55307 1294
AnnaBridge 167:e84263d55307 1295 return HAL_OK;
AnnaBridge 167:e84263d55307 1296 }
AnnaBridge 167:e84263d55307 1297
AnnaBridge 167:e84263d55307 1298 /**
<> 144:ef7eb2e8f9f7 1299 * @brief This function handles IRDA interrupt request.
<> 144:ef7eb2e8f9f7 1300 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1301 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1302 * @retval None
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 uint32_t isrflags = READ_REG(hirda->Instance->SR);
<> 144:ef7eb2e8f9f7 1307 uint32_t cr1its = READ_REG(hirda->Instance->CR1);
<> 144:ef7eb2e8f9f7 1308 uint32_t cr3its = READ_REG(hirda->Instance->CR3);
<> 144:ef7eb2e8f9f7 1309 uint32_t errorflags = 0x00U;
<> 144:ef7eb2e8f9f7 1310 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 /* If no error occurs */
<> 144:ef7eb2e8f9f7 1313 errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
<> 144:ef7eb2e8f9f7 1314 if(errorflags == RESET)
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 /* IRDA in mode Receiver -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1317 if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 144:ef7eb2e8f9f7 1318 {
<> 144:ef7eb2e8f9f7 1319 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 1320 return;
<> 144:ef7eb2e8f9f7 1321 }
<> 144:ef7eb2e8f9f7 1322 }
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* If some errors occur */
<> 144:ef7eb2e8f9f7 1325 if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
<> 144:ef7eb2e8f9f7 1326 {
<> 144:ef7eb2e8f9f7 1327 /* IRDA parity error interrupt occurred -------------------------------*/
<> 144:ef7eb2e8f9f7 1328 if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<> 144:ef7eb2e8f9f7 1329 {
<> 144:ef7eb2e8f9f7 1330 hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
<> 144:ef7eb2e8f9f7 1331 }
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* IRDA noise error interrupt occurred --------------------------------*/
<> 144:ef7eb2e8f9f7 1334 if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 1335 {
<> 144:ef7eb2e8f9f7 1336 hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
<> 144:ef7eb2e8f9f7 1337 }
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* IRDA frame error interrupt occurred --------------------------------*/
<> 144:ef7eb2e8f9f7 1340 if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 1341 {
<> 144:ef7eb2e8f9f7 1342 hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
<> 144:ef7eb2e8f9f7 1343 }
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* IRDA Over-Run interrupt occurred -----------------------------------*/
<> 144:ef7eb2e8f9f7 1346 if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 1347 {
<> 144:ef7eb2e8f9f7 1348 hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
<> 144:ef7eb2e8f9f7 1349 }
<> 144:ef7eb2e8f9f7 1350 /* Call IRDA Error Call back function if need be -----------------------*/
<> 144:ef7eb2e8f9f7 1351 if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1352 {
<> 144:ef7eb2e8f9f7 1353 /* IRDA in mode Receiver ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 1354 if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 144:ef7eb2e8f9f7 1355 {
<> 144:ef7eb2e8f9f7 1356 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1360 /* If Overrun error occurs, or if any error occurs in DMA mode reception,
<> 144:ef7eb2e8f9f7 1361 consider error as blocking */
<> 144:ef7eb2e8f9f7 1362 if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
<> 144:ef7eb2e8f9f7 1363 {
<> 144:ef7eb2e8f9f7 1364 /* Blocking error : transfer is aborted
<> 144:ef7eb2e8f9f7 1365 Set the IRDA state ready to be able to start again the process,
<> 144:ef7eb2e8f9f7 1366 Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<> 144:ef7eb2e8f9f7 1367 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Disable the IRDA DMA Rx request if enabled */
<> 144:ef7eb2e8f9f7 1370 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 144:ef7eb2e8f9f7 1371 {
<> 144:ef7eb2e8f9f7 1372 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1373
<> 144:ef7eb2e8f9f7 1374 /* Abort the IRDA DMA Rx channel */
<> 144:ef7eb2e8f9f7 1375 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1376 {
<> 144:ef7eb2e8f9f7 1377 /* Set the IRDA DMA Abort callback :
<> 144:ef7eb2e8f9f7 1378 will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
<> 144:ef7eb2e8f9f7 1379 hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<> 144:ef7eb2e8f9f7 1382 {
<> 144:ef7eb2e8f9f7 1383 /* Call Directly XferAbortCallback function in case of error */
<> 144:ef7eb2e8f9f7 1384 hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387 else
<> 144:ef7eb2e8f9f7 1388 {
<> 144:ef7eb2e8f9f7 1389 /* Call user error callback */
<> 144:ef7eb2e8f9f7 1390 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1391 }
<> 144:ef7eb2e8f9f7 1392 }
<> 144:ef7eb2e8f9f7 1393 else
<> 144:ef7eb2e8f9f7 1394 {
<> 144:ef7eb2e8f9f7 1395 /* Call user error callback */
<> 144:ef7eb2e8f9f7 1396 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1397 }
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399 else
<> 144:ef7eb2e8f9f7 1400 {
<> 144:ef7eb2e8f9f7 1401 /* Non Blocking error : transfer could go on.
<> 144:ef7eb2e8f9f7 1402 Error is notified to user through user error callback */
<> 144:ef7eb2e8f9f7 1403 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1404 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407 return;
<> 144:ef7eb2e8f9f7 1408 } /* End if some error occurs */
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /* IRDA in mode Transmitter ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1411 if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<> 144:ef7eb2e8f9f7 1412 {
<> 144:ef7eb2e8f9f7 1413 IRDA_Transmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1414 return;
<> 144:ef7eb2e8f9f7 1415 }
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /* IRDA in mode Transmitter end --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1418 if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<> 144:ef7eb2e8f9f7 1419 {
<> 144:ef7eb2e8f9f7 1420 IRDA_EndTransmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1421 return;
<> 144:ef7eb2e8f9f7 1422 }
<> 144:ef7eb2e8f9f7 1423 }
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 /**
<> 144:ef7eb2e8f9f7 1426 * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
<> 144:ef7eb2e8f9f7 1427 * @param hirda: IRDA handle.
<> 144:ef7eb2e8f9f7 1428 * @retval None
<> 144:ef7eb2e8f9f7 1429 */
<> 144:ef7eb2e8f9f7 1430 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1431 {
<> 144:ef7eb2e8f9f7 1432 /* Disable TXEIE and TCIE interrupts */
<> 144:ef7eb2e8f9f7 1433 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 1436 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1437 }
<> 144:ef7eb2e8f9f7 1438
<> 144:ef7eb2e8f9f7 1439 /**
<> 144:ef7eb2e8f9f7 1440 * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
<> 144:ef7eb2e8f9f7 1441 * @param hirda: IRDA handle.
<> 144:ef7eb2e8f9f7 1442 * @retval None
<> 144:ef7eb2e8f9f7 1443 */
<> 144:ef7eb2e8f9f7 1444 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1445 {
<> 144:ef7eb2e8f9f7 1446 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 1447 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 1448 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1451 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1452 }
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 /**
<> 144:ef7eb2e8f9f7 1455 * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
<> 144:ef7eb2e8f9f7 1456 * (To be called at end of DMA Abort procedure following error occurrence).
<> 144:ef7eb2e8f9f7 1457 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 1458 * @retval None
<> 144:ef7eb2e8f9f7 1459 */
<> 144:ef7eb2e8f9f7 1460 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1461 {
<> 144:ef7eb2e8f9f7 1462 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge 167:e84263d55307 1463 hirda->RxXferCount = 0x00;
AnnaBridge 167:e84263d55307 1464 hirda->TxXferCount = 0x00;
AnnaBridge 167:e84263d55307 1465
AnnaBridge 167:e84263d55307 1466 HAL_IRDA_ErrorCallback(hirda);
AnnaBridge 167:e84263d55307 1467 }
AnnaBridge 167:e84263d55307 1468
AnnaBridge 167:e84263d55307 1469 /**
AnnaBridge 167:e84263d55307 1470 * @brief DMA IRDA Tx communication abort callback, when initiated by user
AnnaBridge 167:e84263d55307 1471 * (To be called at end of DMA Tx Abort procedure following user abort request).
AnnaBridge 167:e84263d55307 1472 * @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge 167:e84263d55307 1473 * Abort still ongoing for Rx DMA Handle.
AnnaBridge 167:e84263d55307 1474 * @param hdma DMA handle.
AnnaBridge 167:e84263d55307 1475 * @retval None
AnnaBridge 167:e84263d55307 1476 */
AnnaBridge 167:e84263d55307 1477 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge 167:e84263d55307 1478 {
AnnaBridge 167:e84263d55307 1479 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge 167:e84263d55307 1480
AnnaBridge 167:e84263d55307 1481 hirda->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1482
AnnaBridge 167:e84263d55307 1483 /* Check if an Abort process is still ongoing */
AnnaBridge 167:e84263d55307 1484 if(hirda->hdmarx != NULL)
AnnaBridge 167:e84263d55307 1485 {
AnnaBridge 167:e84263d55307 1486 if(hirda->hdmarx->XferAbortCallback != NULL)
AnnaBridge 167:e84263d55307 1487 {
AnnaBridge 167:e84263d55307 1488 return;
AnnaBridge 167:e84263d55307 1489 }
AnnaBridge 167:e84263d55307 1490 }
AnnaBridge 167:e84263d55307 1491
AnnaBridge 167:e84263d55307 1492 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
AnnaBridge 167:e84263d55307 1493 hirda->TxXferCount = 0x00U;
<> 144:ef7eb2e8f9f7 1494 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1495
AnnaBridge 167:e84263d55307 1496 /* Reset ErrorCode */
AnnaBridge 167:e84263d55307 1497 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
AnnaBridge 167:e84263d55307 1498
AnnaBridge 167:e84263d55307 1499 /* Restore hirda->gState and hirda->RxState to Ready */
AnnaBridge 167:e84263d55307 1500 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1501 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1502
AnnaBridge 167:e84263d55307 1503 /* Call user Abort complete callback */
AnnaBridge 167:e84263d55307 1504 HAL_IRDA_AbortCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1505 }
AnnaBridge 167:e84263d55307 1506
AnnaBridge 167:e84263d55307 1507 /**
AnnaBridge 167:e84263d55307 1508 * @brief DMA IRDA Rx communication abort callback, when initiated by user
AnnaBridge 167:e84263d55307 1509 * (To be called at end of DMA Rx Abort procedure following user abort request).
AnnaBridge 167:e84263d55307 1510 * @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge 167:e84263d55307 1511 * Abort still ongoing for Tx DMA Handle.
AnnaBridge 167:e84263d55307 1512 * @param hdma DMA handle.
AnnaBridge 167:e84263d55307 1513 * @retval None
AnnaBridge 167:e84263d55307 1514 */
AnnaBridge 167:e84263d55307 1515 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge 167:e84263d55307 1516 {
AnnaBridge 167:e84263d55307 1517 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge 167:e84263d55307 1518
AnnaBridge 167:e84263d55307 1519 hirda->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1520
AnnaBridge 167:e84263d55307 1521 /* Check if an Abort process is still ongoing */
AnnaBridge 167:e84263d55307 1522 if(hirda->hdmatx != NULL)
AnnaBridge 167:e84263d55307 1523 {
AnnaBridge 167:e84263d55307 1524 if(hirda->hdmatx->XferAbortCallback != NULL)
AnnaBridge 167:e84263d55307 1525 {
AnnaBridge 167:e84263d55307 1526 return;
AnnaBridge 167:e84263d55307 1527 }
AnnaBridge 167:e84263d55307 1528 }
AnnaBridge 167:e84263d55307 1529
AnnaBridge 167:e84263d55307 1530 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
AnnaBridge 167:e84263d55307 1531 hirda->TxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1532 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1533
AnnaBridge 167:e84263d55307 1534 /* Reset ErrorCode */
AnnaBridge 167:e84263d55307 1535 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
AnnaBridge 167:e84263d55307 1536
AnnaBridge 167:e84263d55307 1537 /* Restore hirda->gState and hirda->RxState to Ready */
AnnaBridge 167:e84263d55307 1538 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1539 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1540
AnnaBridge 167:e84263d55307 1541 /* Call user Abort complete callback */
AnnaBridge 167:e84263d55307 1542 HAL_IRDA_AbortCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1543 }
AnnaBridge 167:e84263d55307 1544
AnnaBridge 167:e84263d55307 1545 /**
AnnaBridge 167:e84263d55307 1546 * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
AnnaBridge 167:e84263d55307 1547 * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
AnnaBridge 167:e84263d55307 1548 * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
AnnaBridge 167:e84263d55307 1549 * and leads to user Tx Abort Complete callback execution).
AnnaBridge 167:e84263d55307 1550 * @param hdma DMA handle.
AnnaBridge 167:e84263d55307 1551 * @retval None
AnnaBridge 167:e84263d55307 1552 */
AnnaBridge 167:e84263d55307 1553 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge 167:e84263d55307 1554 {
AnnaBridge 167:e84263d55307 1555 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge 167:e84263d55307 1556
<> 144:ef7eb2e8f9f7 1557 hirda->TxXferCount = 0x00U;
<> 144:ef7eb2e8f9f7 1558
AnnaBridge 167:e84263d55307 1559 /* Restore hirda->gState to Ready */
AnnaBridge 167:e84263d55307 1560 hirda->gState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1561
AnnaBridge 167:e84263d55307 1562 /* Call user Abort complete callback */
AnnaBridge 167:e84263d55307 1563 HAL_IRDA_AbortTransmitCpltCallback(hirda);
AnnaBridge 167:e84263d55307 1564 }
AnnaBridge 167:e84263d55307 1565
AnnaBridge 167:e84263d55307 1566 /**
AnnaBridge 167:e84263d55307 1567 * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
AnnaBridge 167:e84263d55307 1568 * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
AnnaBridge 167:e84263d55307 1569 * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
AnnaBridge 167:e84263d55307 1570 * and leads to user Rx Abort Complete callback execution).
AnnaBridge 167:e84263d55307 1571 * @param hdma DMA handle.
AnnaBridge 167:e84263d55307 1572 * @retval None
AnnaBridge 167:e84263d55307 1573 */
AnnaBridge 167:e84263d55307 1574 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge 167:e84263d55307 1575 {
AnnaBridge 167:e84263d55307 1576 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge 167:e84263d55307 1577
AnnaBridge 167:e84263d55307 1578 hirda->RxXferCount = 0x00U;
AnnaBridge 167:e84263d55307 1579
AnnaBridge 167:e84263d55307 1580 /* Restore hirda->RxState to Ready */
AnnaBridge 167:e84263d55307 1581 hirda->RxState = HAL_IRDA_STATE_READY;
AnnaBridge 167:e84263d55307 1582
AnnaBridge 167:e84263d55307 1583 /* Call user Abort complete callback */
AnnaBridge 167:e84263d55307 1584 HAL_IRDA_AbortReceiveCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1585 }
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 /**
<> 144:ef7eb2e8f9f7 1588 * @brief Tx Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1589 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1590 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1591 * @retval None
<> 144:ef7eb2e8f9f7 1592 */
<> 144:ef7eb2e8f9f7 1593 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1594 {
<> 144:ef7eb2e8f9f7 1595 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1596 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1597 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1598 the HAL_IRDA_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1599 */
<> 144:ef7eb2e8f9f7 1600 }
<> 144:ef7eb2e8f9f7 1601
<> 144:ef7eb2e8f9f7 1602 /**
<> 144:ef7eb2e8f9f7 1603 * @brief Tx Half Transfer completed callbacks.
<> 144:ef7eb2e8f9f7 1604 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1605 * the configuration information for the specified USART module.
<> 144:ef7eb2e8f9f7 1606 * @retval None
<> 144:ef7eb2e8f9f7 1607 */
<> 144:ef7eb2e8f9f7 1608 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1609 {
<> 144:ef7eb2e8f9f7 1610 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1611 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1612 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1613 the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1614 */
<> 144:ef7eb2e8f9f7 1615 }
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /**
<> 144:ef7eb2e8f9f7 1618 * @brief Rx Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1619 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1620 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1621 * @retval None
<> 144:ef7eb2e8f9f7 1622 */
<> 144:ef7eb2e8f9f7 1623 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1624 {
<> 144:ef7eb2e8f9f7 1625 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1626 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1627 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1628 the HAL_IRDA_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1629 */
<> 144:ef7eb2e8f9f7 1630 }
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 /**
<> 144:ef7eb2e8f9f7 1633 * @brief Rx Half Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1634 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1635 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1636 * @retval None
<> 144:ef7eb2e8f9f7 1637 */
<> 144:ef7eb2e8f9f7 1638 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1639 {
<> 144:ef7eb2e8f9f7 1640 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1641 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1642 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1643 the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1644 */
<> 144:ef7eb2e8f9f7 1645 }
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 /**
<> 144:ef7eb2e8f9f7 1648 * @brief IRDA error callbacks.
<> 144:ef7eb2e8f9f7 1649 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1650 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1651 * @retval None
<> 144:ef7eb2e8f9f7 1652 */
<> 144:ef7eb2e8f9f7 1653 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1654 {
<> 144:ef7eb2e8f9f7 1655 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1656 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1657 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1658 the HAL_IRDA_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1659 */
<> 144:ef7eb2e8f9f7 1660 }
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 /**
AnnaBridge 167:e84263d55307 1663 * @brief IRDA Abort Complete callback.
AnnaBridge 167:e84263d55307 1664 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 1665 * @retval None
AnnaBridge 167:e84263d55307 1666 */
AnnaBridge 167:e84263d55307 1667 __weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 1668 {
AnnaBridge 167:e84263d55307 1669 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 1670 UNUSED(hirda);
AnnaBridge 167:e84263d55307 1671
AnnaBridge 167:e84263d55307 1672 /* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge 167:e84263d55307 1673 the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
AnnaBridge 167:e84263d55307 1674 */
AnnaBridge 167:e84263d55307 1675 }
AnnaBridge 167:e84263d55307 1676
AnnaBridge 167:e84263d55307 1677 /**
AnnaBridge 167:e84263d55307 1678 * @brief IRDA Abort Transmit Complete callback.
AnnaBridge 167:e84263d55307 1679 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 1680 * @retval None
AnnaBridge 167:e84263d55307 1681 */
AnnaBridge 167:e84263d55307 1682 __weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 1683 {
AnnaBridge 167:e84263d55307 1684 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 1685 UNUSED(hirda);
AnnaBridge 167:e84263d55307 1686
AnnaBridge 167:e84263d55307 1687 /* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge 167:e84263d55307 1688 the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
AnnaBridge 167:e84263d55307 1689 */
AnnaBridge 167:e84263d55307 1690 }
AnnaBridge 167:e84263d55307 1691
AnnaBridge 167:e84263d55307 1692 /**
AnnaBridge 167:e84263d55307 1693 * @brief IRDA Abort ReceiveComplete callback.
AnnaBridge 167:e84263d55307 1694 * @param hirda IRDA handle.
AnnaBridge 167:e84263d55307 1695 * @retval None
AnnaBridge 167:e84263d55307 1696 */
AnnaBridge 167:e84263d55307 1697 __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
AnnaBridge 167:e84263d55307 1698 {
AnnaBridge 167:e84263d55307 1699 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 1700 UNUSED(hirda);
AnnaBridge 167:e84263d55307 1701
AnnaBridge 167:e84263d55307 1702 /* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge 167:e84263d55307 1703 the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
AnnaBridge 167:e84263d55307 1704 */
AnnaBridge 167:e84263d55307 1705 }
AnnaBridge 167:e84263d55307 1706
AnnaBridge 167:e84263d55307 1707 /**
<> 144:ef7eb2e8f9f7 1708 * @}
<> 144:ef7eb2e8f9f7 1709 */
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1712 * @brief IRDA State and Errors functions
<> 144:ef7eb2e8f9f7 1713 *
<> 144:ef7eb2e8f9f7 1714 @verbatim
<> 144:ef7eb2e8f9f7 1715 ==============================================================================
<> 144:ef7eb2e8f9f7 1716 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1717 ==============================================================================
<> 144:ef7eb2e8f9f7 1718 [..]
<> 144:ef7eb2e8f9f7 1719 This subsection provides a set of functions allowing to return the State of IrDA
<> 144:ef7eb2e8f9f7 1720 communication process and also return Peripheral Errors occurred during communication process
<> 144:ef7eb2e8f9f7 1721 (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
<> 144:ef7eb2e8f9f7 1722 (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
<> 144:ef7eb2e8f9f7 1723
<> 144:ef7eb2e8f9f7 1724 @endverbatim
<> 144:ef7eb2e8f9f7 1725 * @{
<> 144:ef7eb2e8f9f7 1726 */
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 /**
<> 144:ef7eb2e8f9f7 1729 * @brief Returns the IRDA state.
<> 144:ef7eb2e8f9f7 1730 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1731 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1732 * @retval HAL state
<> 144:ef7eb2e8f9f7 1733 */
<> 144:ef7eb2e8f9f7 1734 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1735 {
<> 144:ef7eb2e8f9f7 1736 uint32_t temp1 = 0x00U, temp2 = 0x00U;
<> 144:ef7eb2e8f9f7 1737 temp1 = hirda->gState;
<> 144:ef7eb2e8f9f7 1738 temp2 = hirda->RxState;
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 1741 }
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /**
<> 144:ef7eb2e8f9f7 1744 * @brief Return the IARDA error code
<> 144:ef7eb2e8f9f7 1745 * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1746 * the configuration information for the specified IRDA.
<> 144:ef7eb2e8f9f7 1747 * @retval IRDA Error Code
<> 144:ef7eb2e8f9f7 1748 */
<> 144:ef7eb2e8f9f7 1749 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1750 {
<> 144:ef7eb2e8f9f7 1751 return hirda->ErrorCode;
<> 144:ef7eb2e8f9f7 1752 }
<> 144:ef7eb2e8f9f7 1753
<> 144:ef7eb2e8f9f7 1754 /**
<> 144:ef7eb2e8f9f7 1755 * @}
<> 144:ef7eb2e8f9f7 1756 */
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 /**
<> 144:ef7eb2e8f9f7 1759 * @brief DMA IRDA transmit process complete callback.
<> 144:ef7eb2e8f9f7 1760 * @param hdma : DMA handle
<> 144:ef7eb2e8f9f7 1761 * @retval None
<> 144:ef7eb2e8f9f7 1762 */
<> 144:ef7eb2e8f9f7 1763 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1764 {
<> 144:ef7eb2e8f9f7 1765 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1766 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1767 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1768 {
AnnaBridge 167:e84263d55307 1769 hirda->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 /* Disable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1772 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1773 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1774
<> 144:ef7eb2e8f9f7 1775 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1776 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1777 }
<> 144:ef7eb2e8f9f7 1778 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 1779 else
<> 144:ef7eb2e8f9f7 1780 {
<> 144:ef7eb2e8f9f7 1781 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1782 }
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 /**
<> 144:ef7eb2e8f9f7 1786 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1787 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1788 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1789 * @retval None
<> 144:ef7eb2e8f9f7 1790 */
<> 144:ef7eb2e8f9f7 1791 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1792 {
<> 144:ef7eb2e8f9f7 1793 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1794
<> 144:ef7eb2e8f9f7 1795 HAL_IRDA_TxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1796 }
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 /**
<> 144:ef7eb2e8f9f7 1799 * @brief DMA IRDA receive process complete callback.
<> 144:ef7eb2e8f9f7 1800 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1801 * @retval None
<> 144:ef7eb2e8f9f7 1802 */
<> 144:ef7eb2e8f9f7 1803 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1804 {
<> 144:ef7eb2e8f9f7 1805 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1806 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1807 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1808 {
AnnaBridge 167:e84263d55307 1809 hirda->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 1812 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 1813 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /* Disable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1816 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1817 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1818
<> 144:ef7eb2e8f9f7 1819 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1820 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1821 }
<> 144:ef7eb2e8f9f7 1822
<> 144:ef7eb2e8f9f7 1823 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1824 }
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 /**
<> 144:ef7eb2e8f9f7 1827 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1828 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1829 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1830 * @retval None
<> 144:ef7eb2e8f9f7 1831 */
<> 144:ef7eb2e8f9f7 1832 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1833 {
<> 144:ef7eb2e8f9f7 1834 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1835 HAL_IRDA_RxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1836 }
<> 144:ef7eb2e8f9f7 1837
<> 144:ef7eb2e8f9f7 1838 /**
<> 144:ef7eb2e8f9f7 1839 * @brief DMA IRDA communication error callback.
<> 144:ef7eb2e8f9f7 1840 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1841 * @retval None
<> 144:ef7eb2e8f9f7 1842 */
<> 144:ef7eb2e8f9f7 1843 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1844 {
<> 144:ef7eb2e8f9f7 1845 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 1846 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /* Stop IRDA DMA Tx request if ongoing */
<> 144:ef7eb2e8f9f7 1849 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1850 if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
<> 144:ef7eb2e8f9f7 1851 {
AnnaBridge 167:e84263d55307 1852 hirda->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1853 IRDA_EndTxTransfer(hirda);
<> 144:ef7eb2e8f9f7 1854 }
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856 /* Stop IRDA DMA Rx request if ongoing */
<> 144:ef7eb2e8f9f7 1857 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1858 if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
<> 144:ef7eb2e8f9f7 1859 {
AnnaBridge 167:e84263d55307 1860 hirda->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1861 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 1862 }
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1867 }
<> 144:ef7eb2e8f9f7 1868
<> 144:ef7eb2e8f9f7 1869 /**
<> 144:ef7eb2e8f9f7 1870 * @brief This function handles IRDA Communication Timeout.
<> 144:ef7eb2e8f9f7 1871 * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1872 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1873 * @param Flag specifies the IRDA flag to check.
<> 144:ef7eb2e8f9f7 1874 * @param Status The new Flag status (SET or RESET).
<> 144:ef7eb2e8f9f7 1875 * @param Tickstart Tick start value
<> 144:ef7eb2e8f9f7 1876 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 1877 * @retval HAL status
<> 144:ef7eb2e8f9f7 1878 */
<> 144:ef7eb2e8f9f7 1879 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1880 {
<> 144:ef7eb2e8f9f7 1881 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1882 while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
<> 144:ef7eb2e8f9f7 1883 {
<> 144:ef7eb2e8f9f7 1884 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1885 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1886 {
<> 144:ef7eb2e8f9f7 1887 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1888 {
<> 144:ef7eb2e8f9f7 1889 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 1890 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
<> 144:ef7eb2e8f9f7 1891 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1892
<> 144:ef7eb2e8f9f7 1893 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1894 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1897 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1898
<> 144:ef7eb2e8f9f7 1899 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1900 }
<> 144:ef7eb2e8f9f7 1901 }
<> 144:ef7eb2e8f9f7 1902 }
<> 144:ef7eb2e8f9f7 1903 return HAL_OK;
<> 144:ef7eb2e8f9f7 1904 }
<> 144:ef7eb2e8f9f7 1905
<> 144:ef7eb2e8f9f7 1906 /**
<> 144:ef7eb2e8f9f7 1907 * @brief Send an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1908 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1909 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1910 * @retval HAL status
<> 144:ef7eb2e8f9f7 1911 */
<> 144:ef7eb2e8f9f7 1912 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1913 {
<> 144:ef7eb2e8f9f7 1914 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1915
<> 144:ef7eb2e8f9f7 1916 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 1917 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1918 {
<> 144:ef7eb2e8f9f7 1919 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 1920 {
<> 144:ef7eb2e8f9f7 1921 tmp = (uint16_t*) hirda->pTxBuffPtr;
AnnaBridge 167:e84263d55307 1922 hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
<> 144:ef7eb2e8f9f7 1923 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 1924 {
AnnaBridge 167:e84263d55307 1925 hirda->pTxBuffPtr += 2;
<> 144:ef7eb2e8f9f7 1926 }
<> 144:ef7eb2e8f9f7 1927 else
<> 144:ef7eb2e8f9f7 1928 {
AnnaBridge 167:e84263d55307 1929 hirda->pTxBuffPtr += 1;
<> 144:ef7eb2e8f9f7 1930 }
<> 144:ef7eb2e8f9f7 1931 }
<> 144:ef7eb2e8f9f7 1932 else
<> 144:ef7eb2e8f9f7 1933 {
AnnaBridge 167:e84263d55307 1934 hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
<> 144:ef7eb2e8f9f7 1935 }
<> 144:ef7eb2e8f9f7 1936
AnnaBridge 167:e84263d55307 1937 if(--hirda->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1938 {
<> 144:ef7eb2e8f9f7 1939 /* Disable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 1940 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1943 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1944 }
<> 144:ef7eb2e8f9f7 1945
<> 144:ef7eb2e8f9f7 1946 return HAL_OK;
<> 144:ef7eb2e8f9f7 1947 }
<> 144:ef7eb2e8f9f7 1948 else
<> 144:ef7eb2e8f9f7 1949 {
<> 144:ef7eb2e8f9f7 1950 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1951 }
<> 144:ef7eb2e8f9f7 1952 }
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 /**
<> 144:ef7eb2e8f9f7 1955 * @brief Wraps up transmission in non blocking mode.
<> 144:ef7eb2e8f9f7 1956 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1957 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1958 * @retval HAL status
<> 144:ef7eb2e8f9f7 1959 */
<> 144:ef7eb2e8f9f7 1960 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1961 {
<> 144:ef7eb2e8f9f7 1962 /* Disable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1963 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1964
<> 144:ef7eb2e8f9f7 1965 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 1966 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 /* Tx process is ended, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 1969 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1970
<> 144:ef7eb2e8f9f7 1971 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1972
<> 144:ef7eb2e8f9f7 1973 return HAL_OK;
<> 144:ef7eb2e8f9f7 1974 }
<> 144:ef7eb2e8f9f7 1975
<> 144:ef7eb2e8f9f7 1976 /**
<> 144:ef7eb2e8f9f7 1977 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1978 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1979 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1980 * @retval HAL status
<> 144:ef7eb2e8f9f7 1981 */
<> 144:ef7eb2e8f9f7 1982 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1983 {
<> 144:ef7eb2e8f9f7 1984 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1985 uint16_t uhdata;
<> 144:ef7eb2e8f9f7 1986
<> 144:ef7eb2e8f9f7 1987 /* Check that a Rx process is ongoing */
<> 144:ef7eb2e8f9f7 1988 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1989 {
<> 144:ef7eb2e8f9f7 1990 uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
<> 144:ef7eb2e8f9f7 1991 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 1992 {
<> 144:ef7eb2e8f9f7 1993 tmp = (uint16_t*) hirda->pRxBuffPtr;
<> 144:ef7eb2e8f9f7 1994 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 1995 {
AnnaBridge 167:e84263d55307 1996 *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
AnnaBridge 167:e84263d55307 1997 hirda->pRxBuffPtr += 2;
<> 144:ef7eb2e8f9f7 1998 }
<> 144:ef7eb2e8f9f7 1999 else
<> 144:ef7eb2e8f9f7 2000 {
AnnaBridge 167:e84263d55307 2001 *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
AnnaBridge 167:e84263d55307 2002 hirda->pRxBuffPtr += 1;
<> 144:ef7eb2e8f9f7 2003 }
<> 144:ef7eb2e8f9f7 2004 }
<> 144:ef7eb2e8f9f7 2005 else
<> 144:ef7eb2e8f9f7 2006 {
<> 144:ef7eb2e8f9f7 2007 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 2008 {
AnnaBridge 167:e84263d55307 2009 *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
<> 144:ef7eb2e8f9f7 2010 }
<> 144:ef7eb2e8f9f7 2011 else
<> 144:ef7eb2e8f9f7 2012 {
AnnaBridge 167:e84263d55307 2013 *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
<> 144:ef7eb2e8f9f7 2014 }
<> 144:ef7eb2e8f9f7 2015 }
<> 144:ef7eb2e8f9f7 2016
AnnaBridge 167:e84263d55307 2017 if(--hirda->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 2018 {
<> 144:ef7eb2e8f9f7 2019 /* Disable the IRDA Data Register not empty Interrupt */
<> 144:ef7eb2e8f9f7 2020 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 2021
<> 144:ef7eb2e8f9f7 2022 /* Disable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 2023 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 2024
<> 144:ef7eb2e8f9f7 2025 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 2026 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2027
<> 144:ef7eb2e8f9f7 2028 /* Rx process is completed, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 2029 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 2030
<> 144:ef7eb2e8f9f7 2031 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 return HAL_OK;
<> 144:ef7eb2e8f9f7 2034 }
<> 144:ef7eb2e8f9f7 2035 return HAL_OK;
<> 144:ef7eb2e8f9f7 2036 }
<> 144:ef7eb2e8f9f7 2037 else
<> 144:ef7eb2e8f9f7 2038 {
<> 144:ef7eb2e8f9f7 2039 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2040 }
<> 144:ef7eb2e8f9f7 2041 }
<> 144:ef7eb2e8f9f7 2042
<> 144:ef7eb2e8f9f7 2043 /**
<> 144:ef7eb2e8f9f7 2044 * @brief Configures the IRDA peripheral.
<> 144:ef7eb2e8f9f7 2045 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2046 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 2047 * @retval None
<> 144:ef7eb2e8f9f7 2048 */
<> 144:ef7eb2e8f9f7 2049 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 2050 {
<> 144:ef7eb2e8f9f7 2051 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2052 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 2053 assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2054 assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
<> 144:ef7eb2e8f9f7 2055 assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
<> 144:ef7eb2e8f9f7 2056 assert_param(IS_IRDA_MODE(hirda->Init.Mode));
<> 144:ef7eb2e8f9f7 2057
<> 144:ef7eb2e8f9f7 2058 /*-------------------------- IRDA CR2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 2059 /* Clear STOP[13:12] bits */
<> 144:ef7eb2e8f9f7 2060 CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
<> 144:ef7eb2e8f9f7 2061
<> 144:ef7eb2e8f9f7 2062 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2063 /* Clear M, PCE, PS, TE and RE bits */
<> 144:ef7eb2e8f9f7 2064 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
<> 144:ef7eb2e8f9f7 2065
<> 144:ef7eb2e8f9f7 2066 /* Configure the USART Word Length, Parity and mode:
<> 144:ef7eb2e8f9f7 2067 Set the M bits according to hirda->Init.WordLength value
<> 144:ef7eb2e8f9f7 2068 Set PCE and PS bits according to hirda->Init.Parity value
<> 144:ef7eb2e8f9f7 2069 Set TE and RE bits according to hirda->Init.Mode value */
<> 144:ef7eb2e8f9f7 2070 /* Write to USART CR1 */
<> 144:ef7eb2e8f9f7 2071 SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
<> 144:ef7eb2e8f9f7 2072
<> 144:ef7eb2e8f9f7 2073 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2074 /* Clear CTSE and RTSE bits */
<> 144:ef7eb2e8f9f7 2075 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2078 if((hirda->Instance == USART1) || (hirda->Instance == USART6))
<> 144:ef7eb2e8f9f7 2079 {
<> 144:ef7eb2e8f9f7 2080 SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2081 }
<> 144:ef7eb2e8f9f7 2082 else
<> 144:ef7eb2e8f9f7 2083 {
<> 144:ef7eb2e8f9f7 2084 SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2085 }
<> 144:ef7eb2e8f9f7 2086 }
<> 144:ef7eb2e8f9f7 2087
<> 144:ef7eb2e8f9f7 2088 /**
<> 144:ef7eb2e8f9f7 2089 * @}
<> 144:ef7eb2e8f9f7 2090 */
<> 144:ef7eb2e8f9f7 2091
<> 144:ef7eb2e8f9f7 2092 #endif /* HAL_IRDA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2093 /**
<> 144:ef7eb2e8f9f7 2094 * @}
<> 144:ef7eb2e8f9f7 2095 */
<> 144:ef7eb2e8f9f7 2096
<> 144:ef7eb2e8f9f7 2097 /**
<> 144:ef7eb2e8f9f7 2098 * @}
<> 144:ef7eb2e8f9f7 2099 */
<> 144:ef7eb2e8f9f7 2100
<> 144:ef7eb2e8f9f7 2101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/