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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2s.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_i2s.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of I2S HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup I2S
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup I2S_Exported_Types I2S Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief I2S Init structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref I2S_Mode */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref I2S_Standard */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref I2S_Data_Format */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref I2S_MCLK_Output */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref I2S_Audio_Frequency */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref I2S_Clock_Polarity */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref I2S_Clock_Source */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 }I2S_InitTypeDef;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 typedef enum
<> 144:ef7eb2e8f9f7 94 {
<> 144:ef7eb2e8f9f7 95 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 96 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
<> 144:ef7eb2e8f9f7 97 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
<> 144:ef7eb2e8f9f7 98 HAL_I2S_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 99 HAL_I2S_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 100 HAL_I2S_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
<> 144:ef7eb2e8f9f7 101 HAL_I2S_STATE_TIMEOUT = 0x03U, /*!< I2S timeout state */
<> 144:ef7eb2e8f9f7 102 HAL_I2S_STATE_ERROR = 0x04U /*!< I2S error state */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 }HAL_I2S_StateTypeDef;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief I2S handle Structure definition
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 typedef struct
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 SPI_TypeDef *Instance; /* I2S registers base address */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 I2S_InitTypeDef Init; /* I2S communication parameters */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 __IO uint16_t RxXferCount; /* I2S Rx transfer counter */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 __IO HAL_LockTypeDef Lock; /* I2S locking object */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 __IO uint32_t ErrorCode; /* I2S Error code */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 }I2S_HandleTypeDef;
<> 144:ef7eb2e8f9f7 138 /**
<> 144:ef7eb2e8f9f7 139 * @}
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /** @defgroup I2S_Exported_Constants I2S Exported Constants
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @defgroup I2S_Error_Code I2S Error Code
<> 144:ef7eb2e8f9f7 148 * @brief I2S Error Code
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
AnnaBridge 167:e84263d55307 151 #define HAL_I2S_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 167:e84263d55307 152 #define HAL_I2S_ERROR_UDR 0x00000001U /*!< I2S Underrun error */
AnnaBridge 167:e84263d55307 153 #define HAL_I2S_ERROR_OVR 0x00000002U /*!< I2S Overrun error */
AnnaBridge 167:e84263d55307 154 #define HAL_I2SEX_ERROR_UDR 0x00000004U /*!< I2S extended Underrun error */
AnnaBridge 167:e84263d55307 155 #define HAL_I2SEX_ERROR_OVR 0x00000008U /*!< I2S extended Overrun error */
AnnaBridge 167:e84263d55307 156 #define HAL_I2S_ERROR_FRE 0x00000010U /*!< I2S Frame format error */
AnnaBridge 167:e84263d55307 157 #define HAL_I2S_ERROR_DMA 0x00000020U /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @defgroup I2S_Clock_Source I2S Clock Source
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
AnnaBridge 167:e84263d55307 165 #define I2S_CLOCK_PLL 0x00000000U
AnnaBridge 167:e84263d55307 166 #define I2S_CLOCK_EXTERNAL 0x00000001U
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup I2S_Mode I2S Mode
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
AnnaBridge 167:e84263d55307 174 #define I2S_MODE_SLAVE_TX 0x00000000U
AnnaBridge 167:e84263d55307 175 #define I2S_MODE_SLAVE_RX 0x00000100U
AnnaBridge 167:e84263d55307 176 #define I2S_MODE_MASTER_TX 0x00000200U
AnnaBridge 167:e84263d55307 177 #define I2S_MODE_MASTER_RX 0x00000300U
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @}
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** @defgroup I2S_Standard I2S Standard
<> 144:ef7eb2e8f9f7 183 * @{
<> 144:ef7eb2e8f9f7 184 */
AnnaBridge 167:e84263d55307 185 #define I2S_STANDARD_PHILIPS 0x00000000U
AnnaBridge 167:e84263d55307 186 #define I2S_STANDARD_MSB 0x00000010U
AnnaBridge 167:e84263d55307 187 #define I2S_STANDARD_LSB 0x00000020U
AnnaBridge 167:e84263d55307 188 #define I2S_STANDARD_PCM_SHORT 0x00000030U
AnnaBridge 167:e84263d55307 189 #define I2S_STANDARD_PCM_LONG 0x000000B0U
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @defgroup I2S_Data_Format I2S Data Format
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
AnnaBridge 167:e84263d55307 197 #define I2S_DATAFORMAT_16B 0x00000000U
AnnaBridge 167:e84263d55307 198 #define I2S_DATAFORMAT_16B_EXTENDED 0x00000001U
AnnaBridge 167:e84263d55307 199 #define I2S_DATAFORMAT_24B 0x00000003U
AnnaBridge 167:e84263d55307 200 #define I2S_DATAFORMAT_32B 0x00000005U
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @}
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup I2S_MCLK_Output I2S Mclk Output
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
AnnaBridge 167:e84263d55307 209 #define I2S_MCLKOUTPUT_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @}
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
<> 144:ef7eb2e8f9f7 215 * @{
<> 144:ef7eb2e8f9f7 216 */
AnnaBridge 167:e84263d55307 217 #define I2S_AUDIOFREQ_192K 192000U
AnnaBridge 167:e84263d55307 218 #define I2S_AUDIOFREQ_96K 96000U
AnnaBridge 167:e84263d55307 219 #define I2S_AUDIOFREQ_48K 48000U
AnnaBridge 167:e84263d55307 220 #define I2S_AUDIOFREQ_44K 44100U
AnnaBridge 167:e84263d55307 221 #define I2S_AUDIOFREQ_32K 32000U
AnnaBridge 167:e84263d55307 222 #define I2S_AUDIOFREQ_22K 22050U
AnnaBridge 167:e84263d55307 223 #define I2S_AUDIOFREQ_16K 16000U
AnnaBridge 167:e84263d55307 224 #define I2S_AUDIOFREQ_11K 11025U
AnnaBridge 167:e84263d55307 225 #define I2S_AUDIOFREQ_8K 8000U
AnnaBridge 167:e84263d55307 226 #define I2S_AUDIOFREQ_DEFAULT 2U
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
AnnaBridge 167:e84263d55307 234 #define I2S_CPOL_LOW 0x00000000U
<> 144:ef7eb2e8f9f7 235 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 #define I2S_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 244 #define I2S_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 245 #define I2S_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @}
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /** @defgroup I2S_Flags_Definition I2S Flags Definition
<> 144:ef7eb2e8f9f7 251 * @{
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253 #define I2S_FLAG_TXE SPI_SR_TXE
<> 144:ef7eb2e8f9f7 254 #define I2S_FLAG_RXNE SPI_SR_RXNE
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 #define I2S_FLAG_UDR SPI_SR_UDR
<> 144:ef7eb2e8f9f7 257 #define I2S_FLAG_OVR SPI_SR_OVR
<> 144:ef7eb2e8f9f7 258 #define I2S_FLAG_FRE SPI_SR_FRE
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
<> 144:ef7eb2e8f9f7 261 #define I2S_FLAG_BSY SPI_SR_BSY
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @}
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 271 /** @defgroup I2S_Exported_Macros I2S Exported Macros
<> 144:ef7eb2e8f9f7 272 * @{
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /** @brief Reset I2S handle state
<> 144:ef7eb2e8f9f7 276 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 277 * @retval None
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
<> 144:ef7eb2e8f9f7 282 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 283 * @retval None
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 286 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** @brief Enable or disable the specified I2S interrupts.
<> 144:ef7eb2e8f9f7 289 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 290 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 144:ef7eb2e8f9f7 291 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 292 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 293 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 294 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 295 * @retval None
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 298 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 301 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 302 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
<> 144:ef7eb2e8f9f7 303 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
<> 144:ef7eb2e8f9f7 304 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 305 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 306 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 307 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 308 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /** @brief Checks whether the specified I2S flag is set or not.
<> 144:ef7eb2e8f9f7 313 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 314 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 315 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 316 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 317 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 318 * @arg I2S_FLAG_UDR: Underrun flag
<> 144:ef7eb2e8f9f7 319 * @arg I2S_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 320 * @arg I2S_FLAG_FRE: Frame error flag
<> 144:ef7eb2e8f9f7 321 * @arg I2S_FLAG_CHSIDE: Channel Side flag
<> 144:ef7eb2e8f9f7 322 * @arg I2S_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 323 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /** @brief Clears the I2S OVR pending flag.
<> 144:ef7eb2e8f9f7 328 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 329 * @retval None
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 332 do{ \
<> 144:ef7eb2e8f9f7 333 __IO uint32_t tmpreg_ovr = 0x00U; \
<> 144:ef7eb2e8f9f7 334 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
<> 144:ef7eb2e8f9f7 335 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 336 UNUSED(tmpreg_ovr ); \
<> 144:ef7eb2e8f9f7 337 } while(0)
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /** @brief Clears the I2S UDR pending flag.
<> 144:ef7eb2e8f9f7 340 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 341 * @retval None
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 344 do{ \
<> 144:ef7eb2e8f9f7 345 __IO uint32_t tmpreg_udr = 0x00U; \
<> 144:ef7eb2e8f9f7 346 tmpreg_udr = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 347 UNUSED(tmpreg_udr); \
<> 144:ef7eb2e8f9f7 348 } while(0)
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 354 /** @addtogroup I2S_Exported_Functions
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /** @addtogroup I2S_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 359 * @{
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 362 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 363 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 364 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 365 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @}
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /** @addtogroup I2S_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 371 * @{
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 374 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 375 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 376 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 379 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 380 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 381 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 384 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 385 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 389 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Peripheral Control and State functions **************************************/
<> 144:ef7eb2e8f9f7 392 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 393 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
<> 144:ef7eb2e8f9f7 396 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 397 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 398 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 399 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 400 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 401 /**
<> 144:ef7eb2e8f9f7 402 * @}
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @}
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 410 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 411 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 412 /** @defgroup I2S_Private_Constants I2S Private Constants
<> 144:ef7eb2e8f9f7 413 * @{
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 421 /** @defgroup I2S_Private_Macros I2S Private Macros
<> 144:ef7eb2e8f9f7 422 * @{
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
<> 144:ef7eb2e8f9f7 425 ((CLOCK) == I2S_CLOCK_PLL))
AnnaBridge 167:e84263d55307 426
<> 144:ef7eb2e8f9f7 427 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
<> 144:ef7eb2e8f9f7 428 ((MODE) == I2S_MODE_SLAVE_RX) || \
<> 144:ef7eb2e8f9f7 429 ((MODE) == I2S_MODE_MASTER_TX) || \
<> 144:ef7eb2e8f9f7 430 ((MODE) == I2S_MODE_MASTER_RX))
AnnaBridge 167:e84263d55307 431
<> 144:ef7eb2e8f9f7 432 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
<> 144:ef7eb2e8f9f7 433 ((STANDARD) == I2S_STANDARD_MSB) || \
<> 144:ef7eb2e8f9f7 434 ((STANDARD) == I2S_STANDARD_LSB) || \
<> 144:ef7eb2e8f9f7 435 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
<> 144:ef7eb2e8f9f7 436 ((STANDARD) == I2S_STANDARD_PCM_LONG))
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
<> 144:ef7eb2e8f9f7 439 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
<> 144:ef7eb2e8f9f7 440 ((FORMAT) == I2S_DATAFORMAT_24B) || \
<> 144:ef7eb2e8f9f7 441 ((FORMAT) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
<> 144:ef7eb2e8f9f7 444 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
AnnaBridge 167:e84263d55307 445
<> 144:ef7eb2e8f9f7 446 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
<> 144:ef7eb2e8f9f7 447 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
<> 144:ef7eb2e8f9f7 448 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
<> 144:ef7eb2e8f9f7 451 ((CPOL) == I2S_CPOL_HIGH))
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 458 /** @defgroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 459 * @{
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 /**
<> 144:ef7eb2e8f9f7 462 * @}
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /**
<> 144:ef7eb2e8f9f7 470 * @}
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 #endif
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 #endif /* __STM32F2xx_HAL_I2S_H */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/