mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_hash.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_hash.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief HASH HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the HASH peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + HASH/HMAC Processing functions by algorithm using polling mode
<> 144:ef7eb2e8f9f7 12 * + HASH/HMAC functions by algorithm using interrupt mode
<> 144:ef7eb2e8f9f7 13 * + HASH/HMAC functions by algorithm using DMA mode
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 The HASH HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 22 (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
<> 144:ef7eb2e8f9f7 23 (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 24 (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
<> 144:ef7eb2e8f9f7 25 (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 26 (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 27 (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
<> 144:ef7eb2e8f9f7 28 (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
<> 144:ef7eb2e8f9f7 29 (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 30 (+++) Configure and enable one DMA stream one for managing data transfer from
<> 144:ef7eb2e8f9f7 31 memory to peripheral (input stream). Managing data transfer from
<> 144:ef7eb2e8f9f7 32 peripheral to memory can be performed only using CPU
<> 144:ef7eb2e8f9f7 33 (+++) Associate the initialized DMA handle to the HASH DMA handle
<> 144:ef7eb2e8f9f7 34 using __HAL_LINKDMA()
<> 144:ef7eb2e8f9f7 35 (+++) Configure the priority and enable the NVIC for the transfer complete
<> 144:ef7eb2e8f9f7 36 interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 37 (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
<> 144:ef7eb2e8f9f7 38 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
<> 144:ef7eb2e8f9f7 39 (##) For HMAC, the encryption key.
<> 144:ef7eb2e8f9f7 40 (##) For HMAC, the key size used for encryption.
<> 144:ef7eb2e8f9f7 41 (#)Three processing functions are available:
<> 144:ef7eb2e8f9f7 42 (##) Polling mode: processing APIs are blocking functions
<> 144:ef7eb2e8f9f7 43 i.e. they process the data and wait till the digest computation is finished
<> 144:ef7eb2e8f9f7 44 e.g. HAL_HASH_SHA1_Start()
<> 144:ef7eb2e8f9f7 45 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
<> 144:ef7eb2e8f9f7 46 i.e. they process the data under interrupt
<> 144:ef7eb2e8f9f7 47 e.g. HAL_HASH_SHA1_Start_IT()
<> 144:ef7eb2e8f9f7 48 (##) DMA mode: processing APIs are not blocking functions and the CPU is
<> 144:ef7eb2e8f9f7 49 not used for data transfer i.e. the data transfer is ensured by DMA
<> 144:ef7eb2e8f9f7 50 e.g. HAL_HASH_SHA1_Start_DMA()
<> 144:ef7eb2e8f9f7 51 (#)When the processing function is called at first time after HAL_HASH_Init()
<> 144:ef7eb2e8f9f7 52 the HASH peripheral is initialized and processes the buffer in input.
<> 144:ef7eb2e8f9f7 53 After that, the digest computation is started.
<> 144:ef7eb2e8f9f7 54 When processing multi-buffer use the accumulate function to write the
<> 144:ef7eb2e8f9f7 55 data in the peripheral without starting the digest computation. In last
<> 144:ef7eb2e8f9f7 56 buffer use the start function to input the last buffer ans start the digest
<> 144:ef7eb2e8f9f7 57 computation.
<> 144:ef7eb2e8f9f7 58 (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
<> 144:ef7eb2e8f9f7 59 (##) write (n-1)th data buffer in the peripheral without starting the digest computation
<> 144:ef7eb2e8f9f7 60 (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
<> 144:ef7eb2e8f9f7 61 (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
<> 144:ef7eb2e8f9f7 62 (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
<> 144:ef7eb2e8f9f7 63 After that, call the finish function in order to get the digest value
<> 144:ef7eb2e8f9f7 64 e.g. HAL_HASH_SHA1_Finish()
<> 144:ef7eb2e8f9f7 65 (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69 * @attention
<> 144:ef7eb2e8f9f7 70 *
AnnaBridge 167:e84263d55307 71 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 74 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 75 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 76 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 79 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 81 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 82 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup HASH HASH
<> 144:ef7eb2e8f9f7 106 * @brief HASH HAL module driver.
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef HAL_HASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #if defined(STM32F215xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup HASH_Private_Functions HASH Private Functions
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 123 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 124 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
<> 144:ef7eb2e8f9f7 125 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /** @addtogroup HASH_Private_Functions
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @brief DMA HASH Input Data complete callback.
<> 144:ef7eb2e8f9f7 137 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 138 * @retval None
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 141 {
<> 144:ef7eb2e8f9f7 142 HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 143 uint32_t inputaddr = 0U;
<> 144:ef7eb2e8f9f7 144 uint32_t buffersize = 0U;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 /* Disable the DMA transfer */
<> 144:ef7eb2e8f9f7 149 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 152 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 155 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 156 }
<> 144:ef7eb2e8f9f7 157 else
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 /* Increment Interrupt counter */
<> 144:ef7eb2e8f9f7 160 hhash->HashInCount++;
<> 144:ef7eb2e8f9f7 161 /* Disable the DMA transfer before starting the next transfer */
<> 144:ef7eb2e8f9f7 162 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 if(hhash->HashInCount <= 2U)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
<> 144:ef7eb2e8f9f7 167 if(hhash->HashInCount == 1U)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 170 buffersize = hhash->HashBuffSize;
<> 144:ef7eb2e8f9f7 171 }
<> 144:ef7eb2e8f9f7 172 /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
<> 144:ef7eb2e8f9f7 173 else if(hhash->HashInCount == 2U)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 inputaddr = (uint32_t)hhash->Init.pKey;
<> 144:ef7eb2e8f9f7 176 buffersize = hhash->Init.KeySize;
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 179 MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Set the HASH DMA transfer complete */
<> 144:ef7eb2e8f9f7 182 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 185 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 188 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 else
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* Disable the DMA transfer */
<> 144:ef7eb2e8f9f7 193 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Reset the InCount */
<> 144:ef7eb2e8f9f7 196 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 199 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 202 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief DMA HASH communication error callback.
<> 144:ef7eb2e8f9f7 209 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 210 * @retval None
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 215 hhash->State= HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 216 HAL_HASH_ErrorCallback(hhash);
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @brief Writes the input buffer in data register.
<> 144:ef7eb2e8f9f7 221 * @param pInBuffer: Pointer to input buffer
<> 144:ef7eb2e8f9f7 222 * @param Size: The size of input buffer
<> 144:ef7eb2e8f9f7 223 * @retval None
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
<> 144:ef7eb2e8f9f7 230 {
AnnaBridge 187:0387e8f68319 231 uint32_t data = (uint32_t) *pInBuffer++;
AnnaBridge 187:0387e8f68319 232 data |= (uint32_t) *pInBuffer++ << 8;
AnnaBridge 187:0387e8f68319 233 data |= (uint32_t) *pInBuffer++ << 16;
AnnaBridge 187:0387e8f68319 234 data |= (uint32_t) *pInBuffer++ << 24;
AnnaBridge 187:0387e8f68319 235 HASH->DIN = data;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /**
<> 144:ef7eb2e8f9f7 240 * @brief Provides the message digest result.
<> 144:ef7eb2e8f9f7 241 * @param pMsgDigest: Pointer to the message digest
<> 144:ef7eb2e8f9f7 242 * @param Size: The size of the message digest in bytes
<> 144:ef7eb2e8f9f7 243 * @retval None
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 uint32_t msgdigest = (uint32_t)pMsgDigest;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 switch(Size)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 case 16U:
<> 144:ef7eb2e8f9f7 252 /* Read the message digest */
<> 144:ef7eb2e8f9f7 253 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 254 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 255 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 256 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 257 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 258 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 259 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 260 break;
<> 144:ef7eb2e8f9f7 261 case 20U:
<> 144:ef7eb2e8f9f7 262 /* Read the message digest */
<> 144:ef7eb2e8f9f7 263 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 264 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 265 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 266 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 267 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 268 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 269 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 270 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 271 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 272 break;
<> 144:ef7eb2e8f9f7 273 case 28U:
<> 144:ef7eb2e8f9f7 274 /* Read the message digest */
<> 144:ef7eb2e8f9f7 275 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 276 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 277 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 278 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 279 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 280 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 281 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 282 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 283 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 284 break;
<> 144:ef7eb2e8f9f7 285 case 32U:
<> 144:ef7eb2e8f9f7 286 /* Read the message digest */
<> 144:ef7eb2e8f9f7 287 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 288 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 289 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 290 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 291 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 292 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 293 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 294 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 295 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 296 break;
<> 144:ef7eb2e8f9f7 297 default:
<> 144:ef7eb2e8f9f7 298 break;
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 307 /** @addtogroup HASH_Exported_Functions
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 313 * @brief Initialization and Configuration functions.
<> 144:ef7eb2e8f9f7 314 *
<> 144:ef7eb2e8f9f7 315 @verbatim
<> 144:ef7eb2e8f9f7 316 ===============================================================================
<> 144:ef7eb2e8f9f7 317 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 318 ===============================================================================
<> 144:ef7eb2e8f9f7 319 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 320 (+) Initialize the HASH according to the specified parameters
<> 144:ef7eb2e8f9f7 321 in the HASH_InitTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 322 (+) DeInitialize the HASH peripheral.
<> 144:ef7eb2e8f9f7 323 (+) Initialize the HASH MSP.
<> 144:ef7eb2e8f9f7 324 (+) DeInitialize HASH MSP.
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 @endverbatim
<> 144:ef7eb2e8f9f7 327 * @{
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @brief Initializes the HASH according to the specified parameters in the
<> 144:ef7eb2e8f9f7 332 HASH_HandleTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 333 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 334 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 335 * @retval HAL status
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 /* Check the hash handle allocation */
<> 144:ef7eb2e8f9f7 340 if(hhash == NULL)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 346 assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 if(hhash->State == HAL_HASH_STATE_RESET)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 351 hhash->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 352 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 353 HAL_HASH_MspInit(hhash);
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 357 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Reset HashInCount, HashBuffSize and HashITCounter */
<> 144:ef7eb2e8f9f7 360 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 361 hhash->HashBuffSize = 0U;
<> 144:ef7eb2e8f9f7 362 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Set the data type */
<> 144:ef7eb2e8f9f7 365 HASH->CR |= (uint32_t) (hhash->Init.DataType);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 368 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Set the default HASH phase */
<> 144:ef7eb2e8f9f7 371 hhash->Phase = HAL_HASH_PHASE_READY;
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Return function status */
<> 144:ef7eb2e8f9f7 374 return HAL_OK;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @brief DeInitializes the HASH peripheral.
<> 144:ef7eb2e8f9f7 379 * @note This API must be called before starting a new processing.
<> 144:ef7eb2e8f9f7 380 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 381 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 382 * @retval HAL status
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 /* Check the HASH handle allocation */
<> 144:ef7eb2e8f9f7 387 if(hhash == NULL)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 393 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Set the default HASH phase */
<> 144:ef7eb2e8f9f7 396 hhash->Phase = HAL_HASH_PHASE_READY;
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Reset HashInCount, HashBuffSize and HashITCounter */
<> 144:ef7eb2e8f9f7 399 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 400 hhash->HashBuffSize = 0U;
<> 144:ef7eb2e8f9f7 401 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 404 HAL_HASH_MspDeInit(hhash);
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 407 hhash->State = HAL_HASH_STATE_RESET;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Release Lock */
<> 144:ef7eb2e8f9f7 410 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Return function status */
<> 144:ef7eb2e8f9f7 413 return HAL_OK;
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @brief Initializes the HASH MSP.
<> 144:ef7eb2e8f9f7 418 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 419 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 420 * @retval None
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 423 {
<> 144:ef7eb2e8f9f7 424 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 425 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 426 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 427 the HAL_HASH_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @brief DeInitializes HASH MSP.
<> 144:ef7eb2e8f9f7 433 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 434 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 435 * @retval None
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 438 {
<> 144:ef7eb2e8f9f7 439 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 440 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 441 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 442 the HAL_HASH_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @brief Input data transfer complete callback.
<> 144:ef7eb2e8f9f7 448 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 449 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 450 * @retval None
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 455 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 456 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 457 the HAL_HASH_InCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /**
<> 144:ef7eb2e8f9f7 462 * @brief Data transfer Error callback.
<> 144:ef7eb2e8f9f7 463 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 464 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 465 * @retval None
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467 __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 470 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 471 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 472 the HAL_HASH_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @brief Digest computation complete callback. It is used only with interrupt.
<> 144:ef7eb2e8f9f7 478 * @note This callback is not relevant with DMA.
<> 144:ef7eb2e8f9f7 479 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 480 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 481 * @retval None
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 486 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 487 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 488 the HAL_HASH_DgstCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
<> 144:ef7eb2e8f9f7 497 * @brief processing functions using polling mode
<> 144:ef7eb2e8f9f7 498 *
<> 144:ef7eb2e8f9f7 499 @verbatim
<> 144:ef7eb2e8f9f7 500 ===============================================================================
<> 144:ef7eb2e8f9f7 501 ##### HASH processing using polling mode functions#####
<> 144:ef7eb2e8f9f7 502 ===============================================================================
<> 144:ef7eb2e8f9f7 503 [..] This section provides functions allowing to calculate in polling mode
<> 144:ef7eb2e8f9f7 504 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 505 (+) MD5
<> 144:ef7eb2e8f9f7 506 (+) SHA1
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 @endverbatim
<> 144:ef7eb2e8f9f7 509 * @{
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 514 The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 515 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 516 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 517 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 518 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 519 * If the Size is multiple of 64 bytes, appending the input buffer is possible.
<> 144:ef7eb2e8f9f7 520 * If the Size is not multiple of 64 bytes, the padding is managed by hardware
<> 144:ef7eb2e8f9f7 521 * and appending the input buffer is no more possible.
<> 144:ef7eb2e8f9f7 522 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 523 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 524 * @retval HAL status
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Process Locked */
<> 144:ef7eb2e8f9f7 531 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 534 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 537 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 540 the message digest of a new message */
<> 144:ef7eb2e8f9f7 541 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Set the phase */
<> 144:ef7eb2e8f9f7 545 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 548 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 551 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 554 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Get tick */
<> 144:ef7eb2e8f9f7 557 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 562 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 /* Change state */
<> 144:ef7eb2e8f9f7 567 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 570 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Read the message digest */
<> 144:ef7eb2e8f9f7 578 HASH_GetDigest(pOutBuffer, 16U);
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 581 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 584 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Return function status */
<> 144:ef7eb2e8f9f7 587 return HAL_OK;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /**
<> 144:ef7eb2e8f9f7 591 * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
<> 144:ef7eb2e8f9f7 592 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 593 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 594 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 595 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 596 * If the Size is multiple of 64 bytes, appending the input buffer is possible.
<> 144:ef7eb2e8f9f7 597 * If the Size is not multiple of 64 bytes, the padding is managed by hardware
<> 144:ef7eb2e8f9f7 598 * and appending the input buffer is no more possible.
<> 144:ef7eb2e8f9f7 599 * @retval HAL status
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 /* Process Locked */
<> 144:ef7eb2e8f9f7 604 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 607 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 610 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 613 the message digest of a new message */
<> 144:ef7eb2e8f9f7 614 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /* Set the phase */
<> 144:ef7eb2e8f9f7 618 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 621 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 624 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 627 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 630 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Return function status */
<> 144:ef7eb2e8f9f7 633 return HAL_OK;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 638 The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 639 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 640 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 641 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 642 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 643 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 644 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 645 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 646 * @retval HAL status
<> 144:ef7eb2e8f9f7 647 */
<> 144:ef7eb2e8f9f7 648 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Process Locked */
<> 144:ef7eb2e8f9f7 653 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 656 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 659 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 662 the message digest of a new message */
<> 144:ef7eb2e8f9f7 663 HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* Set the phase */
<> 144:ef7eb2e8f9f7 667 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 670 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 673 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 676 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Get tick */
<> 144:ef7eb2e8f9f7 679 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 684 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 /* Change state */
<> 144:ef7eb2e8f9f7 689 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 692 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Read the message digest */
<> 144:ef7eb2e8f9f7 700 HASH_GetDigest(pOutBuffer, 20U);
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 703 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 706 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Return function status */
<> 144:ef7eb2e8f9f7 709 return HAL_OK;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /**
<> 144:ef7eb2e8f9f7 713 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 714 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 715 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 716 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 717 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 718 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 719 * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
<> 144:ef7eb2e8f9f7 720 * @retval HAL status
<> 144:ef7eb2e8f9f7 721 */
<> 144:ef7eb2e8f9f7 722 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 /* Check the parameters */
<> 144:ef7eb2e8f9f7 725 assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Process Locked */
<> 144:ef7eb2e8f9f7 728 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 731 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 734 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 737 the message digest of a new message */
<> 144:ef7eb2e8f9f7 738 HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 739 }
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* Set the phase */
<> 144:ef7eb2e8f9f7 742 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 745 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 748 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 751 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 754 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Return function status */
<> 144:ef7eb2e8f9f7 757 return HAL_OK;
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /**
<> 144:ef7eb2e8f9f7 761 * @}
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
<> 144:ef7eb2e8f9f7 765 * @brief processing functions using interrupt mode.
<> 144:ef7eb2e8f9f7 766 *
<> 144:ef7eb2e8f9f7 767 @verbatim
<> 144:ef7eb2e8f9f7 768 ===============================================================================
<> 144:ef7eb2e8f9f7 769 ##### HASH processing using interrupt mode functions #####
<> 144:ef7eb2e8f9f7 770 ===============================================================================
<> 144:ef7eb2e8f9f7 771 [..] This section provides functions allowing to calculate in interrupt mode
<> 144:ef7eb2e8f9f7 772 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 773 (+) MD5
<> 144:ef7eb2e8f9f7 774 (+) SHA1
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 @endverbatim
<> 144:ef7eb2e8f9f7 777 * @{
<> 144:ef7eb2e8f9f7 778 */
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /**
<> 144:ef7eb2e8f9f7 781 * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 782 * The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 783 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 784 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 785 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 786 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 787 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 788 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 789 * @retval HAL status
<> 144:ef7eb2e8f9f7 790 */
<> 144:ef7eb2e8f9f7 791 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 uint32_t inputaddr;
<> 144:ef7eb2e8f9f7 794 uint32_t outputaddr;
<> 144:ef7eb2e8f9f7 795 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 796 uint32_t inputcounter;
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Process Locked */
<> 144:ef7eb2e8f9f7 799 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 if(hhash->State == HAL_HASH_STATE_READY)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 804 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 hhash->HashInCount = Size;
<> 144:ef7eb2e8f9f7 807 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 808 hhash->pHashOutBuffPtr = pOutBuffer;
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 811 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 /* Select the SHA1 mode */
<> 144:ef7eb2e8f9f7 814 HASH->CR |= HASH_ALGOSELECTION_MD5;
<> 144:ef7eb2e8f9f7 815 /* Reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 816 the message digest of a new message */
<> 144:ef7eb2e8f9f7 817 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 /* Reset interrupt counter */
<> 144:ef7eb2e8f9f7 820 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Set the phase */
<> 144:ef7eb2e8f9f7 823 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 826 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 829 HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Return function status */
<> 144:ef7eb2e8f9f7 832 return HAL_OK;
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
<> 144:ef7eb2e8f9f7 837 /* Read the Output block from the Output FIFO */
<> 144:ef7eb2e8f9f7 838 *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 839 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 840 *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 841 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 842 *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 843 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 844 *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 if(hhash->HashInCount == 0U)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 849 HASH->IMR = 0U;
<> 144:ef7eb2e8f9f7 850 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 851 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 852 /* Call digest computation complete callback */
<> 144:ef7eb2e8f9f7 853 HAL_HASH_DgstCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 856 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Return function status */
<> 144:ef7eb2e8f9f7 859 return HAL_OK;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 867 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 868 for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 871 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873 if(hhash->HashITCounter == 0U)
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 880 hhash->HashInCount -= 68U;
<> 144:ef7eb2e8f9f7 881 hhash->pHashInBuffPtr+= 68U;
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 else
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 886 hhash->pHashInBuffPtr+= hhash->HashInCount;
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888 /* Set Interrupt counter */
<> 144:ef7eb2e8f9f7 889 hhash->HashITCounter = 1U;
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891 else
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 894 hhash->HashInCount -= 64U;
<> 144:ef7eb2e8f9f7 895 hhash->pHashInBuffPtr+= 64U;
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898 else
<> 144:ef7eb2e8f9f7 899 {
<> 144:ef7eb2e8f9f7 900 /* Get the buffer address */
<> 144:ef7eb2e8f9f7 901 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 902 /* Get the buffer counter */
<> 144:ef7eb2e8f9f7 903 inputcounter = hhash->HashInCount;
<> 144:ef7eb2e8f9f7 904 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 905 HASH->IMR &= ~(HASH_IT_DINI);
<> 144:ef7eb2e8f9f7 906 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 907 __HAL_HASH_SET_NBVALIDBITS(inputcounter);
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 if((inputcounter > 4U) && (inputcounter%4U))
<> 144:ef7eb2e8f9f7 910 {
<> 144:ef7eb2e8f9f7 911 inputcounter = (inputcounter+4U-inputcounter%4U);
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913 else if ((inputcounter < 4U) && (inputcounter != 0U))
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 inputcounter = 4U;
<> 144:ef7eb2e8f9f7 916 }
<> 144:ef7eb2e8f9f7 917 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 918 for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 921 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 924 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 925 /* Reset buffer counter */
<> 144:ef7eb2e8f9f7 926 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 927 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 928 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 929 }
<> 144:ef7eb2e8f9f7 930 }
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 933 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Return function status */
<> 144:ef7eb2e8f9f7 936 return HAL_OK;
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /**
<> 144:ef7eb2e8f9f7 940 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 941 * The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 942 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 943 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 944 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 945 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 946 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 947 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 948 * @retval HAL status
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<> 144:ef7eb2e8f9f7 951 {
<> 144:ef7eb2e8f9f7 952 uint32_t inputaddr;
<> 144:ef7eb2e8f9f7 953 uint32_t outputaddr;
<> 144:ef7eb2e8f9f7 954 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 955 uint32_t inputcounter;
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /* Process Locked */
<> 144:ef7eb2e8f9f7 958 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 if(hhash->State == HAL_HASH_STATE_READY)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 963 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 hhash->HashInCount = Size;
<> 144:ef7eb2e8f9f7 966 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 967 hhash->pHashOutBuffPtr = pOutBuffer;
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 970 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 /* Select the SHA1 mode */
<> 144:ef7eb2e8f9f7 973 HASH->CR |= HASH_ALGOSELECTION_SHA1;
<> 144:ef7eb2e8f9f7 974 /* Reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 975 the message digest of a new message */
<> 144:ef7eb2e8f9f7 976 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 977 }
<> 144:ef7eb2e8f9f7 978 /* Reset interrupt counter */
<> 144:ef7eb2e8f9f7 979 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Set the phase */
<> 144:ef7eb2e8f9f7 982 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 985 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 988 HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /* Return function status */
<> 144:ef7eb2e8f9f7 991 return HAL_OK;
<> 144:ef7eb2e8f9f7 992 }
<> 144:ef7eb2e8f9f7 993 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
<> 144:ef7eb2e8f9f7 996 /* Read the Output block from the Output FIFO */
<> 144:ef7eb2e8f9f7 997 *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 998 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 999 *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 1000 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 1001 *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 1002 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 1003 *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 1004 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 1005 *(uint32_t*)(outputaddr) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 1006 if(hhash->HashInCount == 0U)
<> 144:ef7eb2e8f9f7 1007 {
<> 144:ef7eb2e8f9f7 1008 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 1009 HASH->IMR = 0U;
<> 144:ef7eb2e8f9f7 1010 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1011 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1012 /* Call digest computation complete callback */
<> 144:ef7eb2e8f9f7 1013 HAL_HASH_DgstCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1016 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Return function status */
<> 144:ef7eb2e8f9f7 1019 return HAL_OK;
<> 144:ef7eb2e8f9f7 1020 }
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 1027 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 1028 for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1031 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 1032 }
<> 144:ef7eb2e8f9f7 1033 if(hhash->HashITCounter == 0U)
<> 144:ef7eb2e8f9f7 1034 {
<> 144:ef7eb2e8f9f7 1035 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1036 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 1039 hhash->HashInCount -= 68U;
<> 144:ef7eb2e8f9f7 1040 hhash->pHashInBuffPtr+= 68U;
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042 else
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1045 hhash->pHashInBuffPtr+= hhash->HashInCount;
<> 144:ef7eb2e8f9f7 1046 }
<> 144:ef7eb2e8f9f7 1047 /* Set Interrupt counter */
<> 144:ef7eb2e8f9f7 1048 hhash->HashITCounter = 1U;
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050 else
<> 144:ef7eb2e8f9f7 1051 {
<> 144:ef7eb2e8f9f7 1052 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 1053 hhash->HashInCount -= 64U;
<> 144:ef7eb2e8f9f7 1054 hhash->pHashInBuffPtr+= 64U;
<> 144:ef7eb2e8f9f7 1055 }
<> 144:ef7eb2e8f9f7 1056 }
<> 144:ef7eb2e8f9f7 1057 else
<> 144:ef7eb2e8f9f7 1058 {
<> 144:ef7eb2e8f9f7 1059 /* Get the buffer address */
<> 144:ef7eb2e8f9f7 1060 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 1061 /* Get the buffer counter */
<> 144:ef7eb2e8f9f7 1062 inputcounter = hhash->HashInCount;
<> 144:ef7eb2e8f9f7 1063 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 1064 HASH->IMR &= ~(HASH_IT_DINI);
<> 144:ef7eb2e8f9f7 1065 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1066 __HAL_HASH_SET_NBVALIDBITS(inputcounter);
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 if((inputcounter > 4U) && (inputcounter%4U))
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 inputcounter = (inputcounter+4U-inputcounter%4U);
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 else if ((inputcounter < 4U) && (inputcounter != 0U))
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 inputcounter = 4U;
<> 144:ef7eb2e8f9f7 1075 }
<> 144:ef7eb2e8f9f7 1076 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 1077 for(buffercounter = 0U; buffercounter < inputcounter/4; buffercounter++)
<> 144:ef7eb2e8f9f7 1078 {
<> 144:ef7eb2e8f9f7 1079 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1080 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 1081 }
<> 144:ef7eb2e8f9f7 1082 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1083 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1084 /* Reset buffer counter */
<> 144:ef7eb2e8f9f7 1085 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1086 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 1087 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 1088 }
<> 144:ef7eb2e8f9f7 1089 }
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1092 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /* Return function status */
<> 144:ef7eb2e8f9f7 1095 return HAL_OK;
<> 144:ef7eb2e8f9f7 1096 }
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /**
<> 144:ef7eb2e8f9f7 1099 * @brief This function handles HASH interrupt request.
<> 144:ef7eb2e8f9f7 1100 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1101 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1102 * @retval None
<> 144:ef7eb2e8f9f7 1103 */
<> 144:ef7eb2e8f9f7 1104 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 1105 {
<> 144:ef7eb2e8f9f7 1106 switch(HASH->CR & HASH_CR_ALGO)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 case HASH_ALGOSELECTION_MD5:
<> 144:ef7eb2e8f9f7 1109 HAL_HASH_MD5_Start_IT(hhash, NULL, 0U, NULL);
<> 144:ef7eb2e8f9f7 1110 break;
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 case HASH_ALGOSELECTION_SHA1:
<> 144:ef7eb2e8f9f7 1113 HAL_HASH_SHA1_Start_IT(hhash, NULL, 0U, NULL);
<> 144:ef7eb2e8f9f7 1114 break;
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 default:
<> 144:ef7eb2e8f9f7 1117 break;
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119 }
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /**
<> 144:ef7eb2e8f9f7 1122 * @}
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
<> 144:ef7eb2e8f9f7 1126 * @brief processing functions using DMA mode.
<> 144:ef7eb2e8f9f7 1127 *
<> 144:ef7eb2e8f9f7 1128 @verbatim
<> 144:ef7eb2e8f9f7 1129 ===============================================================================
<> 144:ef7eb2e8f9f7 1130 ##### HASH processing using DMA mode functions #####
<> 144:ef7eb2e8f9f7 1131 ===============================================================================
<> 144:ef7eb2e8f9f7 1132 [..] This section provides functions allowing to calculate in DMA mode
<> 144:ef7eb2e8f9f7 1133 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1134 (+) MD5
<> 144:ef7eb2e8f9f7 1135 (+) SHA1
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 @endverbatim
<> 144:ef7eb2e8f9f7 1138 * @{
<> 144:ef7eb2e8f9f7 1139 */
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /**
<> 144:ef7eb2e8f9f7 1142 * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
<> 144:ef7eb2e8f9f7 1143 control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
<> 144:ef7eb2e8f9f7 1144 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1145 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1146 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1147 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1148 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1149 * @retval HAL status
<> 144:ef7eb2e8f9f7 1150 */
<> 144:ef7eb2e8f9f7 1151 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1152 {
<> 144:ef7eb2e8f9f7 1153 uint32_t inputaddr = (uint32_t)pInBuffer;
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Process Locked */
<> 144:ef7eb2e8f9f7 1156 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1159 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1162 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 1165 the message digest of a new message */
<> 144:ef7eb2e8f9f7 1166 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 1167 }
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1170 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /* Set the phase */
<> 144:ef7eb2e8f9f7 1173 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1176 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1177 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1178 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 1181 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1184 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1187 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /* Return function status */
<> 144:ef7eb2e8f9f7 1190 return HAL_OK;
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /**
<> 144:ef7eb2e8f9f7 1194 * @brief Returns the computed digest in MD5 mode
<> 144:ef7eb2e8f9f7 1195 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1196 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1197 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 1198 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1199 * @retval HAL status
<> 144:ef7eb2e8f9f7 1200 */
<> 144:ef7eb2e8f9f7 1201 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1202 {
<> 144:ef7eb2e8f9f7 1203 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Process Locked */
<> 144:ef7eb2e8f9f7 1206 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1209 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Get tick */
<> 144:ef7eb2e8f9f7 1212 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 1215 {
<> 144:ef7eb2e8f9f7 1216 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1217 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1218 {
<> 144:ef7eb2e8f9f7 1219 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1220 {
<> 144:ef7eb2e8f9f7 1221 /* Change state */
<> 144:ef7eb2e8f9f7 1222 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1225 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1228 }
<> 144:ef7eb2e8f9f7 1229 }
<> 144:ef7eb2e8f9f7 1230 }
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /* Read the message digest */
AnnaBridge 167:e84263d55307 1233 HASH_GetDigest(pOutBuffer, 16);
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1236 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1239 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /* Return function status */
<> 144:ef7eb2e8f9f7 1242 return HAL_OK;
<> 144:ef7eb2e8f9f7 1243 }
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /**
<> 144:ef7eb2e8f9f7 1246 * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
<> 144:ef7eb2e8f9f7 1247 control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
<> 144:ef7eb2e8f9f7 1248 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1249 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1250 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1251 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1252 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1253 * @retval HAL status
<> 144:ef7eb2e8f9f7 1254 */
<> 144:ef7eb2e8f9f7 1255 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 uint32_t inputaddr = (uint32_t)pInBuffer;
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /* Process Locked */
<> 144:ef7eb2e8f9f7 1260 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1263 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1266 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1267 {
<> 144:ef7eb2e8f9f7 1268 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 1269 the message digest of a new message */
<> 144:ef7eb2e8f9f7 1270 HASH->CR |= HASH_ALGOSELECTION_SHA1;
<> 144:ef7eb2e8f9f7 1271 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 1272 }
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1275 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /* Set the phase */
<> 144:ef7eb2e8f9f7 1278 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1281 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1282 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1283 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /* Enable the DMA In DMA Stream */
AnnaBridge 167:e84263d55307 1286 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1289 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1292 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 /* Return function status */
<> 144:ef7eb2e8f9f7 1295 return HAL_OK;
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /**
<> 144:ef7eb2e8f9f7 1299 * @brief Returns the computed digest in SHA1 mode.
<> 144:ef7eb2e8f9f7 1300 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1301 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1302 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1303 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1304 * @retval HAL status
<> 144:ef7eb2e8f9f7 1305 */
<> 144:ef7eb2e8f9f7 1306 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1307 {
<> 144:ef7eb2e8f9f7 1308 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /* Process Locked */
<> 144:ef7eb2e8f9f7 1311 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1314 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /* Get tick */
<> 144:ef7eb2e8f9f7 1317 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1318 while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 1319 {
<> 144:ef7eb2e8f9f7 1320 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1321 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1322 {
<> 144:ef7eb2e8f9f7 1323 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 /* Change state */
<> 144:ef7eb2e8f9f7 1326 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1329 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333 }
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1337 HASH_GetDigest(pOutBuffer, 20U);
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1340 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 /* Process UnLock */
<> 144:ef7eb2e8f9f7 1343 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* Return function status */
<> 144:ef7eb2e8f9f7 1346 return HAL_OK;
<> 144:ef7eb2e8f9f7 1347 }
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /**
<> 144:ef7eb2e8f9f7 1351 * @}
<> 144:ef7eb2e8f9f7 1352 */
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 /** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
<> 144:ef7eb2e8f9f7 1355 * @brief HMAC processing functions using polling mode .
<> 144:ef7eb2e8f9f7 1356 *
<> 144:ef7eb2e8f9f7 1357 @verbatim
<> 144:ef7eb2e8f9f7 1358 ===============================================================================
<> 144:ef7eb2e8f9f7 1359 ##### HMAC processing using polling mode functions #####
<> 144:ef7eb2e8f9f7 1360 ===============================================================================
<> 144:ef7eb2e8f9f7 1361 [..] This section provides functions allowing to calculate in polling mode
<> 144:ef7eb2e8f9f7 1362 the HMAC value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1363 (+) MD5
<> 144:ef7eb2e8f9f7 1364 (+) SHA1
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 @endverbatim
<> 144:ef7eb2e8f9f7 1367 * @{
<> 144:ef7eb2e8f9f7 1368 */
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /**
<> 144:ef7eb2e8f9f7 1371 * @brief Initializes the HASH peripheral in HMAC MD5 mode
<> 144:ef7eb2e8f9f7 1372 * then processes pInBuffer. The digest is available in pOutBuffer
<> 144:ef7eb2e8f9f7 1373 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1374 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1375 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1376 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1377 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1378 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1379 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1380 * @retval HAL status
<> 144:ef7eb2e8f9f7 1381 */
<> 144:ef7eb2e8f9f7 1382 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1383 {
<> 144:ef7eb2e8f9f7 1384 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /* Process Locked */
<> 144:ef7eb2e8f9f7 1387 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1390 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1393 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1394 {
<> 144:ef7eb2e8f9f7 1395 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1396 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1397 {
<> 144:ef7eb2e8f9f7 1398 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1399 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1400 }
<> 144:ef7eb2e8f9f7 1401 else
<> 144:ef7eb2e8f9f7 1402 {
<> 144:ef7eb2e8f9f7 1403 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1404 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Set the phase */
<> 144:ef7eb2e8f9f7 1409 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /************************** STEP 1 ******************************************/
<> 144:ef7eb2e8f9f7 1412 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1413 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1416 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1419 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Get tick */
<> 144:ef7eb2e8f9f7 1422 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1425 {
<> 144:ef7eb2e8f9f7 1426 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1427 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1430 {
<> 144:ef7eb2e8f9f7 1431 /* Change state */
<> 144:ef7eb2e8f9f7 1432 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1435 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440 }
<> 144:ef7eb2e8f9f7 1441 /************************** STEP 2 ******************************************/
<> 144:ef7eb2e8f9f7 1442 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1443 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1446 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1449 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /* Get tick */
<> 144:ef7eb2e8f9f7 1452 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1455 {
<> 144:ef7eb2e8f9f7 1456 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1457 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1458 {
<> 144:ef7eb2e8f9f7 1459 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1460 {
<> 144:ef7eb2e8f9f7 1461 /* Change state */
<> 144:ef7eb2e8f9f7 1462 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1465 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1468 }
<> 144:ef7eb2e8f9f7 1469 }
<> 144:ef7eb2e8f9f7 1470 }
<> 144:ef7eb2e8f9f7 1471 /************************** STEP 3 ******************************************/
<> 144:ef7eb2e8f9f7 1472 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1473 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1476 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1479 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /* Get tick */
<> 144:ef7eb2e8f9f7 1482 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1485 {
<> 144:ef7eb2e8f9f7 1486 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1487 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1488 {
<> 144:ef7eb2e8f9f7 1489 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1490 {
<> 144:ef7eb2e8f9f7 1491 /* Change state */
<> 144:ef7eb2e8f9f7 1492 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1495 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1498 }
<> 144:ef7eb2e8f9f7 1499 }
<> 144:ef7eb2e8f9f7 1500 }
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1503 HASH_GetDigest(pOutBuffer, 16U);
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1506 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1509 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1510
<> 144:ef7eb2e8f9f7 1511 /* Return function status */
<> 144:ef7eb2e8f9f7 1512 return HAL_OK;
<> 144:ef7eb2e8f9f7 1513 }
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 /**
<> 144:ef7eb2e8f9f7 1516 * @brief Initializes the HASH peripheral in HMAC SHA1 mode
<> 144:ef7eb2e8f9f7 1517 * then processes pInBuffer. The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 1518 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1519 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1520 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1521 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1522 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1523 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1524 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1525 * @retval HAL status
<> 144:ef7eb2e8f9f7 1526 */
<> 144:ef7eb2e8f9f7 1527 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1528 {
<> 144:ef7eb2e8f9f7 1529 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1530
<> 144:ef7eb2e8f9f7 1531 /* Process Locked */
<> 144:ef7eb2e8f9f7 1532 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1535 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1538 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1539 {
<> 144:ef7eb2e8f9f7 1540 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1541 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1542 {
<> 144:ef7eb2e8f9f7 1543 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1544 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1545 }
<> 144:ef7eb2e8f9f7 1546 else
<> 144:ef7eb2e8f9f7 1547 {
<> 144:ef7eb2e8f9f7 1548 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1549 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1550 }
<> 144:ef7eb2e8f9f7 1551 }
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /* Set the phase */
<> 144:ef7eb2e8f9f7 1554 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /************************** STEP 1 ******************************************/
<> 144:ef7eb2e8f9f7 1557 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1558 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1561 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1564 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /* Get tick */
<> 144:ef7eb2e8f9f7 1567 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1570 {
<> 144:ef7eb2e8f9f7 1571 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1572 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1573 {
<> 144:ef7eb2e8f9f7 1574 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1575 {
<> 144:ef7eb2e8f9f7 1576 /* Change state */
<> 144:ef7eb2e8f9f7 1577 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1578
<> 144:ef7eb2e8f9f7 1579 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1580 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1583 }
<> 144:ef7eb2e8f9f7 1584 }
<> 144:ef7eb2e8f9f7 1585 }
<> 144:ef7eb2e8f9f7 1586 /************************** STEP 2 ******************************************/
<> 144:ef7eb2e8f9f7 1587 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1588 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1591 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1594 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /* Get tick */
<> 144:ef7eb2e8f9f7 1597 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1600 {
<> 144:ef7eb2e8f9f7 1601 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1602 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1603 {
<> 144:ef7eb2e8f9f7 1604 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1605 {
<> 144:ef7eb2e8f9f7 1606 /* Change state */
<> 144:ef7eb2e8f9f7 1607 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1610 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1613 }
<> 144:ef7eb2e8f9f7 1614 }
<> 144:ef7eb2e8f9f7 1615 }
<> 144:ef7eb2e8f9f7 1616 /************************** STEP 3 ******************************************/
<> 144:ef7eb2e8f9f7 1617 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1618 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1621 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1622
<> 144:ef7eb2e8f9f7 1623 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1624 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 /* Get tick */
<> 144:ef7eb2e8f9f7 1627 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1630 {
<> 144:ef7eb2e8f9f7 1631 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1632 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1633 {
<> 144:ef7eb2e8f9f7 1634 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1635 {
<> 144:ef7eb2e8f9f7 1636 /* Change state */
<> 144:ef7eb2e8f9f7 1637 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1640 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1643 }
<> 144:ef7eb2e8f9f7 1644 }
<> 144:ef7eb2e8f9f7 1645 }
<> 144:ef7eb2e8f9f7 1646 /* Read the message digest */
AnnaBridge 167:e84263d55307 1647 HASH_GetDigest(pOutBuffer, 20);
<> 144:ef7eb2e8f9f7 1648
<> 144:ef7eb2e8f9f7 1649 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1650 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1653 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 /* Return function status */
<> 144:ef7eb2e8f9f7 1656 return HAL_OK;
<> 144:ef7eb2e8f9f7 1657 }
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 /**
<> 144:ef7eb2e8f9f7 1660 * @}
<> 144:ef7eb2e8f9f7 1661 */
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 /** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
<> 144:ef7eb2e8f9f7 1664 * @brief HMAC processing functions using DMA mode .
<> 144:ef7eb2e8f9f7 1665 *
<> 144:ef7eb2e8f9f7 1666 @verbatim
<> 144:ef7eb2e8f9f7 1667 ===============================================================================
<> 144:ef7eb2e8f9f7 1668 ##### HMAC processing using DMA mode functions #####
<> 144:ef7eb2e8f9f7 1669 ===============================================================================
<> 144:ef7eb2e8f9f7 1670 [..] This section provides functions allowing to calculate in DMA mode
<> 144:ef7eb2e8f9f7 1671 the HMAC value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1672 (+) MD5
<> 144:ef7eb2e8f9f7 1673 (+) SHA1
<> 144:ef7eb2e8f9f7 1674
<> 144:ef7eb2e8f9f7 1675 @endverbatim
<> 144:ef7eb2e8f9f7 1676 * @{
<> 144:ef7eb2e8f9f7 1677 */
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 /**
<> 144:ef7eb2e8f9f7 1680 * @brief Initializes the HASH peripheral in HMAC MD5 mode
<> 144:ef7eb2e8f9f7 1681 * then enables DMA to control data transfer.
<> 144:ef7eb2e8f9f7 1682 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1683 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1684 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1685 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1686 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1687 * @retval HAL status
<> 144:ef7eb2e8f9f7 1688 */
<> 144:ef7eb2e8f9f7 1689 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1690 {
<> 144:ef7eb2e8f9f7 1691 uint32_t inputaddr = 0U;
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 /* Process Locked */
<> 144:ef7eb2e8f9f7 1694 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1697 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 /* Save buffer pointer and size in handle */
<> 144:ef7eb2e8f9f7 1700 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 1701 hhash->HashBuffSize = Size;
<> 144:ef7eb2e8f9f7 1702 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1705 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1706 {
<> 144:ef7eb2e8f9f7 1707 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1708 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1709 {
<> 144:ef7eb2e8f9f7 1710 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1711 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1712 }
<> 144:ef7eb2e8f9f7 1713 else
<> 144:ef7eb2e8f9f7 1714 {
<> 144:ef7eb2e8f9f7 1715 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1716 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1717 }
<> 144:ef7eb2e8f9f7 1718 }
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720 /* Set the phase */
<> 144:ef7eb2e8f9f7 1721 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1722
<> 144:ef7eb2e8f9f7 1723 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1724 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1725
<> 144:ef7eb2e8f9f7 1726 /* Get the key address */
<> 144:ef7eb2e8f9f7 1727 inputaddr = (uint32_t)(hhash->Init.pKey);
<> 144:ef7eb2e8f9f7 1728
<> 144:ef7eb2e8f9f7 1729 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1730 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1731 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1732 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1733
<> 144:ef7eb2e8f9f7 1734 /* Enable the DMA In DMA Stream */
AnnaBridge 167:e84263d55307 1735 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
<> 144:ef7eb2e8f9f7 1736 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1737 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1740 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 /* Return function status */
<> 144:ef7eb2e8f9f7 1743 return HAL_OK;
<> 144:ef7eb2e8f9f7 1744 }
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 /**
<> 144:ef7eb2e8f9f7 1747 * @brief Initializes the HASH peripheral in HMAC SHA1 mode
<> 144:ef7eb2e8f9f7 1748 * then enables DMA to control data transfer.
<> 144:ef7eb2e8f9f7 1749 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1750 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1751 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1752 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1753 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1754 * @retval HAL status
<> 144:ef7eb2e8f9f7 1755 */
<> 144:ef7eb2e8f9f7 1756 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1757 {
<> 144:ef7eb2e8f9f7 1758 uint32_t inputaddr = 0U;
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 /* Process Locked */
<> 144:ef7eb2e8f9f7 1761 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1764 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1765
<> 144:ef7eb2e8f9f7 1766 /* Save buffer pointer and size in handle */
<> 144:ef7eb2e8f9f7 1767 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 1768 hhash->HashBuffSize = Size;
<> 144:ef7eb2e8f9f7 1769 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1772 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1773 {
<> 144:ef7eb2e8f9f7 1774 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1775 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1776 {
<> 144:ef7eb2e8f9f7 1777 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1778 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1779 }
<> 144:ef7eb2e8f9f7 1780 else
<> 144:ef7eb2e8f9f7 1781 {
<> 144:ef7eb2e8f9f7 1782 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1783 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1784 }
<> 144:ef7eb2e8f9f7 1785 }
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 /* Set the phase */
<> 144:ef7eb2e8f9f7 1788 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1791 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1792
<> 144:ef7eb2e8f9f7 1793 /* Get the key address */
<> 144:ef7eb2e8f9f7 1794 inputaddr = (uint32_t)(hhash->Init.pKey);
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1797 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1798 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1799 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 /* Enable the DMA In DMA Stream */
AnnaBridge 167:e84263d55307 1802 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
<> 144:ef7eb2e8f9f7 1803 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1804 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1805
<> 144:ef7eb2e8f9f7 1806 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1807 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1808
<> 144:ef7eb2e8f9f7 1809 /* Return function status */
<> 144:ef7eb2e8f9f7 1810 return HAL_OK;
<> 144:ef7eb2e8f9f7 1811 }
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /**
<> 144:ef7eb2e8f9f7 1814 * @}
<> 144:ef7eb2e8f9f7 1815 */
<> 144:ef7eb2e8f9f7 1816
<> 144:ef7eb2e8f9f7 1817 /** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
<> 144:ef7eb2e8f9f7 1818 * @brief Peripheral State functions.
<> 144:ef7eb2e8f9f7 1819 *
<> 144:ef7eb2e8f9f7 1820 @verbatim
<> 144:ef7eb2e8f9f7 1821 ===============================================================================
<> 144:ef7eb2e8f9f7 1822 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1823 ===============================================================================
<> 144:ef7eb2e8f9f7 1824 [..]
<> 144:ef7eb2e8f9f7 1825 This subsection permits to get in run-time the status of the peripheral.
<> 144:ef7eb2e8f9f7 1826
<> 144:ef7eb2e8f9f7 1827 @endverbatim
<> 144:ef7eb2e8f9f7 1828 * @{
<> 144:ef7eb2e8f9f7 1829 */
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /**
<> 144:ef7eb2e8f9f7 1832 * @brief return the HASH state
<> 144:ef7eb2e8f9f7 1833 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1834 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1835 * @retval HAL state
<> 144:ef7eb2e8f9f7 1836 */
<> 144:ef7eb2e8f9f7 1837 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 1838 {
<> 144:ef7eb2e8f9f7 1839 return hhash->State;
<> 144:ef7eb2e8f9f7 1840 }
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 /**
<> 144:ef7eb2e8f9f7 1843 * @}
<> 144:ef7eb2e8f9f7 1844 */
<> 144:ef7eb2e8f9f7 1845
<> 144:ef7eb2e8f9f7 1846 /**
<> 144:ef7eb2e8f9f7 1847 * @}
<> 144:ef7eb2e8f9f7 1848 */
<> 144:ef7eb2e8f9f7 1849 #endif /* STM32F215xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 1850 #endif /* HAL_HASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1851 /**
<> 144:ef7eb2e8f9f7 1852 * @}
<> 144:ef7eb2e8f9f7 1853 */
<> 144:ef7eb2e8f9f7 1854
<> 144:ef7eb2e8f9f7 1855 /**
<> 144:ef7eb2e8f9f7 1856 * @}
<> 144:ef7eb2e8f9f7 1857 */
<> 144:ef7eb2e8f9f7 1858
<> 144:ef7eb2e8f9f7 1859 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/