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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_eth.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 186:707f6e361f3e

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_eth.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief ETH HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Ethernet (ETH) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	@verbatim
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	18	==============================================================================
<>	144:ef7eb2e8f9f7	19	[..]
<>	144:ef7eb2e8f9f7	20	(#)Declare a ETH_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	21	ETH_HandleTypeDef heth;
<>	144:ef7eb2e8f9f7	22
<>	144:ef7eb2e8f9f7	23	(#)Fill parameters of Init structure in heth handle
<>	144:ef7eb2e8f9f7	24
<>	144:ef7eb2e8f9f7	25	(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
<>	144:ef7eb2e8f9f7	26
<>	144:ef7eb2e8f9f7	27	(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
<>	144:ef7eb2e8f9f7	28	(##) Enable the Ethernet interface clock using
<>	144:ef7eb2e8f9f7	29	(+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	30	(+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	31	(+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	32
<>	144:ef7eb2e8f9f7	33	(##) Initialize the related GPIO clocks
<>	144:ef7eb2e8f9f7	34	(##) Configure Ethernet pin-out
<>	144:ef7eb2e8f9f7	35	(##) Configure Ethernet NVIC interrupt (IT mode)
<>	144:ef7eb2e8f9f7	36
<>	144:ef7eb2e8f9f7	37	(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
<>	144:ef7eb2e8f9f7	38	(##) HAL_ETH_DMATxDescListInit(); for Transmission process
<>	144:ef7eb2e8f9f7	39	(##) HAL_ETH_DMARxDescListInit(); for Reception process
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	(#)Enable MAC and DMA transmission and reception:
<>	144:ef7eb2e8f9f7	42	(##) HAL_ETH_Start();
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
<>	144:ef7eb2e8f9f7	45	the frame to MAC TX FIFO:
<>	144:ef7eb2e8f9f7	46	(##) HAL_ETH_TransmitFrame();
<>	144:ef7eb2e8f9f7	47
<>	144:ef7eb2e8f9f7	48	(#)Poll for a received frame in ETH RX DMA Descriptors and get received
<>	144:ef7eb2e8f9f7	49	frame parameters
<>	144:ef7eb2e8f9f7	50	(##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	(#) Get a received frame when an ETH RX interrupt occurs:
<>	144:ef7eb2e8f9f7	53	(##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	(#) Communicate with external PHY device:
<>	144:ef7eb2e8f9f7	56	(##) Read a specific register from the PHY
<>	144:ef7eb2e8f9f7	57	HAL_ETH_ReadPHYRegister();
<>	144:ef7eb2e8f9f7	58	(##) Write data to a specific RHY register:
<>	144:ef7eb2e8f9f7	59	HAL_ETH_WritePHYRegister();
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	(#) Configure the Ethernet MAC after ETH peripheral initialization
<>	144:ef7eb2e8f9f7	62	HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
<>	144:ef7eb2e8f9f7	63
<>	144:ef7eb2e8f9f7	64	(#) Configure the Ethernet DMA after ETH peripheral initialization
<>	144:ef7eb2e8f9f7	65	HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	@endverbatim
<>	144:ef7eb2e8f9f7	68	******************************************************************************
<>	144:ef7eb2e8f9f7	69	* @attention
<>	144:ef7eb2e8f9f7	70	*
AnnaBridge	167:e84263d55307	71	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	72	*
<>	144:ef7eb2e8f9f7	73	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	74	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	75	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	76	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	77	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	78	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	79	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	80	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	81	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	82	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	83	*
<>	144:ef7eb2e8f9f7	84	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	85	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	86	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	87	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	88	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	89	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	90	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	91	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	92	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	93	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	94	*
<>	144:ef7eb2e8f9f7	95	******************************************************************************
<>	144:ef7eb2e8f9f7	96	*/
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	99	#include "stm32f2xx_hal.h"
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	102	* @{
<>	144:ef7eb2e8f9f7	103	*/
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	/** @defgroup ETH ETH
<>	144:ef7eb2e8f9f7	106	* @brief ETH HAL module driver
<>	144:ef7eb2e8f9f7	107	* @{
<>	144:ef7eb2e8f9f7	108	*/
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	#ifdef HAL_ETH_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	#if defined(STM32F207xx) \|\| defined(STM32F217xx)
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	115	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	116	/** @defgroup ETH_Private_Constants ETH Private Constants
<>	144:ef7eb2e8f9f7	117	* @{
<>	144:ef7eb2e8f9f7	118	*/
AnnaBridge	167:e84263d55307	119	#define ETH_TIMEOUT_SWRESET 500U
AnnaBridge	167:e84263d55307	120	#define ETH_TIMEOUT_LINKED_STATE 5000U
AnnaBridge	167:e84263d55307	121	#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	/**
<>	144:ef7eb2e8f9f7	124	* @}
<>	144:ef7eb2e8f9f7	125	*/
<>	144:ef7eb2e8f9f7	126	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	127	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	128	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	129	/** @defgroup ETH_Private_Functions ETH Private Functions
<>	144:ef7eb2e8f9f7	130	* @{
<>	144:ef7eb2e8f9f7	131	*/
<>	144:ef7eb2e8f9f7	132	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
<>	144:ef7eb2e8f9f7	133	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr);
<>	144:ef7eb2e8f9f7	134	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	135	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	136	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	137	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	138	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	139	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	140	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	141	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	142	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
<>	144:ef7eb2e8f9f7	143	static void ETH_Delay(uint32_t mdelay);
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	/**
<>	144:ef7eb2e8f9f7	146	* @}
<>	144:ef7eb2e8f9f7	147	*/
<>	144:ef7eb2e8f9f7	148	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	/** @defgroup ETH_Exported_Functions ETH Exported Functions
<>	144:ef7eb2e8f9f7	151	* @{
<>	144:ef7eb2e8f9f7	152	*/
<>	144:ef7eb2e8f9f7	153
<>	144:ef7eb2e8f9f7	154	/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	155	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	156	*
<>	144:ef7eb2e8f9f7	157	@verbatim
<>	144:ef7eb2e8f9f7	158	===============================================================================
<>	144:ef7eb2e8f9f7	159	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	160	===============================================================================
<>	144:ef7eb2e8f9f7	161	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	162	(+) Initialize and configure the Ethernet peripheral
<>	144:ef7eb2e8f9f7	163	(+) De-initialize the Ethernet peripheral
<>	144:ef7eb2e8f9f7	164
<>	144:ef7eb2e8f9f7	165	@endverbatim
<>	144:ef7eb2e8f9f7	166	* @{
<>	144:ef7eb2e8f9f7	167	*/
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	/**
<>	144:ef7eb2e8f9f7	170	* @brief Initializes the Ethernet MAC and DMA according to default
<>	144:ef7eb2e8f9f7	171	* parameters.
<>	144:ef7eb2e8f9f7	172	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	173	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	174	* @retval HAL status
<>	144:ef7eb2e8f9f7	175	*/
<>	144:ef7eb2e8f9f7	176	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	177	{
<>	144:ef7eb2e8f9f7	178	uint32_t tmpreg1 = 0U, phyreg = 0U;
<>	144:ef7eb2e8f9f7	179	uint32_t hclk = 60000000U;
<>	144:ef7eb2e8f9f7	180	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	181	uint32_t err = ETH_SUCCESS;
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	/* Check the ETH peripheral state */
<>	144:ef7eb2e8f9f7	184	if(heth == NULL)
<>	144:ef7eb2e8f9f7	185	{
<>	144:ef7eb2e8f9f7	186	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	187	}
<>	144:ef7eb2e8f9f7	188
<>	144:ef7eb2e8f9f7	189	/* Check parameters */
<>	144:ef7eb2e8f9f7	190	assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
<>	144:ef7eb2e8f9f7	191	assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
<>	144:ef7eb2e8f9f7	192	assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
<>	144:ef7eb2e8f9f7	193	assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	if(heth->State == HAL_ETH_STATE_RESET)
<>	144:ef7eb2e8f9f7	196	{
<>	144:ef7eb2e8f9f7	197	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	198	heth->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	199	/* Init the low level hardware : GPIO, CLOCK, NVIC. */
<>	144:ef7eb2e8f9f7	200	HAL_ETH_MspInit(heth);
<>	144:ef7eb2e8f9f7	201	}
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	/* Enable SYSCFG Clock */
<>	144:ef7eb2e8f9f7	204	__HAL_RCC_SYSCFG_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/* Select MII or RMII Mode*/
<>	144:ef7eb2e8f9f7	207	SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
<>	144:ef7eb2e8f9f7	208	SYSCFG->PMC \|= (uint32_t)heth->Init.MediaInterface;
<>	144:ef7eb2e8f9f7	209
<>	144:ef7eb2e8f9f7	210	/* Ethernet Software reset */
<>	144:ef7eb2e8f9f7	211	/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
<>	144:ef7eb2e8f9f7	212	/* After reset all the registers holds their respective reset values */
<>	144:ef7eb2e8f9f7	213	(heth->Instance)->DMABMR \|= ETH_DMABMR_SR;
<>	144:ef7eb2e8f9f7	214
<>	144:ef7eb2e8f9f7	215	/* Get tick */
<>	144:ef7eb2e8f9f7	216	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	/* Wait for software reset */
<>	144:ef7eb2e8f9f7	219	while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
<>	144:ef7eb2e8f9f7	220	{
<>	144:ef7eb2e8f9f7	221	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	222	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
<>	144:ef7eb2e8f9f7	223	{
<>	144:ef7eb2e8f9f7	224	heth->State= HAL_ETH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	227	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
<>	144:ef7eb2e8f9f7	230	not available, please check your external PHY or the IO configuration */
<>	144:ef7eb2e8f9f7	231	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	232	}
<>	144:ef7eb2e8f9f7	233	}
<>	144:ef7eb2e8f9f7	234
<>	144:ef7eb2e8f9f7	235	/-------------------------------- MAC Initialization ----------------------/
<>	144:ef7eb2e8f9f7	236	/* Get the ETHERNET MACMIIAR value */
<>	144:ef7eb2e8f9f7	237	tmpreg1 = (heth->Instance)->MACMIIAR;
<>	144:ef7eb2e8f9f7	238	/* Clear CSR Clock Range CR[2:0] bits */
<>	144:ef7eb2e8f9f7	239	tmpreg1 &= ETH_MACMIIAR_CR_MASK;
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	/* Get hclk frequency value */
<>	144:ef7eb2e8f9f7	242	hclk = HAL_RCC_GetHCLKFreq();
<>	144:ef7eb2e8f9f7	243
<>	144:ef7eb2e8f9f7	244	/* Set CR bits depending on hclk value */
<>	144:ef7eb2e8f9f7	245	if((hclk >= 20000000U)&&(hclk < 35000000U))
<>	144:ef7eb2e8f9f7	246	{
<>	144:ef7eb2e8f9f7	247	/* CSR Clock Range between 20-35 MHz */
<>	144:ef7eb2e8f9f7	248	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div16;
<>	144:ef7eb2e8f9f7	249	}
<>	144:ef7eb2e8f9f7	250	else if((hclk >= 35000000U)&&(hclk < 60000000U))
<>	144:ef7eb2e8f9f7	251	{
<>	144:ef7eb2e8f9f7	252	/* CSR Clock Range between 35-60 MHz */
<>	144:ef7eb2e8f9f7	253	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div26;
<>	144:ef7eb2e8f9f7	254	}
<>	144:ef7eb2e8f9f7	255	else if((hclk >= 60000000U)&&(hclk < 100000000U))
<>	144:ef7eb2e8f9f7	256	{
<>	144:ef7eb2e8f9f7	257	/* CSR Clock Range between 60-100 MHz */
<>	144:ef7eb2e8f9f7	258	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div42;
<>	144:ef7eb2e8f9f7	259	}
<>	144:ef7eb2e8f9f7	260	else /* ((hclk >= 100000000)&&(hclk < 120000000)) */
<>	144:ef7eb2e8f9f7	261	{
<>	144:ef7eb2e8f9f7	262	/* CSR Clock Range between 100-120 MHz */
<>	144:ef7eb2e8f9f7	263	tmpreg1 \|= (uint32_t)ETH_MACMIIAR_CR_Div62;
<>	144:ef7eb2e8f9f7	264	}
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
<>	144:ef7eb2e8f9f7	267	(heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	268
<>	144:ef7eb2e8f9f7	269	/-------------------- PHY initialization and configuration ----------------/
<>	144:ef7eb2e8f9f7	270	/* Put the PHY in reset mode */
<>	144:ef7eb2e8f9f7	271	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
<>	144:ef7eb2e8f9f7	272	{
<>	144:ef7eb2e8f9f7	273	/* In case of write timeout */
<>	144:ef7eb2e8f9f7	274	err = ETH_ERROR;
<>	144:ef7eb2e8f9f7	275
<>	144:ef7eb2e8f9f7	276	/* Config MAC and DMA */
<>	144:ef7eb2e8f9f7	277	ETH_MACDMAConfig(heth, err);
<>	144:ef7eb2e8f9f7	278
<>	144:ef7eb2e8f9f7	279	/* Set the ETH peripheral state to READY */
<>	144:ef7eb2e8f9f7	280	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/* Return HAL_ERROR */
<>	144:ef7eb2e8f9f7	283	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	284	}
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/* Delay to assure PHY reset */
<>	144:ef7eb2e8f9f7	287	HAL_Delay(PHY_RESET_DELAY);
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
<>	144:ef7eb2e8f9f7	290	{
<>	144:ef7eb2e8f9f7	291	/* Get tick */
<>	144:ef7eb2e8f9f7	292	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/* We wait for linked status */
<>	144:ef7eb2e8f9f7	295	do
<>	144:ef7eb2e8f9f7	296	{
<>	144:ef7eb2e8f9f7	297	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
<>	144:ef7eb2e8f9f7	298
<>	144:ef7eb2e8f9f7	299	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	300	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
<>	144:ef7eb2e8f9f7	301	{
<>	144:ef7eb2e8f9f7	302	/* In case of write timeout */
<>	144:ef7eb2e8f9f7	303	err = ETH_ERROR;
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	/* Config MAC and DMA */
<>	144:ef7eb2e8f9f7	306	ETH_MACDMAConfig(heth, err);
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	311	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	314	}
<>	144:ef7eb2e8f9f7	315	} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/* Enable Auto-Negotiation */
<>	144:ef7eb2e8f9f7	319	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
<>	144:ef7eb2e8f9f7	320	{
<>	144:ef7eb2e8f9f7	321	/* In case of write timeout */
<>	144:ef7eb2e8f9f7	322	err = ETH_ERROR;
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/* Config MAC and DMA */
<>	144:ef7eb2e8f9f7	325	ETH_MACDMAConfig(heth, err);
<>	144:ef7eb2e8f9f7	326
<>	144:ef7eb2e8f9f7	327	/* Set the ETH peripheral state to READY */
<>	144:ef7eb2e8f9f7	328	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	/* Return HAL_ERROR */
<>	144:ef7eb2e8f9f7	331	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	332	}
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	/* Get tick */
<>	144:ef7eb2e8f9f7	335	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/* Wait until the auto-negotiation will be completed */
<>	144:ef7eb2e8f9f7	338	do
<>	144:ef7eb2e8f9f7	339	{
<>	144:ef7eb2e8f9f7	340	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	343	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
<>	144:ef7eb2e8f9f7	344	{
<>	144:ef7eb2e8f9f7	345	/* In case of write timeout */
<>	144:ef7eb2e8f9f7	346	err = ETH_ERROR;
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/* Config MAC and DMA */
<>	144:ef7eb2e8f9f7	349	ETH_MACDMAConfig(heth, err);
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	354	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	357	}
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	/* Read the result of the auto-negotiation */
<>	144:ef7eb2e8f9f7	362	if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
<>	144:ef7eb2e8f9f7	363	{
<>	144:ef7eb2e8f9f7	364	/* In case of write timeout */
<>	144:ef7eb2e8f9f7	365	err = ETH_ERROR;
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/* Config MAC and DMA */
<>	144:ef7eb2e8f9f7	368	ETH_MACDMAConfig(heth, err);
<>	144:ef7eb2e8f9f7	369
<>	144:ef7eb2e8f9f7	370	/* Set the ETH peripheral state to READY */
<>	144:ef7eb2e8f9f7	371	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	/* Return HAL_ERROR */
<>	144:ef7eb2e8f9f7	374	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	375	}
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
<>	144:ef7eb2e8f9f7	378	if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
<>	144:ef7eb2e8f9f7	379	{
<>	144:ef7eb2e8f9f7	380	/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
<>	144:ef7eb2e8f9f7	381	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
<>	144:ef7eb2e8f9f7	382	}
<>	144:ef7eb2e8f9f7	383	else
<>	144:ef7eb2e8f9f7	384	{
<>	144:ef7eb2e8f9f7	385	/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
<>	144:ef7eb2e8f9f7	386	(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
<>	144:ef7eb2e8f9f7	387	}
<>	144:ef7eb2e8f9f7	388	/* Configure the MAC with the speed fixed by the auto-negotiation process */
<>	144:ef7eb2e8f9f7	389	if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
<>	144:ef7eb2e8f9f7	390	{
<>	144:ef7eb2e8f9f7	391	/* Set Ethernet speed to 10M following the auto-negotiation */
<>	144:ef7eb2e8f9f7	392	(heth->Init).Speed = ETH_SPEED_10M;
<>	144:ef7eb2e8f9f7	393	}
<>	144:ef7eb2e8f9f7	394	else
<>	144:ef7eb2e8f9f7	395	{
<>	144:ef7eb2e8f9f7	396	/* Set Ethernet speed to 100M following the auto-negotiation */
<>	144:ef7eb2e8f9f7	397	(heth->Init).Speed = ETH_SPEED_100M;
<>	144:ef7eb2e8f9f7	398	}
<>	144:ef7eb2e8f9f7	399	}
<>	144:ef7eb2e8f9f7	400	else /* AutoNegotiation Disable */
<>	144:ef7eb2e8f9f7	401	{
<>	144:ef7eb2e8f9f7	402	/* Check parameters */
<>	144:ef7eb2e8f9f7	403	assert_param(IS_ETH_SPEED(heth->Init.Speed));
<>	144:ef7eb2e8f9f7	404	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
<>	144:ef7eb2e8f9f7	405
<>	144:ef7eb2e8f9f7	406	/* Set MAC Speed and Duplex Mode */
<>	144:ef7eb2e8f9f7	407	if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) \|
<>	144:ef7eb2e8f9f7	408	(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
<>	144:ef7eb2e8f9f7	409	{
<>	144:ef7eb2e8f9f7	410	/* In case of write timeout */
<>	144:ef7eb2e8f9f7	411	err = ETH_ERROR;
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/* Config MAC and DMA */
<>	144:ef7eb2e8f9f7	414	ETH_MACDMAConfig(heth, err);
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/* Set the ETH peripheral state to READY */
<>	144:ef7eb2e8f9f7	417	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	/* Return HAL_ERROR */
<>	144:ef7eb2e8f9f7	420	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	421	}
<>	144:ef7eb2e8f9f7	422
<>	144:ef7eb2e8f9f7	423	/* Delay to assure PHY configuration */
<>	144:ef7eb2e8f9f7	424	HAL_Delay(PHY_CONFIG_DELAY);
<>	144:ef7eb2e8f9f7	425	}
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	/* Config MAC and DMA */
<>	144:ef7eb2e8f9f7	428	ETH_MACDMAConfig(heth, err);
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/* Set ETH HAL State to Ready */
<>	144:ef7eb2e8f9f7	431	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	/* Return function status */
<>	144:ef7eb2e8f9f7	434	return HAL_OK;
<>	144:ef7eb2e8f9f7	435	}
<>	144:ef7eb2e8f9f7	436
<>	144:ef7eb2e8f9f7	437	/**
<>	144:ef7eb2e8f9f7	438	* @brief De-Initializes the ETH peripheral.
<>	144:ef7eb2e8f9f7	439	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	440	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	441	* @retval HAL status
<>	144:ef7eb2e8f9f7	442	*/
<>	144:ef7eb2e8f9f7	443	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	444	{
<>	144:ef7eb2e8f9f7	445	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	446	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
<>	144:ef7eb2e8f9f7	449	HAL_ETH_MspDeInit(heth);
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/* Set ETH HAL state to Disabled */
<>	144:ef7eb2e8f9f7	452	heth->State= HAL_ETH_STATE_RESET;
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/* Release Lock */
<>	144:ef7eb2e8f9f7	455	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	/* Return function status */
<>	144:ef7eb2e8f9f7	458	return HAL_OK;
<>	144:ef7eb2e8f9f7	459	}
<>	144:ef7eb2e8f9f7	460
<>	144:ef7eb2e8f9f7	461	/**
<>	144:ef7eb2e8f9f7	462	* @brief Initializes the DMA Tx descriptors in chain mode.
<>	144:ef7eb2e8f9f7	463	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	464	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	465	* @param DMATxDescTab: Pointer to the first Tx desc list
<>	144:ef7eb2e8f9f7	466	* @param TxBuff: Pointer to the first TxBuffer list
<>	144:ef7eb2e8f9f7	467	* @param TxBuffCount: Number of the used Tx desc in the list
<>	144:ef7eb2e8f9f7	468	* @retval HAL status
<>	144:ef7eb2e8f9f7	469	*/
<>	144:ef7eb2e8f9f7	470	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
<>	144:ef7eb2e8f9f7	471	{
<>	144:ef7eb2e8f9f7	472	uint32_t i = 0U;
<>	144:ef7eb2e8f9f7	473	ETH_DMADescTypeDef *dmatxdesc;
<>	144:ef7eb2e8f9f7	474
<>	144:ef7eb2e8f9f7	475	/* Process Locked */
<>	144:ef7eb2e8f9f7	476	__HAL_LOCK(heth);
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	479	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
<>	144:ef7eb2e8f9f7	482	heth->TxDesc = DMATxDescTab;
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484	/* Fill each DMATxDesc descriptor with the right values */
<>	144:ef7eb2e8f9f7	485	for(i=0U; i < TxBuffCount; i++)
<>	144:ef7eb2e8f9f7	486	{
<>	144:ef7eb2e8f9f7	487	/* Get the pointer on the ith member of the Tx Desc list */
<>	144:ef7eb2e8f9f7	488	dmatxdesc = DMATxDescTab + i;
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	/* Set Second Address Chained bit */
<>	144:ef7eb2e8f9f7	491	dmatxdesc->Status = ETH_DMATXDESC_TCH;
<>	144:ef7eb2e8f9f7	492
<>	144:ef7eb2e8f9f7	493	/* Set Buffer1 address pointer */
<>	144:ef7eb2e8f9f7	494	dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
<>	144:ef7eb2e8f9f7	495
<>	144:ef7eb2e8f9f7	496	if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
<>	144:ef7eb2e8f9f7	497	{
<>	144:ef7eb2e8f9f7	498	/* Set the DMA Tx descriptors checksum insertion */
<>	144:ef7eb2e8f9f7	499	dmatxdesc->Status \|= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
<>	144:ef7eb2e8f9f7	500	}
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
<>	144:ef7eb2e8f9f7	503	if(i < (TxBuffCount-1))
<>	144:ef7eb2e8f9f7	504	{
<>	144:ef7eb2e8f9f7	505	/* Set next descriptor address register with next descriptor base address */
<>	144:ef7eb2e8f9f7	506	dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
<>	144:ef7eb2e8f9f7	507	}
<>	144:ef7eb2e8f9f7	508	else
<>	144:ef7eb2e8f9f7	509	{
<>	144:ef7eb2e8f9f7	510	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
<>	144:ef7eb2e8f9f7	511	dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
<>	144:ef7eb2e8f9f7	512	}
<>	144:ef7eb2e8f9f7	513	}
<>	144:ef7eb2e8f9f7	514
<>	144:ef7eb2e8f9f7	515	/* Set Transmit Descriptor List Address Register */
<>	144:ef7eb2e8f9f7	516	(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
<>	144:ef7eb2e8f9f7	517
<>	144:ef7eb2e8f9f7	518	/* Set ETH HAL State to Ready */
<>	144:ef7eb2e8f9f7	519	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	520
<>	144:ef7eb2e8f9f7	521	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	522	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	523
<>	144:ef7eb2e8f9f7	524	/* Return function status */
<>	144:ef7eb2e8f9f7	525	return HAL_OK;
<>	144:ef7eb2e8f9f7	526	}
<>	144:ef7eb2e8f9f7	527
<>	144:ef7eb2e8f9f7	528	/**
<>	144:ef7eb2e8f9f7	529	* @brief Initializes the DMA Rx descriptors in chain mode.
<>	144:ef7eb2e8f9f7	530	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	531	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	532	* @param DMARxDescTab: Pointer to the first Rx desc list
<>	144:ef7eb2e8f9f7	533	* @param RxBuff: Pointer to the first RxBuffer list
<>	144:ef7eb2e8f9f7	534	* @param RxBuffCount: Number of the used Rx desc in the list
<>	144:ef7eb2e8f9f7	535	* @retval HAL status
<>	144:ef7eb2e8f9f7	536	*/
<>	144:ef7eb2e8f9f7	537	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
<>	144:ef7eb2e8f9f7	538	{
<>	144:ef7eb2e8f9f7	539	uint32_t i = 0U;
<>	144:ef7eb2e8f9f7	540	ETH_DMADescTypeDef *DMARxDesc;
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	/* Process Locked */
<>	144:ef7eb2e8f9f7	543	__HAL_LOCK(heth);
<>	144:ef7eb2e8f9f7	544
<>	144:ef7eb2e8f9f7	545	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	546	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	547
<>	144:ef7eb2e8f9f7	548	/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
<>	144:ef7eb2e8f9f7	549	heth->RxDesc = DMARxDescTab;
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/* Fill each DMARxDesc descriptor with the right values */
<>	144:ef7eb2e8f9f7	552	for(i=0U; i < RxBuffCount; i++)
<>	144:ef7eb2e8f9f7	553	{
<>	144:ef7eb2e8f9f7	554	/* Get the pointer on the ith member of the Rx Desc list */
<>	144:ef7eb2e8f9f7	555	DMARxDesc = DMARxDescTab+i;
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	/* Set Own bit of the Rx descriptor Status */
<>	144:ef7eb2e8f9f7	558	DMARxDesc->Status = ETH_DMARXDESC_OWN;
<>	144:ef7eb2e8f9f7	559
<>	144:ef7eb2e8f9f7	560	/* Set Buffer1 size and Second Address Chained bit */
<>	144:ef7eb2e8f9f7	561	DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH \| ETH_RX_BUF_SIZE;
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	/* Set Buffer1 address pointer */
<>	144:ef7eb2e8f9f7	564	DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
<>	144:ef7eb2e8f9f7	567	{
<>	144:ef7eb2e8f9f7	568	/* Enable Ethernet DMA Rx Descriptor interrupt */
<>	144:ef7eb2e8f9f7	569	DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
<>	144:ef7eb2e8f9f7	570	}
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
<>	144:ef7eb2e8f9f7	573	if(i < (RxBuffCount-1U))
<>	144:ef7eb2e8f9f7	574	{
<>	144:ef7eb2e8f9f7	575	/* Set next descriptor address register with next descriptor base address */
AnnaBridge	167:e84263d55307	576	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
<>	144:ef7eb2e8f9f7	577	}
<>	144:ef7eb2e8f9f7	578	else
<>	144:ef7eb2e8f9f7	579	{
<>	144:ef7eb2e8f9f7	580	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
<>	144:ef7eb2e8f9f7	581	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
<>	144:ef7eb2e8f9f7	582	}
<>	144:ef7eb2e8f9f7	583	}
<>	144:ef7eb2e8f9f7	584
<>	144:ef7eb2e8f9f7	585	/* Set Receive Descriptor List Address Register */
<>	144:ef7eb2e8f9f7	586	(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
<>	144:ef7eb2e8f9f7	587
<>	144:ef7eb2e8f9f7	588	/* Set ETH HAL State to Ready */
<>	144:ef7eb2e8f9f7	589	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	592	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	593
<>	144:ef7eb2e8f9f7	594	/* Return function status */
<>	144:ef7eb2e8f9f7	595	return HAL_OK;
<>	144:ef7eb2e8f9f7	596	}
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	/**
<>	144:ef7eb2e8f9f7	599	* @brief Initializes the ETH MSP.
<>	144:ef7eb2e8f9f7	600	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	601	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	602	* @retval None
<>	144:ef7eb2e8f9f7	603	*/
<>	144:ef7eb2e8f9f7	604	__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	605	{
<>	144:ef7eb2e8f9f7	606	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	607	UNUSED(heth);
<>	144:ef7eb2e8f9f7	608	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	609	the HAL_ETH_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	610	*/
<>	144:ef7eb2e8f9f7	611	}
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	/**
<>	144:ef7eb2e8f9f7	614	* @brief DeInitializes ETH MSP.
<>	144:ef7eb2e8f9f7	615	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	616	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	617	* @retval None
<>	144:ef7eb2e8f9f7	618	*/
<>	144:ef7eb2e8f9f7	619	__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	620	{
<>	144:ef7eb2e8f9f7	621	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	622	UNUSED(heth);
<>	144:ef7eb2e8f9f7	623	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	624	the HAL_ETH_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	625	*/
<>	144:ef7eb2e8f9f7	626	}
<>	144:ef7eb2e8f9f7	627
<>	144:ef7eb2e8f9f7	628	/**
<>	144:ef7eb2e8f9f7	629	* @}
<>	144:ef7eb2e8f9f7	630	*/
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	633	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	634	*
<>	144:ef7eb2e8f9f7	635	@verbatim
<>	144:ef7eb2e8f9f7	636	==============================================================================
<>	144:ef7eb2e8f9f7	637	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	638	==============================================================================
<>	144:ef7eb2e8f9f7	639	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	640	(+) Transmit a frame
<>	144:ef7eb2e8f9f7	641	HAL_ETH_TransmitFrame();
<>	144:ef7eb2e8f9f7	642	(+) Receive a frame
<>	144:ef7eb2e8f9f7	643	HAL_ETH_GetReceivedFrame();
<>	144:ef7eb2e8f9f7	644	HAL_ETH_GetReceivedFrame_IT();
<>	144:ef7eb2e8f9f7	645	(+) Read from an External PHY register
<>	144:ef7eb2e8f9f7	646	HAL_ETH_ReadPHYRegister();
<>	144:ef7eb2e8f9f7	647	(+) Write to an External PHY register
<>	144:ef7eb2e8f9f7	648	HAL_ETH_WritePHYRegister();
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	@endverbatim
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	* @{
<>	144:ef7eb2e8f9f7	653	*/
<>	144:ef7eb2e8f9f7	654
<>	144:ef7eb2e8f9f7	655	/**
<>	144:ef7eb2e8f9f7	656	* @brief Sends an Ethernet frame.
<>	144:ef7eb2e8f9f7	657	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	658	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	659	* @param FrameLength: Amount of data to be sent
<>	144:ef7eb2e8f9f7	660	* @retval HAL status
<>	144:ef7eb2e8f9f7	661	*/
<>	144:ef7eb2e8f9f7	662	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
<>	144:ef7eb2e8f9f7	663	{
<>	144:ef7eb2e8f9f7	664	uint32_t bufcount = 0U, size = 0U, i = 0U;
<>	144:ef7eb2e8f9f7	665
<>	144:ef7eb2e8f9f7	666	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	667	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	if (FrameLength == 0U)
<>	144:ef7eb2e8f9f7	670	{
<>	144:ef7eb2e8f9f7	671	/* Set ETH HAL state to READY */
<>	144:ef7eb2e8f9f7	672	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	673
<>	144:ef7eb2e8f9f7	674	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	675	}
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
<>	144:ef7eb2e8f9f7	678	if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
<>	144:ef7eb2e8f9f7	679	{
<>	144:ef7eb2e8f9f7	680	/* OWN bit set */
<>	144:ef7eb2e8f9f7	681	heth->State = HAL_ETH_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	684	}
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	/* Get the number of needed Tx buffers for the current frame */
<>	144:ef7eb2e8f9f7	687	if (FrameLength > ETH_TX_BUF_SIZE)
<>	144:ef7eb2e8f9f7	688	{
<>	144:ef7eb2e8f9f7	689	bufcount = FrameLength/ETH_TX_BUF_SIZE;
<>	144:ef7eb2e8f9f7	690	if (FrameLength % ETH_TX_BUF_SIZE)
<>	144:ef7eb2e8f9f7	691	{
<>	144:ef7eb2e8f9f7	692	bufcount++;
<>	144:ef7eb2e8f9f7	693	}
<>	144:ef7eb2e8f9f7	694	}
<>	144:ef7eb2e8f9f7	695	else
<>	144:ef7eb2e8f9f7	696	{
<>	144:ef7eb2e8f9f7	697	bufcount = 1U;
<>	144:ef7eb2e8f9f7	698	}
<>	144:ef7eb2e8f9f7	699	if (bufcount == 1U)
<>	144:ef7eb2e8f9f7	700	{
<>	144:ef7eb2e8f9f7	701	/* Set LAST and FIRST segment */
<>	144:ef7eb2e8f9f7	702	heth->TxDesc->Status \|=ETH_DMATXDESC_FS\|ETH_DMATXDESC_LS;
<>	144:ef7eb2e8f9f7	703	/* Set frame size */
<>	144:ef7eb2e8f9f7	704	heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
<>	144:ef7eb2e8f9f7	705	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
<>	144:ef7eb2e8f9f7	706	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
<>	144:ef7eb2e8f9f7	707	/* Point to next descriptor */
<>	144:ef7eb2e8f9f7	708	heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	709	}
<>	144:ef7eb2e8f9f7	710	else
<>	144:ef7eb2e8f9f7	711	{
<>	144:ef7eb2e8f9f7	712	for (i=0U; i< bufcount; i++)
<>	144:ef7eb2e8f9f7	713	{
<>	144:ef7eb2e8f9f7	714	/* Clear FIRST and LAST segment bits */
<>	144:ef7eb2e8f9f7	715	heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS \| ETH_DMATXDESC_LS);
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	if (i == 0U)
<>	144:ef7eb2e8f9f7	718	{
<>	144:ef7eb2e8f9f7	719	/* Setting the first segment bit */
<>	144:ef7eb2e8f9f7	720	heth->TxDesc->Status \|= ETH_DMATXDESC_FS;
<>	144:ef7eb2e8f9f7	721	}
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/* Program size */
<>	144:ef7eb2e8f9f7	724	heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	if (i == (bufcount-1U))
<>	144:ef7eb2e8f9f7	727	{
<>	144:ef7eb2e8f9f7	728	/* Setting the last segment bit */
<>	144:ef7eb2e8f9f7	729	heth->TxDesc->Status \|= ETH_DMATXDESC_LS;
<>	144:ef7eb2e8f9f7	730	size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
<>	144:ef7eb2e8f9f7	731	heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
<>	144:ef7eb2e8f9f7	732	}
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
<>	144:ef7eb2e8f9f7	735	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
<>	144:ef7eb2e8f9f7	736	/* point to next descriptor */
<>	144:ef7eb2e8f9f7	737	heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	738	}
<>	144:ef7eb2e8f9f7	739	}
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
<>	144:ef7eb2e8f9f7	742	if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	/* Clear TBUS ETHERNET DMA flag */
<>	144:ef7eb2e8f9f7	745	(heth->Instance)->DMASR = ETH_DMASR_TBUS;
<>	144:ef7eb2e8f9f7	746	/* Resume DMA transmission*/
<>	144:ef7eb2e8f9f7	747	(heth->Instance)->DMATPDR = 0U;
<>	144:ef7eb2e8f9f7	748	}
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/* Set ETH HAL State to Ready */
<>	144:ef7eb2e8f9f7	751	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	/* Return function status */
<>	144:ef7eb2e8f9f7	754	return HAL_OK;
<>	144:ef7eb2e8f9f7	755	}
<>	144:ef7eb2e8f9f7	756
<>	144:ef7eb2e8f9f7	757	/**
<>	144:ef7eb2e8f9f7	758	* @brief Checks for received frames.
<>	144:ef7eb2e8f9f7	759	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	760	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	761	* @retval HAL status
<>	144:ef7eb2e8f9f7	762	*/
<>	144:ef7eb2e8f9f7	763	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	764	{
<>	144:ef7eb2e8f9f7	765	uint32_t framelength = 0U;
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/* Check the ETH state to BUSY */
<>	144:ef7eb2e8f9f7	768	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	/* Check if segment is not owned by DMA */
<>	144:ef7eb2e8f9f7	771	/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
<>	144:ef7eb2e8f9f7	772	if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
<>	144:ef7eb2e8f9f7	773	{
<>	144:ef7eb2e8f9f7	774	/* Check if last segment */
<>	144:ef7eb2e8f9f7	775	if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
<>	144:ef7eb2e8f9f7	776	{
<>	144:ef7eb2e8f9f7	777	/* increment segment count */
<>	144:ef7eb2e8f9f7	778	(heth->RxFrameInfos).SegCount++;
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/* Check if last segment is first segment: one segment contains the frame */
<>	144:ef7eb2e8f9f7	781	if ((heth->RxFrameInfos).SegCount == 1U)
<>	144:ef7eb2e8f9f7	782	{
<>	144:ef7eb2e8f9f7	783	(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
<>	144:ef7eb2e8f9f7	784	}
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
<>	144:ef7eb2e8f9f7	789	framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
<>	144:ef7eb2e8f9f7	790	heth->RxFrameInfos.length = framelength;
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/* Get the address of the buffer start address */
<>	144:ef7eb2e8f9f7	793	heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
<>	144:ef7eb2e8f9f7	794	/* point to next descriptor */
<>	144:ef7eb2e8f9f7	795	heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797	/* Set HAL State to Ready */
<>	144:ef7eb2e8f9f7	798	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	799
<>	144:ef7eb2e8f9f7	800	/* Return function status */
<>	144:ef7eb2e8f9f7	801	return HAL_OK;
<>	144:ef7eb2e8f9f7	802	}
<>	144:ef7eb2e8f9f7	803	/* Check if first segment */
<>	144:ef7eb2e8f9f7	804	else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
<>	144:ef7eb2e8f9f7	805	{
<>	144:ef7eb2e8f9f7	806	(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
<>	144:ef7eb2e8f9f7	807	(heth->RxFrameInfos).LSRxDesc = NULL;
<>	144:ef7eb2e8f9f7	808	(heth->RxFrameInfos).SegCount = 1U;
<>	144:ef7eb2e8f9f7	809	/* Point to next descriptor */
<>	144:ef7eb2e8f9f7	810	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	811	}
<>	144:ef7eb2e8f9f7	812	/* Check if intermediate segment */
<>	144:ef7eb2e8f9f7	813	else
<>	144:ef7eb2e8f9f7	814	{
<>	144:ef7eb2e8f9f7	815	(heth->RxFrameInfos).SegCount++;
<>	144:ef7eb2e8f9f7	816	/* Point to next descriptor */
<>	144:ef7eb2e8f9f7	817	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	818	}
<>	144:ef7eb2e8f9f7	819	}
<>	144:ef7eb2e8f9f7	820
<>	144:ef7eb2e8f9f7	821	/* Set ETH HAL State to Ready */
<>	144:ef7eb2e8f9f7	822	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	/* Return function status */
<>	144:ef7eb2e8f9f7	825	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	826	}
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	/**
<>	144:ef7eb2e8f9f7	829	* @brief Gets the Received frame in interrupt mode.
<>	144:ef7eb2e8f9f7	830	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	831	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	832	* @retval HAL status
<>	144:ef7eb2e8f9f7	833	*/
<>	144:ef7eb2e8f9f7	834	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	835	{
<>	144:ef7eb2e8f9f7	836	uint32_t descriptorscancounter = 0U;
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Set ETH HAL State to BUSY */
<>	144:ef7eb2e8f9f7	839	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/* Scan descriptors owned by CPU */
<>	144:ef7eb2e8f9f7	842	while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
<>	144:ef7eb2e8f9f7	843	{
<>	144:ef7eb2e8f9f7	844	/* Just for security */
<>	144:ef7eb2e8f9f7	845	descriptorscancounter++;
<>	144:ef7eb2e8f9f7	846
<>	144:ef7eb2e8f9f7	847	/* Check if first segment in frame */
<>	144:ef7eb2e8f9f7	848	/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
<>	144:ef7eb2e8f9f7	849	if((heth->RxDesc->Status & (ETH_DMARXDESC_FS \| ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
<>	144:ef7eb2e8f9f7	850	{
<>	144:ef7eb2e8f9f7	851	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
<>	144:ef7eb2e8f9f7	852	heth->RxFrameInfos.SegCount = 1U;
<>	144:ef7eb2e8f9f7	853	/* Point to next descriptor */
<>	144:ef7eb2e8f9f7	854	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	855	}
<>	144:ef7eb2e8f9f7	856	/* Check if intermediate segment */
<>	144:ef7eb2e8f9f7	857	/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
<>	144:ef7eb2e8f9f7	858	else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS \| ETH_DMARXDESC_FS)) == (uint32_t)RESET)
<>	144:ef7eb2e8f9f7	859	{
<>	144:ef7eb2e8f9f7	860	/* Increment segment count */
<>	144:ef7eb2e8f9f7	861	(heth->RxFrameInfos.SegCount)++;
<>	144:ef7eb2e8f9f7	862	/* Point to next descriptor */
<>	144:ef7eb2e8f9f7	863	heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	864	}
<>	144:ef7eb2e8f9f7	865	/* Should be last segment */
<>	144:ef7eb2e8f9f7	866	else
<>	144:ef7eb2e8f9f7	867	{
<>	144:ef7eb2e8f9f7	868	/* Last segment */
<>	144:ef7eb2e8f9f7	869	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	/* Increment segment count */
<>	144:ef7eb2e8f9f7	872	(heth->RxFrameInfos.SegCount)++;
<>	144:ef7eb2e8f9f7	873
<>	144:ef7eb2e8f9f7	874	/* Check if last segment is first segment: one segment contains the frame */
<>	144:ef7eb2e8f9f7	875	if ((heth->RxFrameInfos.SegCount) == 1U)
<>	144:ef7eb2e8f9f7	876	{
<>	144:ef7eb2e8f9f7	877	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
<>	144:ef7eb2e8f9f7	878	}
<>	144:ef7eb2e8f9f7	879
<>	144:ef7eb2e8f9f7	880	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
<>	144:ef7eb2e8f9f7	881	heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
<>	144:ef7eb2e8f9f7	882
<>	144:ef7eb2e8f9f7	883	/* Get the address of the buffer start address */
<>	144:ef7eb2e8f9f7	884	heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/* Point to next descriptor */
<>	144:ef7eb2e8f9f7	887	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
<>	144:ef7eb2e8f9f7	888
<>	144:ef7eb2e8f9f7	889	/* Set HAL State to Ready */
<>	144:ef7eb2e8f9f7	890	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	/* Return function status */
<>	144:ef7eb2e8f9f7	893	return HAL_OK;
<>	144:ef7eb2e8f9f7	894	}
<>	144:ef7eb2e8f9f7	895	}
<>	144:ef7eb2e8f9f7	896
<>	144:ef7eb2e8f9f7	897	/* Set HAL State to Ready */
<>	144:ef7eb2e8f9f7	898	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	899
<>	144:ef7eb2e8f9f7	900	/* Return function status */
<>	144:ef7eb2e8f9f7	901	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	902	}
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	/**
<>	144:ef7eb2e8f9f7	905	* @brief This function handles ETH interrupt request.
<>	144:ef7eb2e8f9f7	906	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	907	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	908	* @retval HAL status
<>	144:ef7eb2e8f9f7	909	*/
<>	144:ef7eb2e8f9f7	910	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	911	{
<>	144:ef7eb2e8f9f7	912	/* Frame received */
<>	144:ef7eb2e8f9f7	913	if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
<>	144:ef7eb2e8f9f7	914	{
<>	144:ef7eb2e8f9f7	915	/* Receive complete callback */
<>	144:ef7eb2e8f9f7	916	HAL_ETH_RxCpltCallback(heth);
<>	144:ef7eb2e8f9f7	917
<>	144:ef7eb2e8f9f7	918	/* Clear the Eth DMA Rx IT pending bits */
<>	144:ef7eb2e8f9f7	919	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
<>	144:ef7eb2e8f9f7	920
<>	144:ef7eb2e8f9f7	921	/* Set HAL State to Ready */
<>	144:ef7eb2e8f9f7	922	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	923
<>	144:ef7eb2e8f9f7	924	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	925	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	926
<>	144:ef7eb2e8f9f7	927	}
<>	144:ef7eb2e8f9f7	928	/* Frame transmitted */
<>	144:ef7eb2e8f9f7	929	else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
<>	144:ef7eb2e8f9f7	930	{
<>	144:ef7eb2e8f9f7	931	/* Transfer complete callback */
<>	144:ef7eb2e8f9f7	932	HAL_ETH_TxCpltCallback(heth);
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	/* Clear the Eth DMA Tx IT pending bits */
<>	144:ef7eb2e8f9f7	935	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
<>	144:ef7eb2e8f9f7	936
<>	144:ef7eb2e8f9f7	937	/* Set HAL State to Ready */
<>	144:ef7eb2e8f9f7	938	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	939
<>	144:ef7eb2e8f9f7	940	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	941	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	942	}
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Clear the interrupt flags */
<>	144:ef7eb2e8f9f7	945	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* ETH DMA Error */
<>	144:ef7eb2e8f9f7	948	if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
<>	144:ef7eb2e8f9f7	949	{
<>	144:ef7eb2e8f9f7	950	/* Ethernet Error callback */
<>	144:ef7eb2e8f9f7	951	HAL_ETH_ErrorCallback(heth);
<>	144:ef7eb2e8f9f7	952
<>	144:ef7eb2e8f9f7	953	/* Clear the interrupt flags */
<>	144:ef7eb2e8f9f7	954	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
<>	144:ef7eb2e8f9f7	955
<>	144:ef7eb2e8f9f7	956	/* Set HAL State to Ready */
<>	144:ef7eb2e8f9f7	957	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	958
<>	144:ef7eb2e8f9f7	959	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	960	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	961	}
<>	144:ef7eb2e8f9f7	962	}
<>	144:ef7eb2e8f9f7	963
<>	144:ef7eb2e8f9f7	964	/**
<>	144:ef7eb2e8f9f7	965	* @brief Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	966	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	967	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	968	* @retval None
<>	144:ef7eb2e8f9f7	969	*/
<>	144:ef7eb2e8f9f7	970	__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	971	{
<>	144:ef7eb2e8f9f7	972	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	973	UNUSED(heth);
<>	144:ef7eb2e8f9f7	974	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	975	the HAL_ETH_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	976	*/
<>	144:ef7eb2e8f9f7	977	}
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/**
<>	144:ef7eb2e8f9f7	980	* @brief Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	981	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	982	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	983	* @retval None
<>	144:ef7eb2e8f9f7	984	*/
<>	144:ef7eb2e8f9f7	985	__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	986	{
<>	144:ef7eb2e8f9f7	987	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	988	UNUSED(heth);
<>	144:ef7eb2e8f9f7	989	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	990	the HAL_ETH_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	991	*/
<>	144:ef7eb2e8f9f7	992	}
<>	144:ef7eb2e8f9f7	993
<>	144:ef7eb2e8f9f7	994	/**
<>	144:ef7eb2e8f9f7	995	* @brief Ethernet transfer error callbacks
<>	144:ef7eb2e8f9f7	996	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	997	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	998	* @retval None
<>	144:ef7eb2e8f9f7	999	*/
<>	144:ef7eb2e8f9f7	1000	__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1001	{
<>	144:ef7eb2e8f9f7	1002	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1003	UNUSED(heth);
<>	144:ef7eb2e8f9f7	1004	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1005	the HAL_ETH_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1006	*/
<>	144:ef7eb2e8f9f7	1007	}
<>	144:ef7eb2e8f9f7	1008
<>	144:ef7eb2e8f9f7	1009	/**
<>	144:ef7eb2e8f9f7	1010	* @brief Reads a PHY register
<>	144:ef7eb2e8f9f7	1011	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1012	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1013	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
<>	144:ef7eb2e8f9f7	1014	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1015	* PHY_BCR: Transceiver Basic Control Register,
<>	144:ef7eb2e8f9f7	1016	* PHY_BSR: Transceiver Basic Status Register.
<>	144:ef7eb2e8f9f7	1017	* More PHY register could be read depending on the used PHY
<>	144:ef7eb2e8f9f7	1018	* @param RegValue: PHY register value
<>	144:ef7eb2e8f9f7	1019	* @retval HAL status
<>	144:ef7eb2e8f9f7	1020	*/
<>	144:ef7eb2e8f9f7	1021	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue)
<>	144:ef7eb2e8f9f7	1022	{
<>	144:ef7eb2e8f9f7	1023	uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1024	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/* Check parameters */
<>	144:ef7eb2e8f9f7	1027	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/* Check the ETH peripheral state */
<>	144:ef7eb2e8f9f7	1030	if(heth->State == HAL_ETH_STATE_BUSY_RD)
<>	144:ef7eb2e8f9f7	1031	{
<>	144:ef7eb2e8f9f7	1032	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1033	}
<>	144:ef7eb2e8f9f7	1034	/* Set ETH HAL State to BUSY_RD */
<>	144:ef7eb2e8f9f7	1035	heth->State = HAL_ETH_STATE_BUSY_RD;
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/* Get the ETHERNET MACMIIAR value */
<>	144:ef7eb2e8f9f7	1038	tmpreg1 = heth->Instance->MACMIIAR;
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	/* Keep only the CSR Clock Range CR[2:0] bits value */
<>	144:ef7eb2e8f9f7	1041	tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
<>	144:ef7eb2e8f9f7	1042
<>	144:ef7eb2e8f9f7	1043	/* Prepare the MII address register value */
<>	144:ef7eb2e8f9f7	1044	tmpreg1 \|=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
<>	144:ef7eb2e8f9f7	1045	tmpreg1 \|=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
<>	144:ef7eb2e8f9f7	1046	tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
<>	144:ef7eb2e8f9f7	1047	tmpreg1 \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	/* Write the result value into the MII Address register */
<>	144:ef7eb2e8f9f7	1050	heth->Instance->MACMIIAR = tmpreg1;
<>	144:ef7eb2e8f9f7	1051
<>	144:ef7eb2e8f9f7	1052	/* Get tick */
<>	144:ef7eb2e8f9f7	1053	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	/* Check for the Busy flag */
<>	144:ef7eb2e8f9f7	1056	while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
<>	144:ef7eb2e8f9f7	1057	{
<>	144:ef7eb2e8f9f7	1058	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	1059	if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
<>	144:ef7eb2e8f9f7	1060	{
<>	144:ef7eb2e8f9f7	1061	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1062
<>	144:ef7eb2e8f9f7	1063	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1064	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1067	}
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	tmpreg1 = heth->Instance->MACMIIAR;
<>	144:ef7eb2e8f9f7	1070	}
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	/* Get MACMIIDR value */
<>	144:ef7eb2e8f9f7	1073	*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	/* Set ETH HAL State to READY */
<>	144:ef7eb2e8f9f7	1076	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	/* Return function status */
<>	144:ef7eb2e8f9f7	1079	return HAL_OK;
<>	144:ef7eb2e8f9f7	1080	}
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	/**
<>	144:ef7eb2e8f9f7	1083	* @brief Writes to a PHY register.
<>	144:ef7eb2e8f9f7	1084	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1085	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1086	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
<>	144:ef7eb2e8f9f7	1087	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1088	* PHY_BCR: Transceiver Control Register.
<>	144:ef7eb2e8f9f7	1089	* More PHY register could be written depending on the used PHY
<>	144:ef7eb2e8f9f7	1090	* @param RegValue: the value to write
<>	144:ef7eb2e8f9f7	1091	* @retval HAL status
<>	144:ef7eb2e8f9f7	1092	*/
<>	144:ef7eb2e8f9f7	1093	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
<>	144:ef7eb2e8f9f7	1094	{
<>	144:ef7eb2e8f9f7	1095	uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1096	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	/* Check parameters */
<>	144:ef7eb2e8f9f7	1099	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
<>	144:ef7eb2e8f9f7	1100
<>	144:ef7eb2e8f9f7	1101	/* Check the ETH peripheral state */
<>	144:ef7eb2e8f9f7	1102	if(heth->State == HAL_ETH_STATE_BUSY_WR)
<>	144:ef7eb2e8f9f7	1103	{
<>	144:ef7eb2e8f9f7	1104	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1105	}
<>	144:ef7eb2e8f9f7	1106	/* Set ETH HAL State to BUSY_WR */
<>	144:ef7eb2e8f9f7	1107	heth->State = HAL_ETH_STATE_BUSY_WR;
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	/* Get the ETHERNET MACMIIAR value */
<>	144:ef7eb2e8f9f7	1110	tmpreg1 = heth->Instance->MACMIIAR;
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/* Keep only the CSR Clock Range CR[2:0] bits value */
<>	144:ef7eb2e8f9f7	1113	tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
<>	144:ef7eb2e8f9f7	1114
<>	144:ef7eb2e8f9f7	1115	/* Prepare the MII register address value */
<>	144:ef7eb2e8f9f7	1116	tmpreg1 \|=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
<>	144:ef7eb2e8f9f7	1117	tmpreg1 \|=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
<>	144:ef7eb2e8f9f7	1118	tmpreg1 \|= ETH_MACMIIAR_MW; /* Set the write mode */
<>	144:ef7eb2e8f9f7	1119	tmpreg1 \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
<>	144:ef7eb2e8f9f7	1120
<>	144:ef7eb2e8f9f7	1121	/* Give the value to the MII data register */
<>	144:ef7eb2e8f9f7	1122	heth->Instance->MACMIIDR = (uint16_t)RegValue;
<>	144:ef7eb2e8f9f7	1123
<>	144:ef7eb2e8f9f7	1124	/* Write the result value into the MII Address register */
<>	144:ef7eb2e8f9f7	1125	heth->Instance->MACMIIAR = tmpreg1;
<>	144:ef7eb2e8f9f7	1126
<>	144:ef7eb2e8f9f7	1127	/* Get tick */
<>	144:ef7eb2e8f9f7	1128	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1129
<>	144:ef7eb2e8f9f7	1130	/* Check for the Busy flag */
<>	144:ef7eb2e8f9f7	1131	while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
<>	144:ef7eb2e8f9f7	1132	{
<>	144:ef7eb2e8f9f7	1133	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	1134	if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
<>	144:ef7eb2e8f9f7	1135	{
<>	144:ef7eb2e8f9f7	1136	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1137
<>	144:ef7eb2e8f9f7	1138	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1139	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	1140
<>	144:ef7eb2e8f9f7	1141	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1142	}
<>	144:ef7eb2e8f9f7	1143
<>	144:ef7eb2e8f9f7	1144	tmpreg1 = heth->Instance->MACMIIAR;
<>	144:ef7eb2e8f9f7	1145	}
<>	144:ef7eb2e8f9f7	1146
<>	144:ef7eb2e8f9f7	1147	/* Set ETH HAL State to READY */
<>	144:ef7eb2e8f9f7	1148	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	/* Return function status */
<>	144:ef7eb2e8f9f7	1151	return HAL_OK;
<>	144:ef7eb2e8f9f7	1152	}
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/**
<>	144:ef7eb2e8f9f7	1155	* @}
<>	144:ef7eb2e8f9f7	1156	*/
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1159	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	1160	*
<>	144:ef7eb2e8f9f7	1161	@verbatim
<>	144:ef7eb2e8f9f7	1162	===============================================================================
<>	144:ef7eb2e8f9f7	1163	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	1164	===============================================================================
<>	144:ef7eb2e8f9f7	1165	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1166	(+) Enable MAC and DMA transmission and reception.
<>	144:ef7eb2e8f9f7	1167	HAL_ETH_Start();
<>	144:ef7eb2e8f9f7	1168	(+) Disable MAC and DMA transmission and reception.
<>	144:ef7eb2e8f9f7	1169	HAL_ETH_Stop();
<>	144:ef7eb2e8f9f7	1170	(+) Set the MAC configuration in runtime mode
<>	144:ef7eb2e8f9f7	1171	HAL_ETH_ConfigMAC();
<>	144:ef7eb2e8f9f7	1172	(+) Set the DMA configuration in runtime mode
<>	144:ef7eb2e8f9f7	1173	HAL_ETH_ConfigDMA();
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	@endverbatim
<>	144:ef7eb2e8f9f7	1176	* @{
<>	144:ef7eb2e8f9f7	1177	*/
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/**
<>	144:ef7eb2e8f9f7	1180	* @brief Enables Ethernet MAC and DMA reception/transmission
<>	144:ef7eb2e8f9f7	1181	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1182	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1183	* @retval HAL status
<>	144:ef7eb2e8f9f7	1184	*/
<>	144:ef7eb2e8f9f7	1185	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1186	{
<>	144:ef7eb2e8f9f7	1187	/* Process Locked */
<>	144:ef7eb2e8f9f7	1188	__HAL_LOCK(heth);
<>	144:ef7eb2e8f9f7	1189
<>	144:ef7eb2e8f9f7	1190	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	1191	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193	/* Enable transmit state machine of the MAC for transmission on the MII */
<>	144:ef7eb2e8f9f7	1194	ETH_MACTransmissionEnable(heth);
<>	144:ef7eb2e8f9f7	1195
<>	144:ef7eb2e8f9f7	1196	/* Enable receive state machine of the MAC for reception from the MII */
<>	144:ef7eb2e8f9f7	1197	ETH_MACReceptionEnable(heth);
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	/* Flush Transmit FIFO */
<>	144:ef7eb2e8f9f7	1200	ETH_FlushTransmitFIFO(heth);
<>	144:ef7eb2e8f9f7	1201
<>	144:ef7eb2e8f9f7	1202	/* Start DMA transmission */
<>	144:ef7eb2e8f9f7	1203	ETH_DMATransmissionEnable(heth);
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/* Start DMA reception */
<>	144:ef7eb2e8f9f7	1206	ETH_DMAReceptionEnable(heth);
<>	144:ef7eb2e8f9f7	1207
<>	144:ef7eb2e8f9f7	1208	/* Set the ETH state to READY*/
<>	144:ef7eb2e8f9f7	1209	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1212	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	1213
<>	144:ef7eb2e8f9f7	1214	/* Return function status */
<>	144:ef7eb2e8f9f7	1215	return HAL_OK;
<>	144:ef7eb2e8f9f7	1216	}
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/**
<>	144:ef7eb2e8f9f7	1219	* @brief Stop Ethernet MAC and DMA reception/transmission
<>	144:ef7eb2e8f9f7	1220	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1221	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1222	* @retval HAL status
<>	144:ef7eb2e8f9f7	1223	*/
<>	144:ef7eb2e8f9f7	1224	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1225	{
<>	144:ef7eb2e8f9f7	1226	/* Process Locked */
<>	144:ef7eb2e8f9f7	1227	__HAL_LOCK(heth);
<>	144:ef7eb2e8f9f7	1228
<>	144:ef7eb2e8f9f7	1229	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	1230	heth->State = HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1231
<>	144:ef7eb2e8f9f7	1232	/* Stop DMA transmission */
<>	144:ef7eb2e8f9f7	1233	ETH_DMATransmissionDisable(heth);
<>	144:ef7eb2e8f9f7	1234
<>	144:ef7eb2e8f9f7	1235	/* Stop DMA reception */
<>	144:ef7eb2e8f9f7	1236	ETH_DMAReceptionDisable(heth);
<>	144:ef7eb2e8f9f7	1237
<>	144:ef7eb2e8f9f7	1238	/* Disable receive state machine of the MAC for reception from the MII */
<>	144:ef7eb2e8f9f7	1239	ETH_MACReceptionDisable(heth);
<>	144:ef7eb2e8f9f7	1240
<>	144:ef7eb2e8f9f7	1241	/* Flush Transmit FIFO */
<>	144:ef7eb2e8f9f7	1242	ETH_FlushTransmitFIFO(heth);
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	/* Disable transmit state machine of the MAC for transmission on the MII */
<>	144:ef7eb2e8f9f7	1245	ETH_MACTransmissionDisable(heth);
<>	144:ef7eb2e8f9f7	1246
<>	144:ef7eb2e8f9f7	1247	/* Set the ETH state*/
<>	144:ef7eb2e8f9f7	1248	heth->State = HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1249
<>	144:ef7eb2e8f9f7	1250	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1251	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/* Return function status */
<>	144:ef7eb2e8f9f7	1254	return HAL_OK;
<>	144:ef7eb2e8f9f7	1255	}
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257	/**
<>	144:ef7eb2e8f9f7	1258	* @brief Set ETH MAC Configuration.
<>	144:ef7eb2e8f9f7	1259	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1260	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1261	* @param macconf: MAC Configuration structure
<>	144:ef7eb2e8f9f7	1262	* @retval HAL status
<>	144:ef7eb2e8f9f7	1263	*/
<>	144:ef7eb2e8f9f7	1264	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf)
<>	144:ef7eb2e8f9f7	1265	{
<>	144:ef7eb2e8f9f7	1266	uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1267
<>	144:ef7eb2e8f9f7	1268	/* Process Locked */
<>	144:ef7eb2e8f9f7	1269	__HAL_LOCK(heth);
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	1272	heth->State= HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	assert_param(IS_ETH_SPEED(heth->Init.Speed));
<>	144:ef7eb2e8f9f7	1275	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277	if (macconf != NULL)
<>	144:ef7eb2e8f9f7	1278	{
<>	144:ef7eb2e8f9f7	1279	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1280	assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
<>	144:ef7eb2e8f9f7	1281	assert_param(IS_ETH_JABBER(macconf->Jabber));
<>	144:ef7eb2e8f9f7	1282	assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
<>	144:ef7eb2e8f9f7	1283	assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
<>	144:ef7eb2e8f9f7	1284	assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
<>	144:ef7eb2e8f9f7	1285	assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
<>	144:ef7eb2e8f9f7	1286	assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
<>	144:ef7eb2e8f9f7	1287	assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
<>	144:ef7eb2e8f9f7	1288	assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
<>	144:ef7eb2e8f9f7	1289	assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
<>	144:ef7eb2e8f9f7	1290	assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
<>	144:ef7eb2e8f9f7	1291	assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
<>	144:ef7eb2e8f9f7	1292	assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
<>	144:ef7eb2e8f9f7	1293	assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
<>	144:ef7eb2e8f9f7	1294	assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
<>	144:ef7eb2e8f9f7	1295	assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
<>	144:ef7eb2e8f9f7	1296	assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
<>	144:ef7eb2e8f9f7	1297	assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
<>	144:ef7eb2e8f9f7	1298	assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
<>	144:ef7eb2e8f9f7	1299	assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
<>	144:ef7eb2e8f9f7	1300	assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
<>	144:ef7eb2e8f9f7	1301	assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
<>	144:ef7eb2e8f9f7	1302	assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
<>	144:ef7eb2e8f9f7	1303	assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
<>	144:ef7eb2e8f9f7	1304	assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
<>	144:ef7eb2e8f9f7	1305	assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
<>	144:ef7eb2e8f9f7	1306	assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	/------------------------ ETHERNET MACCR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1309	/* Get the ETHERNET MACCR value */
<>	144:ef7eb2e8f9f7	1310	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1311	/* Clear WD, PCE, PS, TE and RE bits */
<>	144:ef7eb2e8f9f7	1312	tmpreg1 &= ETH_MACCR_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	1313
<>	144:ef7eb2e8f9f7	1314	tmpreg1 \|= (uint32_t)(macconf->Watchdog \|
<>	144:ef7eb2e8f9f7	1315	macconf->Jabber \|
<>	144:ef7eb2e8f9f7	1316	macconf->InterFrameGap \|
<>	144:ef7eb2e8f9f7	1317	macconf->CarrierSense \|
<>	144:ef7eb2e8f9f7	1318	(heth->Init).Speed \|
<>	144:ef7eb2e8f9f7	1319	macconf->ReceiveOwn \|
<>	144:ef7eb2e8f9f7	1320	macconf->LoopbackMode \|
<>	144:ef7eb2e8f9f7	1321	(heth->Init).DuplexMode \|
<>	144:ef7eb2e8f9f7	1322	macconf->ChecksumOffload \|
<>	144:ef7eb2e8f9f7	1323	macconf->RetryTransmission \|
<>	144:ef7eb2e8f9f7	1324	macconf->AutomaticPadCRCStrip \|
<>	144:ef7eb2e8f9f7	1325	macconf->BackOffLimit \|
<>	144:ef7eb2e8f9f7	1326	macconf->DeferralCheck);
<>	144:ef7eb2e8f9f7	1327
<>	144:ef7eb2e8f9f7	1328	/* Write to ETHERNET MACCR */
<>	144:ef7eb2e8f9f7	1329	(heth->Instance)->MACCR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	/* Wait until the write operation will be taken into account :
<>	144:ef7eb2e8f9f7	1332	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1333	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1334	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1335	(heth->Instance)->MACCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	/----------------------- ETHERNET MACFFR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1338	/* Write to ETHERNET MACFFR */
<>	144:ef7eb2e8f9f7	1339	(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll \|
<>	144:ef7eb2e8f9f7	1340	macconf->SourceAddrFilter \|
<>	144:ef7eb2e8f9f7	1341	macconf->PassControlFrames \|
<>	144:ef7eb2e8f9f7	1342	macconf->BroadcastFramesReception \|
<>	144:ef7eb2e8f9f7	1343	macconf->DestinationAddrFilter \|
<>	144:ef7eb2e8f9f7	1344	macconf->PromiscuousMode \|
<>	144:ef7eb2e8f9f7	1345	macconf->MulticastFramesFilter \|
<>	144:ef7eb2e8f9f7	1346	macconf->UnicastFramesFilter);
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Wait until the write operation will be taken into account :
<>	144:ef7eb2e8f9f7	1349	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1350	tmpreg1 = (heth->Instance)->MACFFR;
<>	144:ef7eb2e8f9f7	1351	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1352	(heth->Instance)->MACFFR = tmpreg1;
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	/--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------/
<>	144:ef7eb2e8f9f7	1355	/* Write to ETHERNET MACHTHR */
<>	144:ef7eb2e8f9f7	1356	(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
<>	144:ef7eb2e8f9f7	1357
<>	144:ef7eb2e8f9f7	1358	/* Write to ETHERNET MACHTLR */
<>	144:ef7eb2e8f9f7	1359	(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
<>	144:ef7eb2e8f9f7	1360	/----------------------- ETHERNET MACFCR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1361
<>	144:ef7eb2e8f9f7	1362	/* Get the ETHERNET MACFCR value */
<>	144:ef7eb2e8f9f7	1363	tmpreg1 = (heth->Instance)->MACFCR;
<>	144:ef7eb2e8f9f7	1364	/* Clear xx bits */
<>	144:ef7eb2e8f9f7	1365	tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	tmpreg1 \|= (uint32_t)((macconf->PauseTime << 16U) \|
<>	144:ef7eb2e8f9f7	1368	macconf->ZeroQuantaPause \|
<>	144:ef7eb2e8f9f7	1369	macconf->PauseLowThreshold \|
<>	144:ef7eb2e8f9f7	1370	macconf->UnicastPauseFrameDetect \|
<>	144:ef7eb2e8f9f7	1371	macconf->ReceiveFlowControl \|
<>	144:ef7eb2e8f9f7	1372	macconf->TransmitFlowControl);
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374	/* Write to ETHERNET MACFCR */
<>	144:ef7eb2e8f9f7	1375	(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/* Wait until the write operation will be taken into account :
<>	144:ef7eb2e8f9f7	1378	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1379	tmpreg1 = (heth->Instance)->MACFCR;
<>	144:ef7eb2e8f9f7	1380	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1381	(heth->Instance)->MACFCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1382
<>	144:ef7eb2e8f9f7	1383	/----------------------- ETHERNET MACVLANTR Configuration -----------------/
<>	144:ef7eb2e8f9f7	1384	(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison \|
<>	144:ef7eb2e8f9f7	1385	macconf->VLANTagIdentifier);
<>	144:ef7eb2e8f9f7	1386
<>	144:ef7eb2e8f9f7	1387	/* Wait until the write operation will be taken into account :
<>	144:ef7eb2e8f9f7	1388	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1389	tmpreg1 = (heth->Instance)->MACVLANTR;
<>	144:ef7eb2e8f9f7	1390	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1391	(heth->Instance)->MACVLANTR = tmpreg1;
<>	144:ef7eb2e8f9f7	1392	}
<>	144:ef7eb2e8f9f7	1393	else /* macconf == NULL : here we just configure Speed and Duplex mode */
<>	144:ef7eb2e8f9f7	1394	{
<>	144:ef7eb2e8f9f7	1395	/------------------------ ETHERNET MACCR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1396	/* Get the ETHERNET MACCR value */
<>	144:ef7eb2e8f9f7	1397	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399	/* Clear FES and DM bits */
AnnaBridge	167:e84263d55307	1400	tmpreg1 &= ~(0x00004800U);
<>	144:ef7eb2e8f9f7	1401
<>	144:ef7eb2e8f9f7	1402	tmpreg1 \|= (uint32_t)(heth->Init.Speed \| heth->Init.DuplexMode);
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/* Write to ETHERNET MACCR */
<>	144:ef7eb2e8f9f7	1405	(heth->Instance)->MACCR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1408	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1409	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1410	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1411	(heth->Instance)->MACCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1412	}
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	/* Set the ETH state to Ready */
<>	144:ef7eb2e8f9f7	1415	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1418	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	1419
<>	144:ef7eb2e8f9f7	1420	/* Return function status */
<>	144:ef7eb2e8f9f7	1421	return HAL_OK;
<>	144:ef7eb2e8f9f7	1422	}
<>	144:ef7eb2e8f9f7	1423
<>	144:ef7eb2e8f9f7	1424	/**
<>	144:ef7eb2e8f9f7	1425	* @brief Sets ETH DMA Configuration.
<>	144:ef7eb2e8f9f7	1426	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1427	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1428	* @param dmaconf: DMA Configuration structure
<>	144:ef7eb2e8f9f7	1429	* @retval HAL status
<>	144:ef7eb2e8f9f7	1430	*/
<>	144:ef7eb2e8f9f7	1431	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf)
<>	144:ef7eb2e8f9f7	1432	{
<>	144:ef7eb2e8f9f7	1433	uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/* Process Locked */
<>	144:ef7eb2e8f9f7	1436	__HAL_LOCK(heth);
<>	144:ef7eb2e8f9f7	1437
<>	144:ef7eb2e8f9f7	1438	/* Set the ETH peripheral state to BUSY */
<>	144:ef7eb2e8f9f7	1439	heth->State= HAL_ETH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	/* Check parameters */
<>	144:ef7eb2e8f9f7	1442	assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
<>	144:ef7eb2e8f9f7	1443	assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
<>	144:ef7eb2e8f9f7	1444	assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
<>	144:ef7eb2e8f9f7	1445	assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
<>	144:ef7eb2e8f9f7	1446	assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
<>	144:ef7eb2e8f9f7	1447	assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
<>	144:ef7eb2e8f9f7	1448	assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
<>	144:ef7eb2e8f9f7	1449	assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
<>	144:ef7eb2e8f9f7	1450	assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
<>	144:ef7eb2e8f9f7	1451	assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
<>	144:ef7eb2e8f9f7	1452	assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
<>	144:ef7eb2e8f9f7	1453	assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
<>	144:ef7eb2e8f9f7	1454	assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
<>	144:ef7eb2e8f9f7	1455	assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
<>	144:ef7eb2e8f9f7	1456	assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
<>	144:ef7eb2e8f9f7	1457	assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	/----------------------- ETHERNET DMAOMR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1460	/* Get the ETHERNET DMAOMR value */
<>	144:ef7eb2e8f9f7	1461	tmpreg1 = (heth->Instance)->DMAOMR;
<>	144:ef7eb2e8f9f7	1462	/* Clear xx bits */
<>	144:ef7eb2e8f9f7	1463	tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	1464
<>	144:ef7eb2e8f9f7	1465	tmpreg1 \|= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame \|
<>	144:ef7eb2e8f9f7	1466	dmaconf->ReceiveStoreForward \|
<>	144:ef7eb2e8f9f7	1467	dmaconf->FlushReceivedFrame \|
<>	144:ef7eb2e8f9f7	1468	dmaconf->TransmitStoreForward \|
<>	144:ef7eb2e8f9f7	1469	dmaconf->TransmitThresholdControl \|
<>	144:ef7eb2e8f9f7	1470	dmaconf->ForwardErrorFrames \|
<>	144:ef7eb2e8f9f7	1471	dmaconf->ForwardUndersizedGoodFrames \|
<>	144:ef7eb2e8f9f7	1472	dmaconf->ReceiveThresholdControl \|
<>	144:ef7eb2e8f9f7	1473	dmaconf->SecondFrameOperate);
<>	144:ef7eb2e8f9f7	1474
<>	144:ef7eb2e8f9f7	1475	/* Write to ETHERNET DMAOMR */
<>	144:ef7eb2e8f9f7	1476	(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1479	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1480	tmpreg1 = (heth->Instance)->DMAOMR;
<>	144:ef7eb2e8f9f7	1481	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1482	(heth->Instance)->DMAOMR = tmpreg1;
<>	144:ef7eb2e8f9f7	1483
<>	144:ef7eb2e8f9f7	1484	/----------------------- ETHERNET DMABMR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1485	(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats \|
<>	144:ef7eb2e8f9f7	1486	dmaconf->FixedBurst \|
<>	144:ef7eb2e8f9f7	1487	dmaconf->RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
<>	144:ef7eb2e8f9f7	1488	dmaconf->TxDMABurstLength \|
<>	144:ef7eb2e8f9f7	1489	dmaconf->EnhancedDescriptorFormat \|
<>	144:ef7eb2e8f9f7	1490	(dmaconf->DescriptorSkipLength << 2U) \|
<>	144:ef7eb2e8f9f7	1491	dmaconf->DMAArbitration \|
<>	144:ef7eb2e8f9f7	1492	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
<>	144:ef7eb2e8f9f7	1493
<>	144:ef7eb2e8f9f7	1494	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1495	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1496	tmpreg1 = (heth->Instance)->DMABMR;
<>	144:ef7eb2e8f9f7	1497	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1498	(heth->Instance)->DMABMR = tmpreg1;
<>	144:ef7eb2e8f9f7	1499
<>	144:ef7eb2e8f9f7	1500	/* Set the ETH state to Ready */
<>	144:ef7eb2e8f9f7	1501	heth->State= HAL_ETH_STATE_READY;
<>	144:ef7eb2e8f9f7	1502
<>	144:ef7eb2e8f9f7	1503	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1504	__HAL_UNLOCK(heth);
<>	144:ef7eb2e8f9f7	1505
<>	144:ef7eb2e8f9f7	1506	/* Return function status */
<>	144:ef7eb2e8f9f7	1507	return HAL_OK;
<>	144:ef7eb2e8f9f7	1508	}
<>	144:ef7eb2e8f9f7	1509
<>	144:ef7eb2e8f9f7	1510	/**
<>	144:ef7eb2e8f9f7	1511	* @}
<>	144:ef7eb2e8f9f7	1512	*/
<>	144:ef7eb2e8f9f7	1513
<>	144:ef7eb2e8f9f7	1514	/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
<>	144:ef7eb2e8f9f7	1515	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	1516	*
<>	144:ef7eb2e8f9f7	1517	@verbatim
<>	144:ef7eb2e8f9f7	1518	===============================================================================
<>	144:ef7eb2e8f9f7	1519	##### Peripheral State functions #####
<>	144:ef7eb2e8f9f7	1520	===============================================================================
<>	144:ef7eb2e8f9f7	1521	[..]
<>	144:ef7eb2e8f9f7	1522	This subsection permits to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	1523	and the data flow.
<>	144:ef7eb2e8f9f7	1524	(+) Get the ETH handle state:
<>	144:ef7eb2e8f9f7	1525	HAL_ETH_GetState();
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	@endverbatim
<>	144:ef7eb2e8f9f7	1529	* @{
<>	144:ef7eb2e8f9f7	1530	*/
<>	144:ef7eb2e8f9f7	1531
<>	144:ef7eb2e8f9f7	1532	/**
<>	144:ef7eb2e8f9f7	1533	* @brief Return the ETH HAL state
<>	144:ef7eb2e8f9f7	1534	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1535	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1536	* @retval HAL state
<>	144:ef7eb2e8f9f7	1537	*/
<>	144:ef7eb2e8f9f7	1538	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1539	{
<>	144:ef7eb2e8f9f7	1540	/* Return ETH state */
<>	144:ef7eb2e8f9f7	1541	return heth->State;
<>	144:ef7eb2e8f9f7	1542	}
<>	144:ef7eb2e8f9f7	1543
<>	144:ef7eb2e8f9f7	1544	/**
<>	144:ef7eb2e8f9f7	1545	* @}
<>	144:ef7eb2e8f9f7	1546	*/
<>	144:ef7eb2e8f9f7	1547
<>	144:ef7eb2e8f9f7	1548	/**
<>	144:ef7eb2e8f9f7	1549	* @}
<>	144:ef7eb2e8f9f7	1550	*/
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	/** @addtogroup ETH_Private_Functions
<>	144:ef7eb2e8f9f7	1553	* @{
<>	144:ef7eb2e8f9f7	1554	*/
<>	144:ef7eb2e8f9f7	1555
<>	144:ef7eb2e8f9f7	1556	/**
<>	144:ef7eb2e8f9f7	1557	* @brief Configures Ethernet MAC and DMA with default parameters.
<>	144:ef7eb2e8f9f7	1558	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1559	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1560	* @param err: Ethernet Init error
<>	144:ef7eb2e8f9f7	1561	* @retval HAL status
<>	144:ef7eb2e8f9f7	1562	*/
<>	144:ef7eb2e8f9f7	1563	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
<>	144:ef7eb2e8f9f7	1564	{
<>	144:ef7eb2e8f9f7	1565	ETH_MACInitTypeDef macinit;
<>	144:ef7eb2e8f9f7	1566	ETH_DMAInitTypeDef dmainit;
<>	144:ef7eb2e8f9f7	1567	uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1568
<>	144:ef7eb2e8f9f7	1569	if (err != ETH_SUCCESS) /* Auto-negotiation failed */
<>	144:ef7eb2e8f9f7	1570	{
<>	144:ef7eb2e8f9f7	1571	/* Set Ethernet duplex mode to Full-duplex */
<>	144:ef7eb2e8f9f7	1572	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
<>	144:ef7eb2e8f9f7	1573
<>	144:ef7eb2e8f9f7	1574	/* Set Ethernet speed to 100M */
<>	144:ef7eb2e8f9f7	1575	(heth->Init).Speed = ETH_SPEED_100M;
<>	144:ef7eb2e8f9f7	1576	}
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	/* Ethernet MAC default initialization **************************************/
<>	144:ef7eb2e8f9f7	1579	macinit.Watchdog = ETH_WATCHDOG_ENABLE;
<>	144:ef7eb2e8f9f7	1580	macinit.Jabber = ETH_JABBER_ENABLE;
<>	144:ef7eb2e8f9f7	1581	macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
<>	144:ef7eb2e8f9f7	1582	macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
<>	144:ef7eb2e8f9f7	1583	macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
<>	144:ef7eb2e8f9f7	1584	macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
<>	144:ef7eb2e8f9f7	1585	if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
<>	144:ef7eb2e8f9f7	1586	{
<>	144:ef7eb2e8f9f7	1587	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
<>	144:ef7eb2e8f9f7	1588	}
<>	144:ef7eb2e8f9f7	1589	else
<>	144:ef7eb2e8f9f7	1590	{
<>	144:ef7eb2e8f9f7	1591	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
<>	144:ef7eb2e8f9f7	1592	}
<>	144:ef7eb2e8f9f7	1593	macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
<>	144:ef7eb2e8f9f7	1594	macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
<>	144:ef7eb2e8f9f7	1595	macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
<>	144:ef7eb2e8f9f7	1596	macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
<>	144:ef7eb2e8f9f7	1597	macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
<>	144:ef7eb2e8f9f7	1598	macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
<>	144:ef7eb2e8f9f7	1599	macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
<>	144:ef7eb2e8f9f7	1600	macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
<>	144:ef7eb2e8f9f7	1601	macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
<>	144:ef7eb2e8f9f7	1602	macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
<>	144:ef7eb2e8f9f7	1603	macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
<>	144:ef7eb2e8f9f7	1604	macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
<>	144:ef7eb2e8f9f7	1605	macinit.HashTableHigh = 0x0U;
<>	144:ef7eb2e8f9f7	1606	macinit.HashTableLow = 0x0U;
<>	144:ef7eb2e8f9f7	1607	macinit.PauseTime = 0x0U;
<>	144:ef7eb2e8f9f7	1608	macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
<>	144:ef7eb2e8f9f7	1609	macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
<>	144:ef7eb2e8f9f7	1610	macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
<>	144:ef7eb2e8f9f7	1611	macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
<>	144:ef7eb2e8f9f7	1612	macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
<>	144:ef7eb2e8f9f7	1613	macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
<>	144:ef7eb2e8f9f7	1614	macinit.VLANTagIdentifier = 0x0U;
<>	144:ef7eb2e8f9f7	1615
<>	144:ef7eb2e8f9f7	1616	/------------------------ ETHERNET MACCR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1617	/* Get the ETHERNET MACCR value */
<>	144:ef7eb2e8f9f7	1618	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1619	/* Clear WD, PCE, PS, TE and RE bits */
<>	144:ef7eb2e8f9f7	1620	tmpreg1 &= ETH_MACCR_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	1621	/* Set the WD bit according to ETH Watchdog value */
<>	144:ef7eb2e8f9f7	1622	/* Set the JD: bit according to ETH Jabber value */
<>	144:ef7eb2e8f9f7	1623	/* Set the IFG bit according to ETH InterFrameGap value */
<>	144:ef7eb2e8f9f7	1624	/* Set the DCRS bit according to ETH CarrierSense value */
<>	144:ef7eb2e8f9f7	1625	/* Set the FES bit according to ETH Speed value */
<>	144:ef7eb2e8f9f7	1626	/* Set the DO bit according to ETH ReceiveOwn value */
<>	144:ef7eb2e8f9f7	1627	/* Set the LM bit according to ETH LoopbackMode value */
<>	144:ef7eb2e8f9f7	1628	/* Set the DM bit according to ETH Mode value */
<>	144:ef7eb2e8f9f7	1629	/* Set the IPCO bit according to ETH ChecksumOffload value */
<>	144:ef7eb2e8f9f7	1630	/* Set the DR bit according to ETH RetryTransmission value */
<>	144:ef7eb2e8f9f7	1631	/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
<>	144:ef7eb2e8f9f7	1632	/* Set the BL bit according to ETH BackOffLimit value */
<>	144:ef7eb2e8f9f7	1633	/* Set the DC bit according to ETH DeferralCheck value */
<>	144:ef7eb2e8f9f7	1634	tmpreg1 \|= (uint32_t)(macinit.Watchdog \|
<>	144:ef7eb2e8f9f7	1635	macinit.Jabber \|
<>	144:ef7eb2e8f9f7	1636	macinit.InterFrameGap \|
<>	144:ef7eb2e8f9f7	1637	macinit.CarrierSense \|
<>	144:ef7eb2e8f9f7	1638	(heth->Init).Speed \|
<>	144:ef7eb2e8f9f7	1639	macinit.ReceiveOwn \|
<>	144:ef7eb2e8f9f7	1640	macinit.LoopbackMode \|
<>	144:ef7eb2e8f9f7	1641	(heth->Init).DuplexMode \|
<>	144:ef7eb2e8f9f7	1642	macinit.ChecksumOffload \|
<>	144:ef7eb2e8f9f7	1643	macinit.RetryTransmission \|
<>	144:ef7eb2e8f9f7	1644	macinit.AutomaticPadCRCStrip \|
<>	144:ef7eb2e8f9f7	1645	macinit.BackOffLimit \|
<>	144:ef7eb2e8f9f7	1646	macinit.DeferralCheck);
<>	144:ef7eb2e8f9f7	1647
<>	144:ef7eb2e8f9f7	1648	/* Write to ETHERNET MACCR */
<>	144:ef7eb2e8f9f7	1649	(heth->Instance)->MACCR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	1650
<>	144:ef7eb2e8f9f7	1651	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1652	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1653	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1654	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1655	(heth->Instance)->MACCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1656
<>	144:ef7eb2e8f9f7	1657	/----------------------- ETHERNET MACFFR Configuration --------------------/
<>	144:ef7eb2e8f9f7	1658	/* Set the RA bit according to ETH ReceiveAll value */
<>	144:ef7eb2e8f9f7	1659	/* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
<>	144:ef7eb2e8f9f7	1660	/* Set the PCF bit according to ETH PassControlFrames value */
<>	144:ef7eb2e8f9f7	1661	/* Set the DBF bit according to ETH BroadcastFramesReception value */
<>	144:ef7eb2e8f9f7	1662	/* Set the DAIF bit according to ETH DestinationAddrFilter value */
<>	144:ef7eb2e8f9f7	1663	/* Set the PR bit according to ETH PromiscuousMode value */
<>	144:ef7eb2e8f9f7	1664	/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
<>	144:ef7eb2e8f9f7	1665	/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
<>	144:ef7eb2e8f9f7	1666	/* Write to ETHERNET MACFFR */
<>	144:ef7eb2e8f9f7	1667	(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll \|
<>	144:ef7eb2e8f9f7	1668	macinit.SourceAddrFilter \|
<>	144:ef7eb2e8f9f7	1669	macinit.PassControlFrames \|
<>	144:ef7eb2e8f9f7	1670	macinit.BroadcastFramesReception \|
<>	144:ef7eb2e8f9f7	1671	macinit.DestinationAddrFilter \|
<>	144:ef7eb2e8f9f7	1672	macinit.PromiscuousMode \|
<>	144:ef7eb2e8f9f7	1673	macinit.MulticastFramesFilter \|
<>	144:ef7eb2e8f9f7	1674	macinit.UnicastFramesFilter);
<>	144:ef7eb2e8f9f7	1675
<>	144:ef7eb2e8f9f7	1676	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1677	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1678	tmpreg1 = (heth->Instance)->MACFFR;
<>	144:ef7eb2e8f9f7	1679	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1680	(heth->Instance)->MACFFR = tmpreg1;
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------/
<>	144:ef7eb2e8f9f7	1683	/* Write to ETHERNET MACHTHR */
<>	144:ef7eb2e8f9f7	1684	(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	/* Write to ETHERNET MACHTLR */
<>	144:ef7eb2e8f9f7	1687	(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
<>	144:ef7eb2e8f9f7	1688	/----------------------- ETHERNET MACFCR Configuration -------------------/
<>	144:ef7eb2e8f9f7	1689
<>	144:ef7eb2e8f9f7	1690	/* Get the ETHERNET MACFCR value */
<>	144:ef7eb2e8f9f7	1691	tmpreg1 = (heth->Instance)->MACFCR;
<>	144:ef7eb2e8f9f7	1692	/* Clear xx bits */
<>	144:ef7eb2e8f9f7	1693	tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/* Set the PT bit according to ETH PauseTime value */
<>	144:ef7eb2e8f9f7	1696	/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
<>	144:ef7eb2e8f9f7	1697	/* Set the PLT bit according to ETH PauseLowThreshold value */
<>	144:ef7eb2e8f9f7	1698	/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
<>	144:ef7eb2e8f9f7	1699	/* Set the RFE bit according to ETH ReceiveFlowControl value */
<>	144:ef7eb2e8f9f7	1700	/* Set the TFE bit according to ETH TransmitFlowControl value */
<>	144:ef7eb2e8f9f7	1701	tmpreg1 \|= (uint32_t)((macinit.PauseTime << 16U) \|
<>	144:ef7eb2e8f9f7	1702	macinit.ZeroQuantaPause \|
<>	144:ef7eb2e8f9f7	1703	macinit.PauseLowThreshold \|
<>	144:ef7eb2e8f9f7	1704	macinit.UnicastPauseFrameDetect \|
<>	144:ef7eb2e8f9f7	1705	macinit.ReceiveFlowControl \|
<>	144:ef7eb2e8f9f7	1706	macinit.TransmitFlowControl);
<>	144:ef7eb2e8f9f7	1707
<>	144:ef7eb2e8f9f7	1708	/* Write to ETHERNET MACFCR */
<>	144:ef7eb2e8f9f7	1709	(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	1710
<>	144:ef7eb2e8f9f7	1711	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1712	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1713	tmpreg1 = (heth->Instance)->MACFCR;
<>	144:ef7eb2e8f9f7	1714	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1715	(heth->Instance)->MACFCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	/----------------------- ETHERNET MACVLANTR Configuration ----------------/
<>	144:ef7eb2e8f9f7	1718	/* Set the ETV bit according to ETH VLANTagComparison value */
<>	144:ef7eb2e8f9f7	1719	/* Set the VL bit according to ETH VLANTagIdentifier value */
<>	144:ef7eb2e8f9f7	1720	(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison \|
<>	144:ef7eb2e8f9f7	1721	macinit.VLANTagIdentifier);
<>	144:ef7eb2e8f9f7	1722
<>	144:ef7eb2e8f9f7	1723	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1724	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1725	tmpreg1 = (heth->Instance)->MACVLANTR;
<>	144:ef7eb2e8f9f7	1726	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1727	(heth->Instance)->MACVLANTR = tmpreg1;
<>	144:ef7eb2e8f9f7	1728
<>	144:ef7eb2e8f9f7	1729	/* Ethernet DMA default initialization ************************************/
<>	144:ef7eb2e8f9f7	1730	dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
<>	144:ef7eb2e8f9f7	1731	dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
<>	144:ef7eb2e8f9f7	1732	dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
<>	144:ef7eb2e8f9f7	1733	dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
<>	144:ef7eb2e8f9f7	1734	dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
<>	144:ef7eb2e8f9f7	1735	dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
<>	144:ef7eb2e8f9f7	1736	dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
<>	144:ef7eb2e8f9f7	1737	dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
<>	144:ef7eb2e8f9f7	1738	dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
<>	144:ef7eb2e8f9f7	1739	dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
<>	144:ef7eb2e8f9f7	1740	dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
<>	144:ef7eb2e8f9f7	1741	dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
<>	144:ef7eb2e8f9f7	1742	dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
<>	144:ef7eb2e8f9f7	1743	dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
<>	144:ef7eb2e8f9f7	1744	dmainit.DescriptorSkipLength = 0x0U;
<>	144:ef7eb2e8f9f7	1745	dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
<>	144:ef7eb2e8f9f7	1746
<>	144:ef7eb2e8f9f7	1747	/* Get the ETHERNET DMAOMR value */
<>	144:ef7eb2e8f9f7	1748	tmpreg1 = (heth->Instance)->DMAOMR;
<>	144:ef7eb2e8f9f7	1749	/* Clear xx bits */
<>	144:ef7eb2e8f9f7	1750	tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	1751
<>	144:ef7eb2e8f9f7	1752	/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
<>	144:ef7eb2e8f9f7	1753	/* Set the RSF bit according to ETH ReceiveStoreForward value */
<>	144:ef7eb2e8f9f7	1754	/* Set the DFF bit according to ETH FlushReceivedFrame value */
<>	144:ef7eb2e8f9f7	1755	/* Set the TSF bit according to ETH TransmitStoreForward value */
<>	144:ef7eb2e8f9f7	1756	/* Set the TTC bit according to ETH TransmitThresholdControl value */
<>	144:ef7eb2e8f9f7	1757	/* Set the FEF bit according to ETH ForwardErrorFrames value */
<>	144:ef7eb2e8f9f7	1758	/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
<>	144:ef7eb2e8f9f7	1759	/* Set the RTC bit according to ETH ReceiveThresholdControl value */
<>	144:ef7eb2e8f9f7	1760	/* Set the OSF bit according to ETH SecondFrameOperate value */
<>	144:ef7eb2e8f9f7	1761	tmpreg1 \|= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame \|
<>	144:ef7eb2e8f9f7	1762	dmainit.ReceiveStoreForward \|
<>	144:ef7eb2e8f9f7	1763	dmainit.FlushReceivedFrame \|
<>	144:ef7eb2e8f9f7	1764	dmainit.TransmitStoreForward \|
<>	144:ef7eb2e8f9f7	1765	dmainit.TransmitThresholdControl \|
<>	144:ef7eb2e8f9f7	1766	dmainit.ForwardErrorFrames \|
<>	144:ef7eb2e8f9f7	1767	dmainit.ForwardUndersizedGoodFrames \|
<>	144:ef7eb2e8f9f7	1768	dmainit.ReceiveThresholdControl \|
<>	144:ef7eb2e8f9f7	1769	dmainit.SecondFrameOperate);
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/* Write to ETHERNET DMAOMR */
<>	144:ef7eb2e8f9f7	1772	(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
<>	144:ef7eb2e8f9f7	1773
<>	144:ef7eb2e8f9f7	1774	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1775	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1776	tmpreg1 = (heth->Instance)->DMAOMR;
<>	144:ef7eb2e8f9f7	1777	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1778	(heth->Instance)->DMAOMR = tmpreg1;
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780	/----------------------- ETHERNET DMABMR Configuration ------------------/
<>	144:ef7eb2e8f9f7	1781	/* Set the AAL bit according to ETH AddressAlignedBeats value */
<>	144:ef7eb2e8f9f7	1782	/* Set the FB bit according to ETH FixedBurst value */
<>	144:ef7eb2e8f9f7	1783	/* Set the RPBL and 4PBL bits according to ETH RxDMABurstLength value /
<>	144:ef7eb2e8f9f7	1784	/* Set the PBL and 4PBL bits according to ETH TxDMABurstLength value /
<>	144:ef7eb2e8f9f7	1785	/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
<>	144:ef7eb2e8f9f7	1786	/* Set the DSL bit according to ETH DesciptorSkipLength value */
<>	144:ef7eb2e8f9f7	1787	/* Set the PR and DA bits according to ETH DMAArbitration value */
<>	144:ef7eb2e8f9f7	1788	(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats \|
<>	144:ef7eb2e8f9f7	1789	dmainit.FixedBurst \|
<>	144:ef7eb2e8f9f7	1790	dmainit.RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
<>	144:ef7eb2e8f9f7	1791	dmainit.TxDMABurstLength \|
<>	144:ef7eb2e8f9f7	1792	dmainit.EnhancedDescriptorFormat \|
<>	144:ef7eb2e8f9f7	1793	(dmainit.DescriptorSkipLength << 2U) \|
<>	144:ef7eb2e8f9f7	1794	dmainit.DMAArbitration \|
<>	144:ef7eb2e8f9f7	1795	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1798	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1799	tmpreg1 = (heth->Instance)->DMABMR;
<>	144:ef7eb2e8f9f7	1800	HAL_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1801	(heth->Instance)->DMABMR = tmpreg1;
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
<>	144:ef7eb2e8f9f7	1804	{
<>	144:ef7eb2e8f9f7	1805	/* Enable the Ethernet Rx Interrupt */
<>	144:ef7eb2e8f9f7	1806	__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS \| ETH_DMA_IT_R);
<>	144:ef7eb2e8f9f7	1807	}
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	/* Initialize MAC address in ethernet MAC */
<>	144:ef7eb2e8f9f7	1810	ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
<>	144:ef7eb2e8f9f7	1811	}
<>	144:ef7eb2e8f9f7	1812
<>	144:ef7eb2e8f9f7	1813	/**
<>	144:ef7eb2e8f9f7	1814	* @brief Configures the selected MAC address.
<>	144:ef7eb2e8f9f7	1815	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1816	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1817	* @param MacAddr: The MAC address to configure
<>	144:ef7eb2e8f9f7	1818	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1819	* @arg ETH_MAC_Address0: MAC Address0
<>	144:ef7eb2e8f9f7	1820	* @arg ETH_MAC_Address1: MAC Address1
<>	144:ef7eb2e8f9f7	1821	* @arg ETH_MAC_Address2: MAC Address2
<>	144:ef7eb2e8f9f7	1822	* @arg ETH_MAC_Address3: MAC Address3
<>	144:ef7eb2e8f9f7	1823	* @param Addr: Pointer to MAC address buffer data (6 bytes)
<>	144:ef7eb2e8f9f7	1824	* @retval HAL status
<>	144:ef7eb2e8f9f7	1825	*/
<>	144:ef7eb2e8f9f7	1826	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr)
<>	144:ef7eb2e8f9f7	1827	{
<>	144:ef7eb2e8f9f7	1828	uint32_t tmpreg1;
AnnaBridge	167:e84263d55307	1829
AnnaBridge	167:e84263d55307	1830	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	1831	UNUSED(heth);
AnnaBridge	167:e84263d55307	1832
<>	144:ef7eb2e8f9f7	1833	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1834	assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	/* Calculate the selected MAC address high register */
<>	144:ef7eb2e8f9f7	1837	tmpreg1 = ((uint32_t)Addr[5U] << 8U) \| (uint32_t)Addr[4U];
<>	144:ef7eb2e8f9f7	1838	/* Load the selected MAC address high register */
<>	144:ef7eb2e8f9f7	1839	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
<>	144:ef7eb2e8f9f7	1840	/* Calculate the selected MAC address low register */
<>	144:ef7eb2e8f9f7	1841	tmpreg1 = ((uint32_t)Addr[3U] << 24U) \| ((uint32_t)Addr[2U] << 16U) \| ((uint32_t)Addr[1U] << 8U) \| Addr[0U];
<>	144:ef7eb2e8f9f7	1842
<>	144:ef7eb2e8f9f7	1843	/* Load the selected MAC address low register */
<>	144:ef7eb2e8f9f7	1844	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
<>	144:ef7eb2e8f9f7	1845	}
<>	144:ef7eb2e8f9f7	1846
<>	144:ef7eb2e8f9f7	1847	/**
<>	144:ef7eb2e8f9f7	1848	* @brief Enables the MAC transmission.
<>	144:ef7eb2e8f9f7	1849	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1850	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1851	* @retval None
<>	144:ef7eb2e8f9f7	1852	*/
<>	144:ef7eb2e8f9f7	1853	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1854	{
<>	144:ef7eb2e8f9f7	1855	__IO uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1856
<>	144:ef7eb2e8f9f7	1857	/* Enable the MAC transmission */
<>	144:ef7eb2e8f9f7	1858	(heth->Instance)->MACCR \|= ETH_MACCR_TE;
<>	144:ef7eb2e8f9f7	1859
<>	144:ef7eb2e8f9f7	1860	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1861	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1862	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1863	ETH_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1864	(heth->Instance)->MACCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1865	}
<>	144:ef7eb2e8f9f7	1866
<>	144:ef7eb2e8f9f7	1867	/**
<>	144:ef7eb2e8f9f7	1868	* @brief Disables the MAC transmission.
<>	144:ef7eb2e8f9f7	1869	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1870	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1871	* @retval None
<>	144:ef7eb2e8f9f7	1872	*/
<>	144:ef7eb2e8f9f7	1873	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1874	{
<>	144:ef7eb2e8f9f7	1875	__IO uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1876
<>	144:ef7eb2e8f9f7	1877	/* Disable the MAC transmission */
<>	144:ef7eb2e8f9f7	1878	(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
<>	144:ef7eb2e8f9f7	1879
<>	144:ef7eb2e8f9f7	1880	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1881	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1882	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1883	ETH_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1884	(heth->Instance)->MACCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1885	}
<>	144:ef7eb2e8f9f7	1886
<>	144:ef7eb2e8f9f7	1887	/**
<>	144:ef7eb2e8f9f7	1888	* @brief Enables the MAC reception.
<>	144:ef7eb2e8f9f7	1889	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1890	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1891	* @retval None
<>	144:ef7eb2e8f9f7	1892	*/
<>	144:ef7eb2e8f9f7	1893	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1894	{
<>	144:ef7eb2e8f9f7	1895	__IO uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	/* Enable the MAC reception */
<>	144:ef7eb2e8f9f7	1898	(heth->Instance)->MACCR \|= ETH_MACCR_RE;
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1901	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1902	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1903	ETH_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1904	(heth->Instance)->MACCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1905	}
<>	144:ef7eb2e8f9f7	1906
<>	144:ef7eb2e8f9f7	1907	/**
<>	144:ef7eb2e8f9f7	1908	* @brief Disables the MAC reception.
<>	144:ef7eb2e8f9f7	1909	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1910	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1911	* @retval None
<>	144:ef7eb2e8f9f7	1912	*/
<>	144:ef7eb2e8f9f7	1913	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1914	{
<>	144:ef7eb2e8f9f7	1915	__IO uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1916
<>	144:ef7eb2e8f9f7	1917	/* Disable the MAC reception */
<>	144:ef7eb2e8f9f7	1918	(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1921	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1922	tmpreg1 = (heth->Instance)->MACCR;
<>	144:ef7eb2e8f9f7	1923	ETH_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1924	(heth->Instance)->MACCR = tmpreg1;
<>	144:ef7eb2e8f9f7	1925	}
<>	144:ef7eb2e8f9f7	1926
<>	144:ef7eb2e8f9f7	1927	/**
<>	144:ef7eb2e8f9f7	1928	* @brief Enables the DMA transmission.
<>	144:ef7eb2e8f9f7	1929	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1930	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1931	* @retval None
<>	144:ef7eb2e8f9f7	1932	*/
<>	144:ef7eb2e8f9f7	1933	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1934	{
<>	144:ef7eb2e8f9f7	1935	/* Enable the DMA transmission */
<>	144:ef7eb2e8f9f7	1936	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_ST;
<>	144:ef7eb2e8f9f7	1937	}
<>	144:ef7eb2e8f9f7	1938
<>	144:ef7eb2e8f9f7	1939	/**
<>	144:ef7eb2e8f9f7	1940	* @brief Disables the DMA transmission.
<>	144:ef7eb2e8f9f7	1941	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1942	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1943	* @retval None
<>	144:ef7eb2e8f9f7	1944	*/
<>	144:ef7eb2e8f9f7	1945	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1946	{
<>	144:ef7eb2e8f9f7	1947	/* Disable the DMA transmission */
<>	144:ef7eb2e8f9f7	1948	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
<>	144:ef7eb2e8f9f7	1949	}
<>	144:ef7eb2e8f9f7	1950
<>	144:ef7eb2e8f9f7	1951	/**
<>	144:ef7eb2e8f9f7	1952	* @brief Enables the DMA reception.
<>	144:ef7eb2e8f9f7	1953	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1954	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1955	* @retval None
<>	144:ef7eb2e8f9f7	1956	*/
<>	144:ef7eb2e8f9f7	1957	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1958	{
<>	144:ef7eb2e8f9f7	1959	/* Enable the DMA reception */
<>	144:ef7eb2e8f9f7	1960	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_SR;
<>	144:ef7eb2e8f9f7	1961	}
<>	144:ef7eb2e8f9f7	1962
<>	144:ef7eb2e8f9f7	1963	/**
<>	144:ef7eb2e8f9f7	1964	* @brief Disables the DMA reception.
<>	144:ef7eb2e8f9f7	1965	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1966	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1967	* @retval None
<>	144:ef7eb2e8f9f7	1968	*/
<>	144:ef7eb2e8f9f7	1969	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1970	{
<>	144:ef7eb2e8f9f7	1971	/* Disable the DMA reception */
<>	144:ef7eb2e8f9f7	1972	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
<>	144:ef7eb2e8f9f7	1973	}
<>	144:ef7eb2e8f9f7	1974
<>	144:ef7eb2e8f9f7	1975	/**
<>	144:ef7eb2e8f9f7	1976	* @brief Clears the ETHERNET transmit FIFO.
<>	144:ef7eb2e8f9f7	1977	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1978	* the configuration information for ETHERNET module
<>	144:ef7eb2e8f9f7	1979	* @retval None
<>	144:ef7eb2e8f9f7	1980	*/
<>	144:ef7eb2e8f9f7	1981	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
<>	144:ef7eb2e8f9f7	1982	{
<>	144:ef7eb2e8f9f7	1983	__IO uint32_t tmpreg1 = 0U;
<>	144:ef7eb2e8f9f7	1984
<>	144:ef7eb2e8f9f7	1985	/* Set the Flush Transmit FIFO bit */
<>	144:ef7eb2e8f9f7	1986	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_FTF;
<>	144:ef7eb2e8f9f7	1987
<>	144:ef7eb2e8f9f7	1988	/* Wait until the write operation will be taken into account:
<>	144:ef7eb2e8f9f7	1989	at least four TX_CLK/RX_CLK clock cycles */
<>	144:ef7eb2e8f9f7	1990	tmpreg1 = (heth->Instance)->DMAOMR;
<>	144:ef7eb2e8f9f7	1991	ETH_Delay(ETH_REG_WRITE_DELAY);
<>	144:ef7eb2e8f9f7	1992	(heth->Instance)->DMAOMR = tmpreg1;
<>	144:ef7eb2e8f9f7	1993	}
<>	144:ef7eb2e8f9f7	1994
<>	144:ef7eb2e8f9f7	1995	/**
<>	144:ef7eb2e8f9f7	1996	* @brief This function provides delay (in milliseconds) based on CPU cycles method.
<>	144:ef7eb2e8f9f7	1997	* @param mdelay: specifies the delay time length, in milliseconds.
<>	144:ef7eb2e8f9f7	1998	* @retval None
<>	144:ef7eb2e8f9f7	1999	*/
<>	144:ef7eb2e8f9f7	2000	static void ETH_Delay(uint32_t mdelay)
<>	144:ef7eb2e8f9f7	2001	{
<>	144:ef7eb2e8f9f7	2002	__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
<>	144:ef7eb2e8f9f7	2003	do
<>	144:ef7eb2e8f9f7	2004	{
<>	144:ef7eb2e8f9f7	2005	__NOP();
<>	144:ef7eb2e8f9f7	2006	}
<>	144:ef7eb2e8f9f7	2007	while (Delay --);
<>	144:ef7eb2e8f9f7	2008	}
<>	144:ef7eb2e8f9f7	2009
<>	144:ef7eb2e8f9f7	2010	/**
<>	144:ef7eb2e8f9f7	2011	* @}
<>	144:ef7eb2e8f9f7	2012	*/
<>	144:ef7eb2e8f9f7	2013
<>	144:ef7eb2e8f9f7	2014	#endif /* STM32F207xx \|\| STM32F217xx */
<>	144:ef7eb2e8f9f7	2015	#endif /* HAL_ETH_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2016	/**
<>	144:ef7eb2e8f9f7	2017	* @}
<>	144:ef7eb2e8f9f7	2018	*/
<>	144:ef7eb2e8f9f7	2019
<>	144:ef7eb2e8f9f7	2020	/**
<>	144:ef7eb2e8f9f7	2021	* @}
<>	144:ef7eb2e8f9f7	2022	*/
<>	144:ef7eb2e8f9f7	2023
<>	144:ef7eb2e8f9f7	2024	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/