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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_dma.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DMA HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DMA
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup DMA_Exported_Types DMA Exported Types
<> 144:ef7eb2e8f9f7 60 * @brief DMA Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 typedef struct
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref DMA_Channel_selection */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 144:ef7eb2e8f9f7 73 from memory to memory or from peripheral to memory.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref DMA_Memory_data_size */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
<> 144:ef7eb2e8f9f7 89 This parameter can be a value of @ref DMA_mode
<> 144:ef7eb2e8f9f7 90 @note The circular buffer mode cannot be used if the memory-to-memory
<> 144:ef7eb2e8f9f7 91 data transfer is configured on the selected Stream */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
<> 144:ef7eb2e8f9f7 94 This parameter can be a value of @ref DMA_Priority_level */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
<> 144:ef7eb2e8f9f7 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
<> 144:ef7eb2e8f9f7 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
<> 144:ef7eb2e8f9f7 99 memory-to-memory data transfer is configured on the selected stream */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
<> 144:ef7eb2e8f9f7 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
<> 144:ef7eb2e8f9f7 105 It specifies the amount of data to be transferred in a single non interruptible
<> 144:ef7eb2e8f9f7 106 transaction.
<> 144:ef7eb2e8f9f7 107 This parameter can be a value of @ref DMA_Memory_burst
<> 144:ef7eb2e8f9f7 108 @note The burst mode is possible only if the address Increment mode is enabled. */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
<> 144:ef7eb2e8f9f7 111 It specifies the amount of data to be transferred in a single non interruptible
<> 144:ef7eb2e8f9f7 112 transaction.
<> 144:ef7eb2e8f9f7 113 This parameter can be a value of @ref DMA_Peripheral_burst
<> 144:ef7eb2e8f9f7 114 @note The burst mode is possible only if the address Increment mode is enabled. */
<> 144:ef7eb2e8f9f7 115 }DMA_InitTypeDef;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @brief HAL DMA State structures definition
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 typedef enum
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
<> 144:ef7eb2e8f9f7 125 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
<> 144:ef7eb2e8f9f7 126 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
<> 144:ef7eb2e8f9f7 127 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
<> 144:ef7eb2e8f9f7 128 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
<> 144:ef7eb2e8f9f7 129 }HAL_DMA_StateTypeDef;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief HAL DMA Error Code structure definition
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 typedef enum
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
<> 144:ef7eb2e8f9f7 137 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
<> 144:ef7eb2e8f9f7 138 }HAL_DMA_LevelCompleteTypeDef;
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @brief HAL DMA Error Code structure definition
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 typedef enum
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
<> 144:ef7eb2e8f9f7 146 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
<> 144:ef7eb2e8f9f7 147 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
<> 144:ef7eb2e8f9f7 148 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
<> 144:ef7eb2e8f9f7 149 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
<> 144:ef7eb2e8f9f7 150 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
<> 144:ef7eb2e8f9f7 151 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
<> 144:ef7eb2e8f9f7 152 }HAL_DMA_CallbackIDTypeDef;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @brief DMA handle Structure definition
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 typedef struct __DMA_HandleTypeDef
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 DMA_Stream_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 DMA_InitTypeDef Init; /*!< DMA communication parameters */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 HAL_LockTypeDef Lock; /*!< DMA locking object */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 void *Parent; /*!< Parent object state */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 __IO uint32_t ErrorCode; /*!< DMA Error code */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 uint32_t StreamIndex; /*!< DMA Stream Index */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 }DMA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @}
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 144:ef7eb2e8f9f7 196 * @brief DMA Exported constants
<> 144:ef7eb2e8f9f7 197 * @{
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /** @defgroup DMA_Error_Code DMA Error Code
<> 144:ef7eb2e8f9f7 201 * @brief DMA Error Code
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
AnnaBridge 167:e84263d55307 204 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 167:e84263d55307 205 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
AnnaBridge 167:e84263d55307 206 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
AnnaBridge 167:e84263d55307 207 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
AnnaBridge 167:e84263d55307 208 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
AnnaBridge 167:e84263d55307 209 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
AnnaBridge 167:e84263d55307 210 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
AnnaBridge 167:e84263d55307 211 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup DMA_Channel_selection DMA Channel selection
<> 144:ef7eb2e8f9f7 217 * @brief DMA channel selection
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
AnnaBridge 167:e84263d55307 220 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
AnnaBridge 167:e84263d55307 221 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
AnnaBridge 167:e84263d55307 222 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
AnnaBridge 167:e84263d55307 223 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
AnnaBridge 167:e84263d55307 224 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
AnnaBridge 167:e84263d55307 225 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
AnnaBridge 167:e84263d55307 226 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
AnnaBridge 167:e84263d55307 227 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @}
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
<> 144:ef7eb2e8f9f7 233 * @brief DMA data transfer direction
<> 144:ef7eb2e8f9f7 234 * @{
<> 144:ef7eb2e8f9f7 235 */
AnnaBridge 167:e84263d55307 236 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
<> 144:ef7eb2e8f9f7 237 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
<> 144:ef7eb2e8f9f7 238 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
<> 144:ef7eb2e8f9f7 239 /**
<> 144:ef7eb2e8f9f7 240 * @}
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
<> 144:ef7eb2e8f9f7 244 * @brief DMA peripheral incremented mode
<> 144:ef7eb2e8f9f7 245 * @{
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
AnnaBridge 167:e84263d55307 248 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
<> 144:ef7eb2e8f9f7 254 * @brief DMA memory incremented mode
<> 144:ef7eb2e8f9f7 255 * @{
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
AnnaBridge 167:e84263d55307 258 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
<> 144:ef7eb2e8f9f7 264 * @brief DMA peripheral data size
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
AnnaBridge 167:e84263d55307 267 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
<> 144:ef7eb2e8f9f7 268 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
<> 144:ef7eb2e8f9f7 269 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @}
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /** @defgroup DMA_Memory_data_size DMA Memory data size
<> 144:ef7eb2e8f9f7 275 * @brief DMA memory data size
<> 144:ef7eb2e8f9f7 276 * @{
<> 144:ef7eb2e8f9f7 277 */
AnnaBridge 167:e84263d55307 278 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
<> 144:ef7eb2e8f9f7 279 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
<> 144:ef7eb2e8f9f7 280 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** @defgroup DMA_mode DMA mode
<> 144:ef7eb2e8f9f7 286 * @brief DMA mode
<> 144:ef7eb2e8f9f7 287 * @{
<> 144:ef7eb2e8f9f7 288 */
AnnaBridge 167:e84263d55307 289 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
<> 144:ef7eb2e8f9f7 290 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
<> 144:ef7eb2e8f9f7 291 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @}
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /** @defgroup DMA_Priority_level DMA Priority level
<> 144:ef7eb2e8f9f7 297 * @brief DMA priority levels
<> 144:ef7eb2e8f9f7 298 * @{
<> 144:ef7eb2e8f9f7 299 */
AnnaBridge 167:e84263d55307 300 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
<> 144:ef7eb2e8f9f7 301 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
<> 144:ef7eb2e8f9f7 302 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
<> 144:ef7eb2e8f9f7 303 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @}
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
<> 144:ef7eb2e8f9f7 309 * @brief DMA FIFO direct mode
<> 144:ef7eb2e8f9f7 310 * @{
<> 144:ef7eb2e8f9f7 311 */
AnnaBridge 167:e84263d55307 312 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
<> 144:ef7eb2e8f9f7 313 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
<> 144:ef7eb2e8f9f7 319 * @brief DMA FIFO level
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
AnnaBridge 167:e84263d55307 322 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
<> 144:ef7eb2e8f9f7 323 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
<> 144:ef7eb2e8f9f7 324 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
<> 144:ef7eb2e8f9f7 325 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup DMA_Memory_burst DMA Memory burst
<> 144:ef7eb2e8f9f7 331 * @brief DMA memory burst
<> 144:ef7eb2e8f9f7 332 * @{
<> 144:ef7eb2e8f9f7 333 */
AnnaBridge 167:e84263d55307 334 #define DMA_MBURST_SINGLE 0x00000000U
<> 144:ef7eb2e8f9f7 335 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
<> 144:ef7eb2e8f9f7 336 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
<> 144:ef7eb2e8f9f7 337 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
<> 144:ef7eb2e8f9f7 343 * @brief DMA peripheral burst
<> 144:ef7eb2e8f9f7 344 * @{
<> 144:ef7eb2e8f9f7 345 */
AnnaBridge 167:e84263d55307 346 #define DMA_PBURST_SINGLE 0x00000000U
<> 144:ef7eb2e8f9f7 347 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
<> 144:ef7eb2e8f9f7 348 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
<> 144:ef7eb2e8f9f7 349 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
<> 144:ef7eb2e8f9f7 355 * @brief DMA interrupts definition
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
<> 144:ef7eb2e8f9f7 359 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
<> 144:ef7eb2e8f9f7 360 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
<> 144:ef7eb2e8f9f7 361 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
AnnaBridge 167:e84263d55307 362 #define DMA_IT_FE 0x00000080U
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @}
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /** @defgroup DMA_flag_definitions DMA flag definitions
<> 144:ef7eb2e8f9f7 368 * @brief DMA flag definitions
<> 144:ef7eb2e8f9f7 369 * @{
<> 144:ef7eb2e8f9f7 370 */
AnnaBridge 167:e84263d55307 371 #define DMA_FLAG_FEIF0_4 0x00800001U
AnnaBridge 167:e84263d55307 372 #define DMA_FLAG_DMEIF0_4 0x00800004U
AnnaBridge 167:e84263d55307 373 #define DMA_FLAG_TEIF0_4 0x00000008U
AnnaBridge 167:e84263d55307 374 #define DMA_FLAG_HTIF0_4 0x00000010U
AnnaBridge 167:e84263d55307 375 #define DMA_FLAG_TCIF0_4 0x00000020U
AnnaBridge 167:e84263d55307 376 #define DMA_FLAG_FEIF1_5 0x00000040U
AnnaBridge 167:e84263d55307 377 #define DMA_FLAG_DMEIF1_5 0x00000100U
AnnaBridge 167:e84263d55307 378 #define DMA_FLAG_TEIF1_5 0x00000200U
AnnaBridge 167:e84263d55307 379 #define DMA_FLAG_HTIF1_5 0x00000400U
AnnaBridge 167:e84263d55307 380 #define DMA_FLAG_TCIF1_5 0x00000800U
AnnaBridge 167:e84263d55307 381 #define DMA_FLAG_FEIF2_6 0x00010000U
AnnaBridge 167:e84263d55307 382 #define DMA_FLAG_DMEIF2_6 0x00040000U
AnnaBridge 167:e84263d55307 383 #define DMA_FLAG_TEIF2_6 0x00080000U
AnnaBridge 167:e84263d55307 384 #define DMA_FLAG_HTIF2_6 0x00100000U
AnnaBridge 167:e84263d55307 385 #define DMA_FLAG_TCIF2_6 0x00200000U
AnnaBridge 167:e84263d55307 386 #define DMA_FLAG_FEIF3_7 0x00400000U
AnnaBridge 167:e84263d55307 387 #define DMA_FLAG_DMEIF3_7 0x01000000U
AnnaBridge 167:e84263d55307 388 #define DMA_FLAG_TEIF3_7 0x02000000U
AnnaBridge 167:e84263d55307 389 #define DMA_FLAG_HTIF3_7 0x04000000U
AnnaBridge 167:e84263d55307 390 #define DMA_FLAG_TCIF3_7 0x08000000U
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @}
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @}
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @brief Reset DMA handle state
<> 144:ef7eb2e8f9f7 402 * @param __HANDLE__: specifies the DMA handle.
<> 144:ef7eb2e8f9f7 403 * @retval None
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /**
<> 144:ef7eb2e8f9f7 408 * @brief Return the current DMA Stream FIFO filled level.
<> 144:ef7eb2e8f9f7 409 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 410 * @retval The FIFO filling state.
<> 144:ef7eb2e8f9f7 411 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
<> 144:ef7eb2e8f9f7 412 * and not empty.
<> 144:ef7eb2e8f9f7 413 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
<> 144:ef7eb2e8f9f7 414 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
<> 144:ef7eb2e8f9f7 415 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
<> 144:ef7eb2e8f9f7 416 * - DMA_FIFOStatus_Empty: when FIFO is empty
<> 144:ef7eb2e8f9f7 417 * - DMA_FIFOStatus_Full: when FIFO is full
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /**
<> 144:ef7eb2e8f9f7 422 * @brief Enable the specified DMA Stream.
<> 144:ef7eb2e8f9f7 423 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 424 * @retval None
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @brief Disable the specified DMA Stream.
<> 144:ef7eb2e8f9f7 430 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 431 * @retval None
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Return the current DMA Stream transfer complete flag.
<> 144:ef7eb2e8f9f7 439 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 440 * @retval The specified transfer complete flag index.
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
<> 144:ef7eb2e8f9f7 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
<> 144:ef7eb2e8f9f7 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
<> 144:ef7eb2e8f9f7 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
<> 144:ef7eb2e8f9f7 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
<> 144:ef7eb2e8f9f7 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
<> 144:ef7eb2e8f9f7 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
<> 144:ef7eb2e8f9f7 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
<> 144:ef7eb2e8f9f7 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
<> 144:ef7eb2e8f9f7 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
<> 144:ef7eb2e8f9f7 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
<> 144:ef7eb2e8f9f7 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
<> 144:ef7eb2e8f9f7 455 DMA_FLAG_TCIF3_7)
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /**
<> 144:ef7eb2e8f9f7 458 * @brief Return the current DMA Stream half transfer complete flag.
<> 144:ef7eb2e8f9f7 459 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 460 * @retval The specified half transfer complete flag index.
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
<> 144:ef7eb2e8f9f7 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
<> 144:ef7eb2e8f9f7 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
<> 144:ef7eb2e8f9f7 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
<> 144:ef7eb2e8f9f7 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
<> 144:ef7eb2e8f9f7 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
<> 144:ef7eb2e8f9f7 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
<> 144:ef7eb2e8f9f7 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
<> 144:ef7eb2e8f9f7 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
<> 144:ef7eb2e8f9f7 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
<> 144:ef7eb2e8f9f7 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
<> 144:ef7eb2e8f9f7 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
<> 144:ef7eb2e8f9f7 475 DMA_FLAG_HTIF3_7)
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Return the current DMA Stream transfer error flag.
<> 144:ef7eb2e8f9f7 479 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 480 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 483 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
<> 144:ef7eb2e8f9f7 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
<> 144:ef7eb2e8f9f7 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
<> 144:ef7eb2e8f9f7 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
<> 144:ef7eb2e8f9f7 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
<> 144:ef7eb2e8f9f7 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
<> 144:ef7eb2e8f9f7 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
<> 144:ef7eb2e8f9f7 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
<> 144:ef7eb2e8f9f7 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
<> 144:ef7eb2e8f9f7 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
<> 144:ef7eb2e8f9f7 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
<> 144:ef7eb2e8f9f7 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
<> 144:ef7eb2e8f9f7 495 DMA_FLAG_TEIF3_7)
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /**
<> 144:ef7eb2e8f9f7 498 * @brief Return the current DMA Stream FIFO error flag.
<> 144:ef7eb2e8f9f7 499 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 500 * @retval The specified FIFO error flag index.
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 503 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
<> 144:ef7eb2e8f9f7 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
<> 144:ef7eb2e8f9f7 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
<> 144:ef7eb2e8f9f7 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
<> 144:ef7eb2e8f9f7 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
<> 144:ef7eb2e8f9f7 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
<> 144:ef7eb2e8f9f7 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
<> 144:ef7eb2e8f9f7 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
<> 144:ef7eb2e8f9f7 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
<> 144:ef7eb2e8f9f7 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
<> 144:ef7eb2e8f9f7 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
<> 144:ef7eb2e8f9f7 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
<> 144:ef7eb2e8f9f7 515 DMA_FLAG_FEIF3_7)
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @brief Return the current DMA Stream direct mode error flag.
<> 144:ef7eb2e8f9f7 519 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 520 * @retval The specified direct mode error flag index.
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 523 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
<> 144:ef7eb2e8f9f7 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
<> 144:ef7eb2e8f9f7 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
<> 144:ef7eb2e8f9f7 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
<> 144:ef7eb2e8f9f7 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
<> 144:ef7eb2e8f9f7 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
<> 144:ef7eb2e8f9f7 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
<> 144:ef7eb2e8f9f7 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
<> 144:ef7eb2e8f9f7 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
<> 144:ef7eb2e8f9f7 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
<> 144:ef7eb2e8f9f7 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
<> 144:ef7eb2e8f9f7 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
<> 144:ef7eb2e8f9f7 535 DMA_FLAG_DMEIF3_7)
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /**
<> 144:ef7eb2e8f9f7 538 * @brief Get the DMA Stream pending flags.
<> 144:ef7eb2e8f9f7 539 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 540 * @param __FLAG__: Get the specified flag.
<> 144:ef7eb2e8f9f7 541 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 542 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
<> 144:ef7eb2e8f9f7 543 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
<> 144:ef7eb2e8f9f7 544 * @arg DMA_FLAG_TEIFx: Transfer error flag.
<> 144:ef7eb2e8f9f7 545 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
<> 144:ef7eb2e8f9f7 546 * @arg DMA_FLAG_FEIFx: FIFO error flag.
<> 144:ef7eb2e8f9f7 547 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
<> 144:ef7eb2e8f9f7 548 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
<> 144:ef7eb2e8f9f7 551 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 552 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 553 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /**
<> 144:ef7eb2e8f9f7 556 * @brief Clear the DMA Stream pending flags.
<> 144:ef7eb2e8f9f7 557 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 558 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 559 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 560 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
<> 144:ef7eb2e8f9f7 561 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
<> 144:ef7eb2e8f9f7 562 * @arg DMA_FLAG_TEIFx: Transfer error flag.
<> 144:ef7eb2e8f9f7 563 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
<> 144:ef7eb2e8f9f7 564 * @arg DMA_FLAG_FEIFx: FIFO error flag.
<> 144:ef7eb2e8f9f7 565 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
<> 144:ef7eb2e8f9f7 566 * @retval None
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 569 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 570 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 571 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @brief Enable the specified DMA Stream interrupts.
<> 144:ef7eb2e8f9f7 575 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 576 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 577 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 578 * @arg DMA_IT_TC: Transfer complete interrupt mask.
<> 144:ef7eb2e8f9f7 579 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
<> 144:ef7eb2e8f9f7 580 * @arg DMA_IT_TE: Transfer error interrupt mask.
<> 144:ef7eb2e8f9f7 581 * @arg DMA_IT_FE: FIFO error interrupt mask.
<> 144:ef7eb2e8f9f7 582 * @arg DMA_IT_DME: Direct mode error interrupt.
<> 144:ef7eb2e8f9f7 583 * @retval None
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
<> 144:ef7eb2e8f9f7 586 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @brief Disable the specified DMA Stream interrupts.
<> 144:ef7eb2e8f9f7 590 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 591 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 592 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 593 * @arg DMA_IT_TC: Transfer complete interrupt mask.
<> 144:ef7eb2e8f9f7 594 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
<> 144:ef7eb2e8f9f7 595 * @arg DMA_IT_TE: Transfer error interrupt mask.
<> 144:ef7eb2e8f9f7 596 * @arg DMA_IT_FE: FIFO error interrupt mask.
<> 144:ef7eb2e8f9f7 597 * @arg DMA_IT_DME: Direct mode error interrupt.
<> 144:ef7eb2e8f9f7 598 * @retval None
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
<> 144:ef7eb2e8f9f7 601 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
<> 144:ef7eb2e8f9f7 605 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 606 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
<> 144:ef7eb2e8f9f7 607 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 608 * @arg DMA_IT_TC: Transfer complete interrupt mask.
<> 144:ef7eb2e8f9f7 609 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
<> 144:ef7eb2e8f9f7 610 * @arg DMA_IT_TE: Transfer error interrupt mask.
<> 144:ef7eb2e8f9f7 611 * @arg DMA_IT_FE: FIFO error interrupt mask.
<> 144:ef7eb2e8f9f7 612 * @arg DMA_IT_DME: Direct mode error interrupt.
<> 144:ef7eb2e8f9f7 613 * @retval The state of DMA_IT.
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
<> 144:ef7eb2e8f9f7 616 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
<> 144:ef7eb2e8f9f7 617 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /**
<> 144:ef7eb2e8f9f7 620 * @brief Writes the number of data units to be transferred on the DMA Stream.
<> 144:ef7eb2e8f9f7 621 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 622 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
<> 144:ef7eb2e8f9f7 623 * Number of data items depends only on the Peripheral data format.
<> 144:ef7eb2e8f9f7 624 *
<> 144:ef7eb2e8f9f7 625 * @note If Peripheral data format is Bytes: number of data units is equal
<> 144:ef7eb2e8f9f7 626 * to total number of bytes to be transferred.
<> 144:ef7eb2e8f9f7 627 *
<> 144:ef7eb2e8f9f7 628 * @note If Peripheral data format is Half-Word: number of data units is
<> 144:ef7eb2e8f9f7 629 * equal to total number of bytes to be transferred / 2.
<> 144:ef7eb2e8f9f7 630 *
<> 144:ef7eb2e8f9f7 631 * @note If Peripheral data format is Word: number of data units is equal
<> 144:ef7eb2e8f9f7 632 * to total number of bytes to be transferred / 4.
<> 144:ef7eb2e8f9f7 633 *
<> 144:ef7eb2e8f9f7 634 * @retval The number of remaining data units in the current DMAy Streamx transfer.
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
<> 144:ef7eb2e8f9f7 640 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 641 *
<> 144:ef7eb2e8f9f7 642 * @retval The number of remaining data units in the current DMA Stream transfer.
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Include DMA HAL Extension module */
<> 144:ef7eb2e8f9f7 648 #include "stm32f2xx_hal_dma_ex.h"
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 653 * @brief DMA Exported functions
<> 144:ef7eb2e8f9f7 654 * @{
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 658 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 659 * @{
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 662 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @}
<> 144:ef7eb2e8f9f7 665 */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
<> 144:ef7eb2e8f9f7 668 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 669 * @{
<> 144:ef7eb2e8f9f7 670 */
<> 144:ef7eb2e8f9f7 671 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 672 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 673 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 674 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 675 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 676 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 677 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 678 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
<> 144:ef7eb2e8f9f7 679 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @}
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
<> 144:ef7eb2e8f9f7 686 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 687 * @{
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 690 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @}
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @}
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 /* Private Constants -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 698 /** @defgroup DMA_Private_Constants DMA Private Constants
<> 144:ef7eb2e8f9f7 699 * @brief DMA private defines and constants
<> 144:ef7eb2e8f9f7 700 * @{
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702 /**
<> 144:ef7eb2e8f9f7 703 * @}
<> 144:ef7eb2e8f9f7 704 */
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 707 /** @defgroup DMA_Private_Macros DMA Private Macros
<> 144:ef7eb2e8f9f7 708 * @brief DMA private macros
<> 144:ef7eb2e8f9f7 709 * @{
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 712 ((CHANNEL) == DMA_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 713 ((CHANNEL) == DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 714 ((CHANNEL) == DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 715 ((CHANNEL) == DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 716 ((CHANNEL) == DMA_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 717 ((CHANNEL) == DMA_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 718 ((CHANNEL) == DMA_CHANNEL_7))
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
<> 144:ef7eb2e8f9f7 721 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
<> 144:ef7eb2e8f9f7 722 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 727 ((STATE) == DMA_PINC_DISABLE))
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 730 ((STATE) == DMA_MINC_DISABLE))
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 733 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 734 ((SIZE) == DMA_PDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 737 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 738 ((SIZE) == DMA_MDATAALIGN_WORD ))
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
<> 144:ef7eb2e8f9f7 741 ((MODE) == DMA_CIRCULAR) || \
<> 144:ef7eb2e8f9f7 742 ((MODE) == DMA_PFCTRL))
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
<> 144:ef7eb2e8f9f7 745 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
<> 144:ef7eb2e8f9f7 746 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
<> 144:ef7eb2e8f9f7 747 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
<> 144:ef7eb2e8f9f7 750 ((STATE) == DMA_FIFOMODE_ENABLE))
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
<> 144:ef7eb2e8f9f7 753 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
<> 144:ef7eb2e8f9f7 754 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
<> 144:ef7eb2e8f9f7 755 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
<> 144:ef7eb2e8f9f7 758 ((BURST) == DMA_MBURST_INC4) || \
<> 144:ef7eb2e8f9f7 759 ((BURST) == DMA_MBURST_INC8) || \
<> 144:ef7eb2e8f9f7 760 ((BURST) == DMA_MBURST_INC16))
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
<> 144:ef7eb2e8f9f7 763 ((BURST) == DMA_PBURST_INC4) || \
<> 144:ef7eb2e8f9f7 764 ((BURST) == DMA_PBURST_INC8) || \
<> 144:ef7eb2e8f9f7 765 ((BURST) == DMA_PBURST_INC16))
<> 144:ef7eb2e8f9f7 766 /**
<> 144:ef7eb2e8f9f7 767 * @}
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 771 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 772 * @brief DMA private functions
<> 144:ef7eb2e8f9f7 773 * @{
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775 /**
<> 144:ef7eb2e8f9f7 776 * @}
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /**
<> 144:ef7eb2e8f9f7 780 * @}
<> 144:ef7eb2e8f9f7 781 */
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /**
<> 144:ef7eb2e8f9f7 784 * @}
<> 144:ef7eb2e8f9f7 785 */
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789 #endif
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 #endif /* __STM32F2xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/