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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dma.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
<> 144:ef7eb2e8f9f7 20 (except for internal SRAM/FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 21 necessary) please refer to Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 22 and DMA requests.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) For a given Stream, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 25 Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
<> 144:ef7eb2e8f9f7 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
<> 144:ef7eb2e8f9f7 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
<> 144:ef7eb2e8f9f7 31 __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 34 =================================
<> 144:ef7eb2e8f9f7 35 [..]
<> 144:ef7eb2e8f9f7 36 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 37 address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 38 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 39 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 40 (+) Use HAL_DMA_Abort() function to abort the current transfer.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 43 ===================================
<> 144:ef7eb2e8f9f7 44 [..]
<> 144:ef7eb2e8f9f7 45 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 46 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 47 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 48 Source address and destination address and the Length of data to be transferred. In this
<> 144:ef7eb2e8f9f7 49 case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 50 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 51 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 52 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 53 XferErrorCallback (i.e a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 56 detection.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
<> 144:ef7eb2e8f9f7 63 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
<> 144:ef7eb2e8f9f7 64 Half-Word data size for the peripheral to access its data register and set Word data size
<> 144:ef7eb2e8f9f7 65 for the Memory to gain in access time. Each two half words will be packed and written in
<> 144:ef7eb2e8f9f7 66 a single access to a Word in the Memory).
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
<> 144:ef7eb2e8f9f7 69 and Destination. In this case the Peripheral Data Size will be applied to both Source
<> 144:ef7eb2e8f9f7 70 and Destination.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 73 =============================================
<> 144:ef7eb2e8f9f7 74 [..]
<> 144:ef7eb2e8f9f7 75 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
<> 144:ef7eb2e8f9f7 78 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
<> 144:ef7eb2e8f9f7 79 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 [..]
<> 144:ef7eb2e8f9f7 82 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 @endverbatim
<> 144:ef7eb2e8f9f7 85 ******************************************************************************
<> 144:ef7eb2e8f9f7 86 * @attention
<> 144:ef7eb2e8f9f7 87 *
AnnaBridge 167:e84263d55307 88 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 89 *
<> 144:ef7eb2e8f9f7 90 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 91 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 92 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 93 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 94 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 95 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 96 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 97 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 98 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 99 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 102 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 103 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 104 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 105 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 106 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 107 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 108 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 109 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 110 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 ******************************************************************************
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 119 * @{
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 123 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 typedef struct
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 __IO uint32_t ISR; /*!< DMA interrupt status register */
<> 144:ef7eb2e8f9f7 133 __IO uint32_t Reserved0;
<> 144:ef7eb2e8f9f7 134 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
<> 144:ef7eb2e8f9f7 135 } DMA_Base_Registers;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /** @addtogroup DMA_Private_Constants
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
AnnaBridge 167:e84263d55307 142 #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @}
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 147 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 148 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 152 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 153 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
AnnaBridge 167:e84263d55307 158
AnnaBridge 167:e84263d55307 159 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /** @addtogroup DMA_Exported_Functions
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** @addtogroup DMA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 165 *
<> 144:ef7eb2e8f9f7 166 @verbatim
<> 144:ef7eb2e8f9f7 167 ===============================================================================
<> 144:ef7eb2e8f9f7 168 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 169 ===============================================================================
<> 144:ef7eb2e8f9f7 170 [..]
<> 144:ef7eb2e8f9f7 171 This section provides functions allowing to initialize the DMA Stream source
<> 144:ef7eb2e8f9f7 172 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 173 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
<> 144:ef7eb2e8f9f7 174 [..]
<> 144:ef7eb2e8f9f7 175 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 176 reference manual.
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 @endverbatim
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /**
AnnaBridge 167:e84263d55307 183 * @brief Initialize the DMA according to the specified
<> 144:ef7eb2e8f9f7 184 * parameters in the DMA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 185 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 186 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 187 * @retval HAL status
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 192 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 193 DMA_Base_Registers *regs;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 196 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Check the parameters */
<> 144:ef7eb2e8f9f7 202 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 203 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
<> 144:ef7eb2e8f9f7 204 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 205 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 206 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 207 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 208 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 209 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 210 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 211 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
<> 144:ef7eb2e8f9f7 212 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
<> 144:ef7eb2e8f9f7 213 when FIFO mode is enabled */
<> 144:ef7eb2e8f9f7 214 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
<> 144:ef7eb2e8f9f7 218 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Allocate lock resource */
<> 144:ef7eb2e8f9f7 222 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 225 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 228 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Check if the DMA Stream is effectively disabled */
<> 144:ef7eb2e8f9f7 231 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 234 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Update error code */
<> 144:ef7eb2e8f9f7 237 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 240 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 247 tmp = hdma->Instance->CR;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
<> 144:ef7eb2e8f9f7 250 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
<> 144:ef7eb2e8f9f7 251 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
<> 144:ef7eb2e8f9f7 252 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
<> 144:ef7eb2e8f9f7 253 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Prepare the DMA Stream configuration */
<> 144:ef7eb2e8f9f7 256 tmp |= hdma->Init.Channel | hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 257 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 258 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 259 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
<> 144:ef7eb2e8f9f7 262 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /* Get memory burst and peripheral burst */
<> 144:ef7eb2e8f9f7 265 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Write to DMA Stream CR register */
<> 144:ef7eb2e8f9f7 269 hdma->Instance->CR = tmp;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Get the FCR register value */
<> 144:ef7eb2e8f9f7 272 tmp = hdma->Instance->FCR;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Clear Direct mode and FIFO threshold bits */
<> 144:ef7eb2e8f9f7 275 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Prepare the DMA Stream FIFO configuration */
<> 144:ef7eb2e8f9f7 278 tmp |= hdma->Init.FIFOMode;
<> 144:ef7eb2e8f9f7 279
AnnaBridge 167:e84263d55307 280 /* The FIFO threshold is not used when the FIFO mode is disabled */
<> 144:ef7eb2e8f9f7 281 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 /* Get the FIFO threshold */
<> 144:ef7eb2e8f9f7 284 tmp |= hdma->Init.FIFOThreshold;
<> 144:ef7eb2e8f9f7 285
AnnaBridge 167:e84263d55307 286 /* Check compatibility between FIFO threshold level and size of the memory burst */
AnnaBridge 167:e84263d55307 287 /* for INCR4, INCR8, INCR16 bursts */
AnnaBridge 167:e84263d55307 288 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
<> 144:ef7eb2e8f9f7 289 {
AnnaBridge 167:e84263d55307 290 if (DMA_CheckFifoParam(hdma) != HAL_OK)
AnnaBridge 167:e84263d55307 291 {
AnnaBridge 167:e84263d55307 292 /* Update error code */
AnnaBridge 167:e84263d55307 293 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
AnnaBridge 167:e84263d55307 294
AnnaBridge 167:e84263d55307 295 /* Change the DMA state */
AnnaBridge 167:e84263d55307 296 hdma->State = HAL_DMA_STATE_READY;
AnnaBridge 167:e84263d55307 297
AnnaBridge 167:e84263d55307 298 return HAL_ERROR;
AnnaBridge 167:e84263d55307 299 }
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Write to DMA Stream FCR */
<> 144:ef7eb2e8f9f7 304 hdma->Instance->FCR = tmp;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
<> 144:ef7eb2e8f9f7 307 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
<> 144:ef7eb2e8f9f7 308 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Clear all interrupt flags */
<> 144:ef7eb2e8f9f7 311 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 314 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 317 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 return HAL_OK;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @brief DeInitializes the DMA peripheral
<> 144:ef7eb2e8f9f7 324 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 325 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 326 * @retval HAL status
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 DMA_Base_Registers *regs;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 333 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 339 if(hdma->State == HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 /* Return error status */
<> 144:ef7eb2e8f9f7 342 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
AnnaBridge 167:e84263d55307 345 /* Check the parameters */
AnnaBridge 167:e84263d55307 346 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
AnnaBridge 167:e84263d55307 347
<> 144:ef7eb2e8f9f7 348 /* Disable the selected DMA Streamx */
<> 144:ef7eb2e8f9f7 349 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Reset DMA Streamx control register */
<> 144:ef7eb2e8f9f7 352 hdma->Instance->CR = 0U;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Reset DMA Streamx number of data to transfer register */
<> 144:ef7eb2e8f9f7 355 hdma->Instance->NDTR = 0U;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Reset DMA Streamx peripheral address register */
<> 144:ef7eb2e8f9f7 358 hdma->Instance->PAR = 0U;
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Reset DMA Streamx memory 0 address register */
<> 144:ef7eb2e8f9f7 361 hdma->Instance->M0AR = 0U;
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Reset DMA Streamx memory 1 address register */
<> 144:ef7eb2e8f9f7 364 hdma->Instance->M1AR = 0U;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Reset DMA Streamx FIFO control register */
AnnaBridge 167:e84263d55307 367 hdma->Instance->FCR = 0x00000021U;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Get DMA steam Base Address */
<> 144:ef7eb2e8f9f7 370 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 373 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 376 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 379 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Release Lock */
<> 144:ef7eb2e8f9f7 382 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 return HAL_OK;
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /** @addtogroup DMA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 392 *
<> 144:ef7eb2e8f9f7 393 @verbatim
<> 144:ef7eb2e8f9f7 394 ===============================================================================
<> 144:ef7eb2e8f9f7 395 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 396 ===============================================================================
<> 144:ef7eb2e8f9f7 397 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 398 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 399 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 400 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 401 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 402 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 403 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 @endverbatim
<> 144:ef7eb2e8f9f7 406 * @{
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /**
<> 144:ef7eb2e8f9f7 410 * @brief Starts the DMA Transfer.
<> 144:ef7eb2e8f9f7 411 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 412 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 413 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 414 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 415 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 416 * @retval HAL status
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Check the parameters */
<> 144:ef7eb2e8f9f7 423 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Process locked */
<> 144:ef7eb2e8f9f7 426 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 431 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 434 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 437 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 440 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442 else
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 /* Process unlocked */
<> 144:ef7eb2e8f9f7 445 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Return error status */
<> 144:ef7eb2e8f9f7 448 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450 return status;
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
AnnaBridge 167:e84263d55307 454 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 455 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 456 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 457 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 458 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 459 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 460 * @retval HAL status
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 467 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Check the parameters */
<> 144:ef7eb2e8f9f7 470 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Process locked */
<> 144:ef7eb2e8f9f7 473 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 478 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 481 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 484 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 487 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Enable Common interrupts*/
<> 144:ef7eb2e8f9f7 490 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
<> 144:ef7eb2e8f9f7 491 hdma->Instance->FCR |= DMA_IT_FE;
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 hdma->Instance->CR |= DMA_IT_HT;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 499 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 else
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Process unlocked */
<> 144:ef7eb2e8f9f7 504 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Return error status */
<> 144:ef7eb2e8f9f7 507 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 return status;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @brief Aborts the DMA Transfer.
<> 144:ef7eb2e8f9f7 515 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 516 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 517 *
<> 144:ef7eb2e8f9f7 518 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
<> 144:ef7eb2e8f9f7 519 * effectively disabled is added. If a Stream is disabled
<> 144:ef7eb2e8f9f7 520 * while a data transfer is ongoing, the current data will be transferred
<> 144:ef7eb2e8f9f7 521 * and the Stream will be effectively disabled only after the transfer of
<> 144:ef7eb2e8f9f7 522 * this single data is finished.
<> 144:ef7eb2e8f9f7 523 * @retval HAL status
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 526 {
<> 144:ef7eb2e8f9f7 527 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 528 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 if(hdma->State != HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 537 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541 else
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 /* Disable all the transfer interrupts */
<> 144:ef7eb2e8f9f7 544 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
<> 144:ef7eb2e8f9f7 545 hdma->Instance->FCR &= ~(DMA_IT_FE);
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 hdma->Instance->CR &= ~(DMA_IT_HT);
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Disable the stream */
<> 144:ef7eb2e8f9f7 553 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Check if the DMA Stream is effectively disabled */
<> 144:ef7eb2e8f9f7 556 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 559 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 /* Update error code */
<> 144:ef7eb2e8f9f7 562 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 565 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 568 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 575 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 578 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Change the DMA state*/
<> 144:ef7eb2e8f9f7 581 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 return HAL_OK;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 144:ef7eb2e8f9f7 588 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 589 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 590 * @retval HAL status
<> 144:ef7eb2e8f9f7 591 */
<> 144:ef7eb2e8f9f7 592 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 if(hdma->State != HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 597 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599 else
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Set Abort State */
<> 144:ef7eb2e8f9f7 602 hdma->State = HAL_DMA_STATE_ABORT;
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Disable the stream */
<> 144:ef7eb2e8f9f7 605 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 return HAL_OK;
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 613 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 614 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 615 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 616 * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
<> 144:ef7eb2e8f9f7 617 * This model could be used for debug purpose.
<> 144:ef7eb2e8f9f7 618 * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
<> 144:ef7eb2e8f9f7 619 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 620 * @retval HAL status
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 625 uint32_t mask_cpltlevel;
<> 144:ef7eb2e8f9f7 626 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 627 uint32_t tmpisr;
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 630 DMA_Base_Registers *regs;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 /* No transfer ongoing */
<> 144:ef7eb2e8f9f7 635 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 636 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 637 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Polling mode not supported in circular mode and double buffering mode */
<> 144:ef7eb2e8f9f7 641 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
<> 144:ef7eb2e8f9f7 642 {
<> 144:ef7eb2e8f9f7 643 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 144:ef7eb2e8f9f7 644 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 648 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 651 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653 else
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 656 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 660 tmpisr = regs->ISR;
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 /* Check for the Timeout (Not applicable in circular mode)*/
<> 144:ef7eb2e8f9f7 665 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 666 {
AnnaBridge 167:e84263d55307 667 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 /* Update error code */
<> 144:ef7eb2e8f9f7 670 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 673 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 676 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Get the ISR register value */
<> 144:ef7eb2e8f9f7 683 tmpisr = regs->ISR;
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* Update error code */
<> 144:ef7eb2e8f9f7 688 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 691 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 /* Update error code */
<> 144:ef7eb2e8f9f7 697 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Clear the FIFO error flag */
<> 144:ef7eb2e8f9f7 700 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 /* Update error code */
<> 144:ef7eb2e8f9f7 706 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Clear the Direct Mode error flag */
<> 144:ef7eb2e8f9f7 709 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 HAL_DMA_Abort(hdma);
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Clear the half transfer and transfer complete flags */
<> 144:ef7eb2e8f9f7 720 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 723 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 726 hdma->State= HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 }
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 733 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 /* Clear the half transfer and transfer complete flags */
<> 144:ef7eb2e8f9f7 736 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 739 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743 else
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 /* Clear the half transfer and transfer complete flags */
<> 144:ef7eb2e8f9f7 746 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 return status;
<> 144:ef7eb2e8f9f7 750 }
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /**
<> 144:ef7eb2e8f9f7 753 * @brief Handles DMA interrupt request.
<> 144:ef7eb2e8f9f7 754 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 755 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 756 * @retval None
<> 144:ef7eb2e8f9f7 757 */
<> 144:ef7eb2e8f9f7 758 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 uint32_t tmpisr;
AnnaBridge 167:e84263d55307 761 __IO uint32_t count = 0U;
AnnaBridge 167:e84263d55307 762 uint32_t timeout = SystemCoreClock / 9600U;
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 765 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 tmpisr = regs->ISR;
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Transfer Error Interrupt management ***************************************/
<> 144:ef7eb2e8f9f7 770 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 /* Disable the transfer error interrupt */
<> 144:ef7eb2e8f9f7 775 hdma->Instance->CR &= ~(DMA_IT_TE);
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 778 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /* Update error code */
<> 144:ef7eb2e8f9f7 781 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784 /* FIFO Error Interrupt management ******************************************/
<> 144:ef7eb2e8f9f7 785 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 /* Clear the FIFO error flag */
<> 144:ef7eb2e8f9f7 790 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Update error code */
<> 144:ef7eb2e8f9f7 793 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796 /* Direct Mode Error Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 797 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 /* Clear the direct mode error flag */
<> 144:ef7eb2e8f9f7 802 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Update error code */
<> 144:ef7eb2e8f9f7 805 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 809 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 814 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Multi_Buffering mode enabled */
<> 144:ef7eb2e8f9f7 817 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 /* Current memory buffer used is Memory 0 */
<> 144:ef7eb2e8f9f7 820 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 825 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828 /* Current memory buffer used is Memory 1 */
<> 144:ef7eb2e8f9f7 829 else
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 if(hdma->XferM1HalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 834 hdma->XferM1HalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 else
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 841 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 844 hdma->Instance->CR &= ~(DMA_IT_HT);
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 850 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 851 }
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 856 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 857 {
<> 144:ef7eb2e8f9f7 858 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
<> 144:ef7eb2e8f9f7 859 {
<> 144:ef7eb2e8f9f7 860 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 861 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 if(HAL_DMA_STATE_ABORT == hdma->State)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 /* Disable all the transfer interrupts */
<> 144:ef7eb2e8f9f7 866 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
<> 144:ef7eb2e8f9f7 867 hdma->Instance->FCR &= ~(DMA_IT_FE);
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
<> 144:ef7eb2e8f9f7 870 {
<> 144:ef7eb2e8f9f7 871 hdma->Instance->CR &= ~(DMA_IT_HT);
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 875 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 878 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 881 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 hdma->XferAbortCallback(hdma);
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887 return;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
<> 144:ef7eb2e8f9f7 891 {
<> 144:ef7eb2e8f9f7 892 /* Current memory buffer used is Memory 0 */
<> 144:ef7eb2e8f9f7 893 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 if(hdma->XferM1CpltCallback != NULL)
<> 144:ef7eb2e8f9f7 896 {
<> 144:ef7eb2e8f9f7 897 /* Transfer complete Callback for memory1 */
<> 144:ef7eb2e8f9f7 898 hdma->XferM1CpltCallback(hdma);
<> 144:ef7eb2e8f9f7 899 }
<> 144:ef7eb2e8f9f7 900 }
<> 144:ef7eb2e8f9f7 901 /* Current memory buffer used is Memory 1 */
<> 144:ef7eb2e8f9f7 902 else
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 /* Transfer complete Callback for memory0 */
<> 144:ef7eb2e8f9f7 907 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 908 }
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 912 else
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 /* Disable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 917 hdma->Instance->CR &= ~(DMA_IT_TC);
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 920 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 923 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 927 {
<> 144:ef7eb2e8f9f7 928 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 929 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 930 }
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* manage error case */
<> 144:ef7eb2e8f9f7 936 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
<> 144:ef7eb2e8f9f7 939 {
<> 144:ef7eb2e8f9f7 940 hdma->State = HAL_DMA_STATE_ABORT;
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /* Disable the stream */
<> 144:ef7eb2e8f9f7 943 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 do
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 if (++count > timeout)
<> 144:ef7eb2e8f9f7 948 {
<> 144:ef7eb2e8f9f7 949 break;
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 955 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 958 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 959 }
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 if(hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 962 {
<> 144:ef7eb2e8f9f7 963 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 964 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 965 }
<> 144:ef7eb2e8f9f7 966 }
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /**
<> 144:ef7eb2e8f9f7 970 * @brief Register callbacks
<> 144:ef7eb2e8f9f7 971 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 972 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 973 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 974 * a DMA_HandleTypeDef structure as parameter.
<> 144:ef7eb2e8f9f7 975 * @param pCallback: pointer to private callbacsk function which has pointer to
<> 144:ef7eb2e8f9f7 976 * a DMA_HandleTypeDef structure as parameter.
<> 144:ef7eb2e8f9f7 977 * @retval HAL status
<> 144:ef7eb2e8f9f7 978 */
<> 144:ef7eb2e8f9f7 979 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
<> 144:ef7eb2e8f9f7 980 {
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 /* Process locked */
<> 144:ef7eb2e8f9f7 985 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 switch (CallbackID)
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 992 hdma->XferCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 993 break;
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 996 hdma->XferHalfCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 997 break;
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 case HAL_DMA_XFER_M1CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1000 hdma->XferM1CpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 1001 break;
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1004 hdma->XferM1HalfCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 1005 break;
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 1008 hdma->XferErrorCallback = pCallback;
<> 144:ef7eb2e8f9f7 1009 break;
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 1012 hdma->XferAbortCallback = pCallback;
<> 144:ef7eb2e8f9f7 1013 break;
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 default:
<> 144:ef7eb2e8f9f7 1016 break;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019 else
<> 144:ef7eb2e8f9f7 1020 {
<> 144:ef7eb2e8f9f7 1021 /* Return error status */
<> 144:ef7eb2e8f9f7 1022 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /* Release Lock */
<> 144:ef7eb2e8f9f7 1026 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 return status;
<> 144:ef7eb2e8f9f7 1029 }
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /**
<> 144:ef7eb2e8f9f7 1032 * @brief UnRegister callbacks
<> 144:ef7eb2e8f9f7 1033 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1034 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1035 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 1036 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 144:ef7eb2e8f9f7 1037 * @retval HAL status
<> 144:ef7eb2e8f9f7 1038 */
<> 144:ef7eb2e8f9f7 1039 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* Process locked */
<> 144:ef7eb2e8f9f7 1044 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 1047 {
<> 144:ef7eb2e8f9f7 1048 switch (CallbackID)
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1051 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1052 break;
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1055 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1056 break;
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 case HAL_DMA_XFER_M1CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1059 hdma->XferM1CpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1060 break;
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1063 hdma->XferM1HalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1064 break;
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 1067 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 1068 break;
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 1071 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1072 break;
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 case HAL_DMA_XFER_ALL_CB_ID:
<> 144:ef7eb2e8f9f7 1075 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1076 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1077 hdma->XferM1CpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1078 hdma->XferM1HalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1079 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 1080 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1081 break;
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 default:
<> 144:ef7eb2e8f9f7 1084 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1085 break;
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087 }
<> 144:ef7eb2e8f9f7 1088 else
<> 144:ef7eb2e8f9f7 1089 {
<> 144:ef7eb2e8f9f7 1090 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Release Lock */
<> 144:ef7eb2e8f9f7 1094 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 return status;
<> 144:ef7eb2e8f9f7 1097 }
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /**
<> 144:ef7eb2e8f9f7 1100 * @}
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /** @addtogroup DMA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1104 *
<> 144:ef7eb2e8f9f7 1105 @verbatim
<> 144:ef7eb2e8f9f7 1106 ===============================================================================
<> 144:ef7eb2e8f9f7 1107 ##### State and Errors functions #####
<> 144:ef7eb2e8f9f7 1108 ===============================================================================
<> 144:ef7eb2e8f9f7 1109 [..]
<> 144:ef7eb2e8f9f7 1110 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 1111 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 1112 (+) Get error code
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 @endverbatim
<> 144:ef7eb2e8f9f7 1115 * @{
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /**
<> 144:ef7eb2e8f9f7 1119 * @brief Returns the DMA state.
<> 144:ef7eb2e8f9f7 1120 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1121 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1122 * @retval HAL state
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 return hdma->State;
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /**
<> 144:ef7eb2e8f9f7 1130 * @brief Return the DMA error code
<> 144:ef7eb2e8f9f7 1131 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1132 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1133 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 1134 */
<> 144:ef7eb2e8f9f7 1135 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1136 {
<> 144:ef7eb2e8f9f7 1137 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 1138 }
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /**
<> 144:ef7eb2e8f9f7 1141 * @}
<> 144:ef7eb2e8f9f7 1142 */
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /**
<> 144:ef7eb2e8f9f7 1145 * @}
<> 144:ef7eb2e8f9f7 1146 */
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 1149 * @{
<> 144:ef7eb2e8f9f7 1150 */
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 1154 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1155 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1156 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 1157 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 1158 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 1159 * @retval HAL status
<> 144:ef7eb2e8f9f7 1160 */
<> 144:ef7eb2e8f9f7 1161 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 /* Clear DBM bit */
<> 144:ef7eb2e8f9f7 1164 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /* Configure DMA Stream data length */
<> 144:ef7eb2e8f9f7 1167 hdma->Instance->NDTR = DataLength;
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 1170 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 1171 {
<> 144:ef7eb2e8f9f7 1172 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 1173 hdma->Instance->PAR = DstAddress;
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Configure DMA Stream source address */
<> 144:ef7eb2e8f9f7 1176 hdma->Instance->M0AR = SrcAddress;
<> 144:ef7eb2e8f9f7 1177 }
<> 144:ef7eb2e8f9f7 1178 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 1179 else
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 /* Configure DMA Stream source address */
<> 144:ef7eb2e8f9f7 1182 hdma->Instance->PAR = SrcAddress;
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 1185 hdma->Instance->M0AR = DstAddress;
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /**
<> 144:ef7eb2e8f9f7 1190 * @brief Returns the DMA Stream base address depending on stream number
<> 144:ef7eb2e8f9f7 1191 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1192 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1193 * @retval Stream base address
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1196 {
<> 144:ef7eb2e8f9f7 1197 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* lookup table for necessary bitshift of flags within status registers */
<> 144:ef7eb2e8f9f7 1200 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
<> 144:ef7eb2e8f9f7 1201 hdma->StreamIndex = flagBitshiftOffset[stream_number];
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 if (stream_number > 3U)
<> 144:ef7eb2e8f9f7 1204 {
<> 144:ef7eb2e8f9f7 1205 /* return pointer to HISR and HIFCR */
<> 144:ef7eb2e8f9f7 1206 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208 else
<> 144:ef7eb2e8f9f7 1209 {
<> 144:ef7eb2e8f9f7 1210 /* return pointer to LISR and LIFCR */
<> 144:ef7eb2e8f9f7 1211 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
<> 144:ef7eb2e8f9f7 1212 }
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 return hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 1215 }
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 /**
AnnaBridge 167:e84263d55307 1218 * @brief Check compatibility between FIFO threshold level and size of the memory burst
<> 144:ef7eb2e8f9f7 1219 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1220 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1221 * @retval HAL status
<> 144:ef7eb2e8f9f7 1222 */
<> 144:ef7eb2e8f9f7 1223 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1224 {
<> 144:ef7eb2e8f9f7 1225 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1226 uint32_t tmp = hdma->Init.FIFOThreshold;
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /* Memory Data size equal to Byte */
<> 144:ef7eb2e8f9f7 1229 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 switch (tmp)
<> 144:ef7eb2e8f9f7 1232 {
AnnaBridge 167:e84263d55307 1233 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
AnnaBridge 167:e84263d55307 1234 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
AnnaBridge 167:e84263d55307 1235 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
AnnaBridge 167:e84263d55307 1236 {
AnnaBridge 167:e84263d55307 1237 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 1238 }
AnnaBridge 167:e84263d55307 1239 break;
AnnaBridge 167:e84263d55307 1240 case DMA_FIFO_THRESHOLD_HALFFULL:
AnnaBridge 167:e84263d55307 1241 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
AnnaBridge 167:e84263d55307 1242 {
AnnaBridge 167:e84263d55307 1243 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 1244 }
AnnaBridge 167:e84263d55307 1245 break;
AnnaBridge 167:e84263d55307 1246 case DMA_FIFO_THRESHOLD_FULL:
AnnaBridge 167:e84263d55307 1247 break;
AnnaBridge 167:e84263d55307 1248 default:
AnnaBridge 167:e84263d55307 1249 break;
<> 144:ef7eb2e8f9f7 1250 }
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /* Memory Data size equal to Half-Word */
<> 144:ef7eb2e8f9f7 1254 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1255 {
<> 144:ef7eb2e8f9f7 1256 switch (tmp)
<> 144:ef7eb2e8f9f7 1257 {
AnnaBridge 167:e84263d55307 1258 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
AnnaBridge 167:e84263d55307 1259 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
AnnaBridge 167:e84263d55307 1260 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 1261 break;
AnnaBridge 167:e84263d55307 1262 case DMA_FIFO_THRESHOLD_HALFFULL:
AnnaBridge 167:e84263d55307 1263 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
AnnaBridge 167:e84263d55307 1264 {
<> 144:ef7eb2e8f9f7 1265 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 1266 }
AnnaBridge 167:e84263d55307 1267 break;
AnnaBridge 167:e84263d55307 1268 case DMA_FIFO_THRESHOLD_FULL:
AnnaBridge 167:e84263d55307 1269 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
AnnaBridge 167:e84263d55307 1270 {
<> 144:ef7eb2e8f9f7 1271 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 1272 }
AnnaBridge 167:e84263d55307 1273 break;
AnnaBridge 167:e84263d55307 1274 default:
AnnaBridge 167:e84263d55307 1275 break;
<> 144:ef7eb2e8f9f7 1276 }
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Memory Data size equal to Word */
<> 144:ef7eb2e8f9f7 1280 else
<> 144:ef7eb2e8f9f7 1281 {
<> 144:ef7eb2e8f9f7 1282 switch (tmp)
<> 144:ef7eb2e8f9f7 1283 {
AnnaBridge 167:e84263d55307 1284 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
AnnaBridge 167:e84263d55307 1285 case DMA_FIFO_THRESHOLD_HALFFULL:
AnnaBridge 167:e84263d55307 1286 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
AnnaBridge 167:e84263d55307 1287 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 1288 break;
AnnaBridge 167:e84263d55307 1289 case DMA_FIFO_THRESHOLD_FULL:
AnnaBridge 167:e84263d55307 1290 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
AnnaBridge 167:e84263d55307 1291 {
<> 144:ef7eb2e8f9f7 1292 status = HAL_ERROR;
AnnaBridge 167:e84263d55307 1293 }
AnnaBridge 167:e84263d55307 1294 break;
AnnaBridge 167:e84263d55307 1295 default:
AnnaBridge 167:e84263d55307 1296 break;
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298 }
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 return status;
<> 144:ef7eb2e8f9f7 1301 }
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 /**
<> 144:ef7eb2e8f9f7 1304 * @}
<> 144:ef7eb2e8f9f7 1305 */
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1308 /**
<> 144:ef7eb2e8f9f7 1309 * @}
<> 144:ef7eb2e8f9f7 1310 */
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 /**
<> 144:ef7eb2e8f9f7 1313 * @}
<> 144:ef7eb2e8f9f7 1314 */
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/