mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dac.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_dac.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Digital to Analog Converter (DAC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### DAC Peripheral features #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 *** DAC Channels ***
<> 144:ef7eb2e8f9f7 22 ====================
<> 144:ef7eb2e8f9f7 23 [..]
<> 144:ef7eb2e8f9f7 24 The device integrates two 12-bit Digital Analog Converters that can
<> 144:ef7eb2e8f9f7 25 be used independently or simultaneously (dual mode):
<> 144:ef7eb2e8f9f7 26 (#) DAC channel1 with DAC_OUT1 (PA4) as output
<> 144:ef7eb2e8f9f7 27 (#) DAC channel2 with DAC_OUT2 (PA5) as output
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 *** DAC Triggers ***
<> 144:ef7eb2e8f9f7 30 ====================
<> 144:ef7eb2e8f9f7 31 [..]
<> 144:ef7eb2e8f9f7 32 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
<> 144:ef7eb2e8f9f7 33 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
<> 144:ef7eb2e8f9f7 34 [..]
<> 144:ef7eb2e8f9f7 35 Digital to Analog conversion can be triggered by:
<> 144:ef7eb2e8f9f7 36 (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
<> 144:ef7eb2e8f9f7 37 The used pin (GPIOx_Pin9) must be configured in input mode.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
<> 144:ef7eb2e8f9f7 40 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (#) Software using DAC_TRIGGER_SOFTWARE
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 *** DAC Buffer mode feature ***
<> 144:ef7eb2e8f9f7 45 ===============================
<> 144:ef7eb2e8f9f7 46 [..]
<> 144:ef7eb2e8f9f7 47 Each DAC channel integrates an output buffer that can be used to
<> 144:ef7eb2e8f9f7 48 reduce the output impedance, and to drive external loads directly
<> 144:ef7eb2e8f9f7 49 without having to add an external operational amplifier.
<> 144:ef7eb2e8f9f7 50 To enable, the output buffer use
<> 144:ef7eb2e8f9f7 51 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
<> 144:ef7eb2e8f9f7 52 [..]
<> 144:ef7eb2e8f9f7 53 (@) Refer to the device datasheet for more details about output
<> 144:ef7eb2e8f9f7 54 impedance value with and without output buffer.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** DAC wave generation feature ***
<> 144:ef7eb2e8f9f7 57 ===================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 Both DAC channels can be used to generate
<> 144:ef7eb2e8f9f7 60 (#) Noise wave
<> 144:ef7eb2e8f9f7 61 (#) Triangle wave
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 *** DAC data format ***
<> 144:ef7eb2e8f9f7 64 =======================
<> 144:ef7eb2e8f9f7 65 [..]
<> 144:ef7eb2e8f9f7 66 The DAC data format can be:
<> 144:ef7eb2e8f9f7 67 (#) 8-bit right alignment using DAC_ALIGN_8B_R
<> 144:ef7eb2e8f9f7 68 (#) 12-bit left alignment using DAC_ALIGN_12B_L
<> 144:ef7eb2e8f9f7 69 (#) 12-bit right alignment using DAC_ALIGN_12B_R
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 *** DAC data value to voltage correspondence ***
<> 144:ef7eb2e8f9f7 72 ================================================
<> 144:ef7eb2e8f9f7 73 [..]
<> 144:ef7eb2e8f9f7 74 The analog output voltage on each DAC channel pin is determined
<> 144:ef7eb2e8f9f7 75 by the following equation:
<> 144:ef7eb2e8f9f7 76 DAC_OUTx = VREF+ * DOR / 4095
<> 144:ef7eb2e8f9f7 77 with DOR is the Data Output Register
<> 144:ef7eb2e8f9f7 78 VEF+ is the input voltage reference (refer to the device datasheet)
<> 144:ef7eb2e8f9f7 79 e.g. To set DAC_OUT1 to 0.7V, use
<> 144:ef7eb2e8f9f7 80 Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 *** DMA requests ***
<> 144:ef7eb2e8f9f7 83 =====================
<> 144:ef7eb2e8f9f7 84 [..]
<> 144:ef7eb2e8f9f7 85 A DMA1 request can be generated when an external trigger (but not
<> 144:ef7eb2e8f9f7 86 a software trigger) occurs if DMA1 requests are enabled using
<> 144:ef7eb2e8f9f7 87 HAL_DAC_Start_DMA()
<> 144:ef7eb2e8f9f7 88 [..]
<> 144:ef7eb2e8f9f7 89 DMA1 requests are mapped as following:
<> 144:ef7eb2e8f9f7 90 (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
<> 144:ef7eb2e8f9f7 91 already configured
<> 144:ef7eb2e8f9f7 92 (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
<> 144:ef7eb2e8f9f7 93 already configured
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 -@- For Dual mode and specific signal (Triangle and noise) generation please
<> 144:ef7eb2e8f9f7 96 refer to Extension Features Driver description
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 100 ==============================================================================
<> 144:ef7eb2e8f9f7 101 [..]
<> 144:ef7eb2e8f9f7 102 (+) DAC APB clock must be enabled to get write access to DAC
<> 144:ef7eb2e8f9f7 103 registers using HAL_DAC_Init()
<> 144:ef7eb2e8f9f7 104 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
<> 144:ef7eb2e8f9f7 105 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
<> 144:ef7eb2e8f9f7 106 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 109 =================================
<> 144:ef7eb2e8f9f7 110 [..]
<> 144:ef7eb2e8f9f7 111 (+) Start the DAC peripheral using HAL_DAC_Start()
<> 144:ef7eb2e8f9f7 112 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
<> 144:ef7eb2e8f9f7 113 (+) Stop the DAC peripheral using HAL_DAC_Stop()
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 116 ==============================
<> 144:ef7eb2e8f9f7 117 [..]
<> 144:ef7eb2e8f9f7 118 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
<> 144:ef7eb2e8f9f7 119 of data to be transferred at each end of conversion
<> 144:ef7eb2e8f9f7 120 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 121 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 122 HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
<> 144:ef7eb2e8f9f7 123 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
<> 144:ef7eb2e8f9f7 124 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
<> 144:ef7eb2e8f9f7 125 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 *** DAC HAL driver macros list ***
<> 144:ef7eb2e8f9f7 128 =============================================
<> 144:ef7eb2e8f9f7 129 [..]
<> 144:ef7eb2e8f9f7 130 Below the list of most used macros in DAC HAL driver.
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
<> 144:ef7eb2e8f9f7 133 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
<> 144:ef7eb2e8f9f7 134 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
<> 144:ef7eb2e8f9f7 135 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 [..]
<> 144:ef7eb2e8f9f7 138 (@) You can refer to the DAC HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 @endverbatim
<> 144:ef7eb2e8f9f7 141 ******************************************************************************
<> 144:ef7eb2e8f9f7 142 * @attention
<> 144:ef7eb2e8f9f7 143 *
AnnaBridge 167:e84263d55307 144 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 145 *
<> 144:ef7eb2e8f9f7 146 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 147 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 148 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 149 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 150 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 151 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 152 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 153 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 154 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 155 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 156 *
<> 144:ef7eb2e8f9f7 157 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 158 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 159 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 160 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 161 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 162 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 163 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 164 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 165 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 166 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 167 *
<> 144:ef7eb2e8f9f7 168 ******************************************************************************
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 176 * @{
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup DAC DAC
<> 144:ef7eb2e8f9f7 180 * @brief DAC driver modules
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 187 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 188 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 189 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 190 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 191 * @{
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 194 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 195 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 196 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 202 /** @defgroup DAC_Exported_Functions DAC Exported Functions
<> 144:ef7eb2e8f9f7 203 * @{
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 207 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 208 *
<> 144:ef7eb2e8f9f7 209 @verbatim
<> 144:ef7eb2e8f9f7 210 ==============================================================================
<> 144:ef7eb2e8f9f7 211 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 212 ==============================================================================
<> 144:ef7eb2e8f9f7 213 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 214 (+) Initialize and configure the DAC.
<> 144:ef7eb2e8f9f7 215 (+) De-initialize the DAC.
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 @endverbatim
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @brief Initializes the DAC peripheral according to the specified parameters
<> 144:ef7eb2e8f9f7 223 * in the DAC_InitStruct.
<> 144:ef7eb2e8f9f7 224 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 225 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 226 * @retval HAL status
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 231 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 /* Check the parameters */
<> 144:ef7eb2e8f9f7 236 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 if(hdac->State == HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 241 hdac->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 242 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 243 HAL_DAC_MspInit(hdac);
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 247 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 250 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 253 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Return function status */
<> 144:ef7eb2e8f9f7 256 return HAL_OK;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief Deinitializes the DAC peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 261 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 262 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 263 * @retval HAL status
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 268 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Check the parameters */
<> 144:ef7eb2e8f9f7 274 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Change DAC state */
<> 144:ef7eb2e8f9f7 277 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 280 HAL_DAC_MspDeInit(hdac);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 283 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Change DAC state */
<> 144:ef7eb2e8f9f7 286 hdac->State = HAL_DAC_STATE_RESET;
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Release Lock */
<> 144:ef7eb2e8f9f7 289 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Return function status */
<> 144:ef7eb2e8f9f7 292 return HAL_OK;
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Initializes the DAC MSP.
<> 144:ef7eb2e8f9f7 297 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 298 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 299 * @retval None
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 304 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 305 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 306 the HAL_DAC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /**
<> 144:ef7eb2e8f9f7 311 * @brief DeInitializes the DAC MSP.
<> 144:ef7eb2e8f9f7 312 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 313 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 314 * @retval None
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 319 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 320 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 321 the HAL_DAC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @}
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 330 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 331 *
<> 144:ef7eb2e8f9f7 332 @verbatim
<> 144:ef7eb2e8f9f7 333 ==============================================================================
<> 144:ef7eb2e8f9f7 334 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 335 ==============================================================================
<> 144:ef7eb2e8f9f7 336 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 337 (+) Start conversion.
<> 144:ef7eb2e8f9f7 338 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 339 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 340 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 341 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 @endverbatim
<> 144:ef7eb2e8f9f7 344 * @{
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 349 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 350 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 351 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 352 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 353 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 354 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 355 * @retval HAL status
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Check the parameters */
<> 144:ef7eb2e8f9f7 362 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Process locked */
<> 144:ef7eb2e8f9f7 365 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Change DAC state */
<> 144:ef7eb2e8f9f7 368 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 371 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
<> 144:ef7eb2e8f9f7 376 tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
<> 144:ef7eb2e8f9f7 377 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 378 if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 379 {
<> 144:ef7eb2e8f9f7 380 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 381 hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384 else
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
<> 144:ef7eb2e8f9f7 387 tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
<> 144:ef7eb2e8f9f7 388 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 389 if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 392 hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Change DAC state */
<> 144:ef7eb2e8f9f7 397 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Process unlocked */
<> 144:ef7eb2e8f9f7 400 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Return function status */
<> 144:ef7eb2e8f9f7 403 return HAL_OK;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 408 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 409 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 410 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 411 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 412 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 413 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 414 * @retval HAL status
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 417 {
<> 144:ef7eb2e8f9f7 418 /* Check the parameters */
<> 144:ef7eb2e8f9f7 419 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 422 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Change DAC state */
<> 144:ef7eb2e8f9f7 425 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Return function status */
<> 144:ef7eb2e8f9f7 428 return HAL_OK;
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 433 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 434 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 435 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 436 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 437 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 438 * @arg DAC_CHANNEL_2: DAC Channel2 selected
AnnaBridge 167:e84263d55307 439 * @param pData: The Source memory Buffer address.
<> 144:ef7eb2e8f9f7 440 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 441 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 442 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 443 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 444 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 445 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 446 * @retval HAL status
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Check the parameters */
<> 144:ef7eb2e8f9f7 453 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 454 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Process locked */
<> 144:ef7eb2e8f9f7 457 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Change DAC state */
<> 144:ef7eb2e8f9f7 460 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 465 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 468 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 471 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 474 hdac->Instance->CR |= DAC_CR_DMAEN1;
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 477 switch(Alignment)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 480 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 481 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 482 break;
<> 144:ef7eb2e8f9f7 483 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 484 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 485 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 486 break;
<> 144:ef7eb2e8f9f7 487 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 488 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 489 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 490 break;
<> 144:ef7eb2e8f9f7 491 default:
<> 144:ef7eb2e8f9f7 492 break;
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 else
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 498 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 501 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 504 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 507 hdac->Instance->CR |= DAC_CR_DMAEN2;
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 510 switch(Alignment)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 513 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 514 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 515 break;
<> 144:ef7eb2e8f9f7 516 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 517 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 518 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 519 break;
<> 144:ef7eb2e8f9f7 520 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 521 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 522 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 523 break;
<> 144:ef7eb2e8f9f7 524 default:
<> 144:ef7eb2e8f9f7 525 break;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 530 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 533 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 536 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 else
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 541 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 544 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 548 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 551 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Return function status */
<> 144:ef7eb2e8f9f7 554 return HAL_OK;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 559 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 560 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 561 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 562 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 563 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 564 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 565 * @retval HAL status
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Check the parameters */
<> 144:ef7eb2e8f9f7 572 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 575 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 578 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 581 /* Channel1 is used */
<> 144:ef7eb2e8f9f7 582 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 else /* Channel2 is used for */
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 status = HAL_DMA_Abort(hdac->DMA_Handle2);
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 592 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 /* Update DAC state machine to error */
<> 144:ef7eb2e8f9f7 595 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597 else
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 /* Change DAC state */
<> 144:ef7eb2e8f9f7 600 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Return function status */
<> 144:ef7eb2e8f9f7 604 return status;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 609 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 610 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 611 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 612 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 613 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 614 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 615 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 /* Check the parameters */
<> 144:ef7eb2e8f9f7 620 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 623 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 else
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /**
<> 144:ef7eb2e8f9f7 634 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 635 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 636 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 637 * @retval None
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 /* Check underrun channel 1 flag */
<> 144:ef7eb2e8f9f7 642 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 645 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Set DAC error code to channel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 648 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 651 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 654 hdac->Instance->CR &= ~DAC_CR_DMAEN1;
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Error callback */
<> 144:ef7eb2e8f9f7 657 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659 /* Check underrun channel 2 flag */
<> 144:ef7eb2e8f9f7 660 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 663 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Set DAC error code to channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 666 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 669 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 672 hdac->Instance->CR &= ~DAC_CR_DMAEN2;
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Error callback */
<> 144:ef7eb2e8f9f7 675 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Conversion complete callback in non blocking mode for Channel1
<> 144:ef7eb2e8f9f7 681 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 682 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 683 * @retval None
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 688 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 689 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 690 the HAL_DAC_ConvCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
<> 144:ef7eb2e8f9f7 696 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 697 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 698 * @retval None
<> 144:ef7eb2e8f9f7 699 */
<> 144:ef7eb2e8f9f7 700 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 703 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 704 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 705 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 706 */
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /**
<> 144:ef7eb2e8f9f7 710 * @brief Error DAC callback for Channel1.
<> 144:ef7eb2e8f9f7 711 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 712 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 713 * @retval None
<> 144:ef7eb2e8f9f7 714 */
<> 144:ef7eb2e8f9f7 715 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 718 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 719 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 720 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 721 */
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @brief DMA underrun DAC callback for channel1.
<> 144:ef7eb2e8f9f7 726 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 727 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 728 * @retval None
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 733 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 734 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 735 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /**
<> 144:ef7eb2e8f9f7 740 * @}
<> 144:ef7eb2e8f9f7 741 */
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 744 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 745 *
<> 144:ef7eb2e8f9f7 746 @verbatim
<> 144:ef7eb2e8f9f7 747 ==============================================================================
<> 144:ef7eb2e8f9f7 748 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 749 ==============================================================================
<> 144:ef7eb2e8f9f7 750 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 751 (+) Configure channels.
<> 144:ef7eb2e8f9f7 752 (+) Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 @endverbatim
<> 144:ef7eb2e8f9f7 755 * @{
<> 144:ef7eb2e8f9f7 756 */
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /**
<> 144:ef7eb2e8f9f7 759 * @brief Configures the selected DAC channel.
<> 144:ef7eb2e8f9f7 760 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 761 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 762 * @param sConfig: DAC configuration structure.
<> 144:ef7eb2e8f9f7 763 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 764 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 765 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 766 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 767 * @retval HAL status
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Check the DAC parameters */
<> 144:ef7eb2e8f9f7 774 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 775 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 776 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Process locked */
<> 144:ef7eb2e8f9f7 779 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Change DAC state */
<> 144:ef7eb2e8f9f7 782 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Get the DAC CR value */
<> 144:ef7eb2e8f9f7 785 tmpreg1 = hdac->Instance->CR;
<> 144:ef7eb2e8f9f7 786 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 787 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
<> 144:ef7eb2e8f9f7 788 /* Configure for the selected DAC channel: buffer output, trigger */
<> 144:ef7eb2e8f9f7 789 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 790 /* Set BOFFx bit according to DAC_OutputBuffer value */
<> 144:ef7eb2e8f9f7 791 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
<> 144:ef7eb2e8f9f7 792 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 793 tmpreg1 |= tmpreg2 << Channel;
<> 144:ef7eb2e8f9f7 794 /* Write to DAC CR */
<> 144:ef7eb2e8f9f7 795 hdac->Instance->CR = tmpreg1;
<> 144:ef7eb2e8f9f7 796 /* Disable wave generation */
<> 144:ef7eb2e8f9f7 797 hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Change DAC state */
<> 144:ef7eb2e8f9f7 800 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Process unlocked */
<> 144:ef7eb2e8f9f7 803 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Return function status */
<> 144:ef7eb2e8f9f7 806 return HAL_OK;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 811 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 812 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 813 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 814 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 815 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 816 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 817 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 818 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 819 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 820 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 821 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 822 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 823 * @retval HAL status
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 826 {
<> 144:ef7eb2e8f9f7 827 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Check the parameters */
<> 144:ef7eb2e8f9f7 830 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 831 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 832 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 835 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 else
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Set the DAC channel1 selected data holding register */
<> 144:ef7eb2e8f9f7 845 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Return function status */
<> 144:ef7eb2e8f9f7 848 return HAL_OK;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /**
<> 144:ef7eb2e8f9f7 852 * @}
<> 144:ef7eb2e8f9f7 853 */
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 856 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 857 *
<> 144:ef7eb2e8f9f7 858 @verbatim
<> 144:ef7eb2e8f9f7 859 ==============================================================================
<> 144:ef7eb2e8f9f7 860 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 861 ==============================================================================
<> 144:ef7eb2e8f9f7 862 [..]
<> 144:ef7eb2e8f9f7 863 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 864 (+) Check the DAC state.
<> 144:ef7eb2e8f9f7 865 (+) Check the DAC Errors.
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 @endverbatim
<> 144:ef7eb2e8f9f7 868 * @{
<> 144:ef7eb2e8f9f7 869 */
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /**
<> 144:ef7eb2e8f9f7 872 * @brief return the DAC state
<> 144:ef7eb2e8f9f7 873 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 874 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 875 * @retval HAL state
<> 144:ef7eb2e8f9f7 876 */
<> 144:ef7eb2e8f9f7 877 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Return DAC state */
<> 144:ef7eb2e8f9f7 880 return hdac->State;
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /**
<> 144:ef7eb2e8f9f7 885 * @brief Return the DAC error code
<> 144:ef7eb2e8f9f7 886 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 887 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 888 * @retval DAC Error Code
<> 144:ef7eb2e8f9f7 889 */
<> 144:ef7eb2e8f9f7 890 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 891 {
<> 144:ef7eb2e8f9f7 892 return hdac->ErrorCode;
<> 144:ef7eb2e8f9f7 893 }
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /**
<> 144:ef7eb2e8f9f7 896 * @}
<> 144:ef7eb2e8f9f7 897 */
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /**
<> 144:ef7eb2e8f9f7 900 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 901 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 902 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 903 * @retval None
<> 144:ef7eb2e8f9f7 904 */
<> 144:ef7eb2e8f9f7 905 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /**
<> 144:ef7eb2e8f9f7 915 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 916 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 917 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 918 * @retval None
<> 144:ef7eb2e8f9f7 919 */
<> 144:ef7eb2e8f9f7 920 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 923 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 924 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 929 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 930 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 931 * @retval None
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 938 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /**
<> 144:ef7eb2e8f9f7 946 * @}
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /**
<> 144:ef7eb2e8f9f7 952 * @}
<> 144:ef7eb2e8f9f7 953 */
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /**
<> 144:ef7eb2e8f9f7 956 * @}
<> 144:ef7eb2e8f9f7 957 */
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/