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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_adc_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_adc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the ADC extension peripheral:
<> 144:ef7eb2e8f9f7 9 * + Extended features functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
<> 144:ef7eb2e8f9f7 17 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 18 (##) ADC pins configuration
<> 144:ef7eb2e8f9f7 19 (+++) Enable the clock for the ADC GPIOs using the following function:
<> 144:ef7eb2e8f9f7 20 __HAL_RCC_GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 21 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 22 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
<> 144:ef7eb2e8f9f7 23 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 24 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 25 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
<> 144:ef7eb2e8f9f7 26 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
<> 144:ef7eb2e8f9f7 27 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 28 (+++) Configure and enable two DMA streams stream for managing data
<> 144:ef7eb2e8f9f7 29 transfer from peripheral to memory (output stream)
<> 144:ef7eb2e8f9f7 30 (+++) Associate the initialized DMA handle to the ADC DMA handle
<> 144:ef7eb2e8f9f7 31 using __HAL_LINKDMA()
<> 144:ef7eb2e8f9f7 32 (+++) Configure the priority and enable the NVIC for the transfer complete
<> 144:ef7eb2e8f9f7 33 interrupt on the two DMA Streams. The output stream should have higher
<> 144:ef7eb2e8f9f7 34 priority than the input stream.
<> 144:ef7eb2e8f9f7 35 (#) Configure the ADC Prescaler, conversion resolution and data alignment
<> 144:ef7eb2e8f9f7 36 using the HAL_ADC_Init() function.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
<> 144:ef7eb2e8f9f7 39 and HAL_ADC_ConfigChannel() functions.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 44 =================================
<> 144:ef7eb2e8f9f7 45 [..]
<> 144:ef7eb2e8f9f7 46 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
<> 144:ef7eb2e8f9f7 47 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
<> 144:ef7eb2e8f9f7 48 user can specify the value of timeout according to his end application
<> 144:ef7eb2e8f9f7 49 (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
<> 144:ef7eb2e8f9f7 50 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 53 ===================================
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
<> 144:ef7eb2e8f9f7 56 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 57 (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 58 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
<> 144:ef7eb2e8f9f7 59 (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 60 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
<> 144:ef7eb2e8f9f7 61 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 65 ==============================
<> 144:ef7eb2e8f9f7 66 [..]
<> 144:ef7eb2e8f9f7 67 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
<> 144:ef7eb2e8f9f7 68 of data to be transferred at each end of conversion
<> 144:ef7eb2e8f9f7 69 (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 70 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
<> 144:ef7eb2e8f9f7 71 (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 72 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
<> 144:ef7eb2e8f9f7 73 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 *** Multi mode ADCs Regular channels configuration ***
<> 144:ef7eb2e8f9f7 76 ======================================================
<> 144:ef7eb2e8f9f7 77 [..]
<> 144:ef7eb2e8f9f7 78 (+) Select the Multi mode ADC regular channels features (dual or triple mode)
<> 144:ef7eb2e8f9f7 79 and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
<> 144:ef7eb2e8f9f7 80 (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
<> 144:ef7eb2e8f9f7 81 of data to be transferred at each end of conversion
<> 144:ef7eb2e8f9f7 82 (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 @endverbatim
<> 144:ef7eb2e8f9f7 86 ******************************************************************************
<> 144:ef7eb2e8f9f7 87 * @attention
<> 144:ef7eb2e8f9f7 88 *
AnnaBridge 167:e84263d55307 89 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 90 *
<> 144:ef7eb2e8f9f7 91 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 92 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 93 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 94 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 95 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 96 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 97 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 98 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 99 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 100 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 103 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 104 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 105 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 106 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 107 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 108 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 109 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 110 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 111 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 ******************************************************************************
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** @defgroup ADCEx ADCEx
<> 144:ef7eb2e8f9f7 124 * @brief ADC Extended driver modules
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #ifdef HAL_ADC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 133 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 134 /** @addtogroup ADCEx_Private_Functions
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 139 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 140 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
<> 144:ef7eb2e8f9f7 151 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 152 *
<> 144:ef7eb2e8f9f7 153 @verbatim
<> 144:ef7eb2e8f9f7 154 ===============================================================================
<> 144:ef7eb2e8f9f7 155 ##### Extended features functions #####
<> 144:ef7eb2e8f9f7 156 ===============================================================================
<> 144:ef7eb2e8f9f7 157 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 158 (+) Start conversion of injected channel.
<> 144:ef7eb2e8f9f7 159 (+) Stop conversion of injected channel.
<> 144:ef7eb2e8f9f7 160 (+) Start multimode and enable DMA transfer.
<> 144:ef7eb2e8f9f7 161 (+) Stop multimode and disable DMA transfer.
<> 144:ef7eb2e8f9f7 162 (+) Get result of injected channel conversion.
<> 144:ef7eb2e8f9f7 163 (+) Get result of multimode conversion.
<> 144:ef7eb2e8f9f7 164 (+) Configure injected channels.
<> 144:ef7eb2e8f9f7 165 (+) Configure multimode.
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 @endverbatim
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @brief Enables the selected ADC software start conversion of the injected channels.
<> 144:ef7eb2e8f9f7 173 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 174 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 175 * @retval HAL status
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 __IO uint32_t counter = 0U;
<> 144:ef7eb2e8f9f7 180 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Process locked */
<> 144:ef7eb2e8f9f7 183 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Check if ADC peripheral is disabled in order to enable it and wait during
<> 144:ef7eb2e8f9f7 188 Tstab time the ADC's stabilization */
<> 144:ef7eb2e8f9f7 189 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 192 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Delay for ADC stabilization time */
<> 144:ef7eb2e8f9f7 195 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 196 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
<> 144:ef7eb2e8f9f7 197 while(counter != 0U)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 counter--;
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 204 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 /* Set ADC state */
<> 144:ef7eb2e8f9f7 207 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 208 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 209 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 210 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 211 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 214 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 215 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 216 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 217 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 220 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Process unlocked */
<> 144:ef7eb2e8f9f7 224 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 225 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 226 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 229 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 230 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Check if Multimode enabled */
<> 144:ef7eb2e8f9f7 233 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
<> 144:ef7eb2e8f9f7 236 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
<> 144:ef7eb2e8f9f7 237 if(tmp1 && tmp2)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 /* Enable the selected ADC software conversion for injected group */
<> 144:ef7eb2e8f9f7 240 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243 else
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
<> 144:ef7eb2e8f9f7 246 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
<> 144:ef7eb2e8f9f7 247 if((hadc->Instance == ADC1) && tmp1 && tmp2)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /* Enable the selected ADC software conversion for injected group */
<> 144:ef7eb2e8f9f7 250 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Return function status */
<> 144:ef7eb2e8f9f7 256 return HAL_OK;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief Enables the interrupt and starts ADC conversion of injected channels.
<> 144:ef7eb2e8f9f7 261 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 262 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * @retval HAL status.
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 __IO uint32_t counter = 0U;
<> 144:ef7eb2e8f9f7 269 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Process locked */
<> 144:ef7eb2e8f9f7 272 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Check if ADC peripheral is disabled in order to enable it and wait during
<> 144:ef7eb2e8f9f7 277 Tstab time the ADC's stabilization */
<> 144:ef7eb2e8f9f7 278 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 281 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Delay for ADC stabilization time */
<> 144:ef7eb2e8f9f7 284 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 285 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
<> 144:ef7eb2e8f9f7 286 while(counter != 0U)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 counter--;
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 293 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /* Set ADC state */
<> 144:ef7eb2e8f9f7 296 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 297 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 298 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 299 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 300 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 303 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 304 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 305 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 306 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 309 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Process unlocked */
<> 144:ef7eb2e8f9f7 313 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 314 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 315 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 318 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 319 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Enable end of conversion interrupt for injected channels */
AnnaBridge 167:e84263d55307 322 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Check if Multimode enabled */
<> 144:ef7eb2e8f9f7 325 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
<> 144:ef7eb2e8f9f7 328 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
<> 144:ef7eb2e8f9f7 329 if(tmp1 && tmp2)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 /* Enable the selected ADC software conversion for injected group */
<> 144:ef7eb2e8f9f7 332 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335 else
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
<> 144:ef7eb2e8f9f7 338 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
<> 144:ef7eb2e8f9f7 339 if((hadc->Instance == ADC1) && tmp1 && tmp2)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 /* Enable the selected ADC software conversion for injected group */
<> 144:ef7eb2e8f9f7 342 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Return function status */
<> 144:ef7eb2e8f9f7 348 return HAL_OK;
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @brief Stop conversion of injected channels. Disable ADC peripheral if
<> 144:ef7eb2e8f9f7 353 * no regular conversion is on going.
<> 144:ef7eb2e8f9f7 354 * @note If ADC must be disabled and if conversion is on going on
<> 144:ef7eb2e8f9f7 355 * regular group, function HAL_ADC_Stop must be used to stop both
<> 144:ef7eb2e8f9f7 356 * injected and regular groups, and disable the ADC.
<> 144:ef7eb2e8f9f7 357 * @note If injected group mode auto-injection is enabled,
<> 144:ef7eb2e8f9f7 358 * function HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 359 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 360 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 361 * @retval None
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 364 {
<> 144:ef7eb2e8f9f7 365 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Check the parameters */
<> 144:ef7eb2e8f9f7 368 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Process locked */
<> 144:ef7eb2e8f9f7 371 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Stop potential conversion and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 374 /* Conditioned to: */
<> 144:ef7eb2e8f9f7 375 /* - No conversion on the other group (regular group) is intended to */
<> 144:ef7eb2e8f9f7 376 /* continue (injected and regular groups stop conversion and ADC disable */
<> 144:ef7eb2e8f9f7 377 /* are common) */
<> 144:ef7eb2e8f9f7 378 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 379 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
<> 144:ef7eb2e8f9f7 380 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 383 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 384 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 387 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Set ADC state */
<> 144:ef7eb2e8f9f7 390 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 391 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 392 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 else
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 398 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Process unlocked */
<> 144:ef7eb2e8f9f7 404 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Return function status */
<> 144:ef7eb2e8f9f7 407 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @brief Poll for injected conversion complete
<> 144:ef7eb2e8f9f7 412 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 413 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 414 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 415 * @retval HAL status
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Get tick */
<> 144:ef7eb2e8f9f7 422 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Check End of conversion flag */
<> 144:ef7eb2e8f9f7 425 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 428 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 hadc->State= HAL_ADC_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 433 /* Process unlocked */
<> 144:ef7eb2e8f9f7 434 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 435 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 441 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 444 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Determine whether any further conversion upcoming on group injected */
<> 144:ef7eb2e8f9f7 447 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 448 /* Note: On STM32F2, there is no independent flag of end of sequence. */
<> 144:ef7eb2e8f9f7 449 /* The test of scan sequence on going is done either with scan */
<> 144:ef7eb2e8f9f7 450 /* sequence disabled or with end of conversion flag set to */
<> 144:ef7eb2e8f9f7 451 /* of end of sequence. */
<> 144:ef7eb2e8f9f7 452 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
<> 144:ef7eb2e8f9f7 453 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
<> 144:ef7eb2e8f9f7 454 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
<> 144:ef7eb2e8f9f7 455 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
<> 144:ef7eb2e8f9f7 456 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 457 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* Set ADC state */
<> 144:ef7eb2e8f9f7 460 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Return ADC state */
<> 144:ef7eb2e8f9f7 469 return HAL_OK;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @brief Stop conversion of injected channels, disable interruption of
<> 144:ef7eb2e8f9f7 474 * end-of-conversion. Disable ADC peripheral if no regular conversion
<> 144:ef7eb2e8f9f7 475 * is on going.
<> 144:ef7eb2e8f9f7 476 * @note If ADC must be disabled and if conversion is on going on
<> 144:ef7eb2e8f9f7 477 * regular group, function HAL_ADC_Stop must be used to stop both
<> 144:ef7eb2e8f9f7 478 * injected and regular groups, and disable the ADC.
<> 144:ef7eb2e8f9f7 479 * @note If injected group mode auto-injection is enabled,
<> 144:ef7eb2e8f9f7 480 * function HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 481 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 482 * @retval None
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Check the parameters */
<> 144:ef7eb2e8f9f7 489 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Process locked */
<> 144:ef7eb2e8f9f7 492 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Stop potential conversion and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 495 /* Conditioned to: */
<> 144:ef7eb2e8f9f7 496 /* - No conversion on the other group (regular group) is intended to */
<> 144:ef7eb2e8f9f7 497 /* continue (injected and regular groups stop conversion and ADC disable */
<> 144:ef7eb2e8f9f7 498 /* are common) */
<> 144:ef7eb2e8f9f7 499 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 500 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
<> 144:ef7eb2e8f9f7 501 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 504 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 505 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 508 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 /* Disable ADC end of conversion interrupt for injected channels */
AnnaBridge 167:e84263d55307 511 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Set ADC state */
<> 144:ef7eb2e8f9f7 514 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 515 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 516 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 else
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 522 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Process unlocked */
<> 144:ef7eb2e8f9f7 528 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Return function status */
<> 144:ef7eb2e8f9f7 531 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @brief Gets the converted value from data register of injected channel.
<> 144:ef7eb2e8f9f7 536 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 537 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 538 * @param InjectedRank: the ADC injected rank.
<> 144:ef7eb2e8f9f7 539 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 540 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
<> 144:ef7eb2e8f9f7 541 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
<> 144:ef7eb2e8f9f7 542 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
<> 144:ef7eb2e8f9f7 543 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
<> 144:ef7eb2e8f9f7 544 * @retval None
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Check the parameters */
<> 144:ef7eb2e8f9f7 551 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Clear injected group conversion flag to have similar behaviour as */
<> 144:ef7eb2e8f9f7 554 /* regular group: reading data register also clears end of conversion flag. */
<> 144:ef7eb2e8f9f7 555 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Return the selected ADC converted value */
<> 144:ef7eb2e8f9f7 558 switch(InjectedRank)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 case ADC_INJECTED_RANK_4:
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 tmp = hadc->Instance->JDR4;
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564 break;
<> 144:ef7eb2e8f9f7 565 case ADC_INJECTED_RANK_3:
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 tmp = hadc->Instance->JDR3;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569 break;
<> 144:ef7eb2e8f9f7 570 case ADC_INJECTED_RANK_2:
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 tmp = hadc->Instance->JDR2;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 break;
<> 144:ef7eb2e8f9f7 575 case ADC_INJECTED_RANK_1:
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 tmp = hadc->Instance->JDR1;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 break;
<> 144:ef7eb2e8f9f7 580 default:
<> 144:ef7eb2e8f9f7 581 break;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 return tmp;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
<> 144:ef7eb2e8f9f7 588 *
<> 144:ef7eb2e8f9f7 589 * @note Caution: This function must be used only with the ADC master.
<> 144:ef7eb2e8f9f7 590 *
<> 144:ef7eb2e8f9f7 591 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 592 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 593 * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
<> 144:ef7eb2e8f9f7 594 * @param Length: The length of data to be transferred from ADC peripheral to memory.
<> 144:ef7eb2e8f9f7 595 * @retval HAL status
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 __IO uint32_t counter = 0U;
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Check the parameters */
<> 144:ef7eb2e8f9f7 602 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 603 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<> 144:ef7eb2e8f9f7 604 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Process locked */
<> 144:ef7eb2e8f9f7 607 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Check if ADC peripheral is disabled in order to enable it and wait during
<> 144:ef7eb2e8f9f7 610 Tstab time the ADC's stabilization */
<> 144:ef7eb2e8f9f7 611 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 614 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 617 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 618 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
<> 144:ef7eb2e8f9f7 619 while(counter != 0U)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 counter--;
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623 }
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 626 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 /* Set ADC state */
<> 144:ef7eb2e8f9f7 629 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 630 /* - Set state bitfield related to regular group operation */
<> 144:ef7eb2e8f9f7 631 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 632 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
<> 144:ef7eb2e8f9f7 633 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 636 /* update ADC state. */
<> 144:ef7eb2e8f9f7 637 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 643 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 /* Reset ADC error code fields related to conversions on group regular */
<> 144:ef7eb2e8f9f7 646 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 else
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 651 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Process unlocked */
<> 144:ef7eb2e8f9f7 655 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 656 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 657 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 660 hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 663 hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 666 hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 669 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 672 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 673 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 676 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 if (hadc->Init.DMAContinuousRequests != DISABLE)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 /* Enable the selected ADC DMA request after last transfer */
<> 144:ef7eb2e8f9f7 681 ADC->CCR |= ADC_CCR_DDS;
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683 else
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 /* Disable the selected ADC EOC rising on each regular channel conversion */
<> 144:ef7eb2e8f9f7 686 ADC->CCR &= ~ADC_CCR_DDS;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 690 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* if no external trigger present enable software conversion of regular channels */
<> 144:ef7eb2e8f9f7 693 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Enable the selected ADC software conversion for regular group */
<> 144:ef7eb2e8f9f7 696 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Return function status */
<> 144:ef7eb2e8f9f7 701 return HAL_OK;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /**
<> 144:ef7eb2e8f9f7 705 * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
<> 144:ef7eb2e8f9f7 706 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 707 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 708 * @retval HAL status
<> 144:ef7eb2e8f9f7 709 */
<> 144:ef7eb2e8f9f7 710 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Check the parameters */
<> 144:ef7eb2e8f9f7 715 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /* Process locked */
<> 144:ef7eb2e8f9f7 718 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 721 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 722 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 725 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 /* Disable the selected ADC DMA mode for multimode */
<> 144:ef7eb2e8f9f7 728 ADC->CCR &= ~ADC_CCR_DDS;
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 731 /* DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 732 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 735 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Set ADC state */
<> 144:ef7eb2e8f9f7 738 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 739 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 740 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Process unlocked */
<> 144:ef7eb2e8f9f7 744 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Return function status */
<> 144:ef7eb2e8f9f7 747 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /**
<> 144:ef7eb2e8f9f7 751 * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
<> 144:ef7eb2e8f9f7 752 * data in the selected multi mode.
<> 144:ef7eb2e8f9f7 753 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 754 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 755 * @retval The converted data value.
<> 144:ef7eb2e8f9f7 756 */
<> 144:ef7eb2e8f9f7 757 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 758 {
AnnaBridge 167:e84263d55307 759 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 760 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 761 /* Return the multi mode conversion value */
<> 144:ef7eb2e8f9f7 762 return ADC->CDR;
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /**
<> 144:ef7eb2e8f9f7 766 * @brief Injected conversion complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 767 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 768 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 769 * @retval None
<> 144:ef7eb2e8f9f7 770 */
<> 144:ef7eb2e8f9f7 771 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 774 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 775 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 776 the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /**
<> 144:ef7eb2e8f9f7 781 * @brief Configures for the selected ADC injected channel its corresponding
<> 144:ef7eb2e8f9f7 782 * rank in the sequencer and its sample time.
<> 144:ef7eb2e8f9f7 783 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 784 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 785 * @param sConfigInjected: ADC configuration structure for injected channel.
<> 144:ef7eb2e8f9f7 786 * @retval None
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 792 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 793 #endif /* USE_FULL_ASSERT */
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Check the parameters */
<> 144:ef7eb2e8f9f7 796 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 797 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
<> 144:ef7eb2e8f9f7 798 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
<> 144:ef7eb2e8f9f7 799 assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
<> 144:ef7eb2e8f9f7 800 assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
<> 144:ef7eb2e8f9f7 801 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
<> 144:ef7eb2e8f9f7 802 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 805 tmp = ADC_GET_RESOLUTION(hadc);
<> 144:ef7eb2e8f9f7 806 assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
<> 144:ef7eb2e8f9f7 807 #endif /* USE_FULL_ASSERT */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Process locked */
<> 144:ef7eb2e8f9f7 815 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
<> 144:ef7eb2e8f9f7 818 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
<> 144:ef7eb2e8f9f7 819 {
<> 144:ef7eb2e8f9f7 820 /* Clear the old sample time */
<> 144:ef7eb2e8f9f7 821 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Set the new sample time */
<> 144:ef7eb2e8f9f7 824 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 else /* ADC_Channel include in ADC_Channel_[0..9] */
<> 144:ef7eb2e8f9f7 827 {
<> 144:ef7eb2e8f9f7 828 /* Clear the old sample time */
<> 144:ef7eb2e8f9f7 829 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Set the new sample time */
<> 144:ef7eb2e8f9f7 832 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /*---------------------------- ADCx JSQR Configuration -----------------*/
<> 144:ef7eb2e8f9f7 836 hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
<> 144:ef7eb2e8f9f7 837 hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Rank configuration */
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Clear the old SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 842 hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Set the SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 845 hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Enable external trigger if trigger selection is different of software */
<> 144:ef7eb2e8f9f7 848 /* start. */
<> 144:ef7eb2e8f9f7 849 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 850 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 851 /* software start. */
<> 144:ef7eb2e8f9f7 852 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 853 {
<> 144:ef7eb2e8f9f7 854 /* Select external trigger to start conversion */
<> 144:ef7eb2e8f9f7 855 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
<> 144:ef7eb2e8f9f7 856 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Select external trigger polarity */
<> 144:ef7eb2e8f9f7 859 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
<> 144:ef7eb2e8f9f7 860 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862 else
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 /* Reset the external trigger */
<> 144:ef7eb2e8f9f7 865 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
<> 144:ef7eb2e8f9f7 866 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 if (sConfigInjected->AutoInjectedConv != DISABLE)
<> 144:ef7eb2e8f9f7 870 {
<> 144:ef7eb2e8f9f7 871 /* Enable the selected ADC automatic injected group conversion */
<> 144:ef7eb2e8f9f7 872 hadc->Instance->CR1 |= ADC_CR1_JAUTO;
<> 144:ef7eb2e8f9f7 873 }
<> 144:ef7eb2e8f9f7 874 else
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 /* Disable the selected ADC automatic injected group conversion */
<> 144:ef7eb2e8f9f7 877 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
<> 144:ef7eb2e8f9f7 878 }
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 /* Enable the selected ADC injected discontinuous mode */
<> 144:ef7eb2e8f9f7 883 hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
<> 144:ef7eb2e8f9f7 884 }
<> 144:ef7eb2e8f9f7 885 else
<> 144:ef7eb2e8f9f7 886 {
<> 144:ef7eb2e8f9f7 887 /* Disable the selected ADC injected discontinuous mode */
<> 144:ef7eb2e8f9f7 888 hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
<> 144:ef7eb2e8f9f7 889 }
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 switch(sConfigInjected->InjectedRank)
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 case 1:
<> 144:ef7eb2e8f9f7 894 /* Set injected channel 1 offset */
<> 144:ef7eb2e8f9f7 895 hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
<> 144:ef7eb2e8f9f7 896 hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
<> 144:ef7eb2e8f9f7 897 break;
<> 144:ef7eb2e8f9f7 898 case 2:
<> 144:ef7eb2e8f9f7 899 /* Set injected channel 2 offset */
<> 144:ef7eb2e8f9f7 900 hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
<> 144:ef7eb2e8f9f7 901 hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
<> 144:ef7eb2e8f9f7 902 break;
<> 144:ef7eb2e8f9f7 903 case 3:
<> 144:ef7eb2e8f9f7 904 /* Set injected channel 3 offset */
<> 144:ef7eb2e8f9f7 905 hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
<> 144:ef7eb2e8f9f7 906 hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
<> 144:ef7eb2e8f9f7 907 break;
<> 144:ef7eb2e8f9f7 908 default:
<> 144:ef7eb2e8f9f7 909 /* Set injected channel 4 offset */
<> 144:ef7eb2e8f9f7 910 hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
<> 144:ef7eb2e8f9f7 911 hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
<> 144:ef7eb2e8f9f7 912 break;
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* if ADC1 Channel_18 is selected enable VBAT Channel */
<> 144:ef7eb2e8f9f7 916 if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 /* Enable the VBAT channel*/
<> 144:ef7eb2e8f9f7 919 ADC->CCR |= ADC_CCR_VBATE;
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
<> 144:ef7eb2e8f9f7 923 if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 /* Enable the TSVREFE channel*/
<> 144:ef7eb2e8f9f7 926 ADC->CCR |= ADC_CCR_TSVREFE;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Process unlocked */
<> 144:ef7eb2e8f9f7 930 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Return function status */
<> 144:ef7eb2e8f9f7 933 return HAL_OK;
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /**
<> 144:ef7eb2e8f9f7 937 * @brief Configures the ADC multi-mode
<> 144:ef7eb2e8f9f7 938 * @param hadc : pointer to a ADC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 939 * the configuration information for the specified ADC.
<> 144:ef7eb2e8f9f7 940 * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains
<> 144:ef7eb2e8f9f7 941 * the configuration information for multimode.
<> 144:ef7eb2e8f9f7 942 * @retval HAL status
<> 144:ef7eb2e8f9f7 943 */
<> 144:ef7eb2e8f9f7 944 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
<> 144:ef7eb2e8f9f7 945 {
<> 144:ef7eb2e8f9f7 946 /* Check the parameters */
<> 144:ef7eb2e8f9f7 947 assert_param(IS_ADC_MODE(multimode->Mode));
<> 144:ef7eb2e8f9f7 948 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
<> 144:ef7eb2e8f9f7 949 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /* Process locked */
<> 144:ef7eb2e8f9f7 952 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Set ADC mode */
<> 144:ef7eb2e8f9f7 955 ADC->CCR &= ~(ADC_CCR_MULTI);
<> 144:ef7eb2e8f9f7 956 ADC->CCR |= multimode->Mode;
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /* Set the ADC DMA access mode */
<> 144:ef7eb2e8f9f7 959 ADC->CCR &= ~(ADC_CCR_DMA);
<> 144:ef7eb2e8f9f7 960 ADC->CCR |= multimode->DMAAccessMode;
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 /* Set delay between two sampling phases */
<> 144:ef7eb2e8f9f7 963 ADC->CCR &= ~(ADC_CCR_DELAY);
<> 144:ef7eb2e8f9f7 964 ADC->CCR |= multimode->TwoSamplingDelay;
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 /* Process unlocked */
<> 144:ef7eb2e8f9f7 967 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /* Return function status */
<> 144:ef7eb2e8f9f7 970 return HAL_OK;
<> 144:ef7eb2e8f9f7 971 }
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /**
<> 144:ef7eb2e8f9f7 974 * @}
<> 144:ef7eb2e8f9f7 975 */
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 979 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 980 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 981 * @retval None
<> 144:ef7eb2e8f9f7 982 */
<> 144:ef7eb2e8f9f7 983 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 986 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 989 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 992 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 995 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 996 /* Note: On STM32F2, there is no independent flag of end of sequence. */
<> 144:ef7eb2e8f9f7 997 /* The test of scan sequence on going is done either with scan */
<> 144:ef7eb2e8f9f7 998 /* sequence disabled or with end of conversion flag set to */
<> 144:ef7eb2e8f9f7 999 /* of end of sequence. */
<> 144:ef7eb2e8f9f7 1000 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1001 (hadc->Init.ContinuousConvMode == DISABLE) &&
<> 144:ef7eb2e8f9f7 1002 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
<> 144:ef7eb2e8f9f7 1003 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 /* Disable ADC end of single conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 1006 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 1007 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 1008 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 1009 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1012 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1021 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 1022 }
<> 144:ef7eb2e8f9f7 1023 else
<> 144:ef7eb2e8f9f7 1024 {
<> 144:ef7eb2e8f9f7 1025 /* Call DMA error callback */
<> 144:ef7eb2e8f9f7 1026 hadc->DMA_Handle->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 1027 }
<> 144:ef7eb2e8f9f7 1028 }
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /**
<> 144:ef7eb2e8f9f7 1031 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 1032 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1033 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1034 * @retval None
<> 144:ef7eb2e8f9f7 1035 */
<> 144:ef7eb2e8f9f7 1036 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1039 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1040 HAL_ADC_ConvHalfCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /**
<> 144:ef7eb2e8f9f7 1044 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 1045 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1046 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1047 * @retval None
<> 144:ef7eb2e8f9f7 1048 */
<> 144:ef7eb2e8f9f7 1049 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1052 hadc->State= HAL_ADC_STATE_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1053 /* Set ADC error code to DMA error */
<> 144:ef7eb2e8f9f7 1054 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1055 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 1056 }
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 /**
<> 144:ef7eb2e8f9f7 1059 * @}
<> 144:ef7eb2e8f9f7 1060 */
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 #endif /* HAL_ADC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1063 /**
<> 144:ef7eb2e8f9f7 1064 * @}
<> 144:ef7eb2e8f9f7 1065 */
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /**
<> 144:ef7eb2e8f9f7 1068 * @}
<> 144:ef7eb2e8f9f7 1069 */
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/