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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /**
<> 154:37f96f9d4de2 2 ******************************************************************************
<> 154:37f96f9d4de2 3 * @file stm32f1xx_ll_utils.h
<> 154:37f96f9d4de2 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @brief Header file of UTILS LL module.
<> 154:37f96f9d4de2 6 @verbatim
<> 154:37f96f9d4de2 7 ==============================================================================
<> 154:37f96f9d4de2 8 ##### How to use this driver #####
<> 154:37f96f9d4de2 9 ==============================================================================
<> 154:37f96f9d4de2 10 [..]
<> 154:37f96f9d4de2 11 The LL UTILS driver contains a set of generic APIs that can be
<> 154:37f96f9d4de2 12 used by user:
<> 154:37f96f9d4de2 13 (+) Device electronic signature
<> 154:37f96f9d4de2 14 (+) Timing functions
<> 154:37f96f9d4de2 15 (+) PLL configuration functions
<> 154:37f96f9d4de2 16
<> 154:37f96f9d4de2 17 @endverbatim
<> 154:37f96f9d4de2 18 ******************************************************************************
<> 154:37f96f9d4de2 19 * @attention
<> 154:37f96f9d4de2 20 *
<> 154:37f96f9d4de2 21 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 154:37f96f9d4de2 22 *
<> 154:37f96f9d4de2 23 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 24 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 25 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 26 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 27 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 28 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 29 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 30 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 31 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 32 * without specific prior written permission.
<> 154:37f96f9d4de2 33 *
<> 154:37f96f9d4de2 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 41 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 42 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 44 *
<> 154:37f96f9d4de2 45 ******************************************************************************
<> 154:37f96f9d4de2 46 */
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 /* Define to prevent recursive inclusion -------------------------------------*/
<> 154:37f96f9d4de2 49 #ifndef __STM32F1xx_LL_UTILS_H
<> 154:37f96f9d4de2 50 #define __STM32F1xx_LL_UTILS_H
<> 154:37f96f9d4de2 51
<> 154:37f96f9d4de2 52 #ifdef __cplusplus
<> 154:37f96f9d4de2 53 extern "C" {
<> 154:37f96f9d4de2 54 #endif
<> 154:37f96f9d4de2 55
<> 154:37f96f9d4de2 56 /* Includes ------------------------------------------------------------------*/
<> 154:37f96f9d4de2 57 #include "stm32f1xx.h"
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /** @addtogroup STM32F1xx_LL_Driver
<> 154:37f96f9d4de2 60 * @{
<> 154:37f96f9d4de2 61 */
<> 154:37f96f9d4de2 62
<> 154:37f96f9d4de2 63 /** @defgroup UTILS_LL UTILS
<> 154:37f96f9d4de2 64 * @{
<> 154:37f96f9d4de2 65 */
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 /* Private types -------------------------------------------------------------*/
<> 154:37f96f9d4de2 68 /* Private variables ---------------------------------------------------------*/
<> 154:37f96f9d4de2 69
<> 154:37f96f9d4de2 70 /* Private constants ---------------------------------------------------------*/
<> 154:37f96f9d4de2 71 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
<> 154:37f96f9d4de2 72 * @{
<> 154:37f96f9d4de2 73 */
<> 154:37f96f9d4de2 74
<> 154:37f96f9d4de2 75 /* Max delay can be used in LL_mDelay */
<> 154:37f96f9d4de2 76 #define LL_MAX_DELAY 0xFFFFFFFFU
<> 154:37f96f9d4de2 77
<> 154:37f96f9d4de2 78 /**
<> 154:37f96f9d4de2 79 * @brief Unique device ID register base address
<> 154:37f96f9d4de2 80 */
<> 154:37f96f9d4de2 81 #define UID_BASE_ADDRESS UID_BASE
<> 154:37f96f9d4de2 82
<> 154:37f96f9d4de2 83 /**
<> 154:37f96f9d4de2 84 * @brief Flash size data register base address
<> 154:37f96f9d4de2 85 */
<> 154:37f96f9d4de2 86 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
<> 154:37f96f9d4de2 87
<> 154:37f96f9d4de2 88 /**
<> 154:37f96f9d4de2 89 * @}
<> 154:37f96f9d4de2 90 */
<> 154:37f96f9d4de2 91
<> 154:37f96f9d4de2 92 /* Private macros ------------------------------------------------------------*/
<> 154:37f96f9d4de2 93 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
<> 154:37f96f9d4de2 94 * @{
<> 154:37f96f9d4de2 95 */
<> 154:37f96f9d4de2 96 /**
<> 154:37f96f9d4de2 97 * @}
<> 154:37f96f9d4de2 98 */
<> 154:37f96f9d4de2 99 /* Exported types ------------------------------------------------------------*/
<> 154:37f96f9d4de2 100 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
<> 154:37f96f9d4de2 101 * @{
<> 154:37f96f9d4de2 102 */
<> 154:37f96f9d4de2 103 /**
<> 154:37f96f9d4de2 104 * @brief UTILS PLL structure definition
<> 154:37f96f9d4de2 105 */
<> 154:37f96f9d4de2 106 typedef struct
<> 154:37f96f9d4de2 107 {
<> 154:37f96f9d4de2 108 uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
<> 154:37f96f9d4de2 109 This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
<> 154:37f96f9d4de2 110
<> 154:37f96f9d4de2 111 This feature can be modified afterwards using unitary function
<> 154:37f96f9d4de2 112 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 154:37f96f9d4de2 113
<> 154:37f96f9d4de2 114 uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
<> 154:37f96f9d4de2 115 This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
<> 154:37f96f9d4de2 116
<> 154:37f96f9d4de2 117 This feature can be modified afterwards using unitary function
<> 154:37f96f9d4de2 118 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 154:37f96f9d4de2 119 } LL_UTILS_PLLInitTypeDef;
<> 154:37f96f9d4de2 120
<> 154:37f96f9d4de2 121 /**
<> 154:37f96f9d4de2 122 * @brief UTILS System, AHB and APB buses clock configuration structure definition
<> 154:37f96f9d4de2 123 */
<> 154:37f96f9d4de2 124 typedef struct
<> 154:37f96f9d4de2 125 {
<> 154:37f96f9d4de2 126 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<> 154:37f96f9d4de2 127 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 This feature can be modified afterwards using unitary function
<> 154:37f96f9d4de2 130 @ref LL_RCC_SetAHBPrescaler(). */
<> 154:37f96f9d4de2 131
<> 154:37f96f9d4de2 132 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<> 154:37f96f9d4de2 133 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
<> 154:37f96f9d4de2 134
<> 154:37f96f9d4de2 135 This feature can be modified afterwards using unitary function
<> 154:37f96f9d4de2 136 @ref LL_RCC_SetAPB1Prescaler(). */
<> 154:37f96f9d4de2 137
<> 154:37f96f9d4de2 138 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<> 154:37f96f9d4de2 139 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
<> 154:37f96f9d4de2 140
<> 154:37f96f9d4de2 141 This feature can be modified afterwards using unitary function
<> 154:37f96f9d4de2 142 @ref LL_RCC_SetAPB2Prescaler(). */
<> 154:37f96f9d4de2 143
<> 154:37f96f9d4de2 144 } LL_UTILS_ClkInitTypeDef;
<> 154:37f96f9d4de2 145
<> 154:37f96f9d4de2 146 /**
<> 154:37f96f9d4de2 147 * @}
<> 154:37f96f9d4de2 148 */
<> 154:37f96f9d4de2 149
<> 154:37f96f9d4de2 150 /* Exported constants --------------------------------------------------------*/
<> 154:37f96f9d4de2 151 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
<> 154:37f96f9d4de2 152 * @{
<> 154:37f96f9d4de2 153 */
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
<> 154:37f96f9d4de2 156 * @{
<> 154:37f96f9d4de2 157 */
<> 154:37f96f9d4de2 158 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
<> 154:37f96f9d4de2 159 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
<> 154:37f96f9d4de2 160 /**
<> 154:37f96f9d4de2 161 * @}
<> 154:37f96f9d4de2 162 */
<> 154:37f96f9d4de2 163
<> 154:37f96f9d4de2 164 /**
<> 154:37f96f9d4de2 165 * @}
<> 154:37f96f9d4de2 166 */
<> 154:37f96f9d4de2 167
<> 154:37f96f9d4de2 168 /* Exported macro ------------------------------------------------------------*/
<> 154:37f96f9d4de2 169
<> 154:37f96f9d4de2 170 /* Exported functions --------------------------------------------------------*/
<> 154:37f96f9d4de2 171 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
<> 154:37f96f9d4de2 172 * @{
<> 154:37f96f9d4de2 173 */
<> 154:37f96f9d4de2 174
<> 154:37f96f9d4de2 175 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
<> 154:37f96f9d4de2 176 * @{
<> 154:37f96f9d4de2 177 */
<> 154:37f96f9d4de2 178
<> 154:37f96f9d4de2 179 /**
<> 154:37f96f9d4de2 180 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
<> 154:37f96f9d4de2 181 * @retval UID[31:0]
<> 154:37f96f9d4de2 182 */
<> 154:37f96f9d4de2 183 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
<> 154:37f96f9d4de2 184 {
<> 154:37f96f9d4de2 185 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
<> 154:37f96f9d4de2 186 }
<> 154:37f96f9d4de2 187
<> 154:37f96f9d4de2 188 /**
<> 154:37f96f9d4de2 189 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
<> 154:37f96f9d4de2 190 * @retval UID[63:32]
<> 154:37f96f9d4de2 191 */
<> 154:37f96f9d4de2 192 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
<> 154:37f96f9d4de2 193 {
<> 154:37f96f9d4de2 194 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
<> 154:37f96f9d4de2 195 }
<> 154:37f96f9d4de2 196
<> 154:37f96f9d4de2 197 /**
<> 154:37f96f9d4de2 198 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
<> 154:37f96f9d4de2 199 * @retval UID[95:64]
<> 154:37f96f9d4de2 200 */
<> 154:37f96f9d4de2 201 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
<> 154:37f96f9d4de2 202 {
<> 154:37f96f9d4de2 203 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
<> 154:37f96f9d4de2 204 }
<> 154:37f96f9d4de2 205
<> 154:37f96f9d4de2 206 /**
<> 154:37f96f9d4de2 207 * @brief Get Flash memory size
<> 154:37f96f9d4de2 208 * @note This bitfield indicates the size of the device Flash memory expressed in
<> 154:37f96f9d4de2 209 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
<> 154:37f96f9d4de2 210 * @retval FLASH_SIZE[15:0]: Flash memory size
<> 154:37f96f9d4de2 211 */
<> 154:37f96f9d4de2 212 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
<> 154:37f96f9d4de2 213 {
<> 154:37f96f9d4de2 214 return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
<> 154:37f96f9d4de2 215 }
<> 154:37f96f9d4de2 216
<> 154:37f96f9d4de2 217
<> 154:37f96f9d4de2 218 /**
<> 154:37f96f9d4de2 219 * @}
<> 154:37f96f9d4de2 220 */
<> 154:37f96f9d4de2 221
<> 154:37f96f9d4de2 222 /** @defgroup UTILS_LL_EF_DELAY DELAY
<> 154:37f96f9d4de2 223 * @{
<> 154:37f96f9d4de2 224 */
<> 154:37f96f9d4de2 225
<> 154:37f96f9d4de2 226 /**
<> 154:37f96f9d4de2 227 * @brief This function configures the Cortex-M SysTick source of the time base.
<> 154:37f96f9d4de2 228 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<> 154:37f96f9d4de2 229 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
<> 154:37f96f9d4de2 230 * configuration by calling this function, for a delay use rather osDelay RTOS service.
<> 154:37f96f9d4de2 231 * @param Ticks Number of ticks
<> 154:37f96f9d4de2 232 * @retval None
<> 154:37f96f9d4de2 233 */
<> 154:37f96f9d4de2 234 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
<> 154:37f96f9d4de2 235 {
<> 154:37f96f9d4de2 236 /* Configure the SysTick to have interrupt in 1ms time base */
<> 154:37f96f9d4de2 237 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
<> 154:37f96f9d4de2 238 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 154:37f96f9d4de2 239 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 154:37f96f9d4de2 240 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
<> 154:37f96f9d4de2 241 }
<> 154:37f96f9d4de2 242
<> 154:37f96f9d4de2 243 void LL_Init1msTick(uint32_t HCLKFrequency);
<> 154:37f96f9d4de2 244 void LL_mDelay(uint32_t Delay);
<> 154:37f96f9d4de2 245
<> 154:37f96f9d4de2 246 /**
<> 154:37f96f9d4de2 247 * @}
<> 154:37f96f9d4de2 248 */
<> 154:37f96f9d4de2 249
<> 154:37f96f9d4de2 250 /** @defgroup UTILS_EF_SYSTEM SYSTEM
<> 154:37f96f9d4de2 251 * @{
<> 154:37f96f9d4de2 252 */
<> 154:37f96f9d4de2 253
<> 154:37f96f9d4de2 254 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
<> 154:37f96f9d4de2 255 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 154:37f96f9d4de2 256 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 154:37f96f9d4de2 257 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<> 154:37f96f9d4de2 258 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 154:37f96f9d4de2 259
<> 154:37f96f9d4de2 260 /**
<> 154:37f96f9d4de2 261 * @}
<> 154:37f96f9d4de2 262 */
<> 154:37f96f9d4de2 263
<> 154:37f96f9d4de2 264 /**
<> 154:37f96f9d4de2 265 * @}
<> 154:37f96f9d4de2 266 */
<> 154:37f96f9d4de2 267
<> 154:37f96f9d4de2 268 /**
<> 154:37f96f9d4de2 269 * @}
<> 154:37f96f9d4de2 270 */
<> 154:37f96f9d4de2 271
<> 154:37f96f9d4de2 272 /**
<> 154:37f96f9d4de2 273 * @}
<> 154:37f96f9d4de2 274 */
<> 154:37f96f9d4de2 275
<> 154:37f96f9d4de2 276 #ifdef __cplusplus
<> 154:37f96f9d4de2 277 }
<> 154:37f96f9d4de2 278 #endif
<> 154:37f96f9d4de2 279
<> 154:37f96f9d4de2 280 #endif /* __STM32F1xx_LL_UTILS_H */
<> 154:37f96f9d4de2 281
<> 154:37f96f9d4de2 282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/