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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:e614a9f1c9e2	1	/**
AnnaBridge	165:e614a9f1c9e2	2	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	3	* @file stm32f1xx_ll_tim.h
AnnaBridge	165:e614a9f1c9e2	4	* @author MCD Application Team
AnnaBridge	165:e614a9f1c9e2	5	* @brief Header file of TIM LL module.
AnnaBridge	165:e614a9f1c9e2	6	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	7	* @attention
AnnaBridge	165:e614a9f1c9e2	8	*
AnnaBridge	165:e614a9f1c9e2	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	165:e614a9f1c9e2	10	*
AnnaBridge	165:e614a9f1c9e2	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:e614a9f1c9e2	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:e614a9f1c9e2	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:e614a9f1c9e2	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:e614a9f1c9e2	17	* and/or other materials provided with the distribution.
AnnaBridge	165:e614a9f1c9e2	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:e614a9f1c9e2	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:e614a9f1c9e2	20	* without specific prior written permission.
AnnaBridge	165:e614a9f1c9e2	21	*
AnnaBridge	165:e614a9f1c9e2	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:e614a9f1c9e2	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:e614a9f1c9e2	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:e614a9f1c9e2	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:e614a9f1c9e2	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:e614a9f1c9e2	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:e614a9f1c9e2	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:e614a9f1c9e2	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:e614a9f1c9e2	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:e614a9f1c9e2	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:e614a9f1c9e2	32	*
AnnaBridge	165:e614a9f1c9e2	33	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	34	*/
AnnaBridge	165:e614a9f1c9e2	35
AnnaBridge	165:e614a9f1c9e2	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	37	#ifndef __STM32F1xx_LL_TIM_H
AnnaBridge	165:e614a9f1c9e2	38	#define __STM32F1xx_LL_TIM_H
AnnaBridge	165:e614a9f1c9e2	39
AnnaBridge	165:e614a9f1c9e2	40	#ifdef __cplusplus
AnnaBridge	165:e614a9f1c9e2	41	extern "C" {
AnnaBridge	165:e614a9f1c9e2	42	#endif
AnnaBridge	165:e614a9f1c9e2	43
AnnaBridge	165:e614a9f1c9e2	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	45	#include "stm32f1xx.h"
AnnaBridge	165:e614a9f1c9e2	46
AnnaBridge	165:e614a9f1c9e2	47	/** @addtogroup STM32F1xx_LL_Driver
AnnaBridge	165:e614a9f1c9e2	48	* @{
AnnaBridge	165:e614a9f1c9e2	49	*/
AnnaBridge	165:e614a9f1c9e2	50
AnnaBridge	165:e614a9f1c9e2	51	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17)
AnnaBridge	165:e614a9f1c9e2	52
AnnaBridge	165:e614a9f1c9e2	53	/** @defgroup TIM_LL TIM
AnnaBridge	165:e614a9f1c9e2	54	* @{
AnnaBridge	165:e614a9f1c9e2	55	*/
AnnaBridge	165:e614a9f1c9e2	56
AnnaBridge	165:e614a9f1c9e2	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	165:e614a9f1c9e2	60	* @{
AnnaBridge	165:e614a9f1c9e2	61	*/
AnnaBridge	165:e614a9f1c9e2	62	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	165:e614a9f1c9e2	63	{
AnnaBridge	165:e614a9f1c9e2	64	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	165:e614a9f1c9e2	65	0x00U, /* 1: TIMx_CH1N */
AnnaBridge	165:e614a9f1c9e2	66	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	165:e614a9f1c9e2	67	0x00U, /* 3: TIMx_CH2N */
AnnaBridge	165:e614a9f1c9e2	68	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	165:e614a9f1c9e2	69	0x04U, /* 5: TIMx_CH3N */
AnnaBridge	165:e614a9f1c9e2	70	0x04U /* 6: TIMx_CH4 */
AnnaBridge	165:e614a9f1c9e2	71	};
AnnaBridge	165:e614a9f1c9e2	72
AnnaBridge	165:e614a9f1c9e2	73	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	165:e614a9f1c9e2	74	{
AnnaBridge	165:e614a9f1c9e2	75	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	165:e614a9f1c9e2	76	0U, /* 1: - NA */
AnnaBridge	165:e614a9f1c9e2	77	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	165:e614a9f1c9e2	78	0U, /* 3: - NA */
AnnaBridge	165:e614a9f1c9e2	79	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	165:e614a9f1c9e2	80	0U, /* 5: - NA */
AnnaBridge	165:e614a9f1c9e2	81	8U /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	165:e614a9f1c9e2	82	};
AnnaBridge	165:e614a9f1c9e2	83
AnnaBridge	165:e614a9f1c9e2	84	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	165:e614a9f1c9e2	85	{
AnnaBridge	165:e614a9f1c9e2	86	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	165:e614a9f1c9e2	87	0U, /* 1: - NA */
AnnaBridge	165:e614a9f1c9e2	88	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	165:e614a9f1c9e2	89	0U, /* 3: - NA */
AnnaBridge	165:e614a9f1c9e2	90	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	165:e614a9f1c9e2	91	0U, /* 5: - NA */
AnnaBridge	165:e614a9f1c9e2	92	8U /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	165:e614a9f1c9e2	93	};
AnnaBridge	165:e614a9f1c9e2	94
AnnaBridge	165:e614a9f1c9e2	95	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	165:e614a9f1c9e2	96	{
AnnaBridge	165:e614a9f1c9e2	97	0U, /* 0: CC1P */
AnnaBridge	165:e614a9f1c9e2	98	2U, /* 1: CC1NP */
AnnaBridge	165:e614a9f1c9e2	99	4U, /* 2: CC2P */
AnnaBridge	165:e614a9f1c9e2	100	6U, /* 3: CC2NP */
AnnaBridge	165:e614a9f1c9e2	101	8U, /* 4: CC3P */
AnnaBridge	165:e614a9f1c9e2	102	10U, /* 5: CC3NP */
AnnaBridge	165:e614a9f1c9e2	103	12U /* 6: CC4P */
AnnaBridge	165:e614a9f1c9e2	104	};
AnnaBridge	165:e614a9f1c9e2	105
AnnaBridge	165:e614a9f1c9e2	106	static const uint8_t SHIFT_TAB_OISx[] =
AnnaBridge	165:e614a9f1c9e2	107	{
AnnaBridge	165:e614a9f1c9e2	108	0U, /* 0: OIS1 */
AnnaBridge	165:e614a9f1c9e2	109	1U, /* 1: OIS1N */
AnnaBridge	165:e614a9f1c9e2	110	2U, /* 2: OIS2 */
AnnaBridge	165:e614a9f1c9e2	111	3U, /* 3: OIS2N */
AnnaBridge	165:e614a9f1c9e2	112	4U, /* 4: OIS3 */
AnnaBridge	165:e614a9f1c9e2	113	5U, /* 5: OIS3N */
AnnaBridge	165:e614a9f1c9e2	114	6U /* 6: OIS4 */
AnnaBridge	165:e614a9f1c9e2	115	};
AnnaBridge	165:e614a9f1c9e2	116	/**
AnnaBridge	165:e614a9f1c9e2	117	* @}
AnnaBridge	165:e614a9f1c9e2	118	*/
AnnaBridge	165:e614a9f1c9e2	119
AnnaBridge	165:e614a9f1c9e2	120
AnnaBridge	165:e614a9f1c9e2	121	/* Private constants ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	122	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	165:e614a9f1c9e2	123	* @{
AnnaBridge	165:e614a9f1c9e2	124	*/
AnnaBridge	165:e614a9f1c9e2	125
AnnaBridge	165:e614a9f1c9e2	126
AnnaBridge	165:e614a9f1c9e2	127
AnnaBridge	165:e614a9f1c9e2	128	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
AnnaBridge	165:e614a9f1c9e2	129	#define DT_DELAY_1 ((uint8_t)0x7F)
AnnaBridge	165:e614a9f1c9e2	130	#define DT_DELAY_2 ((uint8_t)0x3F)
AnnaBridge	165:e614a9f1c9e2	131	#define DT_DELAY_3 ((uint8_t)0x1F)
AnnaBridge	165:e614a9f1c9e2	132	#define DT_DELAY_4 ((uint8_t)0x1F)
AnnaBridge	165:e614a9f1c9e2	133
AnnaBridge	165:e614a9f1c9e2	134	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
AnnaBridge	165:e614a9f1c9e2	135	#define DT_RANGE_1 ((uint8_t)0x00)
AnnaBridge	165:e614a9f1c9e2	136	#define DT_RANGE_2 ((uint8_t)0x80)
AnnaBridge	165:e614a9f1c9e2	137	#define DT_RANGE_3 ((uint8_t)0xC0)
AnnaBridge	165:e614a9f1c9e2	138	#define DT_RANGE_4 ((uint8_t)0xE0)
AnnaBridge	165:e614a9f1c9e2	139
AnnaBridge	165:e614a9f1c9e2	140
AnnaBridge	165:e614a9f1c9e2	141	/**
AnnaBridge	165:e614a9f1c9e2	142	* @}
AnnaBridge	165:e614a9f1c9e2	143	*/
AnnaBridge	165:e614a9f1c9e2	144
AnnaBridge	165:e614a9f1c9e2	145	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	146	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	165:e614a9f1c9e2	147	* @{
AnnaBridge	165:e614a9f1c9e2	148	*/
AnnaBridge	165:e614a9f1c9e2	149	/** @brief Convert channel id into channel index.
AnnaBridge	165:e614a9f1c9e2	150	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	151	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	152	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	153	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	154	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	155	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	156	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	157	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	158	* @retval none
AnnaBridge	165:e614a9f1c9e2	159	*/
AnnaBridge	165:e614a9f1c9e2	160	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	165:e614a9f1c9e2	161	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	165:e614a9f1c9e2	162	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	165:e614a9f1c9e2	163	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	165:e614a9f1c9e2	164	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	165:e614a9f1c9e2	165	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	165:e614a9f1c9e2	166	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
AnnaBridge	165:e614a9f1c9e2	167
AnnaBridge	165:e614a9f1c9e2	168	/** @brief Calculate the deadtime sampling period(in ps).
AnnaBridge	165:e614a9f1c9e2	169	* @param __TIMCLK__ timer input clock frequency (in Hz).
AnnaBridge	165:e614a9f1c9e2	170	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	171	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:e614a9f1c9e2	172	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:e614a9f1c9e2	173	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:e614a9f1c9e2	174	* @retval none
AnnaBridge	165:e614a9f1c9e2	175	*/
AnnaBridge	165:e614a9f1c9e2	176	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
AnnaBridge	165:e614a9f1c9e2	177	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
AnnaBridge	165:e614a9f1c9e2	178	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
AnnaBridge	165:e614a9f1c9e2	179	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
AnnaBridge	165:e614a9f1c9e2	180	/**
AnnaBridge	165:e614a9f1c9e2	181	* @}
AnnaBridge	165:e614a9f1c9e2	182	*/
AnnaBridge	165:e614a9f1c9e2	183
AnnaBridge	165:e614a9f1c9e2	184
AnnaBridge	165:e614a9f1c9e2	185	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	186	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	187	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	165:e614a9f1c9e2	188	* @{
AnnaBridge	165:e614a9f1c9e2	189	*/
AnnaBridge	165:e614a9f1c9e2	190
AnnaBridge	165:e614a9f1c9e2	191	/**
AnnaBridge	165:e614a9f1c9e2	192	* @brief TIM Time Base configuration structure definition.
AnnaBridge	165:e614a9f1c9e2	193	*/
AnnaBridge	165:e614a9f1c9e2	194	typedef struct
AnnaBridge	165:e614a9f1c9e2	195	{
AnnaBridge	165:e614a9f1c9e2	196	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	165:e614a9f1c9e2	197	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	165:e614a9f1c9e2	198
AnnaBridge	165:e614a9f1c9e2	199	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	165:e614a9f1c9e2	200
AnnaBridge	165:e614a9f1c9e2	201	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	165:e614a9f1c9e2	202	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	165:e614a9f1c9e2	203
AnnaBridge	165:e614a9f1c9e2	204	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	165:e614a9f1c9e2	205
AnnaBridge	165:e614a9f1c9e2	206	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	165:e614a9f1c9e2	207	Auto-Reload Register at the next update event.
AnnaBridge	165:e614a9f1c9e2	208	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	165:e614a9f1c9e2	209	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	165:e614a9f1c9e2	210
AnnaBridge	165:e614a9f1c9e2	211	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	165:e614a9f1c9e2	212
AnnaBridge	165:e614a9f1c9e2	213	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	165:e614a9f1c9e2	214	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	165:e614a9f1c9e2	215
AnnaBridge	165:e614a9f1c9e2	216	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	165:e614a9f1c9e2	217
AnnaBridge	165:e614a9f1c9e2	218	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	165:e614a9f1c9e2	219	reaches zero, an update event is generated and counting restarts
AnnaBridge	165:e614a9f1c9e2	220	from the RCR value (N).
AnnaBridge	165:e614a9f1c9e2	221	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	165:e614a9f1c9e2	222	- the number of PWM periods in edge-aligned mode
AnnaBridge	165:e614a9f1c9e2	223	- the number of half PWM period in center-aligned mode
AnnaBridge	165:e614a9f1c9e2	224	This parameter must be a number between 0x00 and 0xFF.
AnnaBridge	165:e614a9f1c9e2	225
AnnaBridge	165:e614a9f1c9e2	226	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
AnnaBridge	165:e614a9f1c9e2	227	} LL_TIM_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	228
AnnaBridge	165:e614a9f1c9e2	229	/**
AnnaBridge	165:e614a9f1c9e2	230	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	165:e614a9f1c9e2	231	*/
AnnaBridge	165:e614a9f1c9e2	232	typedef struct
AnnaBridge	165:e614a9f1c9e2	233	{
AnnaBridge	165:e614a9f1c9e2	234	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	165:e614a9f1c9e2	235	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	165:e614a9f1c9e2	236
AnnaBridge	165:e614a9f1c9e2	237	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	165:e614a9f1c9e2	238
AnnaBridge	165:e614a9f1c9e2	239	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	165:e614a9f1c9e2	240	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	165:e614a9f1c9e2	241
AnnaBridge	165:e614a9f1c9e2	242	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	165:e614a9f1c9e2	243
AnnaBridge	165:e614a9f1c9e2	244	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
AnnaBridge	165:e614a9f1c9e2	245	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	165:e614a9f1c9e2	246
AnnaBridge	165:e614a9f1c9e2	247	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	165:e614a9f1c9e2	248
AnnaBridge	165:e614a9f1c9e2	249	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	165:e614a9f1c9e2	250	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	165:e614a9f1c9e2	251
AnnaBridge	165:e614a9f1c9e2	252	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	165:e614a9f1c9e2	253
AnnaBridge	165:e614a9f1c9e2	254	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	165:e614a9f1c9e2	255	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	165:e614a9f1c9e2	256
AnnaBridge	165:e614a9f1c9e2	257	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	165:e614a9f1c9e2	258
AnnaBridge	165:e614a9f1c9e2	259	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	165:e614a9f1c9e2	260	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	165:e614a9f1c9e2	261
AnnaBridge	165:e614a9f1c9e2	262	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	165:e614a9f1c9e2	263
AnnaBridge	165:e614a9f1c9e2	264
AnnaBridge	165:e614a9f1c9e2	265	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	165:e614a9f1c9e2	266	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	165:e614a9f1c9e2	267
AnnaBridge	165:e614a9f1c9e2	268	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	165:e614a9f1c9e2	269
AnnaBridge	165:e614a9f1c9e2	270	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	165:e614a9f1c9e2	271	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	165:e614a9f1c9e2	272
AnnaBridge	165:e614a9f1c9e2	273	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	165:e614a9f1c9e2	274	} LL_TIM_OC_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	275
AnnaBridge	165:e614a9f1c9e2	276	/**
AnnaBridge	165:e614a9f1c9e2	277	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	165:e614a9f1c9e2	278	*/
AnnaBridge	165:e614a9f1c9e2	279
AnnaBridge	165:e614a9f1c9e2	280	typedef struct
AnnaBridge	165:e614a9f1c9e2	281	{
AnnaBridge	165:e614a9f1c9e2	282
AnnaBridge	165:e614a9f1c9e2	283	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	165:e614a9f1c9e2	284	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:e614a9f1c9e2	285
AnnaBridge	165:e614a9f1c9e2	286	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:e614a9f1c9e2	287
AnnaBridge	165:e614a9f1c9e2	288	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	165:e614a9f1c9e2	289	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	165:e614a9f1c9e2	290
AnnaBridge	165:e614a9f1c9e2	291	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	165:e614a9f1c9e2	292
AnnaBridge	165:e614a9f1c9e2	293	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	165:e614a9f1c9e2	294	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:e614a9f1c9e2	295
AnnaBridge	165:e614a9f1c9e2	296	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:e614a9f1c9e2	297
AnnaBridge	165:e614a9f1c9e2	298	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	165:e614a9f1c9e2	299	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:e614a9f1c9e2	300
AnnaBridge	165:e614a9f1c9e2	301	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:e614a9f1c9e2	302	} LL_TIM_IC_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	303
AnnaBridge	165:e614a9f1c9e2	304
AnnaBridge	165:e614a9f1c9e2	305	/**
AnnaBridge	165:e614a9f1c9e2	306	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	165:e614a9f1c9e2	307	*/
AnnaBridge	165:e614a9f1c9e2	308	typedef struct
AnnaBridge	165:e614a9f1c9e2	309	{
AnnaBridge	165:e614a9f1c9e2	310	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	165:e614a9f1c9e2	311	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	165:e614a9f1c9e2	312
AnnaBridge	165:e614a9f1c9e2	313	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	165:e614a9f1c9e2	314
AnnaBridge	165:e614a9f1c9e2	315	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	165:e614a9f1c9e2	316	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:e614a9f1c9e2	317
AnnaBridge	165:e614a9f1c9e2	318	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:e614a9f1c9e2	319
AnnaBridge	165:e614a9f1c9e2	320	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	165:e614a9f1c9e2	321	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	165:e614a9f1c9e2	322
AnnaBridge	165:e614a9f1c9e2	323	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	165:e614a9f1c9e2	324
AnnaBridge	165:e614a9f1c9e2	325	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	165:e614a9f1c9e2	326	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:e614a9f1c9e2	327
AnnaBridge	165:e614a9f1c9e2	328	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:e614a9f1c9e2	329
AnnaBridge	165:e614a9f1c9e2	330	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	165:e614a9f1c9e2	331	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:e614a9f1c9e2	332
AnnaBridge	165:e614a9f1c9e2	333	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:e614a9f1c9e2	334
AnnaBridge	165:e614a9f1c9e2	335	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	165:e614a9f1c9e2	336	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:e614a9f1c9e2	337
AnnaBridge	165:e614a9f1c9e2	338	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:e614a9f1c9e2	339
AnnaBridge	165:e614a9f1c9e2	340	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	165:e614a9f1c9e2	341	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	165:e614a9f1c9e2	342
AnnaBridge	165:e614a9f1c9e2	343	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	165:e614a9f1c9e2	344
AnnaBridge	165:e614a9f1c9e2	345	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	165:e614a9f1c9e2	346	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:e614a9f1c9e2	347
AnnaBridge	165:e614a9f1c9e2	348	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:e614a9f1c9e2	349
AnnaBridge	165:e614a9f1c9e2	350	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	165:e614a9f1c9e2	351	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:e614a9f1c9e2	352
AnnaBridge	165:e614a9f1c9e2	353	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:e614a9f1c9e2	354
AnnaBridge	165:e614a9f1c9e2	355	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	356
AnnaBridge	165:e614a9f1c9e2	357	/**
AnnaBridge	165:e614a9f1c9e2	358	* @brief TIM Hall sensor interface configuration structure definition.
AnnaBridge	165:e614a9f1c9e2	359	*/
AnnaBridge	165:e614a9f1c9e2	360	typedef struct
AnnaBridge	165:e614a9f1c9e2	361	{
AnnaBridge	165:e614a9f1c9e2	362
AnnaBridge	165:e614a9f1c9e2	363	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	165:e614a9f1c9e2	364	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	165:e614a9f1c9e2	365
AnnaBridge	165:e614a9f1c9e2	366	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	165:e614a9f1c9e2	367
AnnaBridge	165:e614a9f1c9e2	368	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	165:e614a9f1c9e2	369	Prescaler must be set to get a maximum counter period longer than the
AnnaBridge	165:e614a9f1c9e2	370	time interval between 2 consecutive changes on the Hall inputs.
AnnaBridge	165:e614a9f1c9e2	371	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	165:e614a9f1c9e2	372
AnnaBridge	165:e614a9f1c9e2	373	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	165:e614a9f1c9e2	374
AnnaBridge	165:e614a9f1c9e2	375	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	165:e614a9f1c9e2	376	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	165:e614a9f1c9e2	377
AnnaBridge	165:e614a9f1c9e2	378	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	165:e614a9f1c9e2	379
AnnaBridge	165:e614a9f1c9e2	380	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
AnnaBridge	165:e614a9f1c9e2	381	A positive pulse (TRGO event) is generated with a programmable delay every time
AnnaBridge	165:e614a9f1c9e2	382	a change occurs on the Hall inputs.
AnnaBridge	165:e614a9f1c9e2	383	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
AnnaBridge	165:e614a9f1c9e2	384
AnnaBridge	165:e614a9f1c9e2	385	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
AnnaBridge	165:e614a9f1c9e2	386	} LL_TIM_HALLSENSOR_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	387
AnnaBridge	165:e614a9f1c9e2	388	/**
AnnaBridge	165:e614a9f1c9e2	389	* @brief BDTR (Break and Dead Time) structure definition
AnnaBridge	165:e614a9f1c9e2	390	*/
AnnaBridge	165:e614a9f1c9e2	391	typedef struct
AnnaBridge	165:e614a9f1c9e2	392	{
AnnaBridge	165:e614a9f1c9e2	393	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
AnnaBridge	165:e614a9f1c9e2	394	This parameter can be a value of @ref TIM_LL_EC_OSSR
AnnaBridge	165:e614a9f1c9e2	395
AnnaBridge	165:e614a9f1c9e2	396	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	165:e614a9f1c9e2	397
AnnaBridge	165:e614a9f1c9e2	398	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	165:e614a9f1c9e2	399
AnnaBridge	165:e614a9f1c9e2	400	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
AnnaBridge	165:e614a9f1c9e2	401	This parameter can be a value of @ref TIM_LL_EC_OSSI
AnnaBridge	165:e614a9f1c9e2	402
AnnaBridge	165:e614a9f1c9e2	403	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	165:e614a9f1c9e2	404
AnnaBridge	165:e614a9f1c9e2	405	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	165:e614a9f1c9e2	406
AnnaBridge	165:e614a9f1c9e2	407	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
AnnaBridge	165:e614a9f1c9e2	408	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
AnnaBridge	165:e614a9f1c9e2	409
AnnaBridge	165:e614a9f1c9e2	410	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
AnnaBridge	165:e614a9f1c9e2	411	has been written, their content is frozen until the next reset.*/
AnnaBridge	165:e614a9f1c9e2	412
AnnaBridge	165:e614a9f1c9e2	413	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
AnnaBridge	165:e614a9f1c9e2	414	switching-on of the outputs.
AnnaBridge	165:e614a9f1c9e2	415	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	165:e614a9f1c9e2	416
AnnaBridge	165:e614a9f1c9e2	417	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
AnnaBridge	165:e614a9f1c9e2	418
AnnaBridge	165:e614a9f1c9e2	419	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
AnnaBridge	165:e614a9f1c9e2	420
AnnaBridge	165:e614a9f1c9e2	421	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
AnnaBridge	165:e614a9f1c9e2	422	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
AnnaBridge	165:e614a9f1c9e2	423
AnnaBridge	165:e614a9f1c9e2	424	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
AnnaBridge	165:e614a9f1c9e2	425
AnnaBridge	165:e614a9f1c9e2	426	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:e614a9f1c9e2	427
AnnaBridge	165:e614a9f1c9e2	428	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
AnnaBridge	165:e614a9f1c9e2	429	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
AnnaBridge	165:e614a9f1c9e2	430
AnnaBridge	165:e614a9f1c9e2	431	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	165:e614a9f1c9e2	432
AnnaBridge	165:e614a9f1c9e2	433	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:e614a9f1c9e2	434
AnnaBridge	165:e614a9f1c9e2	435	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
AnnaBridge	165:e614a9f1c9e2	436	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
AnnaBridge	165:e614a9f1c9e2	437
AnnaBridge	165:e614a9f1c9e2	438	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
AnnaBridge	165:e614a9f1c9e2	439
AnnaBridge	165:e614a9f1c9e2	440	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	165:e614a9f1c9e2	441	} LL_TIM_BDTR_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	442
AnnaBridge	165:e614a9f1c9e2	443	/**
AnnaBridge	165:e614a9f1c9e2	444	* @}
AnnaBridge	165:e614a9f1c9e2	445	*/
AnnaBridge	165:e614a9f1c9e2	446	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	447
AnnaBridge	165:e614a9f1c9e2	448	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	449	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	165:e614a9f1c9e2	450	* @{
AnnaBridge	165:e614a9f1c9e2	451	*/
AnnaBridge	165:e614a9f1c9e2	452
AnnaBridge	165:e614a9f1c9e2	453	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	165:e614a9f1c9e2	454	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	165:e614a9f1c9e2	455	* @{
AnnaBridge	165:e614a9f1c9e2	456	*/
AnnaBridge	165:e614a9f1c9e2	457	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	165:e614a9f1c9e2	458	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	165:e614a9f1c9e2	459	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	165:e614a9f1c9e2	460	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	165:e614a9f1c9e2	461	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	165:e614a9f1c9e2	462	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
AnnaBridge	165:e614a9f1c9e2	463	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	165:e614a9f1c9e2	464	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
AnnaBridge	165:e614a9f1c9e2	465	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	165:e614a9f1c9e2	466	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	165:e614a9f1c9e2	467	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	165:e614a9f1c9e2	468	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	165:e614a9f1c9e2	469	/**
AnnaBridge	165:e614a9f1c9e2	470	* @}
AnnaBridge	165:e614a9f1c9e2	471	*/
AnnaBridge	165:e614a9f1c9e2	472
AnnaBridge	165:e614a9f1c9e2	473	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	474	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
AnnaBridge	165:e614a9f1c9e2	475	* @{
AnnaBridge	165:e614a9f1c9e2	476	*/
AnnaBridge	165:e614a9f1c9e2	477	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
AnnaBridge	165:e614a9f1c9e2	478	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
AnnaBridge	165:e614a9f1c9e2	479	/**
AnnaBridge	165:e614a9f1c9e2	480	* @}
AnnaBridge	165:e614a9f1c9e2	481	*/
AnnaBridge	165:e614a9f1c9e2	482
AnnaBridge	165:e614a9f1c9e2	483	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
AnnaBridge	165:e614a9f1c9e2	484	* @{
AnnaBridge	165:e614a9f1c9e2	485	*/
AnnaBridge	165:e614a9f1c9e2	486	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
AnnaBridge	165:e614a9f1c9e2	487	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
AnnaBridge	165:e614a9f1c9e2	488	/**
AnnaBridge	165:e614a9f1c9e2	489	* @}
AnnaBridge	165:e614a9f1c9e2	490	*/
AnnaBridge	165:e614a9f1c9e2	491	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	492
AnnaBridge	165:e614a9f1c9e2	493	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	165:e614a9f1c9e2	494	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	165:e614a9f1c9e2	495	* @{
AnnaBridge	165:e614a9f1c9e2	496	*/
AnnaBridge	165:e614a9f1c9e2	497	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	165:e614a9f1c9e2	498	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	165:e614a9f1c9e2	499	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	165:e614a9f1c9e2	500	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	165:e614a9f1c9e2	501	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	165:e614a9f1c9e2	502	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
AnnaBridge	165:e614a9f1c9e2	503	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	165:e614a9f1c9e2	504	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
AnnaBridge	165:e614a9f1c9e2	505	/**
AnnaBridge	165:e614a9f1c9e2	506	* @}
AnnaBridge	165:e614a9f1c9e2	507	*/
AnnaBridge	165:e614a9f1c9e2	508
AnnaBridge	165:e614a9f1c9e2	509	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	165:e614a9f1c9e2	510	* @{
AnnaBridge	165:e614a9f1c9e2	511	*/
AnnaBridge	165:e614a9f1c9e2	512	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	165:e614a9f1c9e2	513	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	165:e614a9f1c9e2	514	/**
AnnaBridge	165:e614a9f1c9e2	515	* @}
AnnaBridge	165:e614a9f1c9e2	516	*/
AnnaBridge	165:e614a9f1c9e2	517
AnnaBridge	165:e614a9f1c9e2	518	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	165:e614a9f1c9e2	519	* @{
AnnaBridge	165:e614a9f1c9e2	520	*/
AnnaBridge	165:e614a9f1c9e2	521	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	165:e614a9f1c9e2	522	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	165:e614a9f1c9e2	523	/**
AnnaBridge	165:e614a9f1c9e2	524	* @}
AnnaBridge	165:e614a9f1c9e2	525	*/
AnnaBridge	165:e614a9f1c9e2	526
AnnaBridge	165:e614a9f1c9e2	527	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	165:e614a9f1c9e2	528	* @{
AnnaBridge	165:e614a9f1c9e2	529	*/
AnnaBridge	165:e614a9f1c9e2	530	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	165:e614a9f1c9e2	531	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	165:e614a9f1c9e2	532	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	165:e614a9f1c9e2	533	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	165:e614a9f1c9e2	534	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	165:e614a9f1c9e2	535	/**
AnnaBridge	165:e614a9f1c9e2	536	* @}
AnnaBridge	165:e614a9f1c9e2	537	*/
AnnaBridge	165:e614a9f1c9e2	538
AnnaBridge	165:e614a9f1c9e2	539	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	165:e614a9f1c9e2	540	* @{
AnnaBridge	165:e614a9f1c9e2	541	*/
AnnaBridge	165:e614a9f1c9e2	542	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	165:e614a9f1c9e2	543	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	165:e614a9f1c9e2	544	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	165:e614a9f1c9e2	545	/**
AnnaBridge	165:e614a9f1c9e2	546	* @}
AnnaBridge	165:e614a9f1c9e2	547	*/
AnnaBridge	165:e614a9f1c9e2	548
AnnaBridge	165:e614a9f1c9e2	549	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	165:e614a9f1c9e2	550	* @{
AnnaBridge	165:e614a9f1c9e2	551	*/
AnnaBridge	165:e614a9f1c9e2	552	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	165:e614a9f1c9e2	553	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	165:e614a9f1c9e2	554	/**
AnnaBridge	165:e614a9f1c9e2	555	* @}
AnnaBridge	165:e614a9f1c9e2	556	*/
AnnaBridge	165:e614a9f1c9e2	557
AnnaBridge	165:e614a9f1c9e2	558	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
AnnaBridge	165:e614a9f1c9e2	559	* @{
AnnaBridge	165:e614a9f1c9e2	560	*/
AnnaBridge	165:e614a9f1c9e2	561	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
AnnaBridge	165:e614a9f1c9e2	562	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
AnnaBridge	165:e614a9f1c9e2	563	/**
AnnaBridge	165:e614a9f1c9e2	564	* @}
AnnaBridge	165:e614a9f1c9e2	565	*/
AnnaBridge	165:e614a9f1c9e2	566
AnnaBridge	165:e614a9f1c9e2	567	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	165:e614a9f1c9e2	568	* @{
AnnaBridge	165:e614a9f1c9e2	569	*/
AnnaBridge	165:e614a9f1c9e2	570	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	165:e614a9f1c9e2	571	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	165:e614a9f1c9e2	572	/**
AnnaBridge	165:e614a9f1c9e2	573	* @}
AnnaBridge	165:e614a9f1c9e2	574	*/
AnnaBridge	165:e614a9f1c9e2	575
AnnaBridge	165:e614a9f1c9e2	576	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
AnnaBridge	165:e614a9f1c9e2	577	* @{
AnnaBridge	165:e614a9f1c9e2	578	*/
AnnaBridge	165:e614a9f1c9e2	579	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
AnnaBridge	165:e614a9f1c9e2	580	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
AnnaBridge	165:e614a9f1c9e2	581	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
AnnaBridge	165:e614a9f1c9e2	582	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
AnnaBridge	165:e614a9f1c9e2	583	/**
AnnaBridge	165:e614a9f1c9e2	584	* @}
AnnaBridge	165:e614a9f1c9e2	585	*/
AnnaBridge	165:e614a9f1c9e2	586
AnnaBridge	165:e614a9f1c9e2	587	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	165:e614a9f1c9e2	588	* @{
AnnaBridge	165:e614a9f1c9e2	589	*/
AnnaBridge	165:e614a9f1c9e2	590	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	165:e614a9f1c9e2	591	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	165:e614a9f1c9e2	592	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	165:e614a9f1c9e2	593	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	165:e614a9f1c9e2	594	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	165:e614a9f1c9e2	595	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	165:e614a9f1c9e2	596	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	165:e614a9f1c9e2	597	/**
AnnaBridge	165:e614a9f1c9e2	598	* @}
AnnaBridge	165:e614a9f1c9e2	599	*/
AnnaBridge	165:e614a9f1c9e2	600
AnnaBridge	165:e614a9f1c9e2	601	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	602	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	165:e614a9f1c9e2	603	* @{
AnnaBridge	165:e614a9f1c9e2	604	*/
AnnaBridge	165:e614a9f1c9e2	605	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	165:e614a9f1c9e2	606	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	165:e614a9f1c9e2	607	/**
AnnaBridge	165:e614a9f1c9e2	608	* @}
AnnaBridge	165:e614a9f1c9e2	609	*/
AnnaBridge	165:e614a9f1c9e2	610	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	611
AnnaBridge	165:e614a9f1c9e2	612	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	165:e614a9f1c9e2	613	* @{
AnnaBridge	165:e614a9f1c9e2	614	*/
AnnaBridge	165:e614a9f1c9e2	615	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	165:e614a9f1c9e2	616	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	165:e614a9f1c9e2	617	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	165:e614a9f1c9e2	618	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	165:e614a9f1c9e2	619	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	165:e614a9f1c9e2	620	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	165:e614a9f1c9e2	621	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	165:e614a9f1c9e2	622	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	165:e614a9f1c9e2	623	/**
AnnaBridge	165:e614a9f1c9e2	624	* @}
AnnaBridge	165:e614a9f1c9e2	625	*/
AnnaBridge	165:e614a9f1c9e2	626
AnnaBridge	165:e614a9f1c9e2	627	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	165:e614a9f1c9e2	628	* @{
AnnaBridge	165:e614a9f1c9e2	629	*/
AnnaBridge	165:e614a9f1c9e2	630	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	165:e614a9f1c9e2	631	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	165:e614a9f1c9e2	632	/**
AnnaBridge	165:e614a9f1c9e2	633	* @}
AnnaBridge	165:e614a9f1c9e2	634	*/
AnnaBridge	165:e614a9f1c9e2	635
AnnaBridge	165:e614a9f1c9e2	636	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
AnnaBridge	165:e614a9f1c9e2	637	* @{
AnnaBridge	165:e614a9f1c9e2	638	*/
AnnaBridge	165:e614a9f1c9e2	639	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	165:e614a9f1c9e2	640	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	165:e614a9f1c9e2	641	/**
AnnaBridge	165:e614a9f1c9e2	642	* @}
AnnaBridge	165:e614a9f1c9e2	643	*/
AnnaBridge	165:e614a9f1c9e2	644
AnnaBridge	165:e614a9f1c9e2	645
AnnaBridge	165:e614a9f1c9e2	646	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	165:e614a9f1c9e2	647	* @{
AnnaBridge	165:e614a9f1c9e2	648	*/
AnnaBridge	165:e614a9f1c9e2	649	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	165:e614a9f1c9e2	650	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	165:e614a9f1c9e2	651	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	165:e614a9f1c9e2	652	/**
AnnaBridge	165:e614a9f1c9e2	653	* @}
AnnaBridge	165:e614a9f1c9e2	654	*/
AnnaBridge	165:e614a9f1c9e2	655
AnnaBridge	165:e614a9f1c9e2	656	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	165:e614a9f1c9e2	657	* @{
AnnaBridge	165:e614a9f1c9e2	658	*/
AnnaBridge	165:e614a9f1c9e2	659	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	165:e614a9f1c9e2	660	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	165:e614a9f1c9e2	661	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	165:e614a9f1c9e2	662	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	165:e614a9f1c9e2	663	/**
AnnaBridge	165:e614a9f1c9e2	664	* @}
AnnaBridge	165:e614a9f1c9e2	665	*/
AnnaBridge	165:e614a9f1c9e2	666
AnnaBridge	165:e614a9f1c9e2	667	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	165:e614a9f1c9e2	668	* @{
AnnaBridge	165:e614a9f1c9e2	669	*/
AnnaBridge	165:e614a9f1c9e2	670	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	165:e614a9f1c9e2	671	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	165:e614a9f1c9e2	672	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	165:e614a9f1c9e2	673	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	165:e614a9f1c9e2	674	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	165:e614a9f1c9e2	675	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	165:e614a9f1c9e2	676	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	165:e614a9f1c9e2	677	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	165:e614a9f1c9e2	678	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	165:e614a9f1c9e2	679	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	165:e614a9f1c9e2	680	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:e614a9f1c9e2	681	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	165:e614a9f1c9e2	682	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	165:e614a9f1c9e2	683	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	165:e614a9f1c9e2	684	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	165:e614a9f1c9e2	685	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	165:e614a9f1c9e2	686	/**
AnnaBridge	165:e614a9f1c9e2	687	* @}
AnnaBridge	165:e614a9f1c9e2	688	*/
AnnaBridge	165:e614a9f1c9e2	689
AnnaBridge	165:e614a9f1c9e2	690	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	165:e614a9f1c9e2	691	* @{
AnnaBridge	165:e614a9f1c9e2	692	*/
AnnaBridge	165:e614a9f1c9e2	693	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	165:e614a9f1c9e2	694	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	165:e614a9f1c9e2	695	/**
AnnaBridge	165:e614a9f1c9e2	696	* @}
AnnaBridge	165:e614a9f1c9e2	697	*/
AnnaBridge	165:e614a9f1c9e2	698
AnnaBridge	165:e614a9f1c9e2	699	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	165:e614a9f1c9e2	700	* @{
AnnaBridge	165:e614a9f1c9e2	701	*/
AnnaBridge	165:e614a9f1c9e2	702	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	165:e614a9f1c9e2	703	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
AnnaBridge	165:e614a9f1c9e2	704	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	165:e614a9f1c9e2	705	/**
AnnaBridge	165:e614a9f1c9e2	706	* @}
AnnaBridge	165:e614a9f1c9e2	707	*/
AnnaBridge	165:e614a9f1c9e2	708
AnnaBridge	165:e614a9f1c9e2	709	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	165:e614a9f1c9e2	710	* @{
AnnaBridge	165:e614a9f1c9e2	711	*/
AnnaBridge	165:e614a9f1c9e2	712	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	165:e614a9f1c9e2	713	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	165:e614a9f1c9e2	714	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
AnnaBridge	165:e614a9f1c9e2	715	/**
AnnaBridge	165:e614a9f1c9e2	716	* @}
AnnaBridge	165:e614a9f1c9e2	717	*/
AnnaBridge	165:e614a9f1c9e2	718
AnnaBridge	165:e614a9f1c9e2	719	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	165:e614a9f1c9e2	720	* @{
AnnaBridge	165:e614a9f1c9e2	721	*/
AnnaBridge	165:e614a9f1c9e2	722	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	723	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	724	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	725	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	726	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	727	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	728	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	729	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	165:e614a9f1c9e2	730	/**
AnnaBridge	165:e614a9f1c9e2	731	* @}
AnnaBridge	165:e614a9f1c9e2	732	*/
AnnaBridge	165:e614a9f1c9e2	733
AnnaBridge	165:e614a9f1c9e2	734
AnnaBridge	165:e614a9f1c9e2	735	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	165:e614a9f1c9e2	736	* @{
AnnaBridge	165:e614a9f1c9e2	737	*/
AnnaBridge	165:e614a9f1c9e2	738	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	165:e614a9f1c9e2	739	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	165:e614a9f1c9e2	740	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	165:e614a9f1c9e2	741	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	165:e614a9f1c9e2	742	/**
AnnaBridge	165:e614a9f1c9e2	743	* @}
AnnaBridge	165:e614a9f1c9e2	744	*/
AnnaBridge	165:e614a9f1c9e2	745
AnnaBridge	165:e614a9f1c9e2	746	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	165:e614a9f1c9e2	747	* @{
AnnaBridge	165:e614a9f1c9e2	748	*/
AnnaBridge	165:e614a9f1c9e2	749	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	750	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	751	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	752	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	753	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	754	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	755	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	756	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	165:e614a9f1c9e2	757	/**
AnnaBridge	165:e614a9f1c9e2	758	* @}
AnnaBridge	165:e614a9f1c9e2	759	*/
AnnaBridge	165:e614a9f1c9e2	760
AnnaBridge	165:e614a9f1c9e2	761	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	165:e614a9f1c9e2	762	* @{
AnnaBridge	165:e614a9f1c9e2	763	*/
AnnaBridge	165:e614a9f1c9e2	764	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	165:e614a9f1c9e2	765	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	165:e614a9f1c9e2	766	/**
AnnaBridge	165:e614a9f1c9e2	767	* @}
AnnaBridge	165:e614a9f1c9e2	768	*/
AnnaBridge	165:e614a9f1c9e2	769
AnnaBridge	165:e614a9f1c9e2	770	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	165:e614a9f1c9e2	771	* @{
AnnaBridge	165:e614a9f1c9e2	772	*/
AnnaBridge	165:e614a9f1c9e2	773	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	165:e614a9f1c9e2	774	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	165:e614a9f1c9e2	775	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	165:e614a9f1c9e2	776	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	165:e614a9f1c9e2	777	/**
AnnaBridge	165:e614a9f1c9e2	778	* @}
AnnaBridge	165:e614a9f1c9e2	779	*/
AnnaBridge	165:e614a9f1c9e2	780
AnnaBridge	165:e614a9f1c9e2	781	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	165:e614a9f1c9e2	782	* @{
AnnaBridge	165:e614a9f1c9e2	783	*/
AnnaBridge	165:e614a9f1c9e2	784	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	165:e614a9f1c9e2	785	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	165:e614a9f1c9e2	786	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	165:e614a9f1c9e2	787	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	165:e614a9f1c9e2	788	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	165:e614a9f1c9e2	789	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	165:e614a9f1c9e2	790	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	165:e614a9f1c9e2	791	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	165:e614a9f1c9e2	792	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	165:e614a9f1c9e2	793	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:e614a9f1c9e2	794	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	165:e614a9f1c9e2	795	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	165:e614a9f1c9e2	796	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	165:e614a9f1c9e2	797	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	165:e614a9f1c9e2	798	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	165:e614a9f1c9e2	799	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	165:e614a9f1c9e2	800	/**
AnnaBridge	165:e614a9f1c9e2	801	* @}
AnnaBridge	165:e614a9f1c9e2	802	*/
AnnaBridge	165:e614a9f1c9e2	803
AnnaBridge	165:e614a9f1c9e2	804
AnnaBridge	165:e614a9f1c9e2	805	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
AnnaBridge	165:e614a9f1c9e2	806	* @{
AnnaBridge	165:e614a9f1c9e2	807	*/
AnnaBridge	165:e614a9f1c9e2	808	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
AnnaBridge	165:e614a9f1c9e2	809	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
AnnaBridge	165:e614a9f1c9e2	810	/**
AnnaBridge	165:e614a9f1c9e2	811	* @}
AnnaBridge	165:e614a9f1c9e2	812	*/
AnnaBridge	165:e614a9f1c9e2	813
AnnaBridge	165:e614a9f1c9e2	814
AnnaBridge	165:e614a9f1c9e2	815
AnnaBridge	165:e614a9f1c9e2	816
AnnaBridge	165:e614a9f1c9e2	817	/** @defgroup TIM_LL_EC_OSSI OSSI
AnnaBridge	165:e614a9f1c9e2	818	* @{
AnnaBridge	165:e614a9f1c9e2	819	*/
AnnaBridge	165:e614a9f1c9e2	820	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	165:e614a9f1c9e2	821	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
AnnaBridge	165:e614a9f1c9e2	822	/**
AnnaBridge	165:e614a9f1c9e2	823	* @}
AnnaBridge	165:e614a9f1c9e2	824	*/
AnnaBridge	165:e614a9f1c9e2	825
AnnaBridge	165:e614a9f1c9e2	826	/** @defgroup TIM_LL_EC_OSSR OSSR
AnnaBridge	165:e614a9f1c9e2	827	* @{
AnnaBridge	165:e614a9f1c9e2	828	*/
AnnaBridge	165:e614a9f1c9e2	829	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	165:e614a9f1c9e2	830	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
AnnaBridge	165:e614a9f1c9e2	831	/**
AnnaBridge	165:e614a9f1c9e2	832	* @}
AnnaBridge	165:e614a9f1c9e2	833	*/
AnnaBridge	165:e614a9f1c9e2	834
AnnaBridge	165:e614a9f1c9e2	835
AnnaBridge	165:e614a9f1c9e2	836	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	165:e614a9f1c9e2	837	* @{
AnnaBridge	165:e614a9f1c9e2	838	*/
AnnaBridge	165:e614a9f1c9e2	839	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	840	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	841	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	842	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	843	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	844	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	845	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	846	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	847	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	848	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	849	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	850	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	851	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	852	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	853	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	854	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	855	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	856	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	165:e614a9f1c9e2	857	/**
AnnaBridge	165:e614a9f1c9e2	858	* @}
AnnaBridge	165:e614a9f1c9e2	859	*/
AnnaBridge	165:e614a9f1c9e2	860
AnnaBridge	165:e614a9f1c9e2	861	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	165:e614a9f1c9e2	862	* @{
AnnaBridge	165:e614a9f1c9e2	863	*/
AnnaBridge	165:e614a9f1c9e2	864	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	865	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	866	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	867	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	868	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	869	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	870	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	871	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	872	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	873	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	874	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	875	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	876	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	877	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	878	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	879	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	880	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	881	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	165:e614a9f1c9e2	882	/**
AnnaBridge	165:e614a9f1c9e2	883	* @}
AnnaBridge	165:e614a9f1c9e2	884	*/
AnnaBridge	165:e614a9f1c9e2	885
AnnaBridge	165:e614a9f1c9e2	886
AnnaBridge	165:e614a9f1c9e2	887
AnnaBridge	165:e614a9f1c9e2	888	/**
AnnaBridge	165:e614a9f1c9e2	889	* @}
AnnaBridge	165:e614a9f1c9e2	890	*/
AnnaBridge	165:e614a9f1c9e2	891
AnnaBridge	165:e614a9f1c9e2	892	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	893	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	165:e614a9f1c9e2	894	* @{
AnnaBridge	165:e614a9f1c9e2	895	*/
AnnaBridge	165:e614a9f1c9e2	896
AnnaBridge	165:e614a9f1c9e2	897	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	165:e614a9f1c9e2	898	* @{
AnnaBridge	165:e614a9f1c9e2	899	*/
AnnaBridge	165:e614a9f1c9e2	900	/**
AnnaBridge	165:e614a9f1c9e2	901	* @brief Write a value in TIM register.
AnnaBridge	165:e614a9f1c9e2	902	* @param __INSTANCE__ TIM Instance
AnnaBridge	165:e614a9f1c9e2	903	* @param __REG__ Register to be written
AnnaBridge	165:e614a9f1c9e2	904	* @param __VALUE__ Value to be written in the register
AnnaBridge	165:e614a9f1c9e2	905	* @retval None
AnnaBridge	165:e614a9f1c9e2	906	*/
AnnaBridge	165:e614a9f1c9e2	907	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	165:e614a9f1c9e2	908
AnnaBridge	165:e614a9f1c9e2	909	/**
AnnaBridge	165:e614a9f1c9e2	910	* @brief Read a value in TIM register.
AnnaBridge	165:e614a9f1c9e2	911	* @param __INSTANCE__ TIM Instance
AnnaBridge	165:e614a9f1c9e2	912	* @param __REG__ Register to be read
AnnaBridge	165:e614a9f1c9e2	913	* @retval Register value
AnnaBridge	165:e614a9f1c9e2	914	*/
AnnaBridge	165:e614a9f1c9e2	915	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	165:e614a9f1c9e2	916	/**
AnnaBridge	165:e614a9f1c9e2	917	* @}
AnnaBridge	165:e614a9f1c9e2	918	*/
AnnaBridge	165:e614a9f1c9e2	919
AnnaBridge	165:e614a9f1c9e2	920	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	165:e614a9f1c9e2	921	* @{
AnnaBridge	165:e614a9f1c9e2	922	*/
AnnaBridge	165:e614a9f1c9e2	923
AnnaBridge	165:e614a9f1c9e2	924	/**
AnnaBridge	165:e614a9f1c9e2	925	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
AnnaBridge	165:e614a9f1c9e2	926	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
AnnaBridge	165:e614a9f1c9e2	927	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:e614a9f1c9e2	928	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	929	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:e614a9f1c9e2	930	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:e614a9f1c9e2	931	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:e614a9f1c9e2	932	* @param __DT__ deadtime duration (in ns)
AnnaBridge	165:e614a9f1c9e2	933	* @retval DTG[0:7]
AnnaBridge	165:e614a9f1c9e2	934	*/
AnnaBridge	165:e614a9f1c9e2	935	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
AnnaBridge	165:e614a9f1c9e2	936	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
AnnaBridge	165:e614a9f1c9e2	937	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
AnnaBridge	165:e614a9f1c9e2	938	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
AnnaBridge	165:e614a9f1c9e2	939	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
AnnaBridge	165:e614a9f1c9e2	940	0U)
AnnaBridge	165:e614a9f1c9e2	941
AnnaBridge	165:e614a9f1c9e2	942	/**
AnnaBridge	165:e614a9f1c9e2	943	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	165:e614a9f1c9e2	944	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	165:e614a9f1c9e2	945	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:e614a9f1c9e2	946	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	165:e614a9f1c9e2	947	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	948	*/
AnnaBridge	165:e614a9f1c9e2	949	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	165:e614a9f1c9e2	950	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	165:e614a9f1c9e2	951
AnnaBridge	165:e614a9f1c9e2	952	/**
AnnaBridge	165:e614a9f1c9e2	953	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	165:e614a9f1c9e2	954	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	165:e614a9f1c9e2	955	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:e614a9f1c9e2	956	* @param __PSC__ prescaler
AnnaBridge	165:e614a9f1c9e2	957	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	165:e614a9f1c9e2	958	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	959	*/
AnnaBridge	165:e614a9f1c9e2	960	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	165:e614a9f1c9e2	961	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	165:e614a9f1c9e2	962
AnnaBridge	165:e614a9f1c9e2	963	/**
AnnaBridge	165:e614a9f1c9e2	964	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	165:e614a9f1c9e2	965	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	165:e614a9f1c9e2	966	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:e614a9f1c9e2	967	* @param __PSC__ prescaler
AnnaBridge	165:e614a9f1c9e2	968	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	165:e614a9f1c9e2	969	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	970	*/
AnnaBridge	165:e614a9f1c9e2	971	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	165:e614a9f1c9e2	972	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	165:e614a9f1c9e2	973	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	165:e614a9f1c9e2	974
AnnaBridge	165:e614a9f1c9e2	975	/**
AnnaBridge	165:e614a9f1c9e2	976	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	165:e614a9f1c9e2	977	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	165:e614a9f1c9e2	978	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	165:e614a9f1c9e2	979	* @param __PSC__ prescaler
AnnaBridge	165:e614a9f1c9e2	980	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	165:e614a9f1c9e2	981	* @param __PULSE__ pulse duration (in us)
AnnaBridge	165:e614a9f1c9e2	982	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	983	*/
AnnaBridge	165:e614a9f1c9e2	984	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	165:e614a9f1c9e2	985	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	165:e614a9f1c9e2	986	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	165:e614a9f1c9e2	987
AnnaBridge	165:e614a9f1c9e2	988	/**
AnnaBridge	165:e614a9f1c9e2	989	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	165:e614a9f1c9e2	990	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	165:e614a9f1c9e2	991	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	992	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	165:e614a9f1c9e2	993	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	165:e614a9f1c9e2	994	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	165:e614a9f1c9e2	995	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:e614a9f1c9e2	996	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	165:e614a9f1c9e2	997	*/
AnnaBridge	165:e614a9f1c9e2	998	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	165:e614a9f1c9e2	999	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	165:e614a9f1c9e2	1000
AnnaBridge	165:e614a9f1c9e2	1001
AnnaBridge	165:e614a9f1c9e2	1002	/**
AnnaBridge	165:e614a9f1c9e2	1003	* @}
AnnaBridge	165:e614a9f1c9e2	1004	*/
AnnaBridge	165:e614a9f1c9e2	1005
AnnaBridge	165:e614a9f1c9e2	1006
AnnaBridge	165:e614a9f1c9e2	1007	/**
AnnaBridge	165:e614a9f1c9e2	1008	* @}
AnnaBridge	165:e614a9f1c9e2	1009	*/
AnnaBridge	165:e614a9f1c9e2	1010
AnnaBridge	165:e614a9f1c9e2	1011	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1012	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	165:e614a9f1c9e2	1013	* @{
AnnaBridge	165:e614a9f1c9e2	1014	*/
AnnaBridge	165:e614a9f1c9e2	1015
AnnaBridge	165:e614a9f1c9e2	1016	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	165:e614a9f1c9e2	1017	* @{
AnnaBridge	165:e614a9f1c9e2	1018	*/
AnnaBridge	165:e614a9f1c9e2	1019	/**
AnnaBridge	165:e614a9f1c9e2	1020	* @brief Enable timer counter.
AnnaBridge	165:e614a9f1c9e2	1021	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	165:e614a9f1c9e2	1022	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1023	* @retval None
AnnaBridge	165:e614a9f1c9e2	1024	*/
AnnaBridge	165:e614a9f1c9e2	1025	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1026	{
AnnaBridge	165:e614a9f1c9e2	1027	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	165:e614a9f1c9e2	1028	}
AnnaBridge	165:e614a9f1c9e2	1029
AnnaBridge	165:e614a9f1c9e2	1030	/**
AnnaBridge	165:e614a9f1c9e2	1031	* @brief Disable timer counter.
AnnaBridge	165:e614a9f1c9e2	1032	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	165:e614a9f1c9e2	1033	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1034	* @retval None
AnnaBridge	165:e614a9f1c9e2	1035	*/
AnnaBridge	165:e614a9f1c9e2	1036	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1037	{
AnnaBridge	165:e614a9f1c9e2	1038	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	165:e614a9f1c9e2	1039	}
AnnaBridge	165:e614a9f1c9e2	1040
AnnaBridge	165:e614a9f1c9e2	1041	/**
AnnaBridge	165:e614a9f1c9e2	1042	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	165:e614a9f1c9e2	1043	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	165:e614a9f1c9e2	1044	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1045	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1046	*/
AnnaBridge	165:e614a9f1c9e2	1047	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1048	{
AnnaBridge	165:e614a9f1c9e2	1049	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	165:e614a9f1c9e2	1050	}
AnnaBridge	165:e614a9f1c9e2	1051
AnnaBridge	165:e614a9f1c9e2	1052	/**
AnnaBridge	165:e614a9f1c9e2	1053	* @brief Enable update event generation.
AnnaBridge	165:e614a9f1c9e2	1054	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	165:e614a9f1c9e2	1055	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1056	* @retval None
AnnaBridge	165:e614a9f1c9e2	1057	*/
AnnaBridge	165:e614a9f1c9e2	1058	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1059	{
AnnaBridge	165:e614a9f1c9e2	1060	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	165:e614a9f1c9e2	1061	}
AnnaBridge	165:e614a9f1c9e2	1062
AnnaBridge	165:e614a9f1c9e2	1063	/**
AnnaBridge	165:e614a9f1c9e2	1064	* @brief Disable update event generation.
AnnaBridge	165:e614a9f1c9e2	1065	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	165:e614a9f1c9e2	1066	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1067	* @retval None
AnnaBridge	165:e614a9f1c9e2	1068	*/
AnnaBridge	165:e614a9f1c9e2	1069	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1070	{
AnnaBridge	165:e614a9f1c9e2	1071	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	165:e614a9f1c9e2	1072	}
AnnaBridge	165:e614a9f1c9e2	1073
AnnaBridge	165:e614a9f1c9e2	1074	/**
AnnaBridge	165:e614a9f1c9e2	1075	* @brief Indicates whether update event generation is enabled.
AnnaBridge	165:e614a9f1c9e2	1076	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	165:e614a9f1c9e2	1077	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1078	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1079	*/
AnnaBridge	165:e614a9f1c9e2	1080	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1081	{
AnnaBridge	165:e614a9f1c9e2	1082	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
AnnaBridge	165:e614a9f1c9e2	1083	}
AnnaBridge	165:e614a9f1c9e2	1084
AnnaBridge	165:e614a9f1c9e2	1085	/**
AnnaBridge	165:e614a9f1c9e2	1086	* @brief Set update event source
AnnaBridge	165:e614a9f1c9e2	1087	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	165:e614a9f1c9e2	1088	* generate an update interrupt or DMA request if enabled:
AnnaBridge	165:e614a9f1c9e2	1089	* - Counter overflow/underflow
AnnaBridge	165:e614a9f1c9e2	1090	* - Setting the UG bit
AnnaBridge	165:e614a9f1c9e2	1091	* - Update generation through the slave mode controller
AnnaBridge	165:e614a9f1c9e2	1092	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	165:e614a9f1c9e2	1093	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	165:e614a9f1c9e2	1094	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	165:e614a9f1c9e2	1095	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1096	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1097	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	165:e614a9f1c9e2	1098	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	165:e614a9f1c9e2	1099	* @retval None
AnnaBridge	165:e614a9f1c9e2	1100	*/
AnnaBridge	165:e614a9f1c9e2	1101	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	165:e614a9f1c9e2	1102	{
AnnaBridge	165:e614a9f1c9e2	1103	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	165:e614a9f1c9e2	1104	}
AnnaBridge	165:e614a9f1c9e2	1105
AnnaBridge	165:e614a9f1c9e2	1106	/**
AnnaBridge	165:e614a9f1c9e2	1107	* @brief Get actual event update source
AnnaBridge	165:e614a9f1c9e2	1108	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	165:e614a9f1c9e2	1109	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1110	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1111	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	165:e614a9f1c9e2	1112	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	165:e614a9f1c9e2	1113	*/
AnnaBridge	165:e614a9f1c9e2	1114	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1115	{
AnnaBridge	165:e614a9f1c9e2	1116	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	165:e614a9f1c9e2	1117	}
AnnaBridge	165:e614a9f1c9e2	1118
AnnaBridge	165:e614a9f1c9e2	1119	/**
AnnaBridge	165:e614a9f1c9e2	1120	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	165:e614a9f1c9e2	1121	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	165:e614a9f1c9e2	1122	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1123	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1124	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	165:e614a9f1c9e2	1125	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	165:e614a9f1c9e2	1126	* @retval None
AnnaBridge	165:e614a9f1c9e2	1127	*/
AnnaBridge	165:e614a9f1c9e2	1128	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	165:e614a9f1c9e2	1129	{
AnnaBridge	165:e614a9f1c9e2	1130	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	165:e614a9f1c9e2	1131	}
AnnaBridge	165:e614a9f1c9e2	1132
AnnaBridge	165:e614a9f1c9e2	1133	/**
AnnaBridge	165:e614a9f1c9e2	1134	* @brief Get actual one pulse mode.
AnnaBridge	165:e614a9f1c9e2	1135	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	165:e614a9f1c9e2	1136	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1137	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1138	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	165:e614a9f1c9e2	1139	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	165:e614a9f1c9e2	1140	*/
AnnaBridge	165:e614a9f1c9e2	1141	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1142	{
AnnaBridge	165:e614a9f1c9e2	1143	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	165:e614a9f1c9e2	1144	}
AnnaBridge	165:e614a9f1c9e2	1145
AnnaBridge	165:e614a9f1c9e2	1146	/**
AnnaBridge	165:e614a9f1c9e2	1147	* @brief Set the timer counter counting mode.
AnnaBridge	165:e614a9f1c9e2	1148	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	165:e614a9f1c9e2	1149	* check whether or not the counter mode selection feature is supported
AnnaBridge	165:e614a9f1c9e2	1150	* by a timer instance.
AnnaBridge	165:e614a9f1c9e2	1151	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	165:e614a9f1c9e2	1152	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	165:e614a9f1c9e2	1153	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1154	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1155	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	165:e614a9f1c9e2	1156	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	165:e614a9f1c9e2	1157	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	165:e614a9f1c9e2	1158	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	165:e614a9f1c9e2	1159	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	165:e614a9f1c9e2	1160	* @retval None
AnnaBridge	165:e614a9f1c9e2	1161	*/
AnnaBridge	165:e614a9f1c9e2	1162	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	165:e614a9f1c9e2	1163	{
AnnaBridge	165:e614a9f1c9e2	1164	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	165:e614a9f1c9e2	1165	}
AnnaBridge	165:e614a9f1c9e2	1166
AnnaBridge	165:e614a9f1c9e2	1167	/**
AnnaBridge	165:e614a9f1c9e2	1168	* @brief Get actual counter mode.
AnnaBridge	165:e614a9f1c9e2	1169	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	165:e614a9f1c9e2	1170	* check whether or not the counter mode selection feature is supported
AnnaBridge	165:e614a9f1c9e2	1171	* by a timer instance.
AnnaBridge	165:e614a9f1c9e2	1172	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	165:e614a9f1c9e2	1173	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	165:e614a9f1c9e2	1174	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1175	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1176	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	165:e614a9f1c9e2	1177	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	165:e614a9f1c9e2	1178	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	165:e614a9f1c9e2	1179	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	165:e614a9f1c9e2	1180	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	165:e614a9f1c9e2	1181	*/
AnnaBridge	165:e614a9f1c9e2	1182	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1183	{
AnnaBridge	165:e614a9f1c9e2	1184	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	165:e614a9f1c9e2	1185	}
AnnaBridge	165:e614a9f1c9e2	1186
AnnaBridge	165:e614a9f1c9e2	1187	/**
AnnaBridge	165:e614a9f1c9e2	1188	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	165:e614a9f1c9e2	1189	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	165:e614a9f1c9e2	1190	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1191	* @retval None
AnnaBridge	165:e614a9f1c9e2	1192	*/
AnnaBridge	165:e614a9f1c9e2	1193	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1194	{
AnnaBridge	165:e614a9f1c9e2	1195	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	165:e614a9f1c9e2	1196	}
AnnaBridge	165:e614a9f1c9e2	1197
AnnaBridge	165:e614a9f1c9e2	1198	/**
AnnaBridge	165:e614a9f1c9e2	1199	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	165:e614a9f1c9e2	1200	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	165:e614a9f1c9e2	1201	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1202	* @retval None
AnnaBridge	165:e614a9f1c9e2	1203	*/
AnnaBridge	165:e614a9f1c9e2	1204	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1205	{
AnnaBridge	165:e614a9f1c9e2	1206	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	165:e614a9f1c9e2	1207	}
AnnaBridge	165:e614a9f1c9e2	1208
AnnaBridge	165:e614a9f1c9e2	1209	/**
AnnaBridge	165:e614a9f1c9e2	1210	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	165:e614a9f1c9e2	1211	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	165:e614a9f1c9e2	1212	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1213	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1214	*/
AnnaBridge	165:e614a9f1c9e2	1215	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1216	{
AnnaBridge	165:e614a9f1c9e2	1217	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	165:e614a9f1c9e2	1218	}
AnnaBridge	165:e614a9f1c9e2	1219
AnnaBridge	165:e614a9f1c9e2	1220	/**
AnnaBridge	165:e614a9f1c9e2	1221	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	165:e614a9f1c9e2	1222	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	1223	* whether or not the clock division feature is supported by the timer
AnnaBridge	165:e614a9f1c9e2	1224	* instance.
AnnaBridge	165:e614a9f1c9e2	1225	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	165:e614a9f1c9e2	1226	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1227	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1228	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:e614a9f1c9e2	1229	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:e614a9f1c9e2	1230	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:e614a9f1c9e2	1231	* @retval None
AnnaBridge	165:e614a9f1c9e2	1232	*/
AnnaBridge	165:e614a9f1c9e2	1233	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	165:e614a9f1c9e2	1234	{
AnnaBridge	165:e614a9f1c9e2	1235	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	165:e614a9f1c9e2	1236	}
AnnaBridge	165:e614a9f1c9e2	1237
AnnaBridge	165:e614a9f1c9e2	1238	/**
AnnaBridge	165:e614a9f1c9e2	1239	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	165:e614a9f1c9e2	1240	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	1241	* whether or not the clock division feature is supported by the timer
AnnaBridge	165:e614a9f1c9e2	1242	* instance.
AnnaBridge	165:e614a9f1c9e2	1243	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	165:e614a9f1c9e2	1244	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1245	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1246	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	165:e614a9f1c9e2	1247	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	165:e614a9f1c9e2	1248	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	165:e614a9f1c9e2	1249	*/
AnnaBridge	165:e614a9f1c9e2	1250	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1251	{
AnnaBridge	165:e614a9f1c9e2	1252	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	165:e614a9f1c9e2	1253	}
AnnaBridge	165:e614a9f1c9e2	1254
AnnaBridge	165:e614a9f1c9e2	1255	/**
AnnaBridge	165:e614a9f1c9e2	1256	* @brief Set the counter value.
AnnaBridge	165:e614a9f1c9e2	1257	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	165:e614a9f1c9e2	1258	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1259	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
AnnaBridge	165:e614a9f1c9e2	1260	* @retval None
AnnaBridge	165:e614a9f1c9e2	1261	*/
AnnaBridge	165:e614a9f1c9e2	1262	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	165:e614a9f1c9e2	1263	{
AnnaBridge	165:e614a9f1c9e2	1264	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	165:e614a9f1c9e2	1265	}
AnnaBridge	165:e614a9f1c9e2	1266
AnnaBridge	165:e614a9f1c9e2	1267	/**
AnnaBridge	165:e614a9f1c9e2	1268	* @brief Get the counter value.
AnnaBridge	165:e614a9f1c9e2	1269	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	165:e614a9f1c9e2	1270	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1271	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
AnnaBridge	165:e614a9f1c9e2	1272	*/
AnnaBridge	165:e614a9f1c9e2	1273	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1274	{
AnnaBridge	165:e614a9f1c9e2	1275	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	165:e614a9f1c9e2	1276	}
AnnaBridge	165:e614a9f1c9e2	1277
AnnaBridge	165:e614a9f1c9e2	1278	/**
AnnaBridge	165:e614a9f1c9e2	1279	* @brief Get the current direction of the counter
AnnaBridge	165:e614a9f1c9e2	1280	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	165:e614a9f1c9e2	1281	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1282	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1283	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	165:e614a9f1c9e2	1284	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	165:e614a9f1c9e2	1285	*/
AnnaBridge	165:e614a9f1c9e2	1286	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1287	{
AnnaBridge	165:e614a9f1c9e2	1288	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	165:e614a9f1c9e2	1289	}
AnnaBridge	165:e614a9f1c9e2	1290
AnnaBridge	165:e614a9f1c9e2	1291	/**
AnnaBridge	165:e614a9f1c9e2	1292	* @brief Set the prescaler value.
AnnaBridge	165:e614a9f1c9e2	1293	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	165:e614a9f1c9e2	1294	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	165:e614a9f1c9e2	1295	* prescaler ratio is taken into account at the next update event.
AnnaBridge	165:e614a9f1c9e2	1296	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	165:e614a9f1c9e2	1297	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	165:e614a9f1c9e2	1298	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1299	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	165:e614a9f1c9e2	1300	* @retval None
AnnaBridge	165:e614a9f1c9e2	1301	*/
AnnaBridge	165:e614a9f1c9e2	1302	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	165:e614a9f1c9e2	1303	{
AnnaBridge	165:e614a9f1c9e2	1304	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	165:e614a9f1c9e2	1305	}
AnnaBridge	165:e614a9f1c9e2	1306
AnnaBridge	165:e614a9f1c9e2	1307	/**
AnnaBridge	165:e614a9f1c9e2	1308	* @brief Get the prescaler value.
AnnaBridge	165:e614a9f1c9e2	1309	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	165:e614a9f1c9e2	1310	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1311	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	165:e614a9f1c9e2	1312	*/
AnnaBridge	165:e614a9f1c9e2	1313	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1314	{
AnnaBridge	165:e614a9f1c9e2	1315	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	165:e614a9f1c9e2	1316	}
AnnaBridge	165:e614a9f1c9e2	1317
AnnaBridge	165:e614a9f1c9e2	1318	/**
AnnaBridge	165:e614a9f1c9e2	1319	* @brief Set the auto-reload value.
AnnaBridge	165:e614a9f1c9e2	1320	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	165:e614a9f1c9e2	1321	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	165:e614a9f1c9e2	1322	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	165:e614a9f1c9e2	1323	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1324	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	165:e614a9f1c9e2	1325	* @retval None
AnnaBridge	165:e614a9f1c9e2	1326	*/
AnnaBridge	165:e614a9f1c9e2	1327	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	165:e614a9f1c9e2	1328	{
AnnaBridge	165:e614a9f1c9e2	1329	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	165:e614a9f1c9e2	1330	}
AnnaBridge	165:e614a9f1c9e2	1331
AnnaBridge	165:e614a9f1c9e2	1332	/**
AnnaBridge	165:e614a9f1c9e2	1333	* @brief Get the auto-reload value.
AnnaBridge	165:e614a9f1c9e2	1334	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	165:e614a9f1c9e2	1335	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1336	* @retval Auto-reload value
AnnaBridge	165:e614a9f1c9e2	1337	*/
AnnaBridge	165:e614a9f1c9e2	1338	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1339	{
AnnaBridge	165:e614a9f1c9e2	1340	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	165:e614a9f1c9e2	1341	}
AnnaBridge	165:e614a9f1c9e2	1342
AnnaBridge	165:e614a9f1c9e2	1343	/**
AnnaBridge	165:e614a9f1c9e2	1344	* @brief Set the repetition counter value.
AnnaBridge	165:e614a9f1c9e2	1345	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	1346	* whether or not a timer instance supports a repetition counter.
AnnaBridge	165:e614a9f1c9e2	1347	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
AnnaBridge	165:e614a9f1c9e2	1348	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1349	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
AnnaBridge	165:e614a9f1c9e2	1350	* @retval None
AnnaBridge	165:e614a9f1c9e2	1351	*/
AnnaBridge	165:e614a9f1c9e2	1352	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
AnnaBridge	165:e614a9f1c9e2	1353	{
AnnaBridge	165:e614a9f1c9e2	1354	WRITE_REG(TIMx->RCR, RepetitionCounter);
AnnaBridge	165:e614a9f1c9e2	1355	}
AnnaBridge	165:e614a9f1c9e2	1356
AnnaBridge	165:e614a9f1c9e2	1357	/**
AnnaBridge	165:e614a9f1c9e2	1358	* @brief Get the repetition counter value.
AnnaBridge	165:e614a9f1c9e2	1359	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	1360	* whether or not a timer instance supports a repetition counter.
AnnaBridge	165:e614a9f1c9e2	1361	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
AnnaBridge	165:e614a9f1c9e2	1362	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1363	* @retval Repetition counter value
AnnaBridge	165:e614a9f1c9e2	1364	*/
AnnaBridge	165:e614a9f1c9e2	1365	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1366	{
AnnaBridge	165:e614a9f1c9e2	1367	return (uint32_t)(READ_REG(TIMx->RCR));
AnnaBridge	165:e614a9f1c9e2	1368	}
AnnaBridge	165:e614a9f1c9e2	1369
AnnaBridge	165:e614a9f1c9e2	1370	/**
AnnaBridge	165:e614a9f1c9e2	1371	* @}
AnnaBridge	165:e614a9f1c9e2	1372	*/
AnnaBridge	165:e614a9f1c9e2	1373
AnnaBridge	165:e614a9f1c9e2	1374	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	165:e614a9f1c9e2	1375	* @{
AnnaBridge	165:e614a9f1c9e2	1376	*/
AnnaBridge	165:e614a9f1c9e2	1377	/**
AnnaBridge	165:e614a9f1c9e2	1378	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	165:e614a9f1c9e2	1379	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
AnnaBridge	165:e614a9f1c9e2	1380	* they are updated only when a commutation event (COM) occurs.
AnnaBridge	165:e614a9f1c9e2	1381	* @note Only on channels that have a complementary output.
AnnaBridge	165:e614a9f1c9e2	1382	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	1383	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	165:e614a9f1c9e2	1384	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
AnnaBridge	165:e614a9f1c9e2	1385	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1386	* @retval None
AnnaBridge	165:e614a9f1c9e2	1387	*/
AnnaBridge	165:e614a9f1c9e2	1388	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1389	{
AnnaBridge	165:e614a9f1c9e2	1390	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	165:e614a9f1c9e2	1391	}
AnnaBridge	165:e614a9f1c9e2	1392
AnnaBridge	165:e614a9f1c9e2	1393	/**
AnnaBridge	165:e614a9f1c9e2	1394	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	165:e614a9f1c9e2	1395	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	1396	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	165:e614a9f1c9e2	1397	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
AnnaBridge	165:e614a9f1c9e2	1398	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1399	* @retval None
AnnaBridge	165:e614a9f1c9e2	1400	*/
AnnaBridge	165:e614a9f1c9e2	1401	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1402	{
AnnaBridge	165:e614a9f1c9e2	1403	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	165:e614a9f1c9e2	1404	}
AnnaBridge	165:e614a9f1c9e2	1405
AnnaBridge	165:e614a9f1c9e2	1406	/**
AnnaBridge	165:e614a9f1c9e2	1407	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
AnnaBridge	165:e614a9f1c9e2	1408	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	1409	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	165:e614a9f1c9e2	1410	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
AnnaBridge	165:e614a9f1c9e2	1411	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1412	* @param CCUpdateSource This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1413	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
AnnaBridge	165:e614a9f1c9e2	1414	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
AnnaBridge	165:e614a9f1c9e2	1415	* @retval None
AnnaBridge	165:e614a9f1c9e2	1416	*/
AnnaBridge	165:e614a9f1c9e2	1417	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
AnnaBridge	165:e614a9f1c9e2	1418	{
AnnaBridge	165:e614a9f1c9e2	1419	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
AnnaBridge	165:e614a9f1c9e2	1420	}
AnnaBridge	165:e614a9f1c9e2	1421
AnnaBridge	165:e614a9f1c9e2	1422	/**
AnnaBridge	165:e614a9f1c9e2	1423	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	165:e614a9f1c9e2	1424	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	165:e614a9f1c9e2	1425	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1426	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1427	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	165:e614a9f1c9e2	1428	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	165:e614a9f1c9e2	1429	* @retval None
AnnaBridge	165:e614a9f1c9e2	1430	*/
AnnaBridge	165:e614a9f1c9e2	1431	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	165:e614a9f1c9e2	1432	{
AnnaBridge	165:e614a9f1c9e2	1433	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	165:e614a9f1c9e2	1434	}
AnnaBridge	165:e614a9f1c9e2	1435
AnnaBridge	165:e614a9f1c9e2	1436	/**
AnnaBridge	165:e614a9f1c9e2	1437	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	165:e614a9f1c9e2	1438	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	165:e614a9f1c9e2	1439	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1440	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1441	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	165:e614a9f1c9e2	1442	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	165:e614a9f1c9e2	1443	*/
AnnaBridge	165:e614a9f1c9e2	1444	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	1445	{
AnnaBridge	165:e614a9f1c9e2	1446	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	165:e614a9f1c9e2	1447	}
AnnaBridge	165:e614a9f1c9e2	1448
AnnaBridge	165:e614a9f1c9e2	1449	/**
AnnaBridge	165:e614a9f1c9e2	1450	* @brief Set the lock level to freeze the
AnnaBridge	165:e614a9f1c9e2	1451	* configuration of several capture/compare parameters.
AnnaBridge	165:e614a9f1c9e2	1452	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1453	* the lock mechanism is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	1454	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
AnnaBridge	165:e614a9f1c9e2	1455	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1456	* @param LockLevel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1457	* @arg @ref LL_TIM_LOCKLEVEL_OFF
AnnaBridge	165:e614a9f1c9e2	1458	* @arg @ref LL_TIM_LOCKLEVEL_1
AnnaBridge	165:e614a9f1c9e2	1459	* @arg @ref LL_TIM_LOCKLEVEL_2
AnnaBridge	165:e614a9f1c9e2	1460	* @arg @ref LL_TIM_LOCKLEVEL_3
AnnaBridge	165:e614a9f1c9e2	1461	* @retval None
AnnaBridge	165:e614a9f1c9e2	1462	*/
AnnaBridge	165:e614a9f1c9e2	1463	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
AnnaBridge	165:e614a9f1c9e2	1464	{
AnnaBridge	165:e614a9f1c9e2	1465	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
AnnaBridge	165:e614a9f1c9e2	1466	}
AnnaBridge	165:e614a9f1c9e2	1467
AnnaBridge	165:e614a9f1c9e2	1468	/**
AnnaBridge	165:e614a9f1c9e2	1469	* @brief Enable capture/compare channels.
AnnaBridge	165:e614a9f1c9e2	1470	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:e614a9f1c9e2	1471	* CCER CC1NE LL_TIM_CC_EnableChannel\n
AnnaBridge	165:e614a9f1c9e2	1472	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:e614a9f1c9e2	1473	* CCER CC2NE LL_TIM_CC_EnableChannel\n
AnnaBridge	165:e614a9f1c9e2	1474	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	165:e614a9f1c9e2	1475	* CCER CC3NE LL_TIM_CC_EnableChannel\n
AnnaBridge	165:e614a9f1c9e2	1476	* CCER CC4E LL_TIM_CC_EnableChannel
AnnaBridge	165:e614a9f1c9e2	1477	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1478	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	165:e614a9f1c9e2	1479	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1480	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	1481	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1482	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	1483	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1484	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	1485	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1486	* @retval None
AnnaBridge	165:e614a9f1c9e2	1487	*/
AnnaBridge	165:e614a9f1c9e2	1488	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	165:e614a9f1c9e2	1489	{
AnnaBridge	165:e614a9f1c9e2	1490	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	165:e614a9f1c9e2	1491	}
AnnaBridge	165:e614a9f1c9e2	1492
AnnaBridge	165:e614a9f1c9e2	1493	/**
AnnaBridge	165:e614a9f1c9e2	1494	* @brief Disable capture/compare channels.
AnnaBridge	165:e614a9f1c9e2	1495	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:e614a9f1c9e2	1496	* CCER CC1NE LL_TIM_CC_DisableChannel\n
AnnaBridge	165:e614a9f1c9e2	1497	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:e614a9f1c9e2	1498	* CCER CC2NE LL_TIM_CC_DisableChannel\n
AnnaBridge	165:e614a9f1c9e2	1499	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	165:e614a9f1c9e2	1500	* CCER CC3NE LL_TIM_CC_DisableChannel\n
AnnaBridge	165:e614a9f1c9e2	1501	* CCER CC4E LL_TIM_CC_DisableChannel
AnnaBridge	165:e614a9f1c9e2	1502	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1503	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	165:e614a9f1c9e2	1504	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1505	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	1506	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1507	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	1508	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1509	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	1510	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1511	* @retval None
AnnaBridge	165:e614a9f1c9e2	1512	*/
AnnaBridge	165:e614a9f1c9e2	1513	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	165:e614a9f1c9e2	1514	{
AnnaBridge	165:e614a9f1c9e2	1515	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	165:e614a9f1c9e2	1516	}
AnnaBridge	165:e614a9f1c9e2	1517
AnnaBridge	165:e614a9f1c9e2	1518	/**
AnnaBridge	165:e614a9f1c9e2	1519	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	165:e614a9f1c9e2	1520	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:e614a9f1c9e2	1521	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:e614a9f1c9e2	1522	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:e614a9f1c9e2	1523	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:e614a9f1c9e2	1524	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:e614a9f1c9e2	1525	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	165:e614a9f1c9e2	1526	* CCER CC4E LL_TIM_CC_IsEnabledChannel
AnnaBridge	165:e614a9f1c9e2	1527	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1528	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	165:e614a9f1c9e2	1529	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1530	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	1531	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1532	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	1533	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1534	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	1535	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1536	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1537	*/
AnnaBridge	165:e614a9f1c9e2	1538	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	165:e614a9f1c9e2	1539	{
AnnaBridge	165:e614a9f1c9e2	1540	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	165:e614a9f1c9e2	1541	}
AnnaBridge	165:e614a9f1c9e2	1542
AnnaBridge	165:e614a9f1c9e2	1543	/**
AnnaBridge	165:e614a9f1c9e2	1544	* @}
AnnaBridge	165:e614a9f1c9e2	1545	*/
AnnaBridge	165:e614a9f1c9e2	1546
AnnaBridge	165:e614a9f1c9e2	1547	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	165:e614a9f1c9e2	1548	* @{
AnnaBridge	165:e614a9f1c9e2	1549	*/
AnnaBridge	165:e614a9f1c9e2	1550	/**
AnnaBridge	165:e614a9f1c9e2	1551	* @brief Configure an output channel.
AnnaBridge	165:e614a9f1c9e2	1552	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1553	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1554	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1555	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1556	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1557	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1558	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1559	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1560	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1561	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1562	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
AnnaBridge	165:e614a9f1c9e2	1563	* CR2 OIS4 LL_TIM_OC_ConfigOutput
AnnaBridge	165:e614a9f1c9e2	1564	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1565	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1566	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1567	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1568	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1569	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1570	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	165:e614a9f1c9e2	1571	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	1572	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	165:e614a9f1c9e2	1573	* @retval None
AnnaBridge	165:e614a9f1c9e2	1574	*/
AnnaBridge	165:e614a9f1c9e2	1575	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	165:e614a9f1c9e2	1576	{
AnnaBridge	165:e614a9f1c9e2	1577	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1578	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1579	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1580	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	165:e614a9f1c9e2	1581	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1582	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
AnnaBridge	165:e614a9f1c9e2	1583	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1584	}
AnnaBridge	165:e614a9f1c9e2	1585
AnnaBridge	165:e614a9f1c9e2	1586	/**
AnnaBridge	165:e614a9f1c9e2	1587	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	165:e614a9f1c9e2	1588	* OCx and OCxN (when relevant) are derived.
AnnaBridge	165:e614a9f1c9e2	1589	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	165:e614a9f1c9e2	1590	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	165:e614a9f1c9e2	1591	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	165:e614a9f1c9e2	1592	* CCMR2 OC4M LL_TIM_OC_SetMode
AnnaBridge	165:e614a9f1c9e2	1593	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1594	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1595	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1596	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1597	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1598	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1599	* @param Mode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1600	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	165:e614a9f1c9e2	1601	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	165:e614a9f1c9e2	1602	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	165:e614a9f1c9e2	1603	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	165:e614a9f1c9e2	1604	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	165:e614a9f1c9e2	1605	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	165:e614a9f1c9e2	1606	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	165:e614a9f1c9e2	1607	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	165:e614a9f1c9e2	1608	* @retval None
AnnaBridge	165:e614a9f1c9e2	1609	*/
AnnaBridge	165:e614a9f1c9e2	1610	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	165:e614a9f1c9e2	1611	{
AnnaBridge	165:e614a9f1c9e2	1612	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1613	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1614	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1615	}
AnnaBridge	165:e614a9f1c9e2	1616
AnnaBridge	165:e614a9f1c9e2	1617	/**
AnnaBridge	165:e614a9f1c9e2	1618	* @brief Get the output compare mode of an output channel.
AnnaBridge	165:e614a9f1c9e2	1619	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	165:e614a9f1c9e2	1620	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	165:e614a9f1c9e2	1621	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	165:e614a9f1c9e2	1622	* CCMR2 OC4M LL_TIM_OC_GetMode
AnnaBridge	165:e614a9f1c9e2	1623	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1624	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1625	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1626	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1627	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1628	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1629	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1630	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	165:e614a9f1c9e2	1631	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	165:e614a9f1c9e2	1632	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	165:e614a9f1c9e2	1633	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	165:e614a9f1c9e2	1634	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	165:e614a9f1c9e2	1635	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	165:e614a9f1c9e2	1636	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	165:e614a9f1c9e2	1637	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	165:e614a9f1c9e2	1638	*/
AnnaBridge	165:e614a9f1c9e2	1639	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1640	{
AnnaBridge	165:e614a9f1c9e2	1641	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1642	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1643	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1644	}
AnnaBridge	165:e614a9f1c9e2	1645
AnnaBridge	165:e614a9f1c9e2	1646	/**
AnnaBridge	165:e614a9f1c9e2	1647	* @brief Set the polarity of an output channel.
AnnaBridge	165:e614a9f1c9e2	1648	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1649	* CCER CC1NP LL_TIM_OC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1650	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1651	* CCER CC2NP LL_TIM_OC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1652	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1653	* CCER CC3NP LL_TIM_OC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1654	* CCER CC4P LL_TIM_OC_SetPolarity
AnnaBridge	165:e614a9f1c9e2	1655	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1656	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1657	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1658	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	1659	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1660	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	1661	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1662	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	1663	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1664	* @param Polarity This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1665	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	165:e614a9f1c9e2	1666	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	1667	* @retval None
AnnaBridge	165:e614a9f1c9e2	1668	*/
AnnaBridge	165:e614a9f1c9e2	1669	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	165:e614a9f1c9e2	1670	{
AnnaBridge	165:e614a9f1c9e2	1671	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1672	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1673	}
AnnaBridge	165:e614a9f1c9e2	1674
AnnaBridge	165:e614a9f1c9e2	1675	/**
AnnaBridge	165:e614a9f1c9e2	1676	* @brief Get the polarity of an output channel.
AnnaBridge	165:e614a9f1c9e2	1677	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1678	* CCER CC1NP LL_TIM_OC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1679	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1680	* CCER CC2NP LL_TIM_OC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1681	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1682	* CCER CC3NP LL_TIM_OC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	1683	* CCER CC4P LL_TIM_OC_GetPolarity
AnnaBridge	165:e614a9f1c9e2	1684	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1685	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1686	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1687	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	1688	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1689	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	1690	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1691	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	1692	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1693	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1694	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	165:e614a9f1c9e2	1695	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	1696	*/
AnnaBridge	165:e614a9f1c9e2	1697	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1698	{
AnnaBridge	165:e614a9f1c9e2	1699	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1700	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1701	}
AnnaBridge	165:e614a9f1c9e2	1702
AnnaBridge	165:e614a9f1c9e2	1703	/**
AnnaBridge	165:e614a9f1c9e2	1704	* @brief Set the IDLE state of an output channel
AnnaBridge	165:e614a9f1c9e2	1705	* @note This function is significant only for the timer instances
AnnaBridge	165:e614a9f1c9e2	1706	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
AnnaBridge	165:e614a9f1c9e2	1707	* can be used to check whether or not a timer instance provides
AnnaBridge	165:e614a9f1c9e2	1708	* a break input.
AnnaBridge	165:e614a9f1c9e2	1709	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1710	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1711	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1712	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1713	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1714	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1715	* CR2 OIS4 LL_TIM_OC_SetIdleState
AnnaBridge	165:e614a9f1c9e2	1716	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1717	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1718	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1719	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	1720	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1721	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	1722	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1723	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	1724	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1725	* @param IdleState This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1726	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	165:e614a9f1c9e2	1727	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	165:e614a9f1c9e2	1728	* @retval None
AnnaBridge	165:e614a9f1c9e2	1729	*/
AnnaBridge	165:e614a9f1c9e2	1730	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
AnnaBridge	165:e614a9f1c9e2	1731	{
AnnaBridge	165:e614a9f1c9e2	1732	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1733	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1734	}
AnnaBridge	165:e614a9f1c9e2	1735
AnnaBridge	165:e614a9f1c9e2	1736	/**
AnnaBridge	165:e614a9f1c9e2	1737	* @brief Get the IDLE state of an output channel
AnnaBridge	165:e614a9f1c9e2	1738	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1739	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1740	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1741	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1742	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1743	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
AnnaBridge	165:e614a9f1c9e2	1744	* CR2 OIS4 LL_TIM_OC_GetIdleState
AnnaBridge	165:e614a9f1c9e2	1745	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1746	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1747	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1748	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	165:e614a9f1c9e2	1749	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1750	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	165:e614a9f1c9e2	1751	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1752	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	165:e614a9f1c9e2	1753	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1754	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1755	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	165:e614a9f1c9e2	1756	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	165:e614a9f1c9e2	1757	*/
AnnaBridge	165:e614a9f1c9e2	1758	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1759	{
AnnaBridge	165:e614a9f1c9e2	1760	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1761	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	1762	}
AnnaBridge	165:e614a9f1c9e2	1763
AnnaBridge	165:e614a9f1c9e2	1764	/**
AnnaBridge	165:e614a9f1c9e2	1765	* @brief Enable fast mode for the output channel.
AnnaBridge	165:e614a9f1c9e2	1766	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	165:e614a9f1c9e2	1767	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:e614a9f1c9e2	1768	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:e614a9f1c9e2	1769	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	165:e614a9f1c9e2	1770	* CCMR2 OC4FE LL_TIM_OC_EnableFast
AnnaBridge	165:e614a9f1c9e2	1771	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1772	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1773	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1774	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1775	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1776	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1777	* @retval None
AnnaBridge	165:e614a9f1c9e2	1778	*/
AnnaBridge	165:e614a9f1c9e2	1779	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1780	{
AnnaBridge	165:e614a9f1c9e2	1781	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1782	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1783	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1784
AnnaBridge	165:e614a9f1c9e2	1785	}
AnnaBridge	165:e614a9f1c9e2	1786
AnnaBridge	165:e614a9f1c9e2	1787	/**
AnnaBridge	165:e614a9f1c9e2	1788	* @brief Disable fast mode for the output channel.
AnnaBridge	165:e614a9f1c9e2	1789	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:e614a9f1c9e2	1790	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:e614a9f1c9e2	1791	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	165:e614a9f1c9e2	1792	* CCMR2 OC4FE LL_TIM_OC_DisableFast
AnnaBridge	165:e614a9f1c9e2	1793	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1794	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1795	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1796	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1797	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1798	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1799	* @retval None
AnnaBridge	165:e614a9f1c9e2	1800	*/
AnnaBridge	165:e614a9f1c9e2	1801	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1802	{
AnnaBridge	165:e614a9f1c9e2	1803	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1804	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1805	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1806
AnnaBridge	165:e614a9f1c9e2	1807	}
AnnaBridge	165:e614a9f1c9e2	1808
AnnaBridge	165:e614a9f1c9e2	1809	/**
AnnaBridge	165:e614a9f1c9e2	1810	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	165:e614a9f1c9e2	1811	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:e614a9f1c9e2	1812	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:e614a9f1c9e2	1813	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:e614a9f1c9e2	1814	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	165:e614a9f1c9e2	1815	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1816	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1817	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1818	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1819	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1820	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1821	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1822	*/
AnnaBridge	165:e614a9f1c9e2	1823	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1824	{
AnnaBridge	165:e614a9f1c9e2	1825	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1826	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1827	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	165:e614a9f1c9e2	1828	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	165:e614a9f1c9e2	1829	}
AnnaBridge	165:e614a9f1c9e2	1830
AnnaBridge	165:e614a9f1c9e2	1831	/**
AnnaBridge	165:e614a9f1c9e2	1832	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	165:e614a9f1c9e2	1833	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:e614a9f1c9e2	1834	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:e614a9f1c9e2	1835	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	165:e614a9f1c9e2	1836	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
AnnaBridge	165:e614a9f1c9e2	1837	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1838	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1839	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1840	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1841	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1842	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1843	* @retval None
AnnaBridge	165:e614a9f1c9e2	1844	*/
AnnaBridge	165:e614a9f1c9e2	1845	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1846	{
AnnaBridge	165:e614a9f1c9e2	1847	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1848	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1849	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1850	}
AnnaBridge	165:e614a9f1c9e2	1851
AnnaBridge	165:e614a9f1c9e2	1852	/**
AnnaBridge	165:e614a9f1c9e2	1853	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	165:e614a9f1c9e2	1854	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:e614a9f1c9e2	1855	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:e614a9f1c9e2	1856	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	165:e614a9f1c9e2	1857	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
AnnaBridge	165:e614a9f1c9e2	1858	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1859	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1860	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1861	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1862	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1863	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1864	* @retval None
AnnaBridge	165:e614a9f1c9e2	1865	*/
AnnaBridge	165:e614a9f1c9e2	1866	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1867	{
AnnaBridge	165:e614a9f1c9e2	1868	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1869	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1870	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1871	}
AnnaBridge	165:e614a9f1c9e2	1872
AnnaBridge	165:e614a9f1c9e2	1873	/**
AnnaBridge	165:e614a9f1c9e2	1874	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	165:e614a9f1c9e2	1875	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:e614a9f1c9e2	1876	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:e614a9f1c9e2	1877	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:e614a9f1c9e2	1878	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	165:e614a9f1c9e2	1879	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1880	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1881	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1882	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1883	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1884	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1885	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1886	*/
AnnaBridge	165:e614a9f1c9e2	1887	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1888	{
AnnaBridge	165:e614a9f1c9e2	1889	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1890	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1891	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	165:e614a9f1c9e2	1892	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	165:e614a9f1c9e2	1893	}
AnnaBridge	165:e614a9f1c9e2	1894
AnnaBridge	165:e614a9f1c9e2	1895	/**
AnnaBridge	165:e614a9f1c9e2	1896	* @brief Enable clearing the output channel on an external event.
AnnaBridge	165:e614a9f1c9e2	1897	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	165:e614a9f1c9e2	1898	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:e614a9f1c9e2	1899	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	165:e614a9f1c9e2	1900	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:e614a9f1c9e2	1901	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:e614a9f1c9e2	1902	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	165:e614a9f1c9e2	1903	* CCMR2 OC4CE LL_TIM_OC_EnableClear
AnnaBridge	165:e614a9f1c9e2	1904	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1905	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1906	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1907	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1908	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1909	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1910	* @retval None
AnnaBridge	165:e614a9f1c9e2	1911	*/
AnnaBridge	165:e614a9f1c9e2	1912	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1913	{
AnnaBridge	165:e614a9f1c9e2	1914	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1915	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1916	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1917	}
AnnaBridge	165:e614a9f1c9e2	1918
AnnaBridge	165:e614a9f1c9e2	1919	/**
AnnaBridge	165:e614a9f1c9e2	1920	* @brief Disable clearing the output channel on an external event.
AnnaBridge	165:e614a9f1c9e2	1921	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:e614a9f1c9e2	1922	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	165:e614a9f1c9e2	1923	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:e614a9f1c9e2	1924	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:e614a9f1c9e2	1925	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	165:e614a9f1c9e2	1926	* CCMR2 OC4CE LL_TIM_OC_DisableClear
AnnaBridge	165:e614a9f1c9e2	1927	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1928	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1929	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1930	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1931	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1932	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1933	* @retval None
AnnaBridge	165:e614a9f1c9e2	1934	*/
AnnaBridge	165:e614a9f1c9e2	1935	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1936	{
AnnaBridge	165:e614a9f1c9e2	1937	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1938	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1939	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1940	}
AnnaBridge	165:e614a9f1c9e2	1941
AnnaBridge	165:e614a9f1c9e2	1942	/**
AnnaBridge	165:e614a9f1c9e2	1943	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	165:e614a9f1c9e2	1944	* @note This function enables clearing the output channel on an external event.
AnnaBridge	165:e614a9f1c9e2	1945	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	165:e614a9f1c9e2	1946	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	165:e614a9f1c9e2	1947	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	165:e614a9f1c9e2	1948	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:e614a9f1c9e2	1949	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:e614a9f1c9e2	1950	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:e614a9f1c9e2	1951	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	165:e614a9f1c9e2	1952	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1953	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1954	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	1955	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	1956	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	1957	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	1958	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1959	*/
AnnaBridge	165:e614a9f1c9e2	1960	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	1961	{
AnnaBridge	165:e614a9f1c9e2	1962	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	1963	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	1964	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	165:e614a9f1c9e2	1965	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	165:e614a9f1c9e2	1966	}
AnnaBridge	165:e614a9f1c9e2	1967
AnnaBridge	165:e614a9f1c9e2	1968	/**
AnnaBridge	165:e614a9f1c9e2	1969	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
AnnaBridge	165:e614a9f1c9e2	1970	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1971	* dead-time insertion feature is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	1972	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
AnnaBridge	165:e614a9f1c9e2	1973	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
AnnaBridge	165:e614a9f1c9e2	1974	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1975	* @param DeadTime between Min_Data=0 and Max_Data=255
AnnaBridge	165:e614a9f1c9e2	1976	* @retval None
AnnaBridge	165:e614a9f1c9e2	1977	*/
AnnaBridge	165:e614a9f1c9e2	1978	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
AnnaBridge	165:e614a9f1c9e2	1979	{
AnnaBridge	165:e614a9f1c9e2	1980	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
AnnaBridge	165:e614a9f1c9e2	1981	}
AnnaBridge	165:e614a9f1c9e2	1982
AnnaBridge	165:e614a9f1c9e2	1983	/**
AnnaBridge	165:e614a9f1c9e2	1984	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	165:e614a9f1c9e2	1985	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1986	* output channel 1 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	1987	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	165:e614a9f1c9e2	1988	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	1989	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:e614a9f1c9e2	1990	* @retval None
AnnaBridge	165:e614a9f1c9e2	1991	*/
AnnaBridge	165:e614a9f1c9e2	1992	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:e614a9f1c9e2	1993	{
AnnaBridge	165:e614a9f1c9e2	1994	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	165:e614a9f1c9e2	1995	}
AnnaBridge	165:e614a9f1c9e2	1996
AnnaBridge	165:e614a9f1c9e2	1997	/**
AnnaBridge	165:e614a9f1c9e2	1998	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	165:e614a9f1c9e2	1999	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2000	* output channel 2 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2001	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	165:e614a9f1c9e2	2002	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2003	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:e614a9f1c9e2	2004	* @retval None
AnnaBridge	165:e614a9f1c9e2	2005	*/
AnnaBridge	165:e614a9f1c9e2	2006	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:e614a9f1c9e2	2007	{
AnnaBridge	165:e614a9f1c9e2	2008	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	165:e614a9f1c9e2	2009	}
AnnaBridge	165:e614a9f1c9e2	2010
AnnaBridge	165:e614a9f1c9e2	2011	/**
AnnaBridge	165:e614a9f1c9e2	2012	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	165:e614a9f1c9e2	2013	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2014	* output channel is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2015	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	165:e614a9f1c9e2	2016	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2017	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:e614a9f1c9e2	2018	* @retval None
AnnaBridge	165:e614a9f1c9e2	2019	*/
AnnaBridge	165:e614a9f1c9e2	2020	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:e614a9f1c9e2	2021	{
AnnaBridge	165:e614a9f1c9e2	2022	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	165:e614a9f1c9e2	2023	}
AnnaBridge	165:e614a9f1c9e2	2024
AnnaBridge	165:e614a9f1c9e2	2025	/**
AnnaBridge	165:e614a9f1c9e2	2026	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	165:e614a9f1c9e2	2027	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2028	* output channel 4 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2029	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	165:e614a9f1c9e2	2030	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2031	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	165:e614a9f1c9e2	2032	* @retval None
AnnaBridge	165:e614a9f1c9e2	2033	*/
AnnaBridge	165:e614a9f1c9e2	2034	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	165:e614a9f1c9e2	2035	{
AnnaBridge	165:e614a9f1c9e2	2036	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	165:e614a9f1c9e2	2037	}
AnnaBridge	165:e614a9f1c9e2	2038
AnnaBridge	165:e614a9f1c9e2	2039	/**
AnnaBridge	165:e614a9f1c9e2	2040	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	165:e614a9f1c9e2	2041	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2042	* output channel 1 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2043	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	165:e614a9f1c9e2	2044	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2045	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2046	*/
AnnaBridge	165:e614a9f1c9e2	2047	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2048	{
AnnaBridge	165:e614a9f1c9e2	2049	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	165:e614a9f1c9e2	2050	}
AnnaBridge	165:e614a9f1c9e2	2051
AnnaBridge	165:e614a9f1c9e2	2052	/**
AnnaBridge	165:e614a9f1c9e2	2053	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	165:e614a9f1c9e2	2054	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2055	* output channel 2 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2056	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	165:e614a9f1c9e2	2057	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2058	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2059	*/
AnnaBridge	165:e614a9f1c9e2	2060	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2061	{
AnnaBridge	165:e614a9f1c9e2	2062	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	165:e614a9f1c9e2	2063	}
AnnaBridge	165:e614a9f1c9e2	2064
AnnaBridge	165:e614a9f1c9e2	2065	/**
AnnaBridge	165:e614a9f1c9e2	2066	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	165:e614a9f1c9e2	2067	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2068	* output channel 3 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2069	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	165:e614a9f1c9e2	2070	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2071	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2072	*/
AnnaBridge	165:e614a9f1c9e2	2073	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2074	{
AnnaBridge	165:e614a9f1c9e2	2075	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	165:e614a9f1c9e2	2076	}
AnnaBridge	165:e614a9f1c9e2	2077
AnnaBridge	165:e614a9f1c9e2	2078	/**
AnnaBridge	165:e614a9f1c9e2	2079	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	165:e614a9f1c9e2	2080	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2081	* output channel 4 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2082	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	165:e614a9f1c9e2	2083	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2084	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2085	*/
AnnaBridge	165:e614a9f1c9e2	2086	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2087	{
AnnaBridge	165:e614a9f1c9e2	2088	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	165:e614a9f1c9e2	2089	}
AnnaBridge	165:e614a9f1c9e2	2090
AnnaBridge	165:e614a9f1c9e2	2091	/**
AnnaBridge	165:e614a9f1c9e2	2092	* @}
AnnaBridge	165:e614a9f1c9e2	2093	*/
AnnaBridge	165:e614a9f1c9e2	2094
AnnaBridge	165:e614a9f1c9e2	2095	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	165:e614a9f1c9e2	2096	* @{
AnnaBridge	165:e614a9f1c9e2	2097	*/
AnnaBridge	165:e614a9f1c9e2	2098	/**
AnnaBridge	165:e614a9f1c9e2	2099	* @brief Configure input channel.
AnnaBridge	165:e614a9f1c9e2	2100	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2101	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2102	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2103	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2104	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2105	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2106	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2107	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2108	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2109	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2110	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2111	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2112	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2113	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2114	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2115	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2116	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2117	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2118	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	165:e614a9f1c9e2	2119	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2120	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2121	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2122	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2123	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2124	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2125	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	165:e614a9f1c9e2	2126	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	165:e614a9f1c9e2	2127	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:e614a9f1c9e2	2128	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	165:e614a9f1c9e2	2129	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	165:e614a9f1c9e2	2130	* @retval None
AnnaBridge	165:e614a9f1c9e2	2131	*/
AnnaBridge	165:e614a9f1c9e2	2132	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	165:e614a9f1c9e2	2133	{
AnnaBridge	165:e614a9f1c9e2	2134	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2135	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	2136	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	165:e614a9f1c9e2	2137	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	2138	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	165:e614a9f1c9e2	2139	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:e614a9f1c9e2	2140	}
AnnaBridge	165:e614a9f1c9e2	2141
AnnaBridge	165:e614a9f1c9e2	2142	/**
AnnaBridge	165:e614a9f1c9e2	2143	* @brief Set the active input.
AnnaBridge	165:e614a9f1c9e2	2144	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	165:e614a9f1c9e2	2145	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	165:e614a9f1c9e2	2146	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	165:e614a9f1c9e2	2147	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	165:e614a9f1c9e2	2148	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2149	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2150	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2151	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2152	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2153	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2154	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2155	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	165:e614a9f1c9e2	2156	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	165:e614a9f1c9e2	2157	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	165:e614a9f1c9e2	2158	* @retval None
AnnaBridge	165:e614a9f1c9e2	2159	*/
AnnaBridge	165:e614a9f1c9e2	2160	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	165:e614a9f1c9e2	2161	{
AnnaBridge	165:e614a9f1c9e2	2162	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2163	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	2164	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	2165	}
AnnaBridge	165:e614a9f1c9e2	2166
AnnaBridge	165:e614a9f1c9e2	2167	/**
AnnaBridge	165:e614a9f1c9e2	2168	* @brief Get the current active input.
AnnaBridge	165:e614a9f1c9e2	2169	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	165:e614a9f1c9e2	2170	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	165:e614a9f1c9e2	2171	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	165:e614a9f1c9e2	2172	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	165:e614a9f1c9e2	2173	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2174	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2175	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2176	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2177	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2178	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2179	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2180	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	165:e614a9f1c9e2	2181	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	165:e614a9f1c9e2	2182	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	165:e614a9f1c9e2	2183	*/
AnnaBridge	165:e614a9f1c9e2	2184	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	2185	{
AnnaBridge	165:e614a9f1c9e2	2186	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2187	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	2188	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	165:e614a9f1c9e2	2189	}
AnnaBridge	165:e614a9f1c9e2	2190
AnnaBridge	165:e614a9f1c9e2	2191	/**
AnnaBridge	165:e614a9f1c9e2	2192	* @brief Set the prescaler of input channel.
AnnaBridge	165:e614a9f1c9e2	2193	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	165:e614a9f1c9e2	2194	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	165:e614a9f1c9e2	2195	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	165:e614a9f1c9e2	2196	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	165:e614a9f1c9e2	2197	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2198	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2199	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2200	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2201	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2202	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2203	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2204	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	165:e614a9f1c9e2	2205	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	165:e614a9f1c9e2	2206	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	165:e614a9f1c9e2	2207	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:e614a9f1c9e2	2208	* @retval None
AnnaBridge	165:e614a9f1c9e2	2209	*/
AnnaBridge	165:e614a9f1c9e2	2210	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	165:e614a9f1c9e2	2211	{
AnnaBridge	165:e614a9f1c9e2	2212	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2213	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	2214	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	2215	}
AnnaBridge	165:e614a9f1c9e2	2216
AnnaBridge	165:e614a9f1c9e2	2217	/**
AnnaBridge	165:e614a9f1c9e2	2218	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	165:e614a9f1c9e2	2219	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	165:e614a9f1c9e2	2220	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	165:e614a9f1c9e2	2221	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	165:e614a9f1c9e2	2222	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	165:e614a9f1c9e2	2223	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2224	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2225	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2226	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2227	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2228	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2229	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2230	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	165:e614a9f1c9e2	2231	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	165:e614a9f1c9e2	2232	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	165:e614a9f1c9e2	2233	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	165:e614a9f1c9e2	2234	*/
AnnaBridge	165:e614a9f1c9e2	2235	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	2236	{
AnnaBridge	165:e614a9f1c9e2	2237	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2238	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	2239	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	165:e614a9f1c9e2	2240	}
AnnaBridge	165:e614a9f1c9e2	2241
AnnaBridge	165:e614a9f1c9e2	2242	/**
AnnaBridge	165:e614a9f1c9e2	2243	* @brief Set the input filter duration.
AnnaBridge	165:e614a9f1c9e2	2244	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	165:e614a9f1c9e2	2245	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	165:e614a9f1c9e2	2246	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	165:e614a9f1c9e2	2247	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	165:e614a9f1c9e2	2248	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2249	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2250	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2251	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2252	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2253	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2254	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2255	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	165:e614a9f1c9e2	2256	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	165:e614a9f1c9e2	2257	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	165:e614a9f1c9e2	2258	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	165:e614a9f1c9e2	2259	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	165:e614a9f1c9e2	2260	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	165:e614a9f1c9e2	2261	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	165:e614a9f1c9e2	2262	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	165:e614a9f1c9e2	2263	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	165:e614a9f1c9e2	2264	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	165:e614a9f1c9e2	2265	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	165:e614a9f1c9e2	2266	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	165:e614a9f1c9e2	2267	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	165:e614a9f1c9e2	2268	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	165:e614a9f1c9e2	2269	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	165:e614a9f1c9e2	2270	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	165:e614a9f1c9e2	2271	* @retval None
AnnaBridge	165:e614a9f1c9e2	2272	*/
AnnaBridge	165:e614a9f1c9e2	2273	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	165:e614a9f1c9e2	2274	{
AnnaBridge	165:e614a9f1c9e2	2275	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2276	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	2277	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	165:e614a9f1c9e2	2278	}
AnnaBridge	165:e614a9f1c9e2	2279
AnnaBridge	165:e614a9f1c9e2	2280	/**
AnnaBridge	165:e614a9f1c9e2	2281	* @brief Get the input filter duration.
AnnaBridge	165:e614a9f1c9e2	2282	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	165:e614a9f1c9e2	2283	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	165:e614a9f1c9e2	2284	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	165:e614a9f1c9e2	2285	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	165:e614a9f1c9e2	2286	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2287	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2288	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2289	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2290	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2291	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2292	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2293	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	165:e614a9f1c9e2	2294	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	165:e614a9f1c9e2	2295	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	165:e614a9f1c9e2	2296	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	165:e614a9f1c9e2	2297	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	165:e614a9f1c9e2	2298	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	165:e614a9f1c9e2	2299	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	165:e614a9f1c9e2	2300	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	165:e614a9f1c9e2	2301	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	165:e614a9f1c9e2	2302	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	165:e614a9f1c9e2	2303	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	165:e614a9f1c9e2	2304	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	165:e614a9f1c9e2	2305	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	165:e614a9f1c9e2	2306	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	165:e614a9f1c9e2	2307	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	165:e614a9f1c9e2	2308	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	165:e614a9f1c9e2	2309	*/
AnnaBridge	165:e614a9f1c9e2	2310	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	2311	{
AnnaBridge	165:e614a9f1c9e2	2312	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2313	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	165:e614a9f1c9e2	2314	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	165:e614a9f1c9e2	2315	}
AnnaBridge	165:e614a9f1c9e2	2316
AnnaBridge	165:e614a9f1c9e2	2317	/**
AnnaBridge	165:e614a9f1c9e2	2318	* @brief Set the input channel polarity.
AnnaBridge	165:e614a9f1c9e2	2319	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2320	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2321	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2322	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2323	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2324	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2325	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2326	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2327	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2328	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2329	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2330	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2331	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2332	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2333	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	165:e614a9f1c9e2	2334	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	165:e614a9f1c9e2	2335	* @retval None
AnnaBridge	165:e614a9f1c9e2	2336	*/
AnnaBridge	165:e614a9f1c9e2	2337	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	165:e614a9f1c9e2	2338	{
AnnaBridge	165:e614a9f1c9e2	2339	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2340	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	165:e614a9f1c9e2	2341	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:e614a9f1c9e2	2342	}
AnnaBridge	165:e614a9f1c9e2	2343
AnnaBridge	165:e614a9f1c9e2	2344	/**
AnnaBridge	165:e614a9f1c9e2	2345	* @brief Get the current input channel polarity.
AnnaBridge	165:e614a9f1c9e2	2346	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2347	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2348	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2349	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2350	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2351	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2352	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	165:e614a9f1c9e2	2353	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2354	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2355	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	165:e614a9f1c9e2	2356	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	165:e614a9f1c9e2	2357	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	165:e614a9f1c9e2	2358	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	165:e614a9f1c9e2	2359	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2360	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	165:e614a9f1c9e2	2361	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	165:e614a9f1c9e2	2362	*/
AnnaBridge	165:e614a9f1c9e2	2363	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	2364	{
AnnaBridge	165:e614a9f1c9e2	2365	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	165:e614a9f1c9e2	2366	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	165:e614a9f1c9e2	2367	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	165:e614a9f1c9e2	2368	}
AnnaBridge	165:e614a9f1c9e2	2369
AnnaBridge	165:e614a9f1c9e2	2370	/**
AnnaBridge	165:e614a9f1c9e2	2371	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	165:e614a9f1c9e2	2372	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2373	* a timer instance provides an XOR input.
AnnaBridge	165:e614a9f1c9e2	2374	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	165:e614a9f1c9e2	2375	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2376	* @retval None
AnnaBridge	165:e614a9f1c9e2	2377	*/
AnnaBridge	165:e614a9f1c9e2	2378	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2379	{
AnnaBridge	165:e614a9f1c9e2	2380	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	165:e614a9f1c9e2	2381	}
AnnaBridge	165:e614a9f1c9e2	2382
AnnaBridge	165:e614a9f1c9e2	2383	/**
AnnaBridge	165:e614a9f1c9e2	2384	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	165:e614a9f1c9e2	2385	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2386	* a timer instance provides an XOR input.
AnnaBridge	165:e614a9f1c9e2	2387	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	165:e614a9f1c9e2	2388	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2389	* @retval None
AnnaBridge	165:e614a9f1c9e2	2390	*/
AnnaBridge	165:e614a9f1c9e2	2391	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2392	{
AnnaBridge	165:e614a9f1c9e2	2393	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	165:e614a9f1c9e2	2394	}
AnnaBridge	165:e614a9f1c9e2	2395
AnnaBridge	165:e614a9f1c9e2	2396	/**
AnnaBridge	165:e614a9f1c9e2	2397	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	165:e614a9f1c9e2	2398	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2399	* a timer instance provides an XOR input.
AnnaBridge	165:e614a9f1c9e2	2400	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	165:e614a9f1c9e2	2401	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2402	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2403	*/
AnnaBridge	165:e614a9f1c9e2	2404	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2405	{
AnnaBridge	165:e614a9f1c9e2	2406	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	165:e614a9f1c9e2	2407	}
AnnaBridge	165:e614a9f1c9e2	2408
AnnaBridge	165:e614a9f1c9e2	2409	/**
AnnaBridge	165:e614a9f1c9e2	2410	* @brief Get captured value for input channel 1.
AnnaBridge	165:e614a9f1c9e2	2411	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2412	* input channel 1 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2413	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	165:e614a9f1c9e2	2414	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2415	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2416	*/
AnnaBridge	165:e614a9f1c9e2	2417	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2418	{
AnnaBridge	165:e614a9f1c9e2	2419	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	165:e614a9f1c9e2	2420	}
AnnaBridge	165:e614a9f1c9e2	2421
AnnaBridge	165:e614a9f1c9e2	2422	/**
AnnaBridge	165:e614a9f1c9e2	2423	* @brief Get captured value for input channel 2.
AnnaBridge	165:e614a9f1c9e2	2424	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2425	* input channel 2 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2426	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	165:e614a9f1c9e2	2427	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2428	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2429	*/
AnnaBridge	165:e614a9f1c9e2	2430	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2431	{
AnnaBridge	165:e614a9f1c9e2	2432	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	165:e614a9f1c9e2	2433	}
AnnaBridge	165:e614a9f1c9e2	2434
AnnaBridge	165:e614a9f1c9e2	2435	/**
AnnaBridge	165:e614a9f1c9e2	2436	* @brief Get captured value for input channel 3.
AnnaBridge	165:e614a9f1c9e2	2437	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2438	* input channel 3 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2439	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	165:e614a9f1c9e2	2440	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2441	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2442	*/
AnnaBridge	165:e614a9f1c9e2	2443	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2444	{
AnnaBridge	165:e614a9f1c9e2	2445	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	165:e614a9f1c9e2	2446	}
AnnaBridge	165:e614a9f1c9e2	2447
AnnaBridge	165:e614a9f1c9e2	2448	/**
AnnaBridge	165:e614a9f1c9e2	2449	* @brief Get captured value for input channel 4.
AnnaBridge	165:e614a9f1c9e2	2450	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2451	* input channel 4 is supported by a timer instance.
AnnaBridge	165:e614a9f1c9e2	2452	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	165:e614a9f1c9e2	2453	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2454	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	165:e614a9f1c9e2	2455	*/
AnnaBridge	165:e614a9f1c9e2	2456	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2457	{
AnnaBridge	165:e614a9f1c9e2	2458	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	165:e614a9f1c9e2	2459	}
AnnaBridge	165:e614a9f1c9e2	2460
AnnaBridge	165:e614a9f1c9e2	2461	/**
AnnaBridge	165:e614a9f1c9e2	2462	* @}
AnnaBridge	165:e614a9f1c9e2	2463	*/
AnnaBridge	165:e614a9f1c9e2	2464
AnnaBridge	165:e614a9f1c9e2	2465	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	165:e614a9f1c9e2	2466	* @{
AnnaBridge	165:e614a9f1c9e2	2467	*/
AnnaBridge	165:e614a9f1c9e2	2468	/**
AnnaBridge	165:e614a9f1c9e2	2469	* @brief Enable external clock mode 2.
AnnaBridge	165:e614a9f1c9e2	2470	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	165:e614a9f1c9e2	2471	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	2472	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:e614a9f1c9e2	2473	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	165:e614a9f1c9e2	2474	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2475	* @retval None
AnnaBridge	165:e614a9f1c9e2	2476	*/
AnnaBridge	165:e614a9f1c9e2	2477	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2478	{
AnnaBridge	165:e614a9f1c9e2	2479	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	165:e614a9f1c9e2	2480	}
AnnaBridge	165:e614a9f1c9e2	2481
AnnaBridge	165:e614a9f1c9e2	2482	/**
AnnaBridge	165:e614a9f1c9e2	2483	* @brief Disable external clock mode 2.
AnnaBridge	165:e614a9f1c9e2	2484	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	2485	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:e614a9f1c9e2	2486	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	165:e614a9f1c9e2	2487	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2488	* @retval None
AnnaBridge	165:e614a9f1c9e2	2489	*/
AnnaBridge	165:e614a9f1c9e2	2490	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2491	{
AnnaBridge	165:e614a9f1c9e2	2492	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	165:e614a9f1c9e2	2493	}
AnnaBridge	165:e614a9f1c9e2	2494
AnnaBridge	165:e614a9f1c9e2	2495	/**
AnnaBridge	165:e614a9f1c9e2	2496	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	165:e614a9f1c9e2	2497	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	2498	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:e614a9f1c9e2	2499	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	165:e614a9f1c9e2	2500	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2501	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2502	*/
AnnaBridge	165:e614a9f1c9e2	2503	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2504	{
AnnaBridge	165:e614a9f1c9e2	2505	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	165:e614a9f1c9e2	2506	}
AnnaBridge	165:e614a9f1c9e2	2507
AnnaBridge	165:e614a9f1c9e2	2508	/**
AnnaBridge	165:e614a9f1c9e2	2509	* @brief Set the clock source of the counter clock.
AnnaBridge	165:e614a9f1c9e2	2510	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	165:e614a9f1c9e2	2511	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	165:e614a9f1c9e2	2512	* function. This timer input must be configured by calling
AnnaBridge	165:e614a9f1c9e2	2513	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	165:e614a9f1c9e2	2514	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	2515	* whether or not a timer instance supports external clock mode1.
AnnaBridge	165:e614a9f1c9e2	2516	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	2517	* whether or not a timer instance supports external clock mode2.
AnnaBridge	165:e614a9f1c9e2	2518	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	165:e614a9f1c9e2	2519	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	165:e614a9f1c9e2	2520	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2521	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2522	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	165:e614a9f1c9e2	2523	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	165:e614a9f1c9e2	2524	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	165:e614a9f1c9e2	2525	* @retval None
AnnaBridge	165:e614a9f1c9e2	2526	*/
AnnaBridge	165:e614a9f1c9e2	2527	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	165:e614a9f1c9e2	2528	{
AnnaBridge	165:e614a9f1c9e2	2529	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	165:e614a9f1c9e2	2530	}
AnnaBridge	165:e614a9f1c9e2	2531
AnnaBridge	165:e614a9f1c9e2	2532	/**
AnnaBridge	165:e614a9f1c9e2	2533	* @brief Set the encoder interface mode.
AnnaBridge	165:e614a9f1c9e2	2534	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	2535	* whether or not a timer instance supports the encoder mode.
AnnaBridge	165:e614a9f1c9e2	2536	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	165:e614a9f1c9e2	2537	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2538	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2539	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	165:e614a9f1c9e2	2540	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	165:e614a9f1c9e2	2541	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	165:e614a9f1c9e2	2542	* @retval None
AnnaBridge	165:e614a9f1c9e2	2543	*/
AnnaBridge	165:e614a9f1c9e2	2544	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	165:e614a9f1c9e2	2545	{
AnnaBridge	165:e614a9f1c9e2	2546	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	165:e614a9f1c9e2	2547	}
AnnaBridge	165:e614a9f1c9e2	2548
AnnaBridge	165:e614a9f1c9e2	2549	/**
AnnaBridge	165:e614a9f1c9e2	2550	* @}
AnnaBridge	165:e614a9f1c9e2	2551	*/
AnnaBridge	165:e614a9f1c9e2	2552
AnnaBridge	165:e614a9f1c9e2	2553	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	165:e614a9f1c9e2	2554	* @{
AnnaBridge	165:e614a9f1c9e2	2555	*/
AnnaBridge	165:e614a9f1c9e2	2556	/**
AnnaBridge	165:e614a9f1c9e2	2557	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	165:e614a9f1c9e2	2558	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	165:e614a9f1c9e2	2559	* whether or not a timer instance can operate as a master timer.
AnnaBridge	165:e614a9f1c9e2	2560	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	165:e614a9f1c9e2	2561	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2562	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2563	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	165:e614a9f1c9e2	2564	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	165:e614a9f1c9e2	2565	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	165:e614a9f1c9e2	2566	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	165:e614a9f1c9e2	2567	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	165:e614a9f1c9e2	2568	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	165:e614a9f1c9e2	2569	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	165:e614a9f1c9e2	2570	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	165:e614a9f1c9e2	2571	* @retval None
AnnaBridge	165:e614a9f1c9e2	2572	*/
AnnaBridge	165:e614a9f1c9e2	2573	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	165:e614a9f1c9e2	2574	{
AnnaBridge	165:e614a9f1c9e2	2575	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	165:e614a9f1c9e2	2576	}
AnnaBridge	165:e614a9f1c9e2	2577
AnnaBridge	165:e614a9f1c9e2	2578	/**
AnnaBridge	165:e614a9f1c9e2	2579	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	165:e614a9f1c9e2	2580	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2581	* a timer instance can operate as a slave timer.
AnnaBridge	165:e614a9f1c9e2	2582	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	165:e614a9f1c9e2	2583	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2584	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2585	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	165:e614a9f1c9e2	2586	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	165:e614a9f1c9e2	2587	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	165:e614a9f1c9e2	2588	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	165:e614a9f1c9e2	2589	* @retval None
AnnaBridge	165:e614a9f1c9e2	2590	*/
AnnaBridge	165:e614a9f1c9e2	2591	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	165:e614a9f1c9e2	2592	{
AnnaBridge	165:e614a9f1c9e2	2593	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	165:e614a9f1c9e2	2594	}
AnnaBridge	165:e614a9f1c9e2	2595
AnnaBridge	165:e614a9f1c9e2	2596	/**
AnnaBridge	165:e614a9f1c9e2	2597	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	165:e614a9f1c9e2	2598	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2599	* a timer instance can operate as a slave timer.
AnnaBridge	165:e614a9f1c9e2	2600	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	165:e614a9f1c9e2	2601	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2602	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2603	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	165:e614a9f1c9e2	2604	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	165:e614a9f1c9e2	2605	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	165:e614a9f1c9e2	2606	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	165:e614a9f1c9e2	2607	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	165:e614a9f1c9e2	2608	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	165:e614a9f1c9e2	2609	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	165:e614a9f1c9e2	2610	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	165:e614a9f1c9e2	2611	* @retval None
AnnaBridge	165:e614a9f1c9e2	2612	*/
AnnaBridge	165:e614a9f1c9e2	2613	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	165:e614a9f1c9e2	2614	{
AnnaBridge	165:e614a9f1c9e2	2615	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	165:e614a9f1c9e2	2616	}
AnnaBridge	165:e614a9f1c9e2	2617
AnnaBridge	165:e614a9f1c9e2	2618	/**
AnnaBridge	165:e614a9f1c9e2	2619	* @brief Enable the Master/Slave mode.
AnnaBridge	165:e614a9f1c9e2	2620	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2621	* a timer instance can operate as a slave timer.
AnnaBridge	165:e614a9f1c9e2	2622	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	165:e614a9f1c9e2	2623	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2624	* @retval None
AnnaBridge	165:e614a9f1c9e2	2625	*/
AnnaBridge	165:e614a9f1c9e2	2626	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2627	{
AnnaBridge	165:e614a9f1c9e2	2628	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	165:e614a9f1c9e2	2629	}
AnnaBridge	165:e614a9f1c9e2	2630
AnnaBridge	165:e614a9f1c9e2	2631	/**
AnnaBridge	165:e614a9f1c9e2	2632	* @brief Disable the Master/Slave mode.
AnnaBridge	165:e614a9f1c9e2	2633	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2634	* a timer instance can operate as a slave timer.
AnnaBridge	165:e614a9f1c9e2	2635	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	165:e614a9f1c9e2	2636	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2637	* @retval None
AnnaBridge	165:e614a9f1c9e2	2638	*/
AnnaBridge	165:e614a9f1c9e2	2639	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2640	{
AnnaBridge	165:e614a9f1c9e2	2641	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	165:e614a9f1c9e2	2642	}
AnnaBridge	165:e614a9f1c9e2	2643
AnnaBridge	165:e614a9f1c9e2	2644	/**
AnnaBridge	165:e614a9f1c9e2	2645	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	165:e614a9f1c9e2	2646	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2647	* a timer instance can operate as a slave timer.
AnnaBridge	165:e614a9f1c9e2	2648	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	165:e614a9f1c9e2	2649	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2650	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2651	*/
AnnaBridge	165:e614a9f1c9e2	2652	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2653	{
AnnaBridge	165:e614a9f1c9e2	2654	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	165:e614a9f1c9e2	2655	}
AnnaBridge	165:e614a9f1c9e2	2656
AnnaBridge	165:e614a9f1c9e2	2657	/**
AnnaBridge	165:e614a9f1c9e2	2658	* @brief Configure the external trigger (ETR) input.
AnnaBridge	165:e614a9f1c9e2	2659	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2660	* a timer instance provides an external trigger input.
AnnaBridge	165:e614a9f1c9e2	2661	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	165:e614a9f1c9e2	2662	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	165:e614a9f1c9e2	2663	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	165:e614a9f1c9e2	2664	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2665	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2666	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	165:e614a9f1c9e2	2667	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	165:e614a9f1c9e2	2668	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2669	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	165:e614a9f1c9e2	2670	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	165:e614a9f1c9e2	2671	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	165:e614a9f1c9e2	2672	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	165:e614a9f1c9e2	2673	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2674	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	165:e614a9f1c9e2	2675	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	165:e614a9f1c9e2	2676	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	165:e614a9f1c9e2	2677	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	165:e614a9f1c9e2	2678	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	165:e614a9f1c9e2	2679	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	165:e614a9f1c9e2	2680	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	165:e614a9f1c9e2	2681	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	165:e614a9f1c9e2	2682	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	165:e614a9f1c9e2	2683	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	165:e614a9f1c9e2	2684	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	165:e614a9f1c9e2	2685	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	165:e614a9f1c9e2	2686	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	165:e614a9f1c9e2	2687	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	165:e614a9f1c9e2	2688	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	165:e614a9f1c9e2	2689	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	165:e614a9f1c9e2	2690	* @retval None
AnnaBridge	165:e614a9f1c9e2	2691	*/
AnnaBridge	165:e614a9f1c9e2	2692	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	165:e614a9f1c9e2	2693	uint32_t ETRFilter)
AnnaBridge	165:e614a9f1c9e2	2694	{
AnnaBridge	165:e614a9f1c9e2	2695	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	165:e614a9f1c9e2	2696	}
AnnaBridge	165:e614a9f1c9e2	2697
AnnaBridge	165:e614a9f1c9e2	2698	/**
AnnaBridge	165:e614a9f1c9e2	2699	* @}
AnnaBridge	165:e614a9f1c9e2	2700	*/
AnnaBridge	165:e614a9f1c9e2	2701
AnnaBridge	165:e614a9f1c9e2	2702	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
AnnaBridge	165:e614a9f1c9e2	2703	* @{
AnnaBridge	165:e614a9f1c9e2	2704	*/
AnnaBridge	165:e614a9f1c9e2	2705	/**
AnnaBridge	165:e614a9f1c9e2	2706	* @brief Enable the break function.
AnnaBridge	165:e614a9f1c9e2	2707	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2708	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2709	* @rmtoll BDTR BKE LL_TIM_EnableBRK
AnnaBridge	165:e614a9f1c9e2	2710	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2711	* @retval None
AnnaBridge	165:e614a9f1c9e2	2712	*/
AnnaBridge	165:e614a9f1c9e2	2713	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2714	{
AnnaBridge	165:e614a9f1c9e2	2715	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	165:e614a9f1c9e2	2716	}
AnnaBridge	165:e614a9f1c9e2	2717
AnnaBridge	165:e614a9f1c9e2	2718	/**
AnnaBridge	165:e614a9f1c9e2	2719	* @brief Disable the break function.
AnnaBridge	165:e614a9f1c9e2	2720	* @rmtoll BDTR BKE LL_TIM_DisableBRK
AnnaBridge	165:e614a9f1c9e2	2721	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2722	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2723	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2724	* @retval None
AnnaBridge	165:e614a9f1c9e2	2725	*/
AnnaBridge	165:e614a9f1c9e2	2726	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2727	{
AnnaBridge	165:e614a9f1c9e2	2728	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	165:e614a9f1c9e2	2729	}
AnnaBridge	165:e614a9f1c9e2	2730
AnnaBridge	165:e614a9f1c9e2	2731	/**
AnnaBridge	165:e614a9f1c9e2	2732	* @brief Configure the break input.
AnnaBridge	165:e614a9f1c9e2	2733	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2734	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2735	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
AnnaBridge	165:e614a9f1c9e2	2736	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2737	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2738	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	2739	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	165:e614a9f1c9e2	2740	* @retval None
AnnaBridge	165:e614a9f1c9e2	2741	*/
AnnaBridge	165:e614a9f1c9e2	2742	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
AnnaBridge	165:e614a9f1c9e2	2743	{
AnnaBridge	165:e614a9f1c9e2	2744	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
AnnaBridge	165:e614a9f1c9e2	2745	}
AnnaBridge	165:e614a9f1c9e2	2746
AnnaBridge	165:e614a9f1c9e2	2747	/**
AnnaBridge	165:e614a9f1c9e2	2748	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
AnnaBridge	165:e614a9f1c9e2	2749	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2750	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2751	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
AnnaBridge	165:e614a9f1c9e2	2752	* BDTR OSSR LL_TIM_SetOffStates
AnnaBridge	165:e614a9f1c9e2	2753	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2754	* @param OffStateIdle This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2755	* @arg @ref LL_TIM_OSSI_DISABLE
AnnaBridge	165:e614a9f1c9e2	2756	* @arg @ref LL_TIM_OSSI_ENABLE
AnnaBridge	165:e614a9f1c9e2	2757	* @param OffStateRun This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2758	* @arg @ref LL_TIM_OSSR_DISABLE
AnnaBridge	165:e614a9f1c9e2	2759	* @arg @ref LL_TIM_OSSR_ENABLE
AnnaBridge	165:e614a9f1c9e2	2760	* @retval None
AnnaBridge	165:e614a9f1c9e2	2761	*/
AnnaBridge	165:e614a9f1c9e2	2762	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
AnnaBridge	165:e614a9f1c9e2	2763	{
AnnaBridge	165:e614a9f1c9e2	2764	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
AnnaBridge	165:e614a9f1c9e2	2765	}
AnnaBridge	165:e614a9f1c9e2	2766
AnnaBridge	165:e614a9f1c9e2	2767	/**
AnnaBridge	165:e614a9f1c9e2	2768	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
AnnaBridge	165:e614a9f1c9e2	2769	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2770	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2771	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
AnnaBridge	165:e614a9f1c9e2	2772	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2773	* @retval None
AnnaBridge	165:e614a9f1c9e2	2774	*/
AnnaBridge	165:e614a9f1c9e2	2775	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2776	{
AnnaBridge	165:e614a9f1c9e2	2777	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	165:e614a9f1c9e2	2778	}
AnnaBridge	165:e614a9f1c9e2	2779
AnnaBridge	165:e614a9f1c9e2	2780	/**
AnnaBridge	165:e614a9f1c9e2	2781	* @brief Disable automatic output (MOE can be set only by software).
AnnaBridge	165:e614a9f1c9e2	2782	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2783	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2784	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
AnnaBridge	165:e614a9f1c9e2	2785	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2786	* @retval None
AnnaBridge	165:e614a9f1c9e2	2787	*/
AnnaBridge	165:e614a9f1c9e2	2788	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2789	{
AnnaBridge	165:e614a9f1c9e2	2790	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	165:e614a9f1c9e2	2791	}
AnnaBridge	165:e614a9f1c9e2	2792
AnnaBridge	165:e614a9f1c9e2	2793	/**
AnnaBridge	165:e614a9f1c9e2	2794	* @brief Indicate whether automatic output is enabled.
AnnaBridge	165:e614a9f1c9e2	2795	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2796	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2797	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
AnnaBridge	165:e614a9f1c9e2	2798	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2799	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2800	*/
AnnaBridge	165:e614a9f1c9e2	2801	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2802	{
AnnaBridge	165:e614a9f1c9e2	2803	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
AnnaBridge	165:e614a9f1c9e2	2804	}
AnnaBridge	165:e614a9f1c9e2	2805
AnnaBridge	165:e614a9f1c9e2	2806	/**
AnnaBridge	165:e614a9f1c9e2	2807	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
AnnaBridge	165:e614a9f1c9e2	2808	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	165:e614a9f1c9e2	2809	* software and is reset in case of break or break2 event
AnnaBridge	165:e614a9f1c9e2	2810	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2811	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2812	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
AnnaBridge	165:e614a9f1c9e2	2813	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2814	* @retval None
AnnaBridge	165:e614a9f1c9e2	2815	*/
AnnaBridge	165:e614a9f1c9e2	2816	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2817	{
AnnaBridge	165:e614a9f1c9e2	2818	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	165:e614a9f1c9e2	2819	}
AnnaBridge	165:e614a9f1c9e2	2820
AnnaBridge	165:e614a9f1c9e2	2821	/**
AnnaBridge	165:e614a9f1c9e2	2822	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
AnnaBridge	165:e614a9f1c9e2	2823	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	165:e614a9f1c9e2	2824	* software and is reset in case of break or break2 event.
AnnaBridge	165:e614a9f1c9e2	2825	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2826	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2827	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
AnnaBridge	165:e614a9f1c9e2	2828	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2829	* @retval None
AnnaBridge	165:e614a9f1c9e2	2830	*/
AnnaBridge	165:e614a9f1c9e2	2831	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2832	{
AnnaBridge	165:e614a9f1c9e2	2833	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	165:e614a9f1c9e2	2834	}
AnnaBridge	165:e614a9f1c9e2	2835
AnnaBridge	165:e614a9f1c9e2	2836	/**
AnnaBridge	165:e614a9f1c9e2	2837	* @brief Indicates whether outputs are enabled.
AnnaBridge	165:e614a9f1c9e2	2838	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	2839	* a timer instance provides a break input.
AnnaBridge	165:e614a9f1c9e2	2840	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
AnnaBridge	165:e614a9f1c9e2	2841	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2842	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2843	*/
AnnaBridge	165:e614a9f1c9e2	2844	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2845	{
AnnaBridge	165:e614a9f1c9e2	2846	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
AnnaBridge	165:e614a9f1c9e2	2847	}
AnnaBridge	165:e614a9f1c9e2	2848
AnnaBridge	165:e614a9f1c9e2	2849	/**
AnnaBridge	165:e614a9f1c9e2	2850	* @}
AnnaBridge	165:e614a9f1c9e2	2851	*/
AnnaBridge	165:e614a9f1c9e2	2852
AnnaBridge	165:e614a9f1c9e2	2853	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	165:e614a9f1c9e2	2854	* @{
AnnaBridge	165:e614a9f1c9e2	2855	*/
AnnaBridge	165:e614a9f1c9e2	2856	/**
AnnaBridge	165:e614a9f1c9e2	2857	* @brief Configures the timer DMA burst feature.
AnnaBridge	165:e614a9f1c9e2	2858	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	165:e614a9f1c9e2	2859	* not a timer instance supports the DMA burst mode.
AnnaBridge	165:e614a9f1c9e2	2860	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	165:e614a9f1c9e2	2861	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	165:e614a9f1c9e2	2862	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2863	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2864	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	165:e614a9f1c9e2	2865	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	165:e614a9f1c9e2	2866	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	165:e614a9f1c9e2	2867	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	165:e614a9f1c9e2	2868	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	165:e614a9f1c9e2	2869	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	165:e614a9f1c9e2	2870	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	165:e614a9f1c9e2	2871	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	165:e614a9f1c9e2	2872	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	165:e614a9f1c9e2	2873	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	165:e614a9f1c9e2	2874	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	165:e614a9f1c9e2	2875	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	165:e614a9f1c9e2	2876	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	165:e614a9f1c9e2	2877	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	165:e614a9f1c9e2	2878	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	165:e614a9f1c9e2	2879	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	165:e614a9f1c9e2	2880	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	165:e614a9f1c9e2	2881	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	165:e614a9f1c9e2	2882	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2883	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	165:e614a9f1c9e2	2884	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2885	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2886	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2887	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2888	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2889	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2890	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2891	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2892	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2893	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2894	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2895	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2896	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2897	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2898	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2899	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2900	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	165:e614a9f1c9e2	2901	* @retval None
AnnaBridge	165:e614a9f1c9e2	2902	*/
AnnaBridge	165:e614a9f1c9e2	2903	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	165:e614a9f1c9e2	2904	{
AnnaBridge	165:e614a9f1c9e2	2905	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	165:e614a9f1c9e2	2906	}
AnnaBridge	165:e614a9f1c9e2	2907
AnnaBridge	165:e614a9f1c9e2	2908	/**
AnnaBridge	165:e614a9f1c9e2	2909	* @}
AnnaBridge	165:e614a9f1c9e2	2910	*/
AnnaBridge	165:e614a9f1c9e2	2911
AnnaBridge	165:e614a9f1c9e2	2912
AnnaBridge	165:e614a9f1c9e2	2913	/**
AnnaBridge	165:e614a9f1c9e2	2914	* @}
AnnaBridge	165:e614a9f1c9e2	2915	*/
AnnaBridge	165:e614a9f1c9e2	2916
AnnaBridge	165:e614a9f1c9e2	2917
AnnaBridge	165:e614a9f1c9e2	2918	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	165:e614a9f1c9e2	2919	* @{
AnnaBridge	165:e614a9f1c9e2	2920	*/
AnnaBridge	165:e614a9f1c9e2	2921	/**
AnnaBridge	165:e614a9f1c9e2	2922	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	165:e614a9f1c9e2	2923	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	165:e614a9f1c9e2	2924	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2925	* @retval None
AnnaBridge	165:e614a9f1c9e2	2926	*/
AnnaBridge	165:e614a9f1c9e2	2927	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2928	{
AnnaBridge	165:e614a9f1c9e2	2929	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	165:e614a9f1c9e2	2930	}
AnnaBridge	165:e614a9f1c9e2	2931
AnnaBridge	165:e614a9f1c9e2	2932	/**
AnnaBridge	165:e614a9f1c9e2	2933	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	2934	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	165:e614a9f1c9e2	2935	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2936	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2937	*/
AnnaBridge	165:e614a9f1c9e2	2938	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2939	{
AnnaBridge	165:e614a9f1c9e2	2940	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	165:e614a9f1c9e2	2941	}
AnnaBridge	165:e614a9f1c9e2	2942
AnnaBridge	165:e614a9f1c9e2	2943	/**
AnnaBridge	165:e614a9f1c9e2	2944	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	165:e614a9f1c9e2	2945	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	165:e614a9f1c9e2	2946	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2947	* @retval None
AnnaBridge	165:e614a9f1c9e2	2948	*/
AnnaBridge	165:e614a9f1c9e2	2949	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2950	{
AnnaBridge	165:e614a9f1c9e2	2951	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	165:e614a9f1c9e2	2952	}
AnnaBridge	165:e614a9f1c9e2	2953
AnnaBridge	165:e614a9f1c9e2	2954	/**
AnnaBridge	165:e614a9f1c9e2	2955	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	2956	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	165:e614a9f1c9e2	2957	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2958	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2959	*/
AnnaBridge	165:e614a9f1c9e2	2960	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2961	{
AnnaBridge	165:e614a9f1c9e2	2962	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	165:e614a9f1c9e2	2963	}
AnnaBridge	165:e614a9f1c9e2	2964
AnnaBridge	165:e614a9f1c9e2	2965	/**
AnnaBridge	165:e614a9f1c9e2	2966	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	165:e614a9f1c9e2	2967	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	165:e614a9f1c9e2	2968	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2969	* @retval None
AnnaBridge	165:e614a9f1c9e2	2970	*/
AnnaBridge	165:e614a9f1c9e2	2971	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2972	{
AnnaBridge	165:e614a9f1c9e2	2973	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	165:e614a9f1c9e2	2974	}
AnnaBridge	165:e614a9f1c9e2	2975
AnnaBridge	165:e614a9f1c9e2	2976	/**
AnnaBridge	165:e614a9f1c9e2	2977	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	2978	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	165:e614a9f1c9e2	2979	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2980	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2981	*/
AnnaBridge	165:e614a9f1c9e2	2982	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2983	{
AnnaBridge	165:e614a9f1c9e2	2984	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	165:e614a9f1c9e2	2985	}
AnnaBridge	165:e614a9f1c9e2	2986
AnnaBridge	165:e614a9f1c9e2	2987	/**
AnnaBridge	165:e614a9f1c9e2	2988	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	165:e614a9f1c9e2	2989	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	165:e614a9f1c9e2	2990	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	2991	* @retval None
AnnaBridge	165:e614a9f1c9e2	2992	*/
AnnaBridge	165:e614a9f1c9e2	2993	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	2994	{
AnnaBridge	165:e614a9f1c9e2	2995	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	165:e614a9f1c9e2	2996	}
AnnaBridge	165:e614a9f1c9e2	2997
AnnaBridge	165:e614a9f1c9e2	2998	/**
AnnaBridge	165:e614a9f1c9e2	2999	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3000	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	165:e614a9f1c9e2	3001	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3002	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3003	*/
AnnaBridge	165:e614a9f1c9e2	3004	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3005	{
AnnaBridge	165:e614a9f1c9e2	3006	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	165:e614a9f1c9e2	3007	}
AnnaBridge	165:e614a9f1c9e2	3008
AnnaBridge	165:e614a9f1c9e2	3009	/**
AnnaBridge	165:e614a9f1c9e2	3010	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	165:e614a9f1c9e2	3011	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	165:e614a9f1c9e2	3012	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3013	* @retval None
AnnaBridge	165:e614a9f1c9e2	3014	*/
AnnaBridge	165:e614a9f1c9e2	3015	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3016	{
AnnaBridge	165:e614a9f1c9e2	3017	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	165:e614a9f1c9e2	3018	}
AnnaBridge	165:e614a9f1c9e2	3019
AnnaBridge	165:e614a9f1c9e2	3020	/**
AnnaBridge	165:e614a9f1c9e2	3021	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3022	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	165:e614a9f1c9e2	3023	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3024	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3025	*/
AnnaBridge	165:e614a9f1c9e2	3026	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3027	{
AnnaBridge	165:e614a9f1c9e2	3028	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	165:e614a9f1c9e2	3029	}
AnnaBridge	165:e614a9f1c9e2	3030
AnnaBridge	165:e614a9f1c9e2	3031	/**
AnnaBridge	165:e614a9f1c9e2	3032	* @brief Clear the commutation interrupt flag (COMIF).
AnnaBridge	165:e614a9f1c9e2	3033	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
AnnaBridge	165:e614a9f1c9e2	3034	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3035	* @retval None
AnnaBridge	165:e614a9f1c9e2	3036	*/
AnnaBridge	165:e614a9f1c9e2	3037	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3038	{
AnnaBridge	165:e614a9f1c9e2	3039	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
AnnaBridge	165:e614a9f1c9e2	3040	}
AnnaBridge	165:e614a9f1c9e2	3041
AnnaBridge	165:e614a9f1c9e2	3042	/**
AnnaBridge	165:e614a9f1c9e2	3043	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3044	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
AnnaBridge	165:e614a9f1c9e2	3045	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3046	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3047	*/
AnnaBridge	165:e614a9f1c9e2	3048	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3049	{
AnnaBridge	165:e614a9f1c9e2	3050	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
AnnaBridge	165:e614a9f1c9e2	3051	}
AnnaBridge	165:e614a9f1c9e2	3052
AnnaBridge	165:e614a9f1c9e2	3053	/**
AnnaBridge	165:e614a9f1c9e2	3054	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	165:e614a9f1c9e2	3055	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	165:e614a9f1c9e2	3056	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3057	* @retval None
AnnaBridge	165:e614a9f1c9e2	3058	*/
AnnaBridge	165:e614a9f1c9e2	3059	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3060	{
AnnaBridge	165:e614a9f1c9e2	3061	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	165:e614a9f1c9e2	3062	}
AnnaBridge	165:e614a9f1c9e2	3063
AnnaBridge	165:e614a9f1c9e2	3064	/**
AnnaBridge	165:e614a9f1c9e2	3065	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3066	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	165:e614a9f1c9e2	3067	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3068	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3069	*/
AnnaBridge	165:e614a9f1c9e2	3070	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3071	{
AnnaBridge	165:e614a9f1c9e2	3072	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	165:e614a9f1c9e2	3073	}
AnnaBridge	165:e614a9f1c9e2	3074
AnnaBridge	165:e614a9f1c9e2	3075	/**
AnnaBridge	165:e614a9f1c9e2	3076	* @brief Clear the break interrupt flag (BIF).
AnnaBridge	165:e614a9f1c9e2	3077	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
AnnaBridge	165:e614a9f1c9e2	3078	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3079	* @retval None
AnnaBridge	165:e614a9f1c9e2	3080	*/
AnnaBridge	165:e614a9f1c9e2	3081	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3082	{
AnnaBridge	165:e614a9f1c9e2	3083	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
AnnaBridge	165:e614a9f1c9e2	3084	}
AnnaBridge	165:e614a9f1c9e2	3085
AnnaBridge	165:e614a9f1c9e2	3086	/**
AnnaBridge	165:e614a9f1c9e2	3087	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3088	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
AnnaBridge	165:e614a9f1c9e2	3089	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3090	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3091	*/
AnnaBridge	165:e614a9f1c9e2	3092	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3093	{
AnnaBridge	165:e614a9f1c9e2	3094	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
AnnaBridge	165:e614a9f1c9e2	3095	}
AnnaBridge	165:e614a9f1c9e2	3096
AnnaBridge	165:e614a9f1c9e2	3097	/**
AnnaBridge	165:e614a9f1c9e2	3098	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	165:e614a9f1c9e2	3099	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	165:e614a9f1c9e2	3100	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3101	* @retval None
AnnaBridge	165:e614a9f1c9e2	3102	*/
AnnaBridge	165:e614a9f1c9e2	3103	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3104	{
AnnaBridge	165:e614a9f1c9e2	3105	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	165:e614a9f1c9e2	3106	}
AnnaBridge	165:e614a9f1c9e2	3107
AnnaBridge	165:e614a9f1c9e2	3108	/**
AnnaBridge	165:e614a9f1c9e2	3109	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3110	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	165:e614a9f1c9e2	3111	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3112	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3113	*/
AnnaBridge	165:e614a9f1c9e2	3114	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3115	{
AnnaBridge	165:e614a9f1c9e2	3116	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	165:e614a9f1c9e2	3117	}
AnnaBridge	165:e614a9f1c9e2	3118
AnnaBridge	165:e614a9f1c9e2	3119	/**
AnnaBridge	165:e614a9f1c9e2	3120	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	165:e614a9f1c9e2	3121	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	165:e614a9f1c9e2	3122	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3123	* @retval None
AnnaBridge	165:e614a9f1c9e2	3124	*/
AnnaBridge	165:e614a9f1c9e2	3125	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3126	{
AnnaBridge	165:e614a9f1c9e2	3127	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	165:e614a9f1c9e2	3128	}
AnnaBridge	165:e614a9f1c9e2	3129
AnnaBridge	165:e614a9f1c9e2	3130	/**
AnnaBridge	165:e614a9f1c9e2	3131	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3132	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	165:e614a9f1c9e2	3133	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3134	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3135	*/
AnnaBridge	165:e614a9f1c9e2	3136	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3137	{
AnnaBridge	165:e614a9f1c9e2	3138	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	165:e614a9f1c9e2	3139	}
AnnaBridge	165:e614a9f1c9e2	3140
AnnaBridge	165:e614a9f1c9e2	3141	/**
AnnaBridge	165:e614a9f1c9e2	3142	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	165:e614a9f1c9e2	3143	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	165:e614a9f1c9e2	3144	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3145	* @retval None
AnnaBridge	165:e614a9f1c9e2	3146	*/
AnnaBridge	165:e614a9f1c9e2	3147	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3148	{
AnnaBridge	165:e614a9f1c9e2	3149	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	165:e614a9f1c9e2	3150	}
AnnaBridge	165:e614a9f1c9e2	3151
AnnaBridge	165:e614a9f1c9e2	3152	/**
AnnaBridge	165:e614a9f1c9e2	3153	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3154	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	165:e614a9f1c9e2	3155	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3156	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3157	*/
AnnaBridge	165:e614a9f1c9e2	3158	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3159	{
AnnaBridge	165:e614a9f1c9e2	3160	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	165:e614a9f1c9e2	3161	}
AnnaBridge	165:e614a9f1c9e2	3162
AnnaBridge	165:e614a9f1c9e2	3163	/**
AnnaBridge	165:e614a9f1c9e2	3164	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	165:e614a9f1c9e2	3165	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	165:e614a9f1c9e2	3166	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3167	* @retval None
AnnaBridge	165:e614a9f1c9e2	3168	*/
AnnaBridge	165:e614a9f1c9e2	3169	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3170	{
AnnaBridge	165:e614a9f1c9e2	3171	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	165:e614a9f1c9e2	3172	}
AnnaBridge	165:e614a9f1c9e2	3173
AnnaBridge	165:e614a9f1c9e2	3174	/**
AnnaBridge	165:e614a9f1c9e2	3175	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	165:e614a9f1c9e2	3176	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	165:e614a9f1c9e2	3177	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3178	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3179	*/
AnnaBridge	165:e614a9f1c9e2	3180	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3181	{
AnnaBridge	165:e614a9f1c9e2	3182	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	165:e614a9f1c9e2	3183	}
AnnaBridge	165:e614a9f1c9e2	3184
AnnaBridge	165:e614a9f1c9e2	3185	/**
AnnaBridge	165:e614a9f1c9e2	3186	* @}
AnnaBridge	165:e614a9f1c9e2	3187	*/
AnnaBridge	165:e614a9f1c9e2	3188
AnnaBridge	165:e614a9f1c9e2	3189	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	165:e614a9f1c9e2	3190	* @{
AnnaBridge	165:e614a9f1c9e2	3191	*/
AnnaBridge	165:e614a9f1c9e2	3192	/**
AnnaBridge	165:e614a9f1c9e2	3193	* @brief Enable update interrupt (UIE).
AnnaBridge	165:e614a9f1c9e2	3194	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	165:e614a9f1c9e2	3195	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3196	* @retval None
AnnaBridge	165:e614a9f1c9e2	3197	*/
AnnaBridge	165:e614a9f1c9e2	3198	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3199	{
AnnaBridge	165:e614a9f1c9e2	3200	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	165:e614a9f1c9e2	3201	}
AnnaBridge	165:e614a9f1c9e2	3202
AnnaBridge	165:e614a9f1c9e2	3203	/**
AnnaBridge	165:e614a9f1c9e2	3204	* @brief Disable update interrupt (UIE).
AnnaBridge	165:e614a9f1c9e2	3205	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	165:e614a9f1c9e2	3206	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3207	* @retval None
AnnaBridge	165:e614a9f1c9e2	3208	*/
AnnaBridge	165:e614a9f1c9e2	3209	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3210	{
AnnaBridge	165:e614a9f1c9e2	3211	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	165:e614a9f1c9e2	3212	}
AnnaBridge	165:e614a9f1c9e2	3213
AnnaBridge	165:e614a9f1c9e2	3214	/**
AnnaBridge	165:e614a9f1c9e2	3215	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3216	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	165:e614a9f1c9e2	3217	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3218	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3219	*/
AnnaBridge	165:e614a9f1c9e2	3220	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3221	{
AnnaBridge	165:e614a9f1c9e2	3222	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	165:e614a9f1c9e2	3223	}
AnnaBridge	165:e614a9f1c9e2	3224
AnnaBridge	165:e614a9f1c9e2	3225	/**
AnnaBridge	165:e614a9f1c9e2	3226	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	165:e614a9f1c9e2	3227	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	165:e614a9f1c9e2	3228	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3229	* @retval None
AnnaBridge	165:e614a9f1c9e2	3230	*/
AnnaBridge	165:e614a9f1c9e2	3231	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3232	{
AnnaBridge	165:e614a9f1c9e2	3233	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	165:e614a9f1c9e2	3234	}
AnnaBridge	165:e614a9f1c9e2	3235
AnnaBridge	165:e614a9f1c9e2	3236	/**
AnnaBridge	165:e614a9f1c9e2	3237	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	165:e614a9f1c9e2	3238	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	165:e614a9f1c9e2	3239	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3240	* @retval None
AnnaBridge	165:e614a9f1c9e2	3241	*/
AnnaBridge	165:e614a9f1c9e2	3242	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3243	{
AnnaBridge	165:e614a9f1c9e2	3244	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	165:e614a9f1c9e2	3245	}
AnnaBridge	165:e614a9f1c9e2	3246
AnnaBridge	165:e614a9f1c9e2	3247	/**
AnnaBridge	165:e614a9f1c9e2	3248	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3249	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	165:e614a9f1c9e2	3250	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3251	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3252	*/
AnnaBridge	165:e614a9f1c9e2	3253	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3254	{
AnnaBridge	165:e614a9f1c9e2	3255	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	165:e614a9f1c9e2	3256	}
AnnaBridge	165:e614a9f1c9e2	3257
AnnaBridge	165:e614a9f1c9e2	3258	/**
AnnaBridge	165:e614a9f1c9e2	3259	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	165:e614a9f1c9e2	3260	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	165:e614a9f1c9e2	3261	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3262	* @retval None
AnnaBridge	165:e614a9f1c9e2	3263	*/
AnnaBridge	165:e614a9f1c9e2	3264	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3265	{
AnnaBridge	165:e614a9f1c9e2	3266	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	165:e614a9f1c9e2	3267	}
AnnaBridge	165:e614a9f1c9e2	3268
AnnaBridge	165:e614a9f1c9e2	3269	/**
AnnaBridge	165:e614a9f1c9e2	3270	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	165:e614a9f1c9e2	3271	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	165:e614a9f1c9e2	3272	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3273	* @retval None
AnnaBridge	165:e614a9f1c9e2	3274	*/
AnnaBridge	165:e614a9f1c9e2	3275	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3276	{
AnnaBridge	165:e614a9f1c9e2	3277	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	165:e614a9f1c9e2	3278	}
AnnaBridge	165:e614a9f1c9e2	3279
AnnaBridge	165:e614a9f1c9e2	3280	/**
AnnaBridge	165:e614a9f1c9e2	3281	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3282	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	165:e614a9f1c9e2	3283	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3284	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3285	*/
AnnaBridge	165:e614a9f1c9e2	3286	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3287	{
AnnaBridge	165:e614a9f1c9e2	3288	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	165:e614a9f1c9e2	3289	}
AnnaBridge	165:e614a9f1c9e2	3290
AnnaBridge	165:e614a9f1c9e2	3291	/**
AnnaBridge	165:e614a9f1c9e2	3292	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	165:e614a9f1c9e2	3293	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	165:e614a9f1c9e2	3294	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3295	* @retval None
AnnaBridge	165:e614a9f1c9e2	3296	*/
AnnaBridge	165:e614a9f1c9e2	3297	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3298	{
AnnaBridge	165:e614a9f1c9e2	3299	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	165:e614a9f1c9e2	3300	}
AnnaBridge	165:e614a9f1c9e2	3301
AnnaBridge	165:e614a9f1c9e2	3302	/**
AnnaBridge	165:e614a9f1c9e2	3303	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	165:e614a9f1c9e2	3304	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	165:e614a9f1c9e2	3305	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3306	* @retval None
AnnaBridge	165:e614a9f1c9e2	3307	*/
AnnaBridge	165:e614a9f1c9e2	3308	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3309	{
AnnaBridge	165:e614a9f1c9e2	3310	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	165:e614a9f1c9e2	3311	}
AnnaBridge	165:e614a9f1c9e2	3312
AnnaBridge	165:e614a9f1c9e2	3313	/**
AnnaBridge	165:e614a9f1c9e2	3314	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3315	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	165:e614a9f1c9e2	3316	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3317	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3318	*/
AnnaBridge	165:e614a9f1c9e2	3319	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3320	{
AnnaBridge	165:e614a9f1c9e2	3321	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	165:e614a9f1c9e2	3322	}
AnnaBridge	165:e614a9f1c9e2	3323
AnnaBridge	165:e614a9f1c9e2	3324	/**
AnnaBridge	165:e614a9f1c9e2	3325	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	165:e614a9f1c9e2	3326	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	165:e614a9f1c9e2	3327	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3328	* @retval None
AnnaBridge	165:e614a9f1c9e2	3329	*/
AnnaBridge	165:e614a9f1c9e2	3330	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3331	{
AnnaBridge	165:e614a9f1c9e2	3332	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	165:e614a9f1c9e2	3333	}
AnnaBridge	165:e614a9f1c9e2	3334
AnnaBridge	165:e614a9f1c9e2	3335	/**
AnnaBridge	165:e614a9f1c9e2	3336	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	165:e614a9f1c9e2	3337	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	165:e614a9f1c9e2	3338	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3339	* @retval None
AnnaBridge	165:e614a9f1c9e2	3340	*/
AnnaBridge	165:e614a9f1c9e2	3341	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3342	{
AnnaBridge	165:e614a9f1c9e2	3343	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	165:e614a9f1c9e2	3344	}
AnnaBridge	165:e614a9f1c9e2	3345
AnnaBridge	165:e614a9f1c9e2	3346	/**
AnnaBridge	165:e614a9f1c9e2	3347	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3348	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	165:e614a9f1c9e2	3349	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3350	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3351	*/
AnnaBridge	165:e614a9f1c9e2	3352	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3353	{
AnnaBridge	165:e614a9f1c9e2	3354	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	165:e614a9f1c9e2	3355	}
AnnaBridge	165:e614a9f1c9e2	3356
AnnaBridge	165:e614a9f1c9e2	3357	/**
AnnaBridge	165:e614a9f1c9e2	3358	* @brief Enable commutation interrupt (COMIE).
AnnaBridge	165:e614a9f1c9e2	3359	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
AnnaBridge	165:e614a9f1c9e2	3360	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3361	* @retval None
AnnaBridge	165:e614a9f1c9e2	3362	*/
AnnaBridge	165:e614a9f1c9e2	3363	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3364	{
AnnaBridge	165:e614a9f1c9e2	3365	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	165:e614a9f1c9e2	3366	}
AnnaBridge	165:e614a9f1c9e2	3367
AnnaBridge	165:e614a9f1c9e2	3368	/**
AnnaBridge	165:e614a9f1c9e2	3369	* @brief Disable commutation interrupt (COMIE).
AnnaBridge	165:e614a9f1c9e2	3370	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
AnnaBridge	165:e614a9f1c9e2	3371	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3372	* @retval None
AnnaBridge	165:e614a9f1c9e2	3373	*/
AnnaBridge	165:e614a9f1c9e2	3374	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3375	{
AnnaBridge	165:e614a9f1c9e2	3376	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	165:e614a9f1c9e2	3377	}
AnnaBridge	165:e614a9f1c9e2	3378
AnnaBridge	165:e614a9f1c9e2	3379	/**
AnnaBridge	165:e614a9f1c9e2	3380	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3381	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
AnnaBridge	165:e614a9f1c9e2	3382	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3383	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3384	*/
AnnaBridge	165:e614a9f1c9e2	3385	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3386	{
AnnaBridge	165:e614a9f1c9e2	3387	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
AnnaBridge	165:e614a9f1c9e2	3388	}
AnnaBridge	165:e614a9f1c9e2	3389
AnnaBridge	165:e614a9f1c9e2	3390	/**
AnnaBridge	165:e614a9f1c9e2	3391	* @brief Enable trigger interrupt (TIE).
AnnaBridge	165:e614a9f1c9e2	3392	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	165:e614a9f1c9e2	3393	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3394	* @retval None
AnnaBridge	165:e614a9f1c9e2	3395	*/
AnnaBridge	165:e614a9f1c9e2	3396	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3397	{
AnnaBridge	165:e614a9f1c9e2	3398	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	165:e614a9f1c9e2	3399	}
AnnaBridge	165:e614a9f1c9e2	3400
AnnaBridge	165:e614a9f1c9e2	3401	/**
AnnaBridge	165:e614a9f1c9e2	3402	* @brief Disable trigger interrupt (TIE).
AnnaBridge	165:e614a9f1c9e2	3403	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	165:e614a9f1c9e2	3404	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3405	* @retval None
AnnaBridge	165:e614a9f1c9e2	3406	*/
AnnaBridge	165:e614a9f1c9e2	3407	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3408	{
AnnaBridge	165:e614a9f1c9e2	3409	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	165:e614a9f1c9e2	3410	}
AnnaBridge	165:e614a9f1c9e2	3411
AnnaBridge	165:e614a9f1c9e2	3412	/**
AnnaBridge	165:e614a9f1c9e2	3413	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3414	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	165:e614a9f1c9e2	3415	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3416	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3417	*/
AnnaBridge	165:e614a9f1c9e2	3418	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3419	{
AnnaBridge	165:e614a9f1c9e2	3420	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	165:e614a9f1c9e2	3421	}
AnnaBridge	165:e614a9f1c9e2	3422
AnnaBridge	165:e614a9f1c9e2	3423	/**
AnnaBridge	165:e614a9f1c9e2	3424	* @brief Enable break interrupt (BIE).
AnnaBridge	165:e614a9f1c9e2	3425	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
AnnaBridge	165:e614a9f1c9e2	3426	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3427	* @retval None
AnnaBridge	165:e614a9f1c9e2	3428	*/
AnnaBridge	165:e614a9f1c9e2	3429	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3430	{
AnnaBridge	165:e614a9f1c9e2	3431	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	165:e614a9f1c9e2	3432	}
AnnaBridge	165:e614a9f1c9e2	3433
AnnaBridge	165:e614a9f1c9e2	3434	/**
AnnaBridge	165:e614a9f1c9e2	3435	* @brief Disable break interrupt (BIE).
AnnaBridge	165:e614a9f1c9e2	3436	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
AnnaBridge	165:e614a9f1c9e2	3437	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3438	* @retval None
AnnaBridge	165:e614a9f1c9e2	3439	*/
AnnaBridge	165:e614a9f1c9e2	3440	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3441	{
AnnaBridge	165:e614a9f1c9e2	3442	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	165:e614a9f1c9e2	3443	}
AnnaBridge	165:e614a9f1c9e2	3444
AnnaBridge	165:e614a9f1c9e2	3445	/**
AnnaBridge	165:e614a9f1c9e2	3446	* @brief Indicates whether the break interrupt (BIE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3447	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
AnnaBridge	165:e614a9f1c9e2	3448	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3449	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3450	*/
AnnaBridge	165:e614a9f1c9e2	3451	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3452	{
AnnaBridge	165:e614a9f1c9e2	3453	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
AnnaBridge	165:e614a9f1c9e2	3454	}
AnnaBridge	165:e614a9f1c9e2	3455
AnnaBridge	165:e614a9f1c9e2	3456	/**
AnnaBridge	165:e614a9f1c9e2	3457	* @}
AnnaBridge	165:e614a9f1c9e2	3458	*/
AnnaBridge	165:e614a9f1c9e2	3459
AnnaBridge	165:e614a9f1c9e2	3460	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	165:e614a9f1c9e2	3461	* @{
AnnaBridge	165:e614a9f1c9e2	3462	*/
AnnaBridge	165:e614a9f1c9e2	3463	/**
AnnaBridge	165:e614a9f1c9e2	3464	* @brief Enable update DMA request (UDE).
AnnaBridge	165:e614a9f1c9e2	3465	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	165:e614a9f1c9e2	3466	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3467	* @retval None
AnnaBridge	165:e614a9f1c9e2	3468	*/
AnnaBridge	165:e614a9f1c9e2	3469	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3470	{
AnnaBridge	165:e614a9f1c9e2	3471	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	165:e614a9f1c9e2	3472	}
AnnaBridge	165:e614a9f1c9e2	3473
AnnaBridge	165:e614a9f1c9e2	3474	/**
AnnaBridge	165:e614a9f1c9e2	3475	* @brief Disable update DMA request (UDE).
AnnaBridge	165:e614a9f1c9e2	3476	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	165:e614a9f1c9e2	3477	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3478	* @retval None
AnnaBridge	165:e614a9f1c9e2	3479	*/
AnnaBridge	165:e614a9f1c9e2	3480	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3481	{
AnnaBridge	165:e614a9f1c9e2	3482	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	165:e614a9f1c9e2	3483	}
AnnaBridge	165:e614a9f1c9e2	3484
AnnaBridge	165:e614a9f1c9e2	3485	/**
AnnaBridge	165:e614a9f1c9e2	3486	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3487	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	165:e614a9f1c9e2	3488	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3489	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3490	*/
AnnaBridge	165:e614a9f1c9e2	3491	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3492	{
AnnaBridge	165:e614a9f1c9e2	3493	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	165:e614a9f1c9e2	3494	}
AnnaBridge	165:e614a9f1c9e2	3495
AnnaBridge	165:e614a9f1c9e2	3496	/**
AnnaBridge	165:e614a9f1c9e2	3497	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	165:e614a9f1c9e2	3498	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	165:e614a9f1c9e2	3499	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3500	* @retval None
AnnaBridge	165:e614a9f1c9e2	3501	*/
AnnaBridge	165:e614a9f1c9e2	3502	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3503	{
AnnaBridge	165:e614a9f1c9e2	3504	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	165:e614a9f1c9e2	3505	}
AnnaBridge	165:e614a9f1c9e2	3506
AnnaBridge	165:e614a9f1c9e2	3507	/**
AnnaBridge	165:e614a9f1c9e2	3508	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	165:e614a9f1c9e2	3509	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	165:e614a9f1c9e2	3510	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3511	* @retval None
AnnaBridge	165:e614a9f1c9e2	3512	*/
AnnaBridge	165:e614a9f1c9e2	3513	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3514	{
AnnaBridge	165:e614a9f1c9e2	3515	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	165:e614a9f1c9e2	3516	}
AnnaBridge	165:e614a9f1c9e2	3517
AnnaBridge	165:e614a9f1c9e2	3518	/**
AnnaBridge	165:e614a9f1c9e2	3519	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3520	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	165:e614a9f1c9e2	3521	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3522	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3523	*/
AnnaBridge	165:e614a9f1c9e2	3524	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3525	{
AnnaBridge	165:e614a9f1c9e2	3526	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	165:e614a9f1c9e2	3527	}
AnnaBridge	165:e614a9f1c9e2	3528
AnnaBridge	165:e614a9f1c9e2	3529	/**
AnnaBridge	165:e614a9f1c9e2	3530	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	165:e614a9f1c9e2	3531	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	165:e614a9f1c9e2	3532	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3533	* @retval None
AnnaBridge	165:e614a9f1c9e2	3534	*/
AnnaBridge	165:e614a9f1c9e2	3535	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3536	{
AnnaBridge	165:e614a9f1c9e2	3537	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	165:e614a9f1c9e2	3538	}
AnnaBridge	165:e614a9f1c9e2	3539
AnnaBridge	165:e614a9f1c9e2	3540	/**
AnnaBridge	165:e614a9f1c9e2	3541	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	165:e614a9f1c9e2	3542	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	165:e614a9f1c9e2	3543	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3544	* @retval None
AnnaBridge	165:e614a9f1c9e2	3545	*/
AnnaBridge	165:e614a9f1c9e2	3546	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3547	{
AnnaBridge	165:e614a9f1c9e2	3548	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	165:e614a9f1c9e2	3549	}
AnnaBridge	165:e614a9f1c9e2	3550
AnnaBridge	165:e614a9f1c9e2	3551	/**
AnnaBridge	165:e614a9f1c9e2	3552	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3553	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	165:e614a9f1c9e2	3554	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3555	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3556	*/
AnnaBridge	165:e614a9f1c9e2	3557	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3558	{
AnnaBridge	165:e614a9f1c9e2	3559	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	165:e614a9f1c9e2	3560	}
AnnaBridge	165:e614a9f1c9e2	3561
AnnaBridge	165:e614a9f1c9e2	3562	/**
AnnaBridge	165:e614a9f1c9e2	3563	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	165:e614a9f1c9e2	3564	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	165:e614a9f1c9e2	3565	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3566	* @retval None
AnnaBridge	165:e614a9f1c9e2	3567	*/
AnnaBridge	165:e614a9f1c9e2	3568	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3569	{
AnnaBridge	165:e614a9f1c9e2	3570	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	165:e614a9f1c9e2	3571	}
AnnaBridge	165:e614a9f1c9e2	3572
AnnaBridge	165:e614a9f1c9e2	3573	/**
AnnaBridge	165:e614a9f1c9e2	3574	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	165:e614a9f1c9e2	3575	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	165:e614a9f1c9e2	3576	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3577	* @retval None
AnnaBridge	165:e614a9f1c9e2	3578	*/
AnnaBridge	165:e614a9f1c9e2	3579	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3580	{
AnnaBridge	165:e614a9f1c9e2	3581	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	165:e614a9f1c9e2	3582	}
AnnaBridge	165:e614a9f1c9e2	3583
AnnaBridge	165:e614a9f1c9e2	3584	/**
AnnaBridge	165:e614a9f1c9e2	3585	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3586	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	165:e614a9f1c9e2	3587	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3588	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3589	*/
AnnaBridge	165:e614a9f1c9e2	3590	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3591	{
AnnaBridge	165:e614a9f1c9e2	3592	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	165:e614a9f1c9e2	3593	}
AnnaBridge	165:e614a9f1c9e2	3594
AnnaBridge	165:e614a9f1c9e2	3595	/**
AnnaBridge	165:e614a9f1c9e2	3596	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	165:e614a9f1c9e2	3597	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	165:e614a9f1c9e2	3598	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3599	* @retval None
AnnaBridge	165:e614a9f1c9e2	3600	*/
AnnaBridge	165:e614a9f1c9e2	3601	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3602	{
AnnaBridge	165:e614a9f1c9e2	3603	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	165:e614a9f1c9e2	3604	}
AnnaBridge	165:e614a9f1c9e2	3605
AnnaBridge	165:e614a9f1c9e2	3606	/**
AnnaBridge	165:e614a9f1c9e2	3607	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	165:e614a9f1c9e2	3608	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	165:e614a9f1c9e2	3609	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3610	* @retval None
AnnaBridge	165:e614a9f1c9e2	3611	*/
AnnaBridge	165:e614a9f1c9e2	3612	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3613	{
AnnaBridge	165:e614a9f1c9e2	3614	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	165:e614a9f1c9e2	3615	}
AnnaBridge	165:e614a9f1c9e2	3616
AnnaBridge	165:e614a9f1c9e2	3617	/**
AnnaBridge	165:e614a9f1c9e2	3618	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3619	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	165:e614a9f1c9e2	3620	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3621	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3622	*/
AnnaBridge	165:e614a9f1c9e2	3623	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3624	{
AnnaBridge	165:e614a9f1c9e2	3625	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	165:e614a9f1c9e2	3626	}
AnnaBridge	165:e614a9f1c9e2	3627
AnnaBridge	165:e614a9f1c9e2	3628	/**
AnnaBridge	165:e614a9f1c9e2	3629	* @brief Enable commutation DMA request (COMDE).
AnnaBridge	165:e614a9f1c9e2	3630	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
AnnaBridge	165:e614a9f1c9e2	3631	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3632	* @retval None
AnnaBridge	165:e614a9f1c9e2	3633	*/
AnnaBridge	165:e614a9f1c9e2	3634	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3635	{
AnnaBridge	165:e614a9f1c9e2	3636	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	165:e614a9f1c9e2	3637	}
AnnaBridge	165:e614a9f1c9e2	3638
AnnaBridge	165:e614a9f1c9e2	3639	/**
AnnaBridge	165:e614a9f1c9e2	3640	* @brief Disable commutation DMA request (COMDE).
AnnaBridge	165:e614a9f1c9e2	3641	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
AnnaBridge	165:e614a9f1c9e2	3642	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3643	* @retval None
AnnaBridge	165:e614a9f1c9e2	3644	*/
AnnaBridge	165:e614a9f1c9e2	3645	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3646	{
AnnaBridge	165:e614a9f1c9e2	3647	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	165:e614a9f1c9e2	3648	}
AnnaBridge	165:e614a9f1c9e2	3649
AnnaBridge	165:e614a9f1c9e2	3650	/**
AnnaBridge	165:e614a9f1c9e2	3651	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3652	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
AnnaBridge	165:e614a9f1c9e2	3653	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3654	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3655	*/
AnnaBridge	165:e614a9f1c9e2	3656	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3657	{
AnnaBridge	165:e614a9f1c9e2	3658	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
AnnaBridge	165:e614a9f1c9e2	3659	}
AnnaBridge	165:e614a9f1c9e2	3660
AnnaBridge	165:e614a9f1c9e2	3661	/**
AnnaBridge	165:e614a9f1c9e2	3662	* @brief Enable trigger interrupt (TDE).
AnnaBridge	165:e614a9f1c9e2	3663	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	165:e614a9f1c9e2	3664	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3665	* @retval None
AnnaBridge	165:e614a9f1c9e2	3666	*/
AnnaBridge	165:e614a9f1c9e2	3667	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3668	{
AnnaBridge	165:e614a9f1c9e2	3669	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	165:e614a9f1c9e2	3670	}
AnnaBridge	165:e614a9f1c9e2	3671
AnnaBridge	165:e614a9f1c9e2	3672	/**
AnnaBridge	165:e614a9f1c9e2	3673	* @brief Disable trigger interrupt (TDE).
AnnaBridge	165:e614a9f1c9e2	3674	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	165:e614a9f1c9e2	3675	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3676	* @retval None
AnnaBridge	165:e614a9f1c9e2	3677	*/
AnnaBridge	165:e614a9f1c9e2	3678	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3679	{
AnnaBridge	165:e614a9f1c9e2	3680	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	165:e614a9f1c9e2	3681	}
AnnaBridge	165:e614a9f1c9e2	3682
AnnaBridge	165:e614a9f1c9e2	3683	/**
AnnaBridge	165:e614a9f1c9e2	3684	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	165:e614a9f1c9e2	3685	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	165:e614a9f1c9e2	3686	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3687	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	3688	*/
AnnaBridge	165:e614a9f1c9e2	3689	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3690	{
AnnaBridge	165:e614a9f1c9e2	3691	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	165:e614a9f1c9e2	3692	}
AnnaBridge	165:e614a9f1c9e2	3693
AnnaBridge	165:e614a9f1c9e2	3694	/**
AnnaBridge	165:e614a9f1c9e2	3695	* @}
AnnaBridge	165:e614a9f1c9e2	3696	*/
AnnaBridge	165:e614a9f1c9e2	3697
AnnaBridge	165:e614a9f1c9e2	3698	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	165:e614a9f1c9e2	3699	* @{
AnnaBridge	165:e614a9f1c9e2	3700	*/
AnnaBridge	165:e614a9f1c9e2	3701	/**
AnnaBridge	165:e614a9f1c9e2	3702	* @brief Generate an update event.
AnnaBridge	165:e614a9f1c9e2	3703	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	165:e614a9f1c9e2	3704	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3705	* @retval None
AnnaBridge	165:e614a9f1c9e2	3706	*/
AnnaBridge	165:e614a9f1c9e2	3707	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3708	{
AnnaBridge	165:e614a9f1c9e2	3709	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	165:e614a9f1c9e2	3710	}
AnnaBridge	165:e614a9f1c9e2	3711
AnnaBridge	165:e614a9f1c9e2	3712	/**
AnnaBridge	165:e614a9f1c9e2	3713	* @brief Generate Capture/Compare 1 event.
AnnaBridge	165:e614a9f1c9e2	3714	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	165:e614a9f1c9e2	3715	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3716	* @retval None
AnnaBridge	165:e614a9f1c9e2	3717	*/
AnnaBridge	165:e614a9f1c9e2	3718	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3719	{
AnnaBridge	165:e614a9f1c9e2	3720	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	165:e614a9f1c9e2	3721	}
AnnaBridge	165:e614a9f1c9e2	3722
AnnaBridge	165:e614a9f1c9e2	3723	/**
AnnaBridge	165:e614a9f1c9e2	3724	* @brief Generate Capture/Compare 2 event.
AnnaBridge	165:e614a9f1c9e2	3725	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	165:e614a9f1c9e2	3726	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3727	* @retval None
AnnaBridge	165:e614a9f1c9e2	3728	*/
AnnaBridge	165:e614a9f1c9e2	3729	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3730	{
AnnaBridge	165:e614a9f1c9e2	3731	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	165:e614a9f1c9e2	3732	}
AnnaBridge	165:e614a9f1c9e2	3733
AnnaBridge	165:e614a9f1c9e2	3734	/**
AnnaBridge	165:e614a9f1c9e2	3735	* @brief Generate Capture/Compare 3 event.
AnnaBridge	165:e614a9f1c9e2	3736	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	165:e614a9f1c9e2	3737	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3738	* @retval None
AnnaBridge	165:e614a9f1c9e2	3739	*/
AnnaBridge	165:e614a9f1c9e2	3740	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3741	{
AnnaBridge	165:e614a9f1c9e2	3742	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	165:e614a9f1c9e2	3743	}
AnnaBridge	165:e614a9f1c9e2	3744
AnnaBridge	165:e614a9f1c9e2	3745	/**
AnnaBridge	165:e614a9f1c9e2	3746	* @brief Generate Capture/Compare 4 event.
AnnaBridge	165:e614a9f1c9e2	3747	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	165:e614a9f1c9e2	3748	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3749	* @retval None
AnnaBridge	165:e614a9f1c9e2	3750	*/
AnnaBridge	165:e614a9f1c9e2	3751	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3752	{
AnnaBridge	165:e614a9f1c9e2	3753	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	165:e614a9f1c9e2	3754	}
AnnaBridge	165:e614a9f1c9e2	3755
AnnaBridge	165:e614a9f1c9e2	3756	/**
AnnaBridge	165:e614a9f1c9e2	3757	* @brief Generate commutation event.
AnnaBridge	165:e614a9f1c9e2	3758	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
AnnaBridge	165:e614a9f1c9e2	3759	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3760	* @retval None
AnnaBridge	165:e614a9f1c9e2	3761	*/
AnnaBridge	165:e614a9f1c9e2	3762	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3763	{
AnnaBridge	165:e614a9f1c9e2	3764	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
AnnaBridge	165:e614a9f1c9e2	3765	}
AnnaBridge	165:e614a9f1c9e2	3766
AnnaBridge	165:e614a9f1c9e2	3767	/**
AnnaBridge	165:e614a9f1c9e2	3768	* @brief Generate trigger event.
AnnaBridge	165:e614a9f1c9e2	3769	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	165:e614a9f1c9e2	3770	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3771	* @retval None
AnnaBridge	165:e614a9f1c9e2	3772	*/
AnnaBridge	165:e614a9f1c9e2	3773	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3774	{
AnnaBridge	165:e614a9f1c9e2	3775	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	165:e614a9f1c9e2	3776	}
AnnaBridge	165:e614a9f1c9e2	3777
AnnaBridge	165:e614a9f1c9e2	3778	/**
AnnaBridge	165:e614a9f1c9e2	3779	* @brief Generate break event.
AnnaBridge	165:e614a9f1c9e2	3780	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
AnnaBridge	165:e614a9f1c9e2	3781	* @param TIMx Timer instance
AnnaBridge	165:e614a9f1c9e2	3782	* @retval None
AnnaBridge	165:e614a9f1c9e2	3783	*/
AnnaBridge	165:e614a9f1c9e2	3784	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
AnnaBridge	165:e614a9f1c9e2	3785	{
AnnaBridge	165:e614a9f1c9e2	3786	SET_BIT(TIMx->EGR, TIM_EGR_BG);
AnnaBridge	165:e614a9f1c9e2	3787	}
AnnaBridge	165:e614a9f1c9e2	3788
AnnaBridge	165:e614a9f1c9e2	3789	/**
AnnaBridge	165:e614a9f1c9e2	3790	* @}
AnnaBridge	165:e614a9f1c9e2	3791	*/
AnnaBridge	165:e614a9f1c9e2	3792
AnnaBridge	165:e614a9f1c9e2	3793	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	3794	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	165:e614a9f1c9e2	3795	* @{
AnnaBridge	165:e614a9f1c9e2	3796	*/
AnnaBridge	165:e614a9f1c9e2	3797
AnnaBridge	165:e614a9f1c9e2	3798	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	165:e614a9f1c9e2	3799	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	165:e614a9f1c9e2	3800	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	165:e614a9f1c9e2	3801	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	165:e614a9f1c9e2	3802	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	165:e614a9f1c9e2	3803	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	165:e614a9f1c9e2	3804	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	165:e614a9f1c9e2	3805	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	165:e614a9f1c9e2	3806	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	165:e614a9f1c9e2	3807	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
AnnaBridge	165:e614a9f1c9e2	3808	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
AnnaBridge	165:e614a9f1c9e2	3809	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
AnnaBridge	165:e614a9f1c9e2	3810	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
AnnaBridge	165:e614a9f1c9e2	3811	/**
AnnaBridge	165:e614a9f1c9e2	3812	* @}
AnnaBridge	165:e614a9f1c9e2	3813	*/
AnnaBridge	165:e614a9f1c9e2	3814	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	3815
AnnaBridge	165:e614a9f1c9e2	3816	/**
AnnaBridge	165:e614a9f1c9e2	3817	* @}
AnnaBridge	165:e614a9f1c9e2	3818	*/
AnnaBridge	165:e614a9f1c9e2	3819
AnnaBridge	165:e614a9f1c9e2	3820	/**
AnnaBridge	165:e614a9f1c9e2	3821	* @}
AnnaBridge	165:e614a9f1c9e2	3822	*/
AnnaBridge	165:e614a9f1c9e2	3823
AnnaBridge	165:e614a9f1c9e2	3824	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 */
AnnaBridge	165:e614a9f1c9e2	3825
AnnaBridge	165:e614a9f1c9e2	3826	/**
AnnaBridge	165:e614a9f1c9e2	3827	* @}
AnnaBridge	165:e614a9f1c9e2	3828	*/
AnnaBridge	165:e614a9f1c9e2	3829
AnnaBridge	165:e614a9f1c9e2	3830	#ifdef __cplusplus
AnnaBridge	165:e614a9f1c9e2	3831	}
AnnaBridge	165:e614a9f1c9e2	3832	#endif
AnnaBridge	165:e614a9f1c9e2	3833
AnnaBridge	165:e614a9f1c9e2	3834	#endif /* __STM32F1xx_LL_TIM_H */
AnnaBridge	165:e614a9f1c9e2	3835	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/