mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /**
<> 154:37f96f9d4de2 2 ******************************************************************************
<> 154:37f96f9d4de2 3 * @file stm32f1xx_ll_system.h
<> 154:37f96f9d4de2 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @brief Header file of SYSTEM LL module.
<> 154:37f96f9d4de2 6 @verbatim
<> 154:37f96f9d4de2 7 ==============================================================================
<> 154:37f96f9d4de2 8 ##### How to use this driver #####
<> 154:37f96f9d4de2 9 ==============================================================================
<> 154:37f96f9d4de2 10 [..]
<> 154:37f96f9d4de2 11 The LL SYSTEM driver contains a set of generic APIs that can be
<> 154:37f96f9d4de2 12 used by user:
<> 154:37f96f9d4de2 13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
<> 154:37f96f9d4de2 14 (+) Access to DBGCMU registers
<> 154:37f96f9d4de2 15 (+) Access to SYSCFG registers
<> 154:37f96f9d4de2 16
<> 154:37f96f9d4de2 17 @endverbatim
<> 154:37f96f9d4de2 18 ******************************************************************************
<> 154:37f96f9d4de2 19 * @attention
<> 154:37f96f9d4de2 20 *
<> 154:37f96f9d4de2 21 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 154:37f96f9d4de2 22 *
<> 154:37f96f9d4de2 23 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 24 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 25 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 26 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 27 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 28 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 29 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 30 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 31 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 32 * without specific prior written permission.
<> 154:37f96f9d4de2 33 *
<> 154:37f96f9d4de2 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 41 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 42 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 44 *
<> 154:37f96f9d4de2 45 ******************************************************************************
<> 154:37f96f9d4de2 46 */
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 /* Define to prevent recursive inclusion -------------------------------------*/
<> 154:37f96f9d4de2 49 #ifndef __STM32F1xx_LL_SYSTEM_H
<> 154:37f96f9d4de2 50 #define __STM32F1xx_LL_SYSTEM_H
<> 154:37f96f9d4de2 51
<> 154:37f96f9d4de2 52 #ifdef __cplusplus
<> 154:37f96f9d4de2 53 extern "C" {
<> 154:37f96f9d4de2 54 #endif
<> 154:37f96f9d4de2 55
<> 154:37f96f9d4de2 56 /* Includes ------------------------------------------------------------------*/
<> 154:37f96f9d4de2 57 #include "stm32f1xx.h"
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /** @addtogroup STM32F1xx_LL_Driver
<> 154:37f96f9d4de2 60 * @{
<> 154:37f96f9d4de2 61 */
<> 154:37f96f9d4de2 62
<> 154:37f96f9d4de2 63 #if defined (FLASH) || defined (DBGMCU)
<> 154:37f96f9d4de2 64
<> 154:37f96f9d4de2 65 /** @defgroup SYSTEM_LL SYSTEM
<> 154:37f96f9d4de2 66 * @{
<> 154:37f96f9d4de2 67 */
<> 154:37f96f9d4de2 68
<> 154:37f96f9d4de2 69 /* Private types -------------------------------------------------------------*/
<> 154:37f96f9d4de2 70 /* Private variables ---------------------------------------------------------*/
<> 154:37f96f9d4de2 71
<> 154:37f96f9d4de2 72 /* Private constants ---------------------------------------------------------*/
<> 154:37f96f9d4de2 73 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
<> 154:37f96f9d4de2 74 * @{
<> 154:37f96f9d4de2 75 */
<> 154:37f96f9d4de2 76
<> 154:37f96f9d4de2 77 /**
<> 154:37f96f9d4de2 78 * @}
<> 154:37f96f9d4de2 79 */
<> 154:37f96f9d4de2 80
<> 154:37f96f9d4de2 81 /* Private macros ------------------------------------------------------------*/
<> 154:37f96f9d4de2 82
<> 154:37f96f9d4de2 83 /* Exported types ------------------------------------------------------------*/
<> 154:37f96f9d4de2 84 /* Exported constants --------------------------------------------------------*/
<> 154:37f96f9d4de2 85 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
<> 154:37f96f9d4de2 86 * @{
<> 154:37f96f9d4de2 87 */
<> 154:37f96f9d4de2 88
<> 154:37f96f9d4de2 89
<> 154:37f96f9d4de2 90
<> 154:37f96f9d4de2 91 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
<> 154:37f96f9d4de2 92 * @{
<> 154:37f96f9d4de2 93 */
AnnaBridge 165:e614a9f1c9e2 94 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
<> 154:37f96f9d4de2 95 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
<> 154:37f96f9d4de2 96 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
<> 154:37f96f9d4de2 97 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
<> 154:37f96f9d4de2 98 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
<> 154:37f96f9d4de2 99 /**
<> 154:37f96f9d4de2 100 * @}
<> 154:37f96f9d4de2 101 */
<> 154:37f96f9d4de2 102
<> 154:37f96f9d4de2 103 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
<> 154:37f96f9d4de2 104 * @{
<> 154:37f96f9d4de2 105 */
<> 154:37f96f9d4de2 106 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
<> 154:37f96f9d4de2 107 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
<> 154:37f96f9d4de2 108 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
<> 154:37f96f9d4de2 109 #if defined(DBGMCU_CR_DBG_TIM5_STOP)
<> 154:37f96f9d4de2 110 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
<> 154:37f96f9d4de2 111 #endif /* DBGMCU_CR_DBG_TIM5_STOP */
<> 154:37f96f9d4de2 112 #if defined(DBGMCU_CR_DBG_TIM6_STOP)
<> 154:37f96f9d4de2 113 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
<> 154:37f96f9d4de2 114 #endif /* DBGMCU_CR_DBG_TIM6_STOP */
<> 154:37f96f9d4de2 115 #if defined(DBGMCU_CR_DBG_TIM7_STOP)
<> 154:37f96f9d4de2 116 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
<> 154:37f96f9d4de2 117 #endif /* DBGMCU_CR_DBG_TIM7_STOP */
<> 154:37f96f9d4de2 118 #if defined(DBGMCU_CR_DBG_TIM12_STOP)
<> 154:37f96f9d4de2 119 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
<> 154:37f96f9d4de2 120 #endif /* DBGMCU_CR_DBG_TIM12_STOP */
<> 154:37f96f9d4de2 121 #if defined(DBGMCU_CR_DBG_TIM13_STOP)
<> 154:37f96f9d4de2 122 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
<> 154:37f96f9d4de2 123 #endif /* DBGMCU_CR_DBG_TIM13_STOP */
<> 154:37f96f9d4de2 124 #if defined(DBGMCU_CR_DBG_TIM14_STOP)
<> 154:37f96f9d4de2 125 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
<> 154:37f96f9d4de2 126 #endif /* DBGMCU_CR_DBG_TIM14_STOP */
<> 154:37f96f9d4de2 127 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
<> 154:37f96f9d4de2 128 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
AnnaBridge 187:0387e8f68319 129 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
AnnaBridge 187:0387e8f68319 130 #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
AnnaBridge 187:0387e8f68319 131 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
AnnaBridge 187:0387e8f68319 132 #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
<> 154:37f96f9d4de2 133 #if defined(DBGMCU_CR_DBG_CAN1_STOP)
<> 154:37f96f9d4de2 134 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
<> 154:37f96f9d4de2 135 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
<> 154:37f96f9d4de2 136 #if defined(DBGMCU_CR_DBG_CAN2_STOP)
<> 154:37f96f9d4de2 137 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
<> 154:37f96f9d4de2 138 #endif /* DBGMCU_CR_DBG_CAN2_STOP */
<> 154:37f96f9d4de2 139 /**
<> 154:37f96f9d4de2 140 * @}
<> 154:37f96f9d4de2 141 */
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
<> 154:37f96f9d4de2 144 * @{
<> 154:37f96f9d4de2 145 */
<> 154:37f96f9d4de2 146 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
<> 154:37f96f9d4de2 147 #if defined(DBGMCU_CR_DBG_TIM8_STOP)
<> 154:37f96f9d4de2 148 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
<> 154:37f96f9d4de2 149 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
<> 154:37f96f9d4de2 150 #if defined(DBGMCU_CR_DBG_TIM9_STOP)
<> 154:37f96f9d4de2 151 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
<> 154:37f96f9d4de2 152 #endif /* DBGMCU_CR_DBG_TIM9_STOP */
<> 154:37f96f9d4de2 153 #if defined(DBGMCU_CR_DBG_TIM10_STOP)
<> 154:37f96f9d4de2 154 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
<> 154:37f96f9d4de2 155 #endif /* DBGMCU_CR_DBG_TIM10_STOP */
<> 154:37f96f9d4de2 156 #if defined(DBGMCU_CR_DBG_TIM11_STOP)
<> 154:37f96f9d4de2 157 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
<> 154:37f96f9d4de2 158 #endif /* DBGMCU_CR_DBG_TIM11_STOP */
<> 154:37f96f9d4de2 159 #if defined(DBGMCU_CR_DBG_TIM15_STOP)
<> 154:37f96f9d4de2 160 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
<> 154:37f96f9d4de2 161 #endif /* DBGMCU_CR_DBG_TIM15_STOP */
<> 154:37f96f9d4de2 162 #if defined(DBGMCU_CR_DBG_TIM16_STOP)
<> 154:37f96f9d4de2 163 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
<> 154:37f96f9d4de2 164 #endif /* DBGMCU_CR_DBG_TIM16_STOP */
<> 154:37f96f9d4de2 165 #if defined(DBGMCU_CR_DBG_TIM17_STOP)
<> 154:37f96f9d4de2 166 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
<> 154:37f96f9d4de2 167 #endif /* DBGMCU_CR_DBG_TIM17_STOP */
<> 154:37f96f9d4de2 168 /**
<> 154:37f96f9d4de2 169 * @}
<> 154:37f96f9d4de2 170 */
<> 154:37f96f9d4de2 171
<> 154:37f96f9d4de2 172 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
<> 154:37f96f9d4de2 173 * @{
<> 154:37f96f9d4de2 174 */
<> 154:37f96f9d4de2 175 #if defined(FLASH_ACR_LATENCY)
AnnaBridge 165:e614a9f1c9e2 176 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
<> 154:37f96f9d4de2 177 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
<> 154:37f96f9d4de2 178 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
<> 154:37f96f9d4de2 179 #else
<> 154:37f96f9d4de2 180 #endif /* FLASH_ACR_LATENCY */
<> 154:37f96f9d4de2 181 /**
<> 154:37f96f9d4de2 182 * @}
<> 154:37f96f9d4de2 183 */
<> 154:37f96f9d4de2 184
<> 154:37f96f9d4de2 185 /**
<> 154:37f96f9d4de2 186 * @}
<> 154:37f96f9d4de2 187 */
<> 154:37f96f9d4de2 188
<> 154:37f96f9d4de2 189 /* Exported macro ------------------------------------------------------------*/
<> 154:37f96f9d4de2 190
<> 154:37f96f9d4de2 191 /* Exported functions --------------------------------------------------------*/
<> 154:37f96f9d4de2 192 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
<> 154:37f96f9d4de2 193 * @{
<> 154:37f96f9d4de2 194 */
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196
<> 154:37f96f9d4de2 197
<> 154:37f96f9d4de2 198 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
<> 154:37f96f9d4de2 199 * @{
<> 154:37f96f9d4de2 200 */
<> 154:37f96f9d4de2 201
<> 154:37f96f9d4de2 202 /**
<> 154:37f96f9d4de2 203 * @brief Return the device identifier
<> 154:37f96f9d4de2 204 * @note For Low Density devices, the device ID is 0x412
<> 154:37f96f9d4de2 205 * @note For Medium Density devices, the device ID is 0x410
<> 154:37f96f9d4de2 206 * @note For High Density devices, the device ID is 0x414
<> 154:37f96f9d4de2 207 * @note For XL Density devices, the device ID is 0x430
<> 154:37f96f9d4de2 208 * @note For Connectivity Line devices, the device ID is 0x418
<> 154:37f96f9d4de2 209 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
<> 154:37f96f9d4de2 210 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
<> 154:37f96f9d4de2 211 */
<> 154:37f96f9d4de2 212 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
<> 154:37f96f9d4de2 213 {
<> 154:37f96f9d4de2 214 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
<> 154:37f96f9d4de2 215 }
<> 154:37f96f9d4de2 216
<> 154:37f96f9d4de2 217 /**
<> 154:37f96f9d4de2 218 * @brief Return the device revision identifier
<> 154:37f96f9d4de2 219 * @note This field indicates the revision of the device.
<> 154:37f96f9d4de2 220 For example, it is read as revA -> 0x1000,for Low Density devices
<> 154:37f96f9d4de2 221 For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
<> 154:37f96f9d4de2 222 For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
<> 154:37f96f9d4de2 223 For example, it is read as revA or 1 -> 0x1003,for XL Density devices
<> 154:37f96f9d4de2 224 For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
<> 154:37f96f9d4de2 225 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
<> 154:37f96f9d4de2 226 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
<> 154:37f96f9d4de2 227 */
<> 154:37f96f9d4de2 228 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
<> 154:37f96f9d4de2 229 {
AnnaBridge 165:e614a9f1c9e2 230 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
<> 154:37f96f9d4de2 231 }
<> 154:37f96f9d4de2 232
<> 154:37f96f9d4de2 233 /**
<> 154:37f96f9d4de2 234 * @brief Enable the Debug Module during SLEEP mode
<> 154:37f96f9d4de2 235 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
<> 154:37f96f9d4de2 236 * @retval None
<> 154:37f96f9d4de2 237 */
<> 154:37f96f9d4de2 238 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
<> 154:37f96f9d4de2 239 {
<> 154:37f96f9d4de2 240 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<> 154:37f96f9d4de2 241 }
<> 154:37f96f9d4de2 242
<> 154:37f96f9d4de2 243 /**
<> 154:37f96f9d4de2 244 * @brief Disable the Debug Module during SLEEP mode
<> 154:37f96f9d4de2 245 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
<> 154:37f96f9d4de2 246 * @retval None
<> 154:37f96f9d4de2 247 */
<> 154:37f96f9d4de2 248 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
<> 154:37f96f9d4de2 249 {
<> 154:37f96f9d4de2 250 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<> 154:37f96f9d4de2 251 }
<> 154:37f96f9d4de2 252
<> 154:37f96f9d4de2 253 /**
<> 154:37f96f9d4de2 254 * @brief Enable the Debug Module during STOP mode
<> 154:37f96f9d4de2 255 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
<> 154:37f96f9d4de2 256 * @retval None
<> 154:37f96f9d4de2 257 */
<> 154:37f96f9d4de2 258 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
<> 154:37f96f9d4de2 259 {
<> 154:37f96f9d4de2 260 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<> 154:37f96f9d4de2 261 }
<> 154:37f96f9d4de2 262
<> 154:37f96f9d4de2 263 /**
<> 154:37f96f9d4de2 264 * @brief Disable the Debug Module during STOP mode
<> 154:37f96f9d4de2 265 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
<> 154:37f96f9d4de2 266 * @retval None
<> 154:37f96f9d4de2 267 */
<> 154:37f96f9d4de2 268 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
<> 154:37f96f9d4de2 269 {
<> 154:37f96f9d4de2 270 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<> 154:37f96f9d4de2 271 }
<> 154:37f96f9d4de2 272
<> 154:37f96f9d4de2 273 /**
<> 154:37f96f9d4de2 274 * @brief Enable the Debug Module during STANDBY mode
<> 154:37f96f9d4de2 275 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
<> 154:37f96f9d4de2 276 * @retval None
<> 154:37f96f9d4de2 277 */
<> 154:37f96f9d4de2 278 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
<> 154:37f96f9d4de2 279 {
<> 154:37f96f9d4de2 280 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<> 154:37f96f9d4de2 281 }
<> 154:37f96f9d4de2 282
<> 154:37f96f9d4de2 283 /**
<> 154:37f96f9d4de2 284 * @brief Disable the Debug Module during STANDBY mode
<> 154:37f96f9d4de2 285 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
<> 154:37f96f9d4de2 286 * @retval None
<> 154:37f96f9d4de2 287 */
<> 154:37f96f9d4de2 288 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
<> 154:37f96f9d4de2 289 {
<> 154:37f96f9d4de2 290 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<> 154:37f96f9d4de2 291 }
<> 154:37f96f9d4de2 292
<> 154:37f96f9d4de2 293 /**
<> 154:37f96f9d4de2 294 * @brief Set Trace pin assignment control
<> 154:37f96f9d4de2 295 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
<> 154:37f96f9d4de2 296 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
<> 154:37f96f9d4de2 297 * @param PinAssignment This parameter can be one of the following values:
<> 154:37f96f9d4de2 298 * @arg @ref LL_DBGMCU_TRACE_NONE
<> 154:37f96f9d4de2 299 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
<> 154:37f96f9d4de2 300 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<> 154:37f96f9d4de2 301 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<> 154:37f96f9d4de2 302 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<> 154:37f96f9d4de2 303 * @retval None
<> 154:37f96f9d4de2 304 */
<> 154:37f96f9d4de2 305 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
<> 154:37f96f9d4de2 306 {
<> 154:37f96f9d4de2 307 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
<> 154:37f96f9d4de2 308 }
<> 154:37f96f9d4de2 309
<> 154:37f96f9d4de2 310 /**
<> 154:37f96f9d4de2 311 * @brief Get Trace pin assignment control
<> 154:37f96f9d4de2 312 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
<> 154:37f96f9d4de2 313 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
<> 154:37f96f9d4de2 314 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 315 * @arg @ref LL_DBGMCU_TRACE_NONE
<> 154:37f96f9d4de2 316 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
<> 154:37f96f9d4de2 317 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<> 154:37f96f9d4de2 318 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<> 154:37f96f9d4de2 319 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<> 154:37f96f9d4de2 320 */
<> 154:37f96f9d4de2 321 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
<> 154:37f96f9d4de2 322 {
<> 154:37f96f9d4de2 323 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
<> 154:37f96f9d4de2 324 }
<> 154:37f96f9d4de2 325
<> 154:37f96f9d4de2 326 /**
<> 154:37f96f9d4de2 327 * @brief Freeze APB1 peripherals (group1 peripherals)
<> 154:37f96f9d4de2 328 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 329 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 330 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 331 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 332 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 333 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 334 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 335 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 336 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 337 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 338 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 339 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 340 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 341 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 342 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 343 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
<> 154:37f96f9d4de2 344 * @param Periphs This parameter can be a combination of the following values:
<> 154:37f96f9d4de2 345 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<> 154:37f96f9d4de2 346 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<> 154:37f96f9d4de2 347 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
<> 154:37f96f9d4de2 348 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
<> 154:37f96f9d4de2 349 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<> 154:37f96f9d4de2 350 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
<> 154:37f96f9d4de2 351 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
<> 154:37f96f9d4de2 352 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
<> 154:37f96f9d4de2 353 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<> 154:37f96f9d4de2 354 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<> 154:37f96f9d4de2 355 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<> 154:37f96f9d4de2 356 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge 187:0387e8f68319 357 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
<> 154:37f96f9d4de2 358 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
<> 154:37f96f9d4de2 359 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
<> 154:37f96f9d4de2 360 *
<> 154:37f96f9d4de2 361 * (*) value not defined in all devices.
<> 154:37f96f9d4de2 362 * @retval None
<> 154:37f96f9d4de2 363 */
<> 154:37f96f9d4de2 364 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
<> 154:37f96f9d4de2 365 {
<> 154:37f96f9d4de2 366 SET_BIT(DBGMCU->CR, Periphs);
<> 154:37f96f9d4de2 367 }
<> 154:37f96f9d4de2 368
<> 154:37f96f9d4de2 369 /**
<> 154:37f96f9d4de2 370 * @brief Unfreeze APB1 peripherals (group1 peripherals)
<> 154:37f96f9d4de2 371 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 372 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 373 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 374 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 375 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 376 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 377 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 378 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 379 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 380 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 381 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 382 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 383 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 384 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 385 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 154:37f96f9d4de2 386 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
<> 154:37f96f9d4de2 387 * @param Periphs This parameter can be a combination of the following values:
<> 154:37f96f9d4de2 388 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<> 154:37f96f9d4de2 389 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<> 154:37f96f9d4de2 390 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
<> 154:37f96f9d4de2 391 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
<> 154:37f96f9d4de2 392 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<> 154:37f96f9d4de2 393 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
<> 154:37f96f9d4de2 394 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
<> 154:37f96f9d4de2 395 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
<> 154:37f96f9d4de2 396 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<> 154:37f96f9d4de2 397 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<> 154:37f96f9d4de2 398 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<> 154:37f96f9d4de2 399 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<> 154:37f96f9d4de2 400 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge 187:0387e8f68319 401 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
<> 154:37f96f9d4de2 402 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
<> 154:37f96f9d4de2 403 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
<> 154:37f96f9d4de2 404 *
<> 154:37f96f9d4de2 405 * (*) value not defined in all devices.
<> 154:37f96f9d4de2 406 * @retval None
<> 154:37f96f9d4de2 407 */
<> 154:37f96f9d4de2 408 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
<> 154:37f96f9d4de2 409 {
<> 154:37f96f9d4de2 410 CLEAR_BIT(DBGMCU->CR, Periphs);
<> 154:37f96f9d4de2 411 }
<> 154:37f96f9d4de2 412
<> 154:37f96f9d4de2 413 /**
<> 154:37f96f9d4de2 414 * @brief Freeze APB2 peripherals
<> 154:37f96f9d4de2 415 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 416 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 417 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 418 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 419 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 420 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 421 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 422 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
<> 154:37f96f9d4de2 423 * @param Periphs This parameter can be a combination of the following values:
<> 154:37f96f9d4de2 424 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
<> 154:37f96f9d4de2 425 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
<> 154:37f96f9d4de2 426 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
<> 154:37f96f9d4de2 427 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
<> 154:37f96f9d4de2 428 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
<> 154:37f96f9d4de2 429 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
<> 154:37f96f9d4de2 430 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
<> 154:37f96f9d4de2 431 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
<> 154:37f96f9d4de2 432 *
<> 154:37f96f9d4de2 433 * (*) value not defined in all devices.
<> 154:37f96f9d4de2 434 * @retval None
<> 154:37f96f9d4de2 435 */
<> 154:37f96f9d4de2 436 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
<> 154:37f96f9d4de2 437 {
<> 154:37f96f9d4de2 438 SET_BIT(DBGMCU->CR, Periphs);
<> 154:37f96f9d4de2 439 }
<> 154:37f96f9d4de2 440
<> 154:37f96f9d4de2 441 /**
<> 154:37f96f9d4de2 442 * @brief Unfreeze APB2 peripherals
<> 154:37f96f9d4de2 443 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 444 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 445 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 446 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 447 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 448 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 449 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 154:37f96f9d4de2 450 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
<> 154:37f96f9d4de2 451 * @param Periphs This parameter can be a combination of the following values:
<> 154:37f96f9d4de2 452 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
<> 154:37f96f9d4de2 453 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
<> 154:37f96f9d4de2 454 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
<> 154:37f96f9d4de2 455 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
<> 154:37f96f9d4de2 456 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
<> 154:37f96f9d4de2 457 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
<> 154:37f96f9d4de2 458 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
<> 154:37f96f9d4de2 459 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
<> 154:37f96f9d4de2 460 *
<> 154:37f96f9d4de2 461 * (*) value not defined in all devices.
<> 154:37f96f9d4de2 462 * @retval None
<> 154:37f96f9d4de2 463 */
<> 154:37f96f9d4de2 464 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
<> 154:37f96f9d4de2 465 {
<> 154:37f96f9d4de2 466 CLEAR_BIT(DBGMCU->CR, Periphs);
<> 154:37f96f9d4de2 467 }
<> 154:37f96f9d4de2 468 /**
<> 154:37f96f9d4de2 469 * @}
<> 154:37f96f9d4de2 470 */
<> 154:37f96f9d4de2 471
<> 154:37f96f9d4de2 472 #if defined(FLASH_ACR_LATENCY)
<> 154:37f96f9d4de2 473 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
<> 154:37f96f9d4de2 474 * @{
<> 154:37f96f9d4de2 475 */
<> 154:37f96f9d4de2 476
<> 154:37f96f9d4de2 477 /**
<> 154:37f96f9d4de2 478 * @brief Set FLASH Latency
<> 154:37f96f9d4de2 479 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
<> 154:37f96f9d4de2 480 * @param Latency This parameter can be one of the following values:
<> 154:37f96f9d4de2 481 * @arg @ref LL_FLASH_LATENCY_0
<> 154:37f96f9d4de2 482 * @arg @ref LL_FLASH_LATENCY_1
<> 154:37f96f9d4de2 483 * @arg @ref LL_FLASH_LATENCY_2
<> 154:37f96f9d4de2 484 * @retval None
<> 154:37f96f9d4de2 485 */
<> 154:37f96f9d4de2 486 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
<> 154:37f96f9d4de2 487 {
<> 154:37f96f9d4de2 488 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
<> 154:37f96f9d4de2 489 }
<> 154:37f96f9d4de2 490
<> 154:37f96f9d4de2 491 /**
<> 154:37f96f9d4de2 492 * @brief Get FLASH Latency
<> 154:37f96f9d4de2 493 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
<> 154:37f96f9d4de2 494 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 495 * @arg @ref LL_FLASH_LATENCY_0
<> 154:37f96f9d4de2 496 * @arg @ref LL_FLASH_LATENCY_1
<> 154:37f96f9d4de2 497 * @arg @ref LL_FLASH_LATENCY_2
<> 154:37f96f9d4de2 498 */
<> 154:37f96f9d4de2 499 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
<> 154:37f96f9d4de2 500 {
<> 154:37f96f9d4de2 501 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
<> 154:37f96f9d4de2 502 }
<> 154:37f96f9d4de2 503
<> 154:37f96f9d4de2 504 /**
<> 154:37f96f9d4de2 505 * @brief Enable Prefetch
<> 154:37f96f9d4de2 506 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
<> 154:37f96f9d4de2 507 * @retval None
<> 154:37f96f9d4de2 508 */
<> 154:37f96f9d4de2 509 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
<> 154:37f96f9d4de2 510 {
<> 154:37f96f9d4de2 511 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
<> 154:37f96f9d4de2 512 }
<> 154:37f96f9d4de2 513
<> 154:37f96f9d4de2 514 /**
<> 154:37f96f9d4de2 515 * @brief Disable Prefetch
<> 154:37f96f9d4de2 516 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
<> 154:37f96f9d4de2 517 * @retval None
<> 154:37f96f9d4de2 518 */
<> 154:37f96f9d4de2 519 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
<> 154:37f96f9d4de2 520 {
<> 154:37f96f9d4de2 521 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
<> 154:37f96f9d4de2 522 }
<> 154:37f96f9d4de2 523
<> 154:37f96f9d4de2 524 /**
<> 154:37f96f9d4de2 525 * @brief Check if Prefetch buffer is enabled
<> 154:37f96f9d4de2 526 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
<> 154:37f96f9d4de2 527 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 528 */
<> 154:37f96f9d4de2 529 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
<> 154:37f96f9d4de2 530 {
<> 154:37f96f9d4de2 531 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
<> 154:37f96f9d4de2 532 }
<> 154:37f96f9d4de2 533
<> 154:37f96f9d4de2 534 #endif /* FLASH_ACR_LATENCY */
<> 154:37f96f9d4de2 535 /**
<> 154:37f96f9d4de2 536 * @brief Enable Flash Half Cycle Access
<> 154:37f96f9d4de2 537 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
<> 154:37f96f9d4de2 538 * @retval None
<> 154:37f96f9d4de2 539 */
<> 154:37f96f9d4de2 540 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
<> 154:37f96f9d4de2 541 {
<> 154:37f96f9d4de2 542 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
<> 154:37f96f9d4de2 543 }
<> 154:37f96f9d4de2 544
<> 154:37f96f9d4de2 545 /**
<> 154:37f96f9d4de2 546 * @brief Disable Flash Half Cycle Access
<> 154:37f96f9d4de2 547 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
<> 154:37f96f9d4de2 548 * @retval None
<> 154:37f96f9d4de2 549 */
<> 154:37f96f9d4de2 550 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
<> 154:37f96f9d4de2 551 {
<> 154:37f96f9d4de2 552 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
<> 154:37f96f9d4de2 553 }
<> 154:37f96f9d4de2 554
<> 154:37f96f9d4de2 555 /**
<> 154:37f96f9d4de2 556 * @brief Check if Flash Half Cycle Access is enabled or not
<> 154:37f96f9d4de2 557 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
<> 154:37f96f9d4de2 558 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 559 */
<> 154:37f96f9d4de2 560 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
<> 154:37f96f9d4de2 561 {
<> 154:37f96f9d4de2 562 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
<> 154:37f96f9d4de2 563 }
<> 154:37f96f9d4de2 564
<> 154:37f96f9d4de2 565
<> 154:37f96f9d4de2 566 /**
<> 154:37f96f9d4de2 567 * @}
<> 154:37f96f9d4de2 568 */
<> 154:37f96f9d4de2 569
<> 154:37f96f9d4de2 570 /**
<> 154:37f96f9d4de2 571 * @}
<> 154:37f96f9d4de2 572 */
<> 154:37f96f9d4de2 573
<> 154:37f96f9d4de2 574 /**
<> 154:37f96f9d4de2 575 * @}
<> 154:37f96f9d4de2 576 */
<> 154:37f96f9d4de2 577
<> 154:37f96f9d4de2 578 #endif /* defined (FLASH) || defined (DBGMCU) */
<> 154:37f96f9d4de2 579
<> 154:37f96f9d4de2 580 /**
<> 154:37f96f9d4de2 581 * @}
<> 154:37f96f9d4de2 582 */
<> 154:37f96f9d4de2 583
<> 154:37f96f9d4de2 584 #ifdef __cplusplus
<> 154:37f96f9d4de2 585 }
<> 154:37f96f9d4de2 586 #endif
<> 154:37f96f9d4de2 587
<> 154:37f96f9d4de2 588 #endif /* __STM32F1xx_LL_SYSTEM_H */
<> 154:37f96f9d4de2 589
<> 154:37f96f9d4de2 590 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/