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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /**
<> 154:37f96f9d4de2 2 ******************************************************************************
<> 154:37f96f9d4de2 3 * @file stm32f1xx_ll_rcc.h
<> 154:37f96f9d4de2 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @brief Header file of RCC LL module.
<> 154:37f96f9d4de2 6 ******************************************************************************
<> 154:37f96f9d4de2 7 * @attention
<> 154:37f96f9d4de2 8 *
<> 154:37f96f9d4de2 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 12 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 14 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 16 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 17 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 19 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 20 * without specific prior written permission.
<> 154:37f96f9d4de2 21 *
<> 154:37f96f9d4de2 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 32 *
<> 154:37f96f9d4de2 33 ******************************************************************************
<> 154:37f96f9d4de2 34 */
<> 154:37f96f9d4de2 35
<> 154:37f96f9d4de2 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 154:37f96f9d4de2 37 #ifndef __STM32F1xx_LL_RCC_H
<> 154:37f96f9d4de2 38 #define __STM32F1xx_LL_RCC_H
<> 154:37f96f9d4de2 39
<> 154:37f96f9d4de2 40 #ifdef __cplusplus
<> 154:37f96f9d4de2 41 extern "C" {
<> 154:37f96f9d4de2 42 #endif
<> 154:37f96f9d4de2 43
<> 154:37f96f9d4de2 44 /* Includes ------------------------------------------------------------------*/
<> 154:37f96f9d4de2 45 #include "stm32f1xx.h"
<> 154:37f96f9d4de2 46
<> 154:37f96f9d4de2 47 /** @addtogroup STM32F1xx_LL_Driver
<> 154:37f96f9d4de2 48 * @{
<> 154:37f96f9d4de2 49 */
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 #if defined(RCC)
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 /** @defgroup RCC_LL RCC
<> 154:37f96f9d4de2 54 * @{
<> 154:37f96f9d4de2 55 */
<> 154:37f96f9d4de2 56
<> 154:37f96f9d4de2 57 /* Private types -------------------------------------------------------------*/
<> 154:37f96f9d4de2 58 /* Private variables ---------------------------------------------------------*/
<> 154:37f96f9d4de2 59 /* Private constants ---------------------------------------------------------*/
<> 154:37f96f9d4de2 60 /* Private macros ------------------------------------------------------------*/
<> 154:37f96f9d4de2 61 #if defined(USE_FULL_LL_DRIVER)
<> 154:37f96f9d4de2 62 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
<> 154:37f96f9d4de2 63 * @{
<> 154:37f96f9d4de2 64 */
<> 154:37f96f9d4de2 65 /**
<> 154:37f96f9d4de2 66 * @}
<> 154:37f96f9d4de2 67 */
<> 154:37f96f9d4de2 68 #endif /*USE_FULL_LL_DRIVER*/
<> 154:37f96f9d4de2 69 /* Exported types ------------------------------------------------------------*/
<> 154:37f96f9d4de2 70 #if defined(USE_FULL_LL_DRIVER)
<> 154:37f96f9d4de2 71 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
<> 154:37f96f9d4de2 72 * @{
<> 154:37f96f9d4de2 73 */
<> 154:37f96f9d4de2 74
<> 154:37f96f9d4de2 75 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
<> 154:37f96f9d4de2 76 * @{
<> 154:37f96f9d4de2 77 */
<> 154:37f96f9d4de2 78
<> 154:37f96f9d4de2 79 /**
<> 154:37f96f9d4de2 80 * @brief RCC Clocks Frequency Structure
<> 154:37f96f9d4de2 81 */
<> 154:37f96f9d4de2 82 typedef struct
<> 154:37f96f9d4de2 83 {
<> 154:37f96f9d4de2 84 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
<> 154:37f96f9d4de2 85 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
<> 154:37f96f9d4de2 86 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
<> 154:37f96f9d4de2 87 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
<> 154:37f96f9d4de2 88 } LL_RCC_ClocksTypeDef;
<> 154:37f96f9d4de2 89
<> 154:37f96f9d4de2 90 /**
<> 154:37f96f9d4de2 91 * @}
<> 154:37f96f9d4de2 92 */
<> 154:37f96f9d4de2 93
<> 154:37f96f9d4de2 94 /**
<> 154:37f96f9d4de2 95 * @}
<> 154:37f96f9d4de2 96 */
<> 154:37f96f9d4de2 97 #endif /* USE_FULL_LL_DRIVER */
<> 154:37f96f9d4de2 98
<> 154:37f96f9d4de2 99 /* Exported constants --------------------------------------------------------*/
<> 154:37f96f9d4de2 100 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
<> 154:37f96f9d4de2 101 * @{
<> 154:37f96f9d4de2 102 */
<> 154:37f96f9d4de2 103
<> 154:37f96f9d4de2 104 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
<> 154:37f96f9d4de2 105 * @brief Defines used to adapt values of different oscillators
<> 154:37f96f9d4de2 106 * @note These values could be modified in the user environment according to
<> 154:37f96f9d4de2 107 * HW set-up.
<> 154:37f96f9d4de2 108 * @{
<> 154:37f96f9d4de2 109 */
<> 154:37f96f9d4de2 110 #if !defined (HSE_VALUE)
AnnaBridge 165:e614a9f1c9e2 111 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
<> 154:37f96f9d4de2 112 #endif /* HSE_VALUE */
<> 154:37f96f9d4de2 113
<> 154:37f96f9d4de2 114 #if !defined (HSI_VALUE)
AnnaBridge 165:e614a9f1c9e2 115 #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
<> 154:37f96f9d4de2 116 #endif /* HSI_VALUE */
<> 154:37f96f9d4de2 117
<> 154:37f96f9d4de2 118 #if !defined (LSE_VALUE)
AnnaBridge 165:e614a9f1c9e2 119 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
<> 154:37f96f9d4de2 120 #endif /* LSE_VALUE */
<> 154:37f96f9d4de2 121
<> 154:37f96f9d4de2 122 #if !defined (LSI_VALUE)
AnnaBridge 165:e614a9f1c9e2 123 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
<> 154:37f96f9d4de2 124 #endif /* LSI_VALUE */
<> 154:37f96f9d4de2 125 /**
<> 154:37f96f9d4de2 126 * @}
<> 154:37f96f9d4de2 127 */
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 154:37f96f9d4de2 130 * @brief Flags defines which can be used with LL_RCC_WriteReg function
<> 154:37f96f9d4de2 131 * @{
<> 154:37f96f9d4de2 132 */
<> 154:37f96f9d4de2 133 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
<> 154:37f96f9d4de2 134 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
<> 154:37f96f9d4de2 135 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
<> 154:37f96f9d4de2 136 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
<> 154:37f96f9d4de2 137 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
<> 154:37f96f9d4de2 138 #define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */
<> 154:37f96f9d4de2 139 #define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */
<> 154:37f96f9d4de2 140 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
<> 154:37f96f9d4de2 141 /**
<> 154:37f96f9d4de2 142 * @}
<> 154:37f96f9d4de2 143 */
<> 154:37f96f9d4de2 144
<> 154:37f96f9d4de2 145 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
<> 154:37f96f9d4de2 146 * @brief Flags defines which can be used with LL_RCC_ReadReg function
<> 154:37f96f9d4de2 147 * @{
<> 154:37f96f9d4de2 148 */
<> 154:37f96f9d4de2 149 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
<> 154:37f96f9d4de2 150 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
<> 154:37f96f9d4de2 151 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
<> 154:37f96f9d4de2 152 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
<> 154:37f96f9d4de2 153 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
<> 154:37f96f9d4de2 154 #define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */
<> 154:37f96f9d4de2 155 #define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
AnnaBridge 165:e614a9f1c9e2 156 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
AnnaBridge 165:e614a9f1c9e2 157 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
AnnaBridge 165:e614a9f1c9e2 158 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
AnnaBridge 165:e614a9f1c9e2 159 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
AnnaBridge 165:e614a9f1c9e2 160 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
AnnaBridge 165:e614a9f1c9e2 161 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
AnnaBridge 165:e614a9f1c9e2 162 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
<> 154:37f96f9d4de2 163 /**
<> 154:37f96f9d4de2 164 * @}
<> 154:37f96f9d4de2 165 */
<> 154:37f96f9d4de2 166
<> 154:37f96f9d4de2 167 /** @defgroup RCC_LL_EC_IT IT Defines
<> 154:37f96f9d4de2 168 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
<> 154:37f96f9d4de2 169 * @{
<> 154:37f96f9d4de2 170 */
<> 154:37f96f9d4de2 171 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
<> 154:37f96f9d4de2 172 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
<> 154:37f96f9d4de2 173 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
<> 154:37f96f9d4de2 174 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
<> 154:37f96f9d4de2 175 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
AnnaBridge 165:e614a9f1c9e2 176 #define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */
AnnaBridge 165:e614a9f1c9e2 177 #define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */
<> 154:37f96f9d4de2 178 /**
<> 154:37f96f9d4de2 179 * @}
<> 154:37f96f9d4de2 180 */
<> 154:37f96f9d4de2 181
AnnaBridge 165:e614a9f1c9e2 182 #if defined(RCC_CFGR2_PREDIV2)
<> 154:37f96f9d4de2 183 /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
<> 154:37f96f9d4de2 184 * @{
<> 154:37f96f9d4de2 185 */
<> 154:37f96f9d4de2 186 #define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
<> 154:37f96f9d4de2 187 #define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
<> 154:37f96f9d4de2 188 #define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
<> 154:37f96f9d4de2 189 #define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
<> 154:37f96f9d4de2 190 #define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
<> 154:37f96f9d4de2 191 #define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
<> 154:37f96f9d4de2 192 #define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
<> 154:37f96f9d4de2 193 #define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
<> 154:37f96f9d4de2 194 #define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
<> 154:37f96f9d4de2 195 #define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
<> 154:37f96f9d4de2 196 #define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
<> 154:37f96f9d4de2 197 #define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
<> 154:37f96f9d4de2 198 #define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
<> 154:37f96f9d4de2 199 #define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
<> 154:37f96f9d4de2 200 #define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
<> 154:37f96f9d4de2 201 #define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
<> 154:37f96f9d4de2 202 /**
<> 154:37f96f9d4de2 203 * @}
<> 154:37f96f9d4de2 204 */
<> 154:37f96f9d4de2 205
AnnaBridge 165:e614a9f1c9e2 206 #endif /* RCC_CFGR2_PREDIV2 */
<> 154:37f96f9d4de2 207
<> 154:37f96f9d4de2 208 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
<> 154:37f96f9d4de2 209 * @{
<> 154:37f96f9d4de2 210 */
<> 154:37f96f9d4de2 211 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
<> 154:37f96f9d4de2 212 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
<> 154:37f96f9d4de2 213 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
<> 154:37f96f9d4de2 214 /**
<> 154:37f96f9d4de2 215 * @}
<> 154:37f96f9d4de2 216 */
<> 154:37f96f9d4de2 217
<> 154:37f96f9d4de2 218 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
<> 154:37f96f9d4de2 219 * @{
<> 154:37f96f9d4de2 220 */
<> 154:37f96f9d4de2 221 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
<> 154:37f96f9d4de2 222 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
<> 154:37f96f9d4de2 223 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
<> 154:37f96f9d4de2 224 /**
<> 154:37f96f9d4de2 225 * @}
<> 154:37f96f9d4de2 226 */
<> 154:37f96f9d4de2 227
<> 154:37f96f9d4de2 228 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
<> 154:37f96f9d4de2 229 * @{
<> 154:37f96f9d4de2 230 */
<> 154:37f96f9d4de2 231 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
<> 154:37f96f9d4de2 232 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
<> 154:37f96f9d4de2 233 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
<> 154:37f96f9d4de2 234 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
<> 154:37f96f9d4de2 235 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
<> 154:37f96f9d4de2 236 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
<> 154:37f96f9d4de2 237 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
<> 154:37f96f9d4de2 238 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
<> 154:37f96f9d4de2 239 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
<> 154:37f96f9d4de2 240 /**
<> 154:37f96f9d4de2 241 * @}
<> 154:37f96f9d4de2 242 */
<> 154:37f96f9d4de2 243
<> 154:37f96f9d4de2 244 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
<> 154:37f96f9d4de2 245 * @{
<> 154:37f96f9d4de2 246 */
<> 154:37f96f9d4de2 247 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
<> 154:37f96f9d4de2 248 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
<> 154:37f96f9d4de2 249 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
<> 154:37f96f9d4de2 250 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
<> 154:37f96f9d4de2 251 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
<> 154:37f96f9d4de2 252 /**
<> 154:37f96f9d4de2 253 * @}
<> 154:37f96f9d4de2 254 */
<> 154:37f96f9d4de2 255
<> 154:37f96f9d4de2 256 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
<> 154:37f96f9d4de2 257 * @{
<> 154:37f96f9d4de2 258 */
<> 154:37f96f9d4de2 259 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
<> 154:37f96f9d4de2 260 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
<> 154:37f96f9d4de2 261 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
<> 154:37f96f9d4de2 262 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
<> 154:37f96f9d4de2 263 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
<> 154:37f96f9d4de2 264 /**
<> 154:37f96f9d4de2 265 * @}
<> 154:37f96f9d4de2 266 */
<> 154:37f96f9d4de2 267
<> 154:37f96f9d4de2 268 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
<> 154:37f96f9d4de2 269 * @{
<> 154:37f96f9d4de2 270 */
<> 154:37f96f9d4de2 271 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
<> 154:37f96f9d4de2 272 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
<> 154:37f96f9d4de2 273 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
<> 154:37f96f9d4de2 274 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
<> 154:37f96f9d4de2 275 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
<> 154:37f96f9d4de2 276 #if defined(RCC_CFGR_MCOSEL_PLL2CLK)
<> 154:37f96f9d4de2 277 #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /*!< PLL2 clock selected as MCO source*/
<> 154:37f96f9d4de2 278 #endif /* RCC_CFGR_MCOSEL_PLL2CLK */
<> 154:37f96f9d4de2 279 #if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
<> 154:37f96f9d4de2 280 #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/
<> 154:37f96f9d4de2 281 #endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
<> 154:37f96f9d4de2 282 #if defined(RCC_CFGR_MCOSEL_EXT_HSE)
<> 154:37f96f9d4de2 283 #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
<> 154:37f96f9d4de2 284 #endif /* RCC_CFGR_MCOSEL_EXT_HSE */
<> 154:37f96f9d4de2 285 #if defined(RCC_CFGR_MCOSEL_PLL3CLK)
AnnaBridge 165:e614a9f1c9e2 286 #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */
<> 154:37f96f9d4de2 287 #endif /* RCC_CFGR_MCOSEL_PLL3CLK */
<> 154:37f96f9d4de2 288 /**
<> 154:37f96f9d4de2 289 * @}
<> 154:37f96f9d4de2 290 */
<> 154:37f96f9d4de2 291
<> 154:37f96f9d4de2 292 #if defined(USE_FULL_LL_DRIVER)
<> 154:37f96f9d4de2 293 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
<> 154:37f96f9d4de2 294 * @{
<> 154:37f96f9d4de2 295 */
AnnaBridge 165:e614a9f1c9e2 296 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
AnnaBridge 165:e614a9f1c9e2 297 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
<> 154:37f96f9d4de2 298 /**
<> 154:37f96f9d4de2 299 * @}
<> 154:37f96f9d4de2 300 */
<> 154:37f96f9d4de2 301 #endif /* USE_FULL_LL_DRIVER */
<> 154:37f96f9d4de2 302
<> 154:37f96f9d4de2 303 #if defined(RCC_CFGR2_I2S2SRC)
<> 154:37f96f9d4de2 304 /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
<> 154:37f96f9d4de2 305 * @{
<> 154:37f96f9d4de2 306 */
AnnaBridge 165:e614a9f1c9e2 307 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */
AnnaBridge 165:e614a9f1c9e2 308 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */
AnnaBridge 165:e614a9f1c9e2 309 #define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */
AnnaBridge 165:e614a9f1c9e2 310 #define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */
<> 154:37f96f9d4de2 311 /**
<> 154:37f96f9d4de2 312 * @}
<> 154:37f96f9d4de2 313 */
<> 154:37f96f9d4de2 314 #endif /* RCC_CFGR2_I2S2SRC */
<> 154:37f96f9d4de2 315
<> 154:37f96f9d4de2 316 #if defined(USB_OTG_FS) || defined(USB)
<> 154:37f96f9d4de2 317 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
<> 154:37f96f9d4de2 318 * @{
<> 154:37f96f9d4de2 319 */
<> 154:37f96f9d4de2 320 #if defined(RCC_CFGR_USBPRE)
AnnaBridge 165:e614a9f1c9e2 321 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */
AnnaBridge 165:e614a9f1c9e2 322 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */
AnnaBridge 165:e614a9f1c9e2 323 #endif /*RCC_CFGR_USBPRE*/
AnnaBridge 165:e614a9f1c9e2 324 #if defined(RCC_CFGR_OTGFSPRE)
AnnaBridge 165:e614a9f1c9e2 325 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */
AnnaBridge 165:e614a9f1c9e2 326 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */
<> 154:37f96f9d4de2 327 #endif /*RCC_CFGR_OTGFSPRE*/
<> 154:37f96f9d4de2 328 /**
<> 154:37f96f9d4de2 329 * @}
<> 154:37f96f9d4de2 330 */
<> 154:37f96f9d4de2 331 #endif /* USB_OTG_FS || USB */
<> 154:37f96f9d4de2 332
<> 154:37f96f9d4de2 333 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
<> 154:37f96f9d4de2 334 * @{
<> 154:37f96f9d4de2 335 */
<> 154:37f96f9d4de2 336 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
<> 154:37f96f9d4de2 337 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
<> 154:37f96f9d4de2 338 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
<> 154:37f96f9d4de2 339 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
<> 154:37f96f9d4de2 340 /**
<> 154:37f96f9d4de2 341 * @}
<> 154:37f96f9d4de2 342 */
<> 154:37f96f9d4de2 343
<> 154:37f96f9d4de2 344 #if defined(RCC_CFGR2_I2S2SRC)
<> 154:37f96f9d4de2 345 /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
<> 154:37f96f9d4de2 346 * @{
<> 154:37f96f9d4de2 347 */
<> 154:37f96f9d4de2 348 #define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */
<> 154:37f96f9d4de2 349 #define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */
<> 154:37f96f9d4de2 350 /**
<> 154:37f96f9d4de2 351 * @}
<> 154:37f96f9d4de2 352 */
<> 154:37f96f9d4de2 353
<> 154:37f96f9d4de2 354 #endif /* RCC_CFGR2_I2S2SRC */
<> 154:37f96f9d4de2 355
<> 154:37f96f9d4de2 356 #if defined(USB_OTG_FS) || defined(USB)
<> 154:37f96f9d4de2 357 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
<> 154:37f96f9d4de2 358 * @{
<> 154:37f96f9d4de2 359 */
AnnaBridge 165:e614a9f1c9e2 360 #define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */
<> 154:37f96f9d4de2 361 /**
<> 154:37f96f9d4de2 362 * @}
<> 154:37f96f9d4de2 363 */
<> 154:37f96f9d4de2 364
<> 154:37f96f9d4de2 365 #endif /* USB_OTG_FS || USB */
<> 154:37f96f9d4de2 366
<> 154:37f96f9d4de2 367 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
<> 154:37f96f9d4de2 368 * @{
<> 154:37f96f9d4de2 369 */
<> 154:37f96f9d4de2 370 #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
<> 154:37f96f9d4de2 371 /**
<> 154:37f96f9d4de2 372 * @}
<> 154:37f96f9d4de2 373 */
<> 154:37f96f9d4de2 374
<> 154:37f96f9d4de2 375 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
<> 154:37f96f9d4de2 376 * @{
<> 154:37f96f9d4de2 377 */
AnnaBridge 165:e614a9f1c9e2 378 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
<> 154:37f96f9d4de2 379 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
<> 154:37f96f9d4de2 380 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 165:e614a9f1c9e2 381 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */
<> 154:37f96f9d4de2 382 /**
<> 154:37f96f9d4de2 383 * @}
<> 154:37f96f9d4de2 384 */
<> 154:37f96f9d4de2 385
<> 154:37f96f9d4de2 386 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
<> 154:37f96f9d4de2 387 * @{
<> 154:37f96f9d4de2 388 */
<> 154:37f96f9d4de2 389 #if defined(RCC_CFGR_PLLMULL2)
<> 154:37f96f9d4de2 390 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */
<> 154:37f96f9d4de2 391 #endif /*RCC_CFGR_PLLMULL2*/
<> 154:37f96f9d4de2 392 #if defined(RCC_CFGR_PLLMULL3)
<> 154:37f96f9d4de2 393 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */
<> 154:37f96f9d4de2 394 #endif /*RCC_CFGR_PLLMULL3*/
<> 154:37f96f9d4de2 395 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */
<> 154:37f96f9d4de2 396 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */
<> 154:37f96f9d4de2 397 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */
<> 154:37f96f9d4de2 398 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */
<> 154:37f96f9d4de2 399 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */
<> 154:37f96f9d4de2 400 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */
<> 154:37f96f9d4de2 401 #if defined(RCC_CFGR_PLLMULL6_5)
<> 154:37f96f9d4de2 402 #define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
<> 154:37f96f9d4de2 403 #else
<> 154:37f96f9d4de2 404 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */
<> 154:37f96f9d4de2 405 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */
<> 154:37f96f9d4de2 406 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */
<> 154:37f96f9d4de2 407 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */
<> 154:37f96f9d4de2 408 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */
<> 154:37f96f9d4de2 409 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */
<> 154:37f96f9d4de2 410 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */
<> 154:37f96f9d4de2 411 #endif /*RCC_CFGR_PLLMULL6_5*/
<> 154:37f96f9d4de2 412 /**
<> 154:37f96f9d4de2 413 * @}
<> 154:37f96f9d4de2 414 */
<> 154:37f96f9d4de2 415
<> 154:37f96f9d4de2 416 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
<> 154:37f96f9d4de2 417 * @{
<> 154:37f96f9d4de2 418 */
AnnaBridge 165:e614a9f1c9e2 419 #define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 420 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 421 #if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge 165:e614a9f1c9e2 422 #define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 423 #endif /*RCC_CFGR2_PREDIV1SRC*/
<> 154:37f96f9d4de2 424
AnnaBridge 165:e614a9f1c9e2 425 #if defined(RCC_CFGR2_PREDIV1)
AnnaBridge 187:0387e8f68319 426 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 427 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 428 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 429 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 430 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 431 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 432 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 433 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 434 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 435 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 436 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 437 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 438 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 439 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 440 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 441 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 442 #if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge 187:0387e8f68319 443 #define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 444 #define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 445 #define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 446 #define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 447 #define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 448 #define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 449 #define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 450 #define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 451 #define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 452 #define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 453 #define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 454 #define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 455 #define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 456 #define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 457 #define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 458 #define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 459 #endif /*RCC_CFGR2_PREDIV1SRC*/
<> 154:37f96f9d4de2 460 #else
AnnaBridge 187:0387e8f68319 461 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */
<> 154:37f96f9d4de2 462 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */
AnnaBridge 165:e614a9f1c9e2 463 #endif /*RCC_CFGR2_PREDIV1*/
<> 154:37f96f9d4de2 464 /**
<> 154:37f96f9d4de2 465 * @}
<> 154:37f96f9d4de2 466 */
<> 154:37f96f9d4de2 467
<> 154:37f96f9d4de2 468 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
<> 154:37f96f9d4de2 469 * @{
<> 154:37f96f9d4de2 470 */
AnnaBridge 165:e614a9f1c9e2 471 #if defined(RCC_CFGR2_PREDIV1)
<> 154:37f96f9d4de2 472 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */
<> 154:37f96f9d4de2 473 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */
<> 154:37f96f9d4de2 474 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */
<> 154:37f96f9d4de2 475 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */
<> 154:37f96f9d4de2 476 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */
<> 154:37f96f9d4de2 477 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */
<> 154:37f96f9d4de2 478 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */
<> 154:37f96f9d4de2 479 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */
<> 154:37f96f9d4de2 480 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */
<> 154:37f96f9d4de2 481 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */
<> 154:37f96f9d4de2 482 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */
<> 154:37f96f9d4de2 483 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */
<> 154:37f96f9d4de2 484 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */
<> 154:37f96f9d4de2 485 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */
<> 154:37f96f9d4de2 486 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */
<> 154:37f96f9d4de2 487 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */
<> 154:37f96f9d4de2 488 #else
AnnaBridge 165:e614a9f1c9e2 489 #define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */
AnnaBridge 165:e614a9f1c9e2 490 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */
AnnaBridge 165:e614a9f1c9e2 491 #endif /*RCC_CFGR2_PREDIV1*/
<> 154:37f96f9d4de2 492 /**
<> 154:37f96f9d4de2 493 * @}
<> 154:37f96f9d4de2 494 */
<> 154:37f96f9d4de2 495
<> 154:37f96f9d4de2 496 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 497 /** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
<> 154:37f96f9d4de2 498 * @{
<> 154:37f96f9d4de2 499 */
<> 154:37f96f9d4de2 500 #define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
<> 154:37f96f9d4de2 501 #define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
<> 154:37f96f9d4de2 502 #define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
<> 154:37f96f9d4de2 503 #define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
<> 154:37f96f9d4de2 504 #define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
<> 154:37f96f9d4de2 505 #define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
<> 154:37f96f9d4de2 506 #define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
<> 154:37f96f9d4de2 507 #define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
<> 154:37f96f9d4de2 508 #define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
<> 154:37f96f9d4de2 509 /**
<> 154:37f96f9d4de2 510 * @}
<> 154:37f96f9d4de2 511 */
<> 154:37f96f9d4de2 512
<> 154:37f96f9d4de2 513 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 514
<> 154:37f96f9d4de2 515 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 516 /** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
<> 154:37f96f9d4de2 517 * @{
<> 154:37f96f9d4de2 518 */
<> 154:37f96f9d4de2 519 #define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
<> 154:37f96f9d4de2 520 #define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
<> 154:37f96f9d4de2 521 #define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
<> 154:37f96f9d4de2 522 #define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
<> 154:37f96f9d4de2 523 #define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
<> 154:37f96f9d4de2 524 #define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
<> 154:37f96f9d4de2 525 #define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
<> 154:37f96f9d4de2 526 #define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
<> 154:37f96f9d4de2 527 #define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
<> 154:37f96f9d4de2 528 /**
<> 154:37f96f9d4de2 529 * @}
<> 154:37f96f9d4de2 530 */
<> 154:37f96f9d4de2 531
<> 154:37f96f9d4de2 532 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 533
<> 154:37f96f9d4de2 534 /**
<> 154:37f96f9d4de2 535 * @}
<> 154:37f96f9d4de2 536 */
<> 154:37f96f9d4de2 537
<> 154:37f96f9d4de2 538 /* Exported macro ------------------------------------------------------------*/
<> 154:37f96f9d4de2 539 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
<> 154:37f96f9d4de2 540 * @{
<> 154:37f96f9d4de2 541 */
<> 154:37f96f9d4de2 542
<> 154:37f96f9d4de2 543 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
<> 154:37f96f9d4de2 544 * @{
<> 154:37f96f9d4de2 545 */
<> 154:37f96f9d4de2 546
<> 154:37f96f9d4de2 547 /**
<> 154:37f96f9d4de2 548 * @brief Write a value in RCC register
<> 154:37f96f9d4de2 549 * @param __REG__ Register to be written
<> 154:37f96f9d4de2 550 * @param __VALUE__ Value to be written in the register
<> 154:37f96f9d4de2 551 * @retval None
<> 154:37f96f9d4de2 552 */
<> 154:37f96f9d4de2 553 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
<> 154:37f96f9d4de2 554
<> 154:37f96f9d4de2 555 /**
<> 154:37f96f9d4de2 556 * @brief Read a value in RCC register
<> 154:37f96f9d4de2 557 * @param __REG__ Register to be read
<> 154:37f96f9d4de2 558 * @retval Register value
<> 154:37f96f9d4de2 559 */
<> 154:37f96f9d4de2 560 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
<> 154:37f96f9d4de2 561 /**
<> 154:37f96f9d4de2 562 * @}
<> 154:37f96f9d4de2 563 */
<> 154:37f96f9d4de2 564
<> 154:37f96f9d4de2 565 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
<> 154:37f96f9d4de2 566 * @{
<> 154:37f96f9d4de2 567 */
<> 154:37f96f9d4de2 568
<> 154:37f96f9d4de2 569 #if defined(RCC_CFGR_PLLMULL6_5)
<> 154:37f96f9d4de2 570 /**
<> 154:37f96f9d4de2 571 * @brief Helper macro to calculate the PLLCLK frequency
<> 154:37f96f9d4de2 572 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
<> 154:37f96f9d4de2 573 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
<> 154:37f96f9d4de2 574 * @param __PLLMUL__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 575 * @arg @ref LL_RCC_PLL_MUL_4
<> 154:37f96f9d4de2 576 * @arg @ref LL_RCC_PLL_MUL_5
<> 154:37f96f9d4de2 577 * @arg @ref LL_RCC_PLL_MUL_6
<> 154:37f96f9d4de2 578 * @arg @ref LL_RCC_PLL_MUL_7
<> 154:37f96f9d4de2 579 * @arg @ref LL_RCC_PLL_MUL_8
<> 154:37f96f9d4de2 580 * @arg @ref LL_RCC_PLL_MUL_9
<> 154:37f96f9d4de2 581 * @arg @ref LL_RCC_PLL_MUL_6_5
<> 154:37f96f9d4de2 582 * @retval PLL clock frequency (in Hz)
<> 154:37f96f9d4de2 583 */
<> 154:37f96f9d4de2 584 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
<> 154:37f96f9d4de2 585 (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
AnnaBridge 165:e614a9f1c9e2 586 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
<> 154:37f96f9d4de2 587 (((__INPUTFREQ__) * 13U) / 2U))
<> 154:37f96f9d4de2 588
<> 154:37f96f9d4de2 589 #else
<> 154:37f96f9d4de2 590 /**
<> 154:37f96f9d4de2 591 * @brief Helper macro to calculate the PLLCLK frequency
<> 154:37f96f9d4de2 592 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
<> 154:37f96f9d4de2 593 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
<> 154:37f96f9d4de2 594 * @param __PLLMUL__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 595 * @arg @ref LL_RCC_PLL_MUL_2
<> 154:37f96f9d4de2 596 * @arg @ref LL_RCC_PLL_MUL_3
<> 154:37f96f9d4de2 597 * @arg @ref LL_RCC_PLL_MUL_4
<> 154:37f96f9d4de2 598 * @arg @ref LL_RCC_PLL_MUL_5
<> 154:37f96f9d4de2 599 * @arg @ref LL_RCC_PLL_MUL_6
<> 154:37f96f9d4de2 600 * @arg @ref LL_RCC_PLL_MUL_7
<> 154:37f96f9d4de2 601 * @arg @ref LL_RCC_PLL_MUL_8
<> 154:37f96f9d4de2 602 * @arg @ref LL_RCC_PLL_MUL_9
<> 154:37f96f9d4de2 603 * @arg @ref LL_RCC_PLL_MUL_10
<> 154:37f96f9d4de2 604 * @arg @ref LL_RCC_PLL_MUL_11
<> 154:37f96f9d4de2 605 * @arg @ref LL_RCC_PLL_MUL_12
<> 154:37f96f9d4de2 606 * @arg @ref LL_RCC_PLL_MUL_13
<> 154:37f96f9d4de2 607 * @arg @ref LL_RCC_PLL_MUL_14
<> 154:37f96f9d4de2 608 * @arg @ref LL_RCC_PLL_MUL_15
<> 154:37f96f9d4de2 609 * @arg @ref LL_RCC_PLL_MUL_16
<> 154:37f96f9d4de2 610 * @retval PLL clock frequency (in Hz)
<> 154:37f96f9d4de2 611 */
AnnaBridge 165:e614a9f1c9e2 612 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
<> 154:37f96f9d4de2 613 #endif /* RCC_CFGR_PLLMULL6_5 */
<> 154:37f96f9d4de2 614
<> 154:37f96f9d4de2 615 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 616 /**
<> 154:37f96f9d4de2 617 * @brief Helper macro to calculate the PLLI2S frequency
<> 154:37f96f9d4de2 618 * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
<> 154:37f96f9d4de2 619 * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
<> 154:37f96f9d4de2 620 * @param __PLLI2SMUL__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 621 * @arg @ref LL_RCC_PLLI2S_MUL_8
<> 154:37f96f9d4de2 622 * @arg @ref LL_RCC_PLLI2S_MUL_9
<> 154:37f96f9d4de2 623 * @arg @ref LL_RCC_PLLI2S_MUL_10
<> 154:37f96f9d4de2 624 * @arg @ref LL_RCC_PLLI2S_MUL_11
<> 154:37f96f9d4de2 625 * @arg @ref LL_RCC_PLLI2S_MUL_12
<> 154:37f96f9d4de2 626 * @arg @ref LL_RCC_PLLI2S_MUL_13
<> 154:37f96f9d4de2 627 * @arg @ref LL_RCC_PLLI2S_MUL_14
<> 154:37f96f9d4de2 628 * @arg @ref LL_RCC_PLLI2S_MUL_16
<> 154:37f96f9d4de2 629 * @arg @ref LL_RCC_PLLI2S_MUL_20
<> 154:37f96f9d4de2 630 * @param __PLLI2SDIV__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 631 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<> 154:37f96f9d4de2 632 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<> 154:37f96f9d4de2 633 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<> 154:37f96f9d4de2 634 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<> 154:37f96f9d4de2 635 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<> 154:37f96f9d4de2 636 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<> 154:37f96f9d4de2 637 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<> 154:37f96f9d4de2 638 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<> 154:37f96f9d4de2 639 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<> 154:37f96f9d4de2 640 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<> 154:37f96f9d4de2 641 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<> 154:37f96f9d4de2 642 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<> 154:37f96f9d4de2 643 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<> 154:37f96f9d4de2 644 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<> 154:37f96f9d4de2 645 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<> 154:37f96f9d4de2 646 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<> 154:37f96f9d4de2 647 * @retval PLLI2S clock frequency (in Hz)
<> 154:37f96f9d4de2 648 */
AnnaBridge 165:e614a9f1c9e2 649 #define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
<> 154:37f96f9d4de2 650 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 651
<> 154:37f96f9d4de2 652 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 653 /**
<> 154:37f96f9d4de2 654 * @brief Helper macro to calculate the PLL2 frequency
<> 154:37f96f9d4de2 655 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
<> 154:37f96f9d4de2 656 * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
<> 154:37f96f9d4de2 657 * @param __PLL2MUL__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 658 * @arg @ref LL_RCC_PLL2_MUL_8
<> 154:37f96f9d4de2 659 * @arg @ref LL_RCC_PLL2_MUL_9
<> 154:37f96f9d4de2 660 * @arg @ref LL_RCC_PLL2_MUL_10
<> 154:37f96f9d4de2 661 * @arg @ref LL_RCC_PLL2_MUL_11
<> 154:37f96f9d4de2 662 * @arg @ref LL_RCC_PLL2_MUL_12
<> 154:37f96f9d4de2 663 * @arg @ref LL_RCC_PLL2_MUL_13
<> 154:37f96f9d4de2 664 * @arg @ref LL_RCC_PLL2_MUL_14
<> 154:37f96f9d4de2 665 * @arg @ref LL_RCC_PLL2_MUL_16
<> 154:37f96f9d4de2 666 * @arg @ref LL_RCC_PLL2_MUL_20
<> 154:37f96f9d4de2 667 * @param __PLL2DIV__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 668 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<> 154:37f96f9d4de2 669 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<> 154:37f96f9d4de2 670 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<> 154:37f96f9d4de2 671 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<> 154:37f96f9d4de2 672 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<> 154:37f96f9d4de2 673 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<> 154:37f96f9d4de2 674 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<> 154:37f96f9d4de2 675 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<> 154:37f96f9d4de2 676 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<> 154:37f96f9d4de2 677 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<> 154:37f96f9d4de2 678 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<> 154:37f96f9d4de2 679 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<> 154:37f96f9d4de2 680 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<> 154:37f96f9d4de2 681 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<> 154:37f96f9d4de2 682 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<> 154:37f96f9d4de2 683 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<> 154:37f96f9d4de2 684 * @retval PLL2 clock frequency (in Hz)
<> 154:37f96f9d4de2 685 */
AnnaBridge 165:e614a9f1c9e2 686 #define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
<> 154:37f96f9d4de2 687 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 688
<> 154:37f96f9d4de2 689 /**
<> 154:37f96f9d4de2 690 * @brief Helper macro to calculate the HCLK frequency
<> 154:37f96f9d4de2 691 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
<> 154:37f96f9d4de2 692 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
<> 154:37f96f9d4de2 693 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
<> 154:37f96f9d4de2 694 * @param __AHBPRESCALER__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 695 * @arg @ref LL_RCC_SYSCLK_DIV_1
<> 154:37f96f9d4de2 696 * @arg @ref LL_RCC_SYSCLK_DIV_2
<> 154:37f96f9d4de2 697 * @arg @ref LL_RCC_SYSCLK_DIV_4
<> 154:37f96f9d4de2 698 * @arg @ref LL_RCC_SYSCLK_DIV_8
<> 154:37f96f9d4de2 699 * @arg @ref LL_RCC_SYSCLK_DIV_16
<> 154:37f96f9d4de2 700 * @arg @ref LL_RCC_SYSCLK_DIV_64
<> 154:37f96f9d4de2 701 * @arg @ref LL_RCC_SYSCLK_DIV_128
<> 154:37f96f9d4de2 702 * @arg @ref LL_RCC_SYSCLK_DIV_256
<> 154:37f96f9d4de2 703 * @arg @ref LL_RCC_SYSCLK_DIV_512
<> 154:37f96f9d4de2 704 * @retval HCLK clock frequency (in Hz)
<> 154:37f96f9d4de2 705 */
AnnaBridge 165:e614a9f1c9e2 706 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
<> 154:37f96f9d4de2 707
<> 154:37f96f9d4de2 708 /**
<> 154:37f96f9d4de2 709 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
<> 154:37f96f9d4de2 710 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
<> 154:37f96f9d4de2 711 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
<> 154:37f96f9d4de2 712 * @param __HCLKFREQ__ HCLK frequency
<> 154:37f96f9d4de2 713 * @param __APB1PRESCALER__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 714 * @arg @ref LL_RCC_APB1_DIV_1
<> 154:37f96f9d4de2 715 * @arg @ref LL_RCC_APB1_DIV_2
<> 154:37f96f9d4de2 716 * @arg @ref LL_RCC_APB1_DIV_4
<> 154:37f96f9d4de2 717 * @arg @ref LL_RCC_APB1_DIV_8
<> 154:37f96f9d4de2 718 * @arg @ref LL_RCC_APB1_DIV_16
<> 154:37f96f9d4de2 719 * @retval PCLK1 clock frequency (in Hz)
<> 154:37f96f9d4de2 720 */
AnnaBridge 165:e614a9f1c9e2 721 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
<> 154:37f96f9d4de2 722
<> 154:37f96f9d4de2 723 /**
<> 154:37f96f9d4de2 724 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
<> 154:37f96f9d4de2 725 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
<> 154:37f96f9d4de2 726 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
<> 154:37f96f9d4de2 727 * @param __HCLKFREQ__ HCLK frequency
<> 154:37f96f9d4de2 728 * @param __APB2PRESCALER__: This parameter can be one of the following values:
<> 154:37f96f9d4de2 729 * @arg @ref LL_RCC_APB2_DIV_1
<> 154:37f96f9d4de2 730 * @arg @ref LL_RCC_APB2_DIV_2
<> 154:37f96f9d4de2 731 * @arg @ref LL_RCC_APB2_DIV_4
<> 154:37f96f9d4de2 732 * @arg @ref LL_RCC_APB2_DIV_8
<> 154:37f96f9d4de2 733 * @arg @ref LL_RCC_APB2_DIV_16
<> 154:37f96f9d4de2 734 * @retval PCLK2 clock frequency (in Hz)
<> 154:37f96f9d4de2 735 */
AnnaBridge 165:e614a9f1c9e2 736 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
<> 154:37f96f9d4de2 737
<> 154:37f96f9d4de2 738 /**
<> 154:37f96f9d4de2 739 * @}
<> 154:37f96f9d4de2 740 */
<> 154:37f96f9d4de2 741
<> 154:37f96f9d4de2 742 /**
<> 154:37f96f9d4de2 743 * @}
<> 154:37f96f9d4de2 744 */
<> 154:37f96f9d4de2 745
<> 154:37f96f9d4de2 746 /* Exported functions --------------------------------------------------------*/
<> 154:37f96f9d4de2 747 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
<> 154:37f96f9d4de2 748 * @{
<> 154:37f96f9d4de2 749 */
<> 154:37f96f9d4de2 750
<> 154:37f96f9d4de2 751 /** @defgroup RCC_LL_EF_HSE HSE
<> 154:37f96f9d4de2 752 * @{
<> 154:37f96f9d4de2 753 */
<> 154:37f96f9d4de2 754
<> 154:37f96f9d4de2 755 /**
<> 154:37f96f9d4de2 756 * @brief Enable the Clock Security System.
<> 154:37f96f9d4de2 757 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
<> 154:37f96f9d4de2 758 * @retval None
<> 154:37f96f9d4de2 759 */
<> 154:37f96f9d4de2 760 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
<> 154:37f96f9d4de2 761 {
<> 154:37f96f9d4de2 762 SET_BIT(RCC->CR, RCC_CR_CSSON);
<> 154:37f96f9d4de2 763 }
<> 154:37f96f9d4de2 764
<> 154:37f96f9d4de2 765 /**
<> 154:37f96f9d4de2 766 * @brief Enable HSE external oscillator (HSE Bypass)
<> 154:37f96f9d4de2 767 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
<> 154:37f96f9d4de2 768 * @retval None
<> 154:37f96f9d4de2 769 */
<> 154:37f96f9d4de2 770 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
<> 154:37f96f9d4de2 771 {
<> 154:37f96f9d4de2 772 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 154:37f96f9d4de2 773 }
<> 154:37f96f9d4de2 774
<> 154:37f96f9d4de2 775 /**
<> 154:37f96f9d4de2 776 * @brief Disable HSE external oscillator (HSE Bypass)
<> 154:37f96f9d4de2 777 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
<> 154:37f96f9d4de2 778 * @retval None
<> 154:37f96f9d4de2 779 */
<> 154:37f96f9d4de2 780 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
<> 154:37f96f9d4de2 781 {
<> 154:37f96f9d4de2 782 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 154:37f96f9d4de2 783 }
<> 154:37f96f9d4de2 784
<> 154:37f96f9d4de2 785 /**
<> 154:37f96f9d4de2 786 * @brief Enable HSE crystal oscillator (HSE ON)
<> 154:37f96f9d4de2 787 * @rmtoll CR HSEON LL_RCC_HSE_Enable
<> 154:37f96f9d4de2 788 * @retval None
<> 154:37f96f9d4de2 789 */
<> 154:37f96f9d4de2 790 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
<> 154:37f96f9d4de2 791 {
<> 154:37f96f9d4de2 792 SET_BIT(RCC->CR, RCC_CR_HSEON);
<> 154:37f96f9d4de2 793 }
<> 154:37f96f9d4de2 794
<> 154:37f96f9d4de2 795 /**
<> 154:37f96f9d4de2 796 * @brief Disable HSE crystal oscillator (HSE ON)
<> 154:37f96f9d4de2 797 * @rmtoll CR HSEON LL_RCC_HSE_Disable
<> 154:37f96f9d4de2 798 * @retval None
<> 154:37f96f9d4de2 799 */
<> 154:37f96f9d4de2 800 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
<> 154:37f96f9d4de2 801 {
<> 154:37f96f9d4de2 802 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
<> 154:37f96f9d4de2 803 }
<> 154:37f96f9d4de2 804
<> 154:37f96f9d4de2 805 /**
<> 154:37f96f9d4de2 806 * @brief Check if HSE oscillator Ready
<> 154:37f96f9d4de2 807 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
<> 154:37f96f9d4de2 808 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 809 */
<> 154:37f96f9d4de2 810 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
<> 154:37f96f9d4de2 811 {
<> 154:37f96f9d4de2 812 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
<> 154:37f96f9d4de2 813 }
<> 154:37f96f9d4de2 814
AnnaBridge 165:e614a9f1c9e2 815 #if defined(RCC_CFGR2_PREDIV2)
<> 154:37f96f9d4de2 816 /**
<> 154:37f96f9d4de2 817 * @brief Get PREDIV2 division factor
<> 154:37f96f9d4de2 818 * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
<> 154:37f96f9d4de2 819 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 820 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<> 154:37f96f9d4de2 821 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<> 154:37f96f9d4de2 822 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<> 154:37f96f9d4de2 823 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<> 154:37f96f9d4de2 824 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<> 154:37f96f9d4de2 825 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<> 154:37f96f9d4de2 826 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<> 154:37f96f9d4de2 827 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<> 154:37f96f9d4de2 828 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<> 154:37f96f9d4de2 829 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<> 154:37f96f9d4de2 830 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<> 154:37f96f9d4de2 831 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<> 154:37f96f9d4de2 832 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<> 154:37f96f9d4de2 833 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<> 154:37f96f9d4de2 834 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<> 154:37f96f9d4de2 835 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<> 154:37f96f9d4de2 836 */
<> 154:37f96f9d4de2 837 __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
<> 154:37f96f9d4de2 838 {
<> 154:37f96f9d4de2 839 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
<> 154:37f96f9d4de2 840 }
AnnaBridge 165:e614a9f1c9e2 841 #endif /* RCC_CFGR2_PREDIV2 */
<> 154:37f96f9d4de2 842
<> 154:37f96f9d4de2 843 /**
<> 154:37f96f9d4de2 844 * @}
<> 154:37f96f9d4de2 845 */
<> 154:37f96f9d4de2 846
<> 154:37f96f9d4de2 847 /** @defgroup RCC_LL_EF_HSI HSI
<> 154:37f96f9d4de2 848 * @{
<> 154:37f96f9d4de2 849 */
<> 154:37f96f9d4de2 850
<> 154:37f96f9d4de2 851 /**
<> 154:37f96f9d4de2 852 * @brief Enable HSI oscillator
<> 154:37f96f9d4de2 853 * @rmtoll CR HSION LL_RCC_HSI_Enable
<> 154:37f96f9d4de2 854 * @retval None
<> 154:37f96f9d4de2 855 */
<> 154:37f96f9d4de2 856 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
<> 154:37f96f9d4de2 857 {
<> 154:37f96f9d4de2 858 SET_BIT(RCC->CR, RCC_CR_HSION);
<> 154:37f96f9d4de2 859 }
<> 154:37f96f9d4de2 860
<> 154:37f96f9d4de2 861 /**
<> 154:37f96f9d4de2 862 * @brief Disable HSI oscillator
<> 154:37f96f9d4de2 863 * @rmtoll CR HSION LL_RCC_HSI_Disable
<> 154:37f96f9d4de2 864 * @retval None
<> 154:37f96f9d4de2 865 */
<> 154:37f96f9d4de2 866 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
<> 154:37f96f9d4de2 867 {
<> 154:37f96f9d4de2 868 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
<> 154:37f96f9d4de2 869 }
<> 154:37f96f9d4de2 870
<> 154:37f96f9d4de2 871 /**
<> 154:37f96f9d4de2 872 * @brief Check if HSI clock is ready
<> 154:37f96f9d4de2 873 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
<> 154:37f96f9d4de2 874 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 875 */
<> 154:37f96f9d4de2 876 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
<> 154:37f96f9d4de2 877 {
<> 154:37f96f9d4de2 878 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
<> 154:37f96f9d4de2 879 }
<> 154:37f96f9d4de2 880
<> 154:37f96f9d4de2 881 /**
<> 154:37f96f9d4de2 882 * @brief Get HSI Calibration value
<> 154:37f96f9d4de2 883 * @note When HSITRIM is written, HSICAL is updated with the sum of
<> 154:37f96f9d4de2 884 * HSITRIM and the factory trim value
<> 154:37f96f9d4de2 885 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
<> 154:37f96f9d4de2 886 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<> 154:37f96f9d4de2 887 */
<> 154:37f96f9d4de2 888 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
<> 154:37f96f9d4de2 889 {
AnnaBridge 165:e614a9f1c9e2 890 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
<> 154:37f96f9d4de2 891 }
<> 154:37f96f9d4de2 892
<> 154:37f96f9d4de2 893 /**
<> 154:37f96f9d4de2 894 * @brief Set HSI Calibration trimming
<> 154:37f96f9d4de2 895 * @note user-programmable trimming value that is added to the HSICAL
<> 154:37f96f9d4de2 896 * @note Default value is 16, which, when added to the HSICAL value,
<> 154:37f96f9d4de2 897 * should trim the HSI to 16 MHz +/- 1 %
<> 154:37f96f9d4de2 898 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
<> 154:37f96f9d4de2 899 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
<> 154:37f96f9d4de2 900 * @retval None
<> 154:37f96f9d4de2 901 */
<> 154:37f96f9d4de2 902 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
<> 154:37f96f9d4de2 903 {
AnnaBridge 165:e614a9f1c9e2 904 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
<> 154:37f96f9d4de2 905 }
<> 154:37f96f9d4de2 906
<> 154:37f96f9d4de2 907 /**
<> 154:37f96f9d4de2 908 * @brief Get HSI Calibration trimming
<> 154:37f96f9d4de2 909 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
<> 154:37f96f9d4de2 910 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<> 154:37f96f9d4de2 911 */
<> 154:37f96f9d4de2 912 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
<> 154:37f96f9d4de2 913 {
AnnaBridge 165:e614a9f1c9e2 914 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
<> 154:37f96f9d4de2 915 }
<> 154:37f96f9d4de2 916
<> 154:37f96f9d4de2 917 /**
<> 154:37f96f9d4de2 918 * @}
<> 154:37f96f9d4de2 919 */
<> 154:37f96f9d4de2 920
<> 154:37f96f9d4de2 921 /** @defgroup RCC_LL_EF_LSE LSE
<> 154:37f96f9d4de2 922 * @{
<> 154:37f96f9d4de2 923 */
<> 154:37f96f9d4de2 924
<> 154:37f96f9d4de2 925 /**
<> 154:37f96f9d4de2 926 * @brief Enable Low Speed External (LSE) crystal.
<> 154:37f96f9d4de2 927 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
<> 154:37f96f9d4de2 928 * @retval None
<> 154:37f96f9d4de2 929 */
<> 154:37f96f9d4de2 930 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
<> 154:37f96f9d4de2 931 {
<> 154:37f96f9d4de2 932 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<> 154:37f96f9d4de2 933 }
<> 154:37f96f9d4de2 934
<> 154:37f96f9d4de2 935 /**
<> 154:37f96f9d4de2 936 * @brief Disable Low Speed External (LSE) crystal.
<> 154:37f96f9d4de2 937 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
<> 154:37f96f9d4de2 938 * @retval None
<> 154:37f96f9d4de2 939 */
<> 154:37f96f9d4de2 940 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
<> 154:37f96f9d4de2 941 {
<> 154:37f96f9d4de2 942 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<> 154:37f96f9d4de2 943 }
<> 154:37f96f9d4de2 944
<> 154:37f96f9d4de2 945 /**
<> 154:37f96f9d4de2 946 * @brief Enable external clock source (LSE bypass).
<> 154:37f96f9d4de2 947 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
<> 154:37f96f9d4de2 948 * @retval None
<> 154:37f96f9d4de2 949 */
<> 154:37f96f9d4de2 950 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
<> 154:37f96f9d4de2 951 {
<> 154:37f96f9d4de2 952 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<> 154:37f96f9d4de2 953 }
<> 154:37f96f9d4de2 954
<> 154:37f96f9d4de2 955 /**
<> 154:37f96f9d4de2 956 * @brief Disable external clock source (LSE bypass).
<> 154:37f96f9d4de2 957 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
<> 154:37f96f9d4de2 958 * @retval None
<> 154:37f96f9d4de2 959 */
<> 154:37f96f9d4de2 960 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
<> 154:37f96f9d4de2 961 {
<> 154:37f96f9d4de2 962 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<> 154:37f96f9d4de2 963 }
<> 154:37f96f9d4de2 964
<> 154:37f96f9d4de2 965 /**
<> 154:37f96f9d4de2 966 * @brief Check if LSE oscillator Ready
<> 154:37f96f9d4de2 967 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
<> 154:37f96f9d4de2 968 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 969 */
<> 154:37f96f9d4de2 970 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
<> 154:37f96f9d4de2 971 {
<> 154:37f96f9d4de2 972 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
<> 154:37f96f9d4de2 973 }
<> 154:37f96f9d4de2 974
<> 154:37f96f9d4de2 975 /**
<> 154:37f96f9d4de2 976 * @}
<> 154:37f96f9d4de2 977 */
<> 154:37f96f9d4de2 978
<> 154:37f96f9d4de2 979 /** @defgroup RCC_LL_EF_LSI LSI
<> 154:37f96f9d4de2 980 * @{
<> 154:37f96f9d4de2 981 */
<> 154:37f96f9d4de2 982
<> 154:37f96f9d4de2 983 /**
<> 154:37f96f9d4de2 984 * @brief Enable LSI Oscillator
<> 154:37f96f9d4de2 985 * @rmtoll CSR LSION LL_RCC_LSI_Enable
<> 154:37f96f9d4de2 986 * @retval None
<> 154:37f96f9d4de2 987 */
<> 154:37f96f9d4de2 988 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
<> 154:37f96f9d4de2 989 {
<> 154:37f96f9d4de2 990 SET_BIT(RCC->CSR, RCC_CSR_LSION);
<> 154:37f96f9d4de2 991 }
<> 154:37f96f9d4de2 992
<> 154:37f96f9d4de2 993 /**
<> 154:37f96f9d4de2 994 * @brief Disable LSI Oscillator
<> 154:37f96f9d4de2 995 * @rmtoll CSR LSION LL_RCC_LSI_Disable
<> 154:37f96f9d4de2 996 * @retval None
<> 154:37f96f9d4de2 997 */
<> 154:37f96f9d4de2 998 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
<> 154:37f96f9d4de2 999 {
<> 154:37f96f9d4de2 1000 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
<> 154:37f96f9d4de2 1001 }
<> 154:37f96f9d4de2 1002
<> 154:37f96f9d4de2 1003 /**
<> 154:37f96f9d4de2 1004 * @brief Check if LSI is Ready
<> 154:37f96f9d4de2 1005 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
<> 154:37f96f9d4de2 1006 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1007 */
<> 154:37f96f9d4de2 1008 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
<> 154:37f96f9d4de2 1009 {
<> 154:37f96f9d4de2 1010 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
<> 154:37f96f9d4de2 1011 }
<> 154:37f96f9d4de2 1012
<> 154:37f96f9d4de2 1013 /**
<> 154:37f96f9d4de2 1014 * @}
<> 154:37f96f9d4de2 1015 */
<> 154:37f96f9d4de2 1016
<> 154:37f96f9d4de2 1017 /** @defgroup RCC_LL_EF_System System
<> 154:37f96f9d4de2 1018 * @{
<> 154:37f96f9d4de2 1019 */
<> 154:37f96f9d4de2 1020
<> 154:37f96f9d4de2 1021 /**
<> 154:37f96f9d4de2 1022 * @brief Configure the system clock source
<> 154:37f96f9d4de2 1023 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
<> 154:37f96f9d4de2 1024 * @param Source This parameter can be one of the following values:
<> 154:37f96f9d4de2 1025 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
<> 154:37f96f9d4de2 1026 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
<> 154:37f96f9d4de2 1027 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
<> 154:37f96f9d4de2 1028 * @retval None
<> 154:37f96f9d4de2 1029 */
<> 154:37f96f9d4de2 1030 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
<> 154:37f96f9d4de2 1031 {
<> 154:37f96f9d4de2 1032 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
<> 154:37f96f9d4de2 1033 }
<> 154:37f96f9d4de2 1034
<> 154:37f96f9d4de2 1035 /**
<> 154:37f96f9d4de2 1036 * @brief Get the system clock source
<> 154:37f96f9d4de2 1037 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
<> 154:37f96f9d4de2 1038 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1039 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
<> 154:37f96f9d4de2 1040 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
<> 154:37f96f9d4de2 1041 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
<> 154:37f96f9d4de2 1042 */
<> 154:37f96f9d4de2 1043 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
<> 154:37f96f9d4de2 1044 {
<> 154:37f96f9d4de2 1045 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
<> 154:37f96f9d4de2 1046 }
<> 154:37f96f9d4de2 1047
<> 154:37f96f9d4de2 1048 /**
<> 154:37f96f9d4de2 1049 * @brief Set AHB prescaler
<> 154:37f96f9d4de2 1050 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
<> 154:37f96f9d4de2 1051 * @param Prescaler This parameter can be one of the following values:
<> 154:37f96f9d4de2 1052 * @arg @ref LL_RCC_SYSCLK_DIV_1
<> 154:37f96f9d4de2 1053 * @arg @ref LL_RCC_SYSCLK_DIV_2
<> 154:37f96f9d4de2 1054 * @arg @ref LL_RCC_SYSCLK_DIV_4
<> 154:37f96f9d4de2 1055 * @arg @ref LL_RCC_SYSCLK_DIV_8
<> 154:37f96f9d4de2 1056 * @arg @ref LL_RCC_SYSCLK_DIV_16
<> 154:37f96f9d4de2 1057 * @arg @ref LL_RCC_SYSCLK_DIV_64
<> 154:37f96f9d4de2 1058 * @arg @ref LL_RCC_SYSCLK_DIV_128
<> 154:37f96f9d4de2 1059 * @arg @ref LL_RCC_SYSCLK_DIV_256
<> 154:37f96f9d4de2 1060 * @arg @ref LL_RCC_SYSCLK_DIV_512
<> 154:37f96f9d4de2 1061 * @retval None
<> 154:37f96f9d4de2 1062 */
<> 154:37f96f9d4de2 1063 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
<> 154:37f96f9d4de2 1064 {
<> 154:37f96f9d4de2 1065 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
<> 154:37f96f9d4de2 1066 }
<> 154:37f96f9d4de2 1067
<> 154:37f96f9d4de2 1068 /**
<> 154:37f96f9d4de2 1069 * @brief Set APB1 prescaler
<> 154:37f96f9d4de2 1070 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
<> 154:37f96f9d4de2 1071 * @param Prescaler This parameter can be one of the following values:
<> 154:37f96f9d4de2 1072 * @arg @ref LL_RCC_APB1_DIV_1
<> 154:37f96f9d4de2 1073 * @arg @ref LL_RCC_APB1_DIV_2
<> 154:37f96f9d4de2 1074 * @arg @ref LL_RCC_APB1_DIV_4
<> 154:37f96f9d4de2 1075 * @arg @ref LL_RCC_APB1_DIV_8
<> 154:37f96f9d4de2 1076 * @arg @ref LL_RCC_APB1_DIV_16
<> 154:37f96f9d4de2 1077 * @retval None
<> 154:37f96f9d4de2 1078 */
<> 154:37f96f9d4de2 1079 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
<> 154:37f96f9d4de2 1080 {
<> 154:37f96f9d4de2 1081 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
<> 154:37f96f9d4de2 1082 }
<> 154:37f96f9d4de2 1083
<> 154:37f96f9d4de2 1084 /**
<> 154:37f96f9d4de2 1085 * @brief Set APB2 prescaler
<> 154:37f96f9d4de2 1086 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
<> 154:37f96f9d4de2 1087 * @param Prescaler This parameter can be one of the following values:
<> 154:37f96f9d4de2 1088 * @arg @ref LL_RCC_APB2_DIV_1
<> 154:37f96f9d4de2 1089 * @arg @ref LL_RCC_APB2_DIV_2
<> 154:37f96f9d4de2 1090 * @arg @ref LL_RCC_APB2_DIV_4
<> 154:37f96f9d4de2 1091 * @arg @ref LL_RCC_APB2_DIV_8
<> 154:37f96f9d4de2 1092 * @arg @ref LL_RCC_APB2_DIV_16
<> 154:37f96f9d4de2 1093 * @retval None
<> 154:37f96f9d4de2 1094 */
<> 154:37f96f9d4de2 1095 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
<> 154:37f96f9d4de2 1096 {
<> 154:37f96f9d4de2 1097 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
<> 154:37f96f9d4de2 1098 }
<> 154:37f96f9d4de2 1099
<> 154:37f96f9d4de2 1100 /**
<> 154:37f96f9d4de2 1101 * @brief Get AHB prescaler
<> 154:37f96f9d4de2 1102 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
<> 154:37f96f9d4de2 1103 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1104 * @arg @ref LL_RCC_SYSCLK_DIV_1
<> 154:37f96f9d4de2 1105 * @arg @ref LL_RCC_SYSCLK_DIV_2
<> 154:37f96f9d4de2 1106 * @arg @ref LL_RCC_SYSCLK_DIV_4
<> 154:37f96f9d4de2 1107 * @arg @ref LL_RCC_SYSCLK_DIV_8
<> 154:37f96f9d4de2 1108 * @arg @ref LL_RCC_SYSCLK_DIV_16
<> 154:37f96f9d4de2 1109 * @arg @ref LL_RCC_SYSCLK_DIV_64
<> 154:37f96f9d4de2 1110 * @arg @ref LL_RCC_SYSCLK_DIV_128
<> 154:37f96f9d4de2 1111 * @arg @ref LL_RCC_SYSCLK_DIV_256
<> 154:37f96f9d4de2 1112 * @arg @ref LL_RCC_SYSCLK_DIV_512
<> 154:37f96f9d4de2 1113 */
<> 154:37f96f9d4de2 1114 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
<> 154:37f96f9d4de2 1115 {
<> 154:37f96f9d4de2 1116 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
<> 154:37f96f9d4de2 1117 }
<> 154:37f96f9d4de2 1118
<> 154:37f96f9d4de2 1119 /**
<> 154:37f96f9d4de2 1120 * @brief Get APB1 prescaler
<> 154:37f96f9d4de2 1121 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
<> 154:37f96f9d4de2 1122 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1123 * @arg @ref LL_RCC_APB1_DIV_1
<> 154:37f96f9d4de2 1124 * @arg @ref LL_RCC_APB1_DIV_2
<> 154:37f96f9d4de2 1125 * @arg @ref LL_RCC_APB1_DIV_4
<> 154:37f96f9d4de2 1126 * @arg @ref LL_RCC_APB1_DIV_8
<> 154:37f96f9d4de2 1127 * @arg @ref LL_RCC_APB1_DIV_16
<> 154:37f96f9d4de2 1128 */
<> 154:37f96f9d4de2 1129 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
<> 154:37f96f9d4de2 1130 {
<> 154:37f96f9d4de2 1131 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
<> 154:37f96f9d4de2 1132 }
<> 154:37f96f9d4de2 1133
<> 154:37f96f9d4de2 1134 /**
<> 154:37f96f9d4de2 1135 * @brief Get APB2 prescaler
<> 154:37f96f9d4de2 1136 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
<> 154:37f96f9d4de2 1137 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1138 * @arg @ref LL_RCC_APB2_DIV_1
<> 154:37f96f9d4de2 1139 * @arg @ref LL_RCC_APB2_DIV_2
<> 154:37f96f9d4de2 1140 * @arg @ref LL_RCC_APB2_DIV_4
<> 154:37f96f9d4de2 1141 * @arg @ref LL_RCC_APB2_DIV_8
<> 154:37f96f9d4de2 1142 * @arg @ref LL_RCC_APB2_DIV_16
<> 154:37f96f9d4de2 1143 */
<> 154:37f96f9d4de2 1144 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
<> 154:37f96f9d4de2 1145 {
<> 154:37f96f9d4de2 1146 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
<> 154:37f96f9d4de2 1147 }
<> 154:37f96f9d4de2 1148
<> 154:37f96f9d4de2 1149 /**
<> 154:37f96f9d4de2 1150 * @}
<> 154:37f96f9d4de2 1151 */
<> 154:37f96f9d4de2 1152
<> 154:37f96f9d4de2 1153 /** @defgroup RCC_LL_EF_MCO MCO
<> 154:37f96f9d4de2 1154 * @{
<> 154:37f96f9d4de2 1155 */
<> 154:37f96f9d4de2 1156
<> 154:37f96f9d4de2 1157 /**
<> 154:37f96f9d4de2 1158 * @brief Configure MCOx
<> 154:37f96f9d4de2 1159 * @rmtoll CFGR MCO LL_RCC_ConfigMCO
<> 154:37f96f9d4de2 1160 * @param MCOxSource This parameter can be one of the following values:
<> 154:37f96f9d4de2 1161 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
<> 154:37f96f9d4de2 1162 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
<> 154:37f96f9d4de2 1163 * @arg @ref LL_RCC_MCO1SOURCE_HSI
<> 154:37f96f9d4de2 1164 * @arg @ref LL_RCC_MCO1SOURCE_HSE
<> 154:37f96f9d4de2 1165 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
<> 154:37f96f9d4de2 1166 * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
<> 154:37f96f9d4de2 1167 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
<> 154:37f96f9d4de2 1168 * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
<> 154:37f96f9d4de2 1169 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
<> 154:37f96f9d4de2 1170 *
<> 154:37f96f9d4de2 1171 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1172 * @retval None
<> 154:37f96f9d4de2 1173 */
<> 154:37f96f9d4de2 1174 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
<> 154:37f96f9d4de2 1175 {
<> 154:37f96f9d4de2 1176 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
<> 154:37f96f9d4de2 1177 }
<> 154:37f96f9d4de2 1178
<> 154:37f96f9d4de2 1179 /**
<> 154:37f96f9d4de2 1180 * @}
<> 154:37f96f9d4de2 1181 */
<> 154:37f96f9d4de2 1182
<> 154:37f96f9d4de2 1183 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
<> 154:37f96f9d4de2 1184 * @{
<> 154:37f96f9d4de2 1185 */
<> 154:37f96f9d4de2 1186
<> 154:37f96f9d4de2 1187 #if defined(RCC_CFGR2_I2S2SRC)
<> 154:37f96f9d4de2 1188 /**
<> 154:37f96f9d4de2 1189 * @brief Configure I2Sx clock source
<> 154:37f96f9d4de2 1190 * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
<> 154:37f96f9d4de2 1191 * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
<> 154:37f96f9d4de2 1192 * @param I2SxSource This parameter can be one of the following values:
<> 154:37f96f9d4de2 1193 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
<> 154:37f96f9d4de2 1194 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
<> 154:37f96f9d4de2 1195 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
<> 154:37f96f9d4de2 1196 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
<> 154:37f96f9d4de2 1197 * @retval None
<> 154:37f96f9d4de2 1198 */
<> 154:37f96f9d4de2 1199 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
<> 154:37f96f9d4de2 1200 {
<> 154:37f96f9d4de2 1201 MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
<> 154:37f96f9d4de2 1202 }
<> 154:37f96f9d4de2 1203 #endif /* RCC_CFGR2_I2S2SRC */
<> 154:37f96f9d4de2 1204
<> 154:37f96f9d4de2 1205 #if defined(USB_OTG_FS) || defined(USB)
<> 154:37f96f9d4de2 1206 /**
<> 154:37f96f9d4de2 1207 * @brief Configure USB clock source
<> 154:37f96f9d4de2 1208 * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
<> 154:37f96f9d4de2 1209 * CFGR USBPRE LL_RCC_SetUSBClockSource
<> 154:37f96f9d4de2 1210 * @param USBxSource This parameter can be one of the following values:
<> 154:37f96f9d4de2 1211 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
<> 154:37f96f9d4de2 1212 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
<> 154:37f96f9d4de2 1213 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
<> 154:37f96f9d4de2 1214 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
<> 154:37f96f9d4de2 1215 *
<> 154:37f96f9d4de2 1216 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1217 * @retval None
<> 154:37f96f9d4de2 1218 */
<> 154:37f96f9d4de2 1219 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
<> 154:37f96f9d4de2 1220 {
<> 154:37f96f9d4de2 1221 #if defined(RCC_CFGR_USBPRE)
<> 154:37f96f9d4de2 1222 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
<> 154:37f96f9d4de2 1223 #else /*RCC_CFGR_OTGFSPRE*/
<> 154:37f96f9d4de2 1224 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
<> 154:37f96f9d4de2 1225 #endif /*RCC_CFGR_USBPRE*/
<> 154:37f96f9d4de2 1226 }
<> 154:37f96f9d4de2 1227 #endif /* USB_OTG_FS || USB */
<> 154:37f96f9d4de2 1228
<> 154:37f96f9d4de2 1229 /**
<> 154:37f96f9d4de2 1230 * @brief Configure ADC clock source
<> 154:37f96f9d4de2 1231 * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
<> 154:37f96f9d4de2 1232 * @param ADCxSource This parameter can be one of the following values:
<> 154:37f96f9d4de2 1233 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
<> 154:37f96f9d4de2 1234 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
<> 154:37f96f9d4de2 1235 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
<> 154:37f96f9d4de2 1236 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
<> 154:37f96f9d4de2 1237 * @retval None
<> 154:37f96f9d4de2 1238 */
<> 154:37f96f9d4de2 1239 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
<> 154:37f96f9d4de2 1240 {
<> 154:37f96f9d4de2 1241 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
<> 154:37f96f9d4de2 1242 }
<> 154:37f96f9d4de2 1243
<> 154:37f96f9d4de2 1244 #if defined(RCC_CFGR2_I2S2SRC)
<> 154:37f96f9d4de2 1245 /**
<> 154:37f96f9d4de2 1246 * @brief Get I2Sx clock source
<> 154:37f96f9d4de2 1247 * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
<> 154:37f96f9d4de2 1248 * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
<> 154:37f96f9d4de2 1249 * @param I2Sx This parameter can be one of the following values:
<> 154:37f96f9d4de2 1250 * @arg @ref LL_RCC_I2S2_CLKSOURCE
<> 154:37f96f9d4de2 1251 * @arg @ref LL_RCC_I2S3_CLKSOURCE
<> 154:37f96f9d4de2 1252 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1253 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
<> 154:37f96f9d4de2 1254 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
<> 154:37f96f9d4de2 1255 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
<> 154:37f96f9d4de2 1256 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
<> 154:37f96f9d4de2 1257 */
<> 154:37f96f9d4de2 1258 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
<> 154:37f96f9d4de2 1259 {
AnnaBridge 165:e614a9f1c9e2 1260 return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
<> 154:37f96f9d4de2 1261 }
<> 154:37f96f9d4de2 1262 #endif /* RCC_CFGR2_I2S2SRC */
<> 154:37f96f9d4de2 1263
<> 154:37f96f9d4de2 1264 #if defined(USB_OTG_FS) || defined(USB)
<> 154:37f96f9d4de2 1265 /**
<> 154:37f96f9d4de2 1266 * @brief Get USBx clock source
<> 154:37f96f9d4de2 1267 * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
<> 154:37f96f9d4de2 1268 * CFGR USBPRE LL_RCC_GetUSBClockSource
<> 154:37f96f9d4de2 1269 * @param USBx This parameter can be one of the following values:
<> 154:37f96f9d4de2 1270 * @arg @ref LL_RCC_USB_CLKSOURCE
<> 154:37f96f9d4de2 1271 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1272 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
<> 154:37f96f9d4de2 1273 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
<> 154:37f96f9d4de2 1274 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
<> 154:37f96f9d4de2 1275 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
<> 154:37f96f9d4de2 1276 *
<> 154:37f96f9d4de2 1277 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1278 */
<> 154:37f96f9d4de2 1279 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
<> 154:37f96f9d4de2 1280 {
<> 154:37f96f9d4de2 1281 return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
<> 154:37f96f9d4de2 1282 }
<> 154:37f96f9d4de2 1283 #endif /* USB_OTG_FS || USB */
<> 154:37f96f9d4de2 1284
<> 154:37f96f9d4de2 1285 /**
<> 154:37f96f9d4de2 1286 * @brief Get ADCx clock source
<> 154:37f96f9d4de2 1287 * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
<> 154:37f96f9d4de2 1288 * @param ADCx This parameter can be one of the following values:
<> 154:37f96f9d4de2 1289 * @arg @ref LL_RCC_ADC_CLKSOURCE
<> 154:37f96f9d4de2 1290 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1291 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
<> 154:37f96f9d4de2 1292 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
<> 154:37f96f9d4de2 1293 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
<> 154:37f96f9d4de2 1294 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
<> 154:37f96f9d4de2 1295 */
<> 154:37f96f9d4de2 1296 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
<> 154:37f96f9d4de2 1297 {
<> 154:37f96f9d4de2 1298 return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
<> 154:37f96f9d4de2 1299 }
<> 154:37f96f9d4de2 1300
<> 154:37f96f9d4de2 1301 /**
<> 154:37f96f9d4de2 1302 * @}
<> 154:37f96f9d4de2 1303 */
<> 154:37f96f9d4de2 1304
<> 154:37f96f9d4de2 1305 /** @defgroup RCC_LL_EF_RTC RTC
<> 154:37f96f9d4de2 1306 * @{
<> 154:37f96f9d4de2 1307 */
<> 154:37f96f9d4de2 1308
<> 154:37f96f9d4de2 1309 /**
<> 154:37f96f9d4de2 1310 * @brief Set RTC Clock Source
<> 154:37f96f9d4de2 1311 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
<> 154:37f96f9d4de2 1312 * the Backup domain is reset. The BDRST bit can be used to reset them.
<> 154:37f96f9d4de2 1313 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
<> 154:37f96f9d4de2 1314 * @param Source This parameter can be one of the following values:
<> 154:37f96f9d4de2 1315 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<> 154:37f96f9d4de2 1316 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<> 154:37f96f9d4de2 1317 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<> 154:37f96f9d4de2 1318 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
<> 154:37f96f9d4de2 1319 * @retval None
<> 154:37f96f9d4de2 1320 */
<> 154:37f96f9d4de2 1321 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
<> 154:37f96f9d4de2 1322 {
<> 154:37f96f9d4de2 1323 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
<> 154:37f96f9d4de2 1324 }
<> 154:37f96f9d4de2 1325
<> 154:37f96f9d4de2 1326 /**
<> 154:37f96f9d4de2 1327 * @brief Get RTC Clock Source
<> 154:37f96f9d4de2 1328 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
<> 154:37f96f9d4de2 1329 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1330 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<> 154:37f96f9d4de2 1331 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<> 154:37f96f9d4de2 1332 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<> 154:37f96f9d4de2 1333 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
<> 154:37f96f9d4de2 1334 */
<> 154:37f96f9d4de2 1335 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
<> 154:37f96f9d4de2 1336 {
<> 154:37f96f9d4de2 1337 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
<> 154:37f96f9d4de2 1338 }
<> 154:37f96f9d4de2 1339
<> 154:37f96f9d4de2 1340 /**
<> 154:37f96f9d4de2 1341 * @brief Enable RTC
<> 154:37f96f9d4de2 1342 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
<> 154:37f96f9d4de2 1343 * @retval None
<> 154:37f96f9d4de2 1344 */
<> 154:37f96f9d4de2 1345 __STATIC_INLINE void LL_RCC_EnableRTC(void)
<> 154:37f96f9d4de2 1346 {
<> 154:37f96f9d4de2 1347 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<> 154:37f96f9d4de2 1348 }
<> 154:37f96f9d4de2 1349
<> 154:37f96f9d4de2 1350 /**
<> 154:37f96f9d4de2 1351 * @brief Disable RTC
<> 154:37f96f9d4de2 1352 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
<> 154:37f96f9d4de2 1353 * @retval None
<> 154:37f96f9d4de2 1354 */
<> 154:37f96f9d4de2 1355 __STATIC_INLINE void LL_RCC_DisableRTC(void)
<> 154:37f96f9d4de2 1356 {
<> 154:37f96f9d4de2 1357 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<> 154:37f96f9d4de2 1358 }
<> 154:37f96f9d4de2 1359
<> 154:37f96f9d4de2 1360 /**
<> 154:37f96f9d4de2 1361 * @brief Check if RTC has been enabled or not
<> 154:37f96f9d4de2 1362 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
<> 154:37f96f9d4de2 1363 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1364 */
<> 154:37f96f9d4de2 1365 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
<> 154:37f96f9d4de2 1366 {
<> 154:37f96f9d4de2 1367 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
<> 154:37f96f9d4de2 1368 }
<> 154:37f96f9d4de2 1369
<> 154:37f96f9d4de2 1370 /**
<> 154:37f96f9d4de2 1371 * @brief Force the Backup domain reset
<> 154:37f96f9d4de2 1372 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
<> 154:37f96f9d4de2 1373 * @retval None
<> 154:37f96f9d4de2 1374 */
<> 154:37f96f9d4de2 1375 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
<> 154:37f96f9d4de2 1376 {
<> 154:37f96f9d4de2 1377 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<> 154:37f96f9d4de2 1378 }
<> 154:37f96f9d4de2 1379
<> 154:37f96f9d4de2 1380 /**
<> 154:37f96f9d4de2 1381 * @brief Release the Backup domain reset
<> 154:37f96f9d4de2 1382 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
<> 154:37f96f9d4de2 1383 * @retval None
<> 154:37f96f9d4de2 1384 */
<> 154:37f96f9d4de2 1385 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
<> 154:37f96f9d4de2 1386 {
<> 154:37f96f9d4de2 1387 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<> 154:37f96f9d4de2 1388 }
<> 154:37f96f9d4de2 1389
<> 154:37f96f9d4de2 1390 /**
<> 154:37f96f9d4de2 1391 * @}
<> 154:37f96f9d4de2 1392 */
<> 154:37f96f9d4de2 1393
<> 154:37f96f9d4de2 1394 /** @defgroup RCC_LL_EF_PLL PLL
<> 154:37f96f9d4de2 1395 * @{
<> 154:37f96f9d4de2 1396 */
<> 154:37f96f9d4de2 1397
<> 154:37f96f9d4de2 1398 /**
<> 154:37f96f9d4de2 1399 * @brief Enable PLL
<> 154:37f96f9d4de2 1400 * @rmtoll CR PLLON LL_RCC_PLL_Enable
<> 154:37f96f9d4de2 1401 * @retval None
<> 154:37f96f9d4de2 1402 */
<> 154:37f96f9d4de2 1403 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
<> 154:37f96f9d4de2 1404 {
<> 154:37f96f9d4de2 1405 SET_BIT(RCC->CR, RCC_CR_PLLON);
<> 154:37f96f9d4de2 1406 }
<> 154:37f96f9d4de2 1407
<> 154:37f96f9d4de2 1408 /**
<> 154:37f96f9d4de2 1409 * @brief Disable PLL
<> 154:37f96f9d4de2 1410 * @note Cannot be disabled if the PLL clock is used as the system clock
<> 154:37f96f9d4de2 1411 * @rmtoll CR PLLON LL_RCC_PLL_Disable
<> 154:37f96f9d4de2 1412 * @retval None
<> 154:37f96f9d4de2 1413 */
<> 154:37f96f9d4de2 1414 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
<> 154:37f96f9d4de2 1415 {
<> 154:37f96f9d4de2 1416 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<> 154:37f96f9d4de2 1417 }
<> 154:37f96f9d4de2 1418
<> 154:37f96f9d4de2 1419 /**
<> 154:37f96f9d4de2 1420 * @brief Check if PLL Ready
<> 154:37f96f9d4de2 1421 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
<> 154:37f96f9d4de2 1422 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1423 */
<> 154:37f96f9d4de2 1424 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
<> 154:37f96f9d4de2 1425 {
<> 154:37f96f9d4de2 1426 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
<> 154:37f96f9d4de2 1427 }
<> 154:37f96f9d4de2 1428
<> 154:37f96f9d4de2 1429 /**
<> 154:37f96f9d4de2 1430 * @brief Configure PLL used for SYSCLK Domain
<> 154:37f96f9d4de2 1431 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<> 154:37f96f9d4de2 1432 * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
<> 154:37f96f9d4de2 1433 * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
<> 154:37f96f9d4de2 1434 * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
<> 154:37f96f9d4de2 1435 * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
<> 154:37f96f9d4de2 1436 * @param Source This parameter can be one of the following values:
<> 154:37f96f9d4de2 1437 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
<> 154:37f96f9d4de2 1438 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
<> 154:37f96f9d4de2 1439 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
<> 154:37f96f9d4de2 1440 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
<> 154:37f96f9d4de2 1441 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
<> 154:37f96f9d4de2 1442 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
<> 154:37f96f9d4de2 1443 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
<> 154:37f96f9d4de2 1444 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
<> 154:37f96f9d4de2 1445 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
<> 154:37f96f9d4de2 1446 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
<> 154:37f96f9d4de2 1447 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
<> 154:37f96f9d4de2 1448 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
<> 154:37f96f9d4de2 1449 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
<> 154:37f96f9d4de2 1450 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
<> 154:37f96f9d4de2 1451 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
<> 154:37f96f9d4de2 1452 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
<> 154:37f96f9d4de2 1453 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
AnnaBridge 187:0387e8f68319 1454 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*)
<> 154:37f96f9d4de2 1455 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
<> 154:37f96f9d4de2 1456 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
<> 154:37f96f9d4de2 1457 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
<> 154:37f96f9d4de2 1458 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
<> 154:37f96f9d4de2 1459 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
<> 154:37f96f9d4de2 1460 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
<> 154:37f96f9d4de2 1461 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
<> 154:37f96f9d4de2 1462 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
<> 154:37f96f9d4de2 1463 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
<> 154:37f96f9d4de2 1464 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
<> 154:37f96f9d4de2 1465 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
<> 154:37f96f9d4de2 1466 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
<> 154:37f96f9d4de2 1467 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
<> 154:37f96f9d4de2 1468 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
<> 154:37f96f9d4de2 1469 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
<> 154:37f96f9d4de2 1470 *
<> 154:37f96f9d4de2 1471 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1472 * @param PLLMul This parameter can be one of the following values:
<> 154:37f96f9d4de2 1473 * @arg @ref LL_RCC_PLL_MUL_2 (*)
<> 154:37f96f9d4de2 1474 * @arg @ref LL_RCC_PLL_MUL_3 (*)
<> 154:37f96f9d4de2 1475 * @arg @ref LL_RCC_PLL_MUL_4
<> 154:37f96f9d4de2 1476 * @arg @ref LL_RCC_PLL_MUL_5
<> 154:37f96f9d4de2 1477 * @arg @ref LL_RCC_PLL_MUL_6
<> 154:37f96f9d4de2 1478 * @arg @ref LL_RCC_PLL_MUL_7
<> 154:37f96f9d4de2 1479 * @arg @ref LL_RCC_PLL_MUL_8
<> 154:37f96f9d4de2 1480 * @arg @ref LL_RCC_PLL_MUL_9
<> 154:37f96f9d4de2 1481 * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
<> 154:37f96f9d4de2 1482 * @arg @ref LL_RCC_PLL_MUL_10 (*)
<> 154:37f96f9d4de2 1483 * @arg @ref LL_RCC_PLL_MUL_11 (*)
<> 154:37f96f9d4de2 1484 * @arg @ref LL_RCC_PLL_MUL_12 (*)
<> 154:37f96f9d4de2 1485 * @arg @ref LL_RCC_PLL_MUL_13 (*)
<> 154:37f96f9d4de2 1486 * @arg @ref LL_RCC_PLL_MUL_14 (*)
<> 154:37f96f9d4de2 1487 * @arg @ref LL_RCC_PLL_MUL_15 (*)
<> 154:37f96f9d4de2 1488 * @arg @ref LL_RCC_PLL_MUL_16 (*)
<> 154:37f96f9d4de2 1489 *
<> 154:37f96f9d4de2 1490 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1491 * @retval None
<> 154:37f96f9d4de2 1492 */
<> 154:37f96f9d4de2 1493 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
<> 154:37f96f9d4de2 1494 {
<> 154:37f96f9d4de2 1495 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
<> 154:37f96f9d4de2 1496 (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul);
AnnaBridge 165:e614a9f1c9e2 1497 #if defined(RCC_CFGR2_PREDIV1)
AnnaBridge 165:e614a9f1c9e2 1498 #if defined(RCC_CFGR2_PREDIV1SRC)
<> 154:37f96f9d4de2 1499 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC),
AnnaBridge 165:e614a9f1c9e2 1500 (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
<> 154:37f96f9d4de2 1501 #else
<> 154:37f96f9d4de2 1502 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
AnnaBridge 165:e614a9f1c9e2 1503 #endif /*RCC_CFGR2_PREDIV1SRC*/
AnnaBridge 165:e614a9f1c9e2 1504 #endif /*RCC_CFGR2_PREDIV1*/
<> 154:37f96f9d4de2 1505 }
<> 154:37f96f9d4de2 1506
<> 154:37f96f9d4de2 1507 /**
AnnaBridge 187:0387e8f68319 1508 * @brief Configure PLL clock source
AnnaBridge 187:0387e8f68319 1509 * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n
AnnaBridge 187:0387e8f68319 1510 * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource
AnnaBridge 187:0387e8f68319 1511 * @param PLLSource This parameter can be one of the following values:
AnnaBridge 187:0387e8f68319 1512 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
AnnaBridge 187:0387e8f68319 1513 * @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge 187:0387e8f68319 1514 * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
AnnaBridge 187:0387e8f68319 1515 * @retval None
AnnaBridge 187:0387e8f68319 1516 */
AnnaBridge 187:0387e8f68319 1517 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
AnnaBridge 187:0387e8f68319 1518 {
AnnaBridge 187:0387e8f68319 1519 #if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge 187:0387e8f68319 1520 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
AnnaBridge 187:0387e8f68319 1521 #endif /* RCC_CFGR2_PREDIV1SRC */
AnnaBridge 187:0387e8f68319 1522 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
AnnaBridge 187:0387e8f68319 1523 }
AnnaBridge 187:0387e8f68319 1524
AnnaBridge 187:0387e8f68319 1525 /**
<> 154:37f96f9d4de2 1526 * @brief Get the oscillator used as PLL clock source.
<> 154:37f96f9d4de2 1527 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
<> 154:37f96f9d4de2 1528 * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
<> 154:37f96f9d4de2 1529 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1530 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
<> 154:37f96f9d4de2 1531 * @arg @ref LL_RCC_PLLSOURCE_HSE
<> 154:37f96f9d4de2 1532 * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
<> 154:37f96f9d4de2 1533 *
<> 154:37f96f9d4de2 1534 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1535 */
<> 154:37f96f9d4de2 1536 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
<> 154:37f96f9d4de2 1537 {
AnnaBridge 165:e614a9f1c9e2 1538 #if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge 165:e614a9f1c9e2 1539 register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
AnnaBridge 165:e614a9f1c9e2 1540 register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
AnnaBridge 165:e614a9f1c9e2 1541 return (uint32_t)(pllsrc | predivsrc);
<> 154:37f96f9d4de2 1542 #else
<> 154:37f96f9d4de2 1543 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
AnnaBridge 165:e614a9f1c9e2 1544 #endif /*RCC_CFGR2_PREDIV1SRC*/
<> 154:37f96f9d4de2 1545 }
<> 154:37f96f9d4de2 1546
<> 154:37f96f9d4de2 1547 /**
<> 154:37f96f9d4de2 1548 * @brief Get PLL multiplication Factor
<> 154:37f96f9d4de2 1549 * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
<> 154:37f96f9d4de2 1550 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1551 * @arg @ref LL_RCC_PLL_MUL_2 (*)
<> 154:37f96f9d4de2 1552 * @arg @ref LL_RCC_PLL_MUL_3 (*)
<> 154:37f96f9d4de2 1553 * @arg @ref LL_RCC_PLL_MUL_4
<> 154:37f96f9d4de2 1554 * @arg @ref LL_RCC_PLL_MUL_5
<> 154:37f96f9d4de2 1555 * @arg @ref LL_RCC_PLL_MUL_6
<> 154:37f96f9d4de2 1556 * @arg @ref LL_RCC_PLL_MUL_7
<> 154:37f96f9d4de2 1557 * @arg @ref LL_RCC_PLL_MUL_8
<> 154:37f96f9d4de2 1558 * @arg @ref LL_RCC_PLL_MUL_9
<> 154:37f96f9d4de2 1559 * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
<> 154:37f96f9d4de2 1560 * @arg @ref LL_RCC_PLL_MUL_10 (*)
<> 154:37f96f9d4de2 1561 * @arg @ref LL_RCC_PLL_MUL_11 (*)
<> 154:37f96f9d4de2 1562 * @arg @ref LL_RCC_PLL_MUL_12 (*)
<> 154:37f96f9d4de2 1563 * @arg @ref LL_RCC_PLL_MUL_13 (*)
<> 154:37f96f9d4de2 1564 * @arg @ref LL_RCC_PLL_MUL_14 (*)
<> 154:37f96f9d4de2 1565 * @arg @ref LL_RCC_PLL_MUL_15 (*)
<> 154:37f96f9d4de2 1566 * @arg @ref LL_RCC_PLL_MUL_16 (*)
<> 154:37f96f9d4de2 1567 *
<> 154:37f96f9d4de2 1568 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1569 */
<> 154:37f96f9d4de2 1570 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
<> 154:37f96f9d4de2 1571 {
<> 154:37f96f9d4de2 1572 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
<> 154:37f96f9d4de2 1573 }
<> 154:37f96f9d4de2 1574
<> 154:37f96f9d4de2 1575 /**
<> 154:37f96f9d4de2 1576 * @brief Get PREDIV1 division factor for the main PLL
<> 154:37f96f9d4de2 1577 * @note They can be written only when the PLL is disabled
<> 154:37f96f9d4de2 1578 * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
<> 154:37f96f9d4de2 1579 * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
<> 154:37f96f9d4de2 1580 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1581 * @arg @ref LL_RCC_PREDIV_DIV_1
<> 154:37f96f9d4de2 1582 * @arg @ref LL_RCC_PREDIV_DIV_2
<> 154:37f96f9d4de2 1583 * @arg @ref LL_RCC_PREDIV_DIV_3 (*)
<> 154:37f96f9d4de2 1584 * @arg @ref LL_RCC_PREDIV_DIV_4 (*)
<> 154:37f96f9d4de2 1585 * @arg @ref LL_RCC_PREDIV_DIV_5 (*)
<> 154:37f96f9d4de2 1586 * @arg @ref LL_RCC_PREDIV_DIV_6 (*)
<> 154:37f96f9d4de2 1587 * @arg @ref LL_RCC_PREDIV_DIV_7 (*)
<> 154:37f96f9d4de2 1588 * @arg @ref LL_RCC_PREDIV_DIV_8 (*)
<> 154:37f96f9d4de2 1589 * @arg @ref LL_RCC_PREDIV_DIV_9 (*)
<> 154:37f96f9d4de2 1590 * @arg @ref LL_RCC_PREDIV_DIV_10 (*)
<> 154:37f96f9d4de2 1591 * @arg @ref LL_RCC_PREDIV_DIV_11 (*)
<> 154:37f96f9d4de2 1592 * @arg @ref LL_RCC_PREDIV_DIV_12 (*)
<> 154:37f96f9d4de2 1593 * @arg @ref LL_RCC_PREDIV_DIV_13 (*)
<> 154:37f96f9d4de2 1594 * @arg @ref LL_RCC_PREDIV_DIV_14 (*)
<> 154:37f96f9d4de2 1595 * @arg @ref LL_RCC_PREDIV_DIV_15 (*)
<> 154:37f96f9d4de2 1596 * @arg @ref LL_RCC_PREDIV_DIV_16 (*)
<> 154:37f96f9d4de2 1597 *
<> 154:37f96f9d4de2 1598 * (*) value not defined in all devices
<> 154:37f96f9d4de2 1599 */
<> 154:37f96f9d4de2 1600 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
<> 154:37f96f9d4de2 1601 {
AnnaBridge 165:e614a9f1c9e2 1602 #if defined(RCC_CFGR2_PREDIV1)
<> 154:37f96f9d4de2 1603 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
<> 154:37f96f9d4de2 1604 #else
<> 154:37f96f9d4de2 1605 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
AnnaBridge 165:e614a9f1c9e2 1606 #endif /*RCC_CFGR2_PREDIV1*/
<> 154:37f96f9d4de2 1607 }
<> 154:37f96f9d4de2 1608
<> 154:37f96f9d4de2 1609 /**
<> 154:37f96f9d4de2 1610 * @}
<> 154:37f96f9d4de2 1611 */
<> 154:37f96f9d4de2 1612
<> 154:37f96f9d4de2 1613 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 1614 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
<> 154:37f96f9d4de2 1615 * @{
<> 154:37f96f9d4de2 1616 */
<> 154:37f96f9d4de2 1617
<> 154:37f96f9d4de2 1618 /**
<> 154:37f96f9d4de2 1619 * @brief Enable PLLI2S
<> 154:37f96f9d4de2 1620 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
<> 154:37f96f9d4de2 1621 * @retval None
<> 154:37f96f9d4de2 1622 */
<> 154:37f96f9d4de2 1623 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
<> 154:37f96f9d4de2 1624 {
<> 154:37f96f9d4de2 1625 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
<> 154:37f96f9d4de2 1626 }
<> 154:37f96f9d4de2 1627
<> 154:37f96f9d4de2 1628 /**
<> 154:37f96f9d4de2 1629 * @brief Disable PLLI2S
<> 154:37f96f9d4de2 1630 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
<> 154:37f96f9d4de2 1631 * @retval None
<> 154:37f96f9d4de2 1632 */
<> 154:37f96f9d4de2 1633 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
<> 154:37f96f9d4de2 1634 {
<> 154:37f96f9d4de2 1635 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
<> 154:37f96f9d4de2 1636 }
<> 154:37f96f9d4de2 1637
<> 154:37f96f9d4de2 1638 /**
<> 154:37f96f9d4de2 1639 * @brief Check if PLLI2S Ready
<> 154:37f96f9d4de2 1640 * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
<> 154:37f96f9d4de2 1641 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1642 */
<> 154:37f96f9d4de2 1643 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
<> 154:37f96f9d4de2 1644 {
<> 154:37f96f9d4de2 1645 return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
<> 154:37f96f9d4de2 1646 }
<> 154:37f96f9d4de2 1647
<> 154:37f96f9d4de2 1648 /**
<> 154:37f96f9d4de2 1649 * @brief Configure PLLI2S used for I2S Domain
<> 154:37f96f9d4de2 1650 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
<> 154:37f96f9d4de2 1651 * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
<> 154:37f96f9d4de2 1652 * @param Divider This parameter can be one of the following values:
<> 154:37f96f9d4de2 1653 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<> 154:37f96f9d4de2 1654 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<> 154:37f96f9d4de2 1655 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<> 154:37f96f9d4de2 1656 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<> 154:37f96f9d4de2 1657 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<> 154:37f96f9d4de2 1658 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<> 154:37f96f9d4de2 1659 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<> 154:37f96f9d4de2 1660 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<> 154:37f96f9d4de2 1661 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<> 154:37f96f9d4de2 1662 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<> 154:37f96f9d4de2 1663 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<> 154:37f96f9d4de2 1664 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<> 154:37f96f9d4de2 1665 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<> 154:37f96f9d4de2 1666 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<> 154:37f96f9d4de2 1667 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<> 154:37f96f9d4de2 1668 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<> 154:37f96f9d4de2 1669 * @param Multiplicator This parameter can be one of the following values:
<> 154:37f96f9d4de2 1670 * @arg @ref LL_RCC_PLLI2S_MUL_8
<> 154:37f96f9d4de2 1671 * @arg @ref LL_RCC_PLLI2S_MUL_9
<> 154:37f96f9d4de2 1672 * @arg @ref LL_RCC_PLLI2S_MUL_10
<> 154:37f96f9d4de2 1673 * @arg @ref LL_RCC_PLLI2S_MUL_11
<> 154:37f96f9d4de2 1674 * @arg @ref LL_RCC_PLLI2S_MUL_12
<> 154:37f96f9d4de2 1675 * @arg @ref LL_RCC_PLLI2S_MUL_13
<> 154:37f96f9d4de2 1676 * @arg @ref LL_RCC_PLLI2S_MUL_14
<> 154:37f96f9d4de2 1677 * @arg @ref LL_RCC_PLLI2S_MUL_16
<> 154:37f96f9d4de2 1678 * @arg @ref LL_RCC_PLLI2S_MUL_20
<> 154:37f96f9d4de2 1679 * @retval None
<> 154:37f96f9d4de2 1680 */
<> 154:37f96f9d4de2 1681 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
<> 154:37f96f9d4de2 1682 {
<> 154:37f96f9d4de2 1683 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator);
<> 154:37f96f9d4de2 1684 }
<> 154:37f96f9d4de2 1685
<> 154:37f96f9d4de2 1686 /**
<> 154:37f96f9d4de2 1687 * @brief Get PLLI2S Multiplication Factor
<> 154:37f96f9d4de2 1688 * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
<> 154:37f96f9d4de2 1689 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1690 * @arg @ref LL_RCC_PLLI2S_MUL_8
<> 154:37f96f9d4de2 1691 * @arg @ref LL_RCC_PLLI2S_MUL_9
<> 154:37f96f9d4de2 1692 * @arg @ref LL_RCC_PLLI2S_MUL_10
<> 154:37f96f9d4de2 1693 * @arg @ref LL_RCC_PLLI2S_MUL_11
<> 154:37f96f9d4de2 1694 * @arg @ref LL_RCC_PLLI2S_MUL_12
<> 154:37f96f9d4de2 1695 * @arg @ref LL_RCC_PLLI2S_MUL_13
<> 154:37f96f9d4de2 1696 * @arg @ref LL_RCC_PLLI2S_MUL_14
<> 154:37f96f9d4de2 1697 * @arg @ref LL_RCC_PLLI2S_MUL_16
<> 154:37f96f9d4de2 1698 * @arg @ref LL_RCC_PLLI2S_MUL_20
<> 154:37f96f9d4de2 1699 */
<> 154:37f96f9d4de2 1700 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
<> 154:37f96f9d4de2 1701 {
<> 154:37f96f9d4de2 1702 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
<> 154:37f96f9d4de2 1703 }
<> 154:37f96f9d4de2 1704
<> 154:37f96f9d4de2 1705 /**
<> 154:37f96f9d4de2 1706 * @}
<> 154:37f96f9d4de2 1707 */
<> 154:37f96f9d4de2 1708 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 1709
<> 154:37f96f9d4de2 1710 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 1711 /** @defgroup RCC_LL_EF_PLL2 PLL2
<> 154:37f96f9d4de2 1712 * @{
<> 154:37f96f9d4de2 1713 */
<> 154:37f96f9d4de2 1714
<> 154:37f96f9d4de2 1715 /**
<> 154:37f96f9d4de2 1716 * @brief Enable PLL2
<> 154:37f96f9d4de2 1717 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
<> 154:37f96f9d4de2 1718 * @retval None
<> 154:37f96f9d4de2 1719 */
<> 154:37f96f9d4de2 1720 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
<> 154:37f96f9d4de2 1721 {
<> 154:37f96f9d4de2 1722 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
<> 154:37f96f9d4de2 1723 }
<> 154:37f96f9d4de2 1724
<> 154:37f96f9d4de2 1725 /**
<> 154:37f96f9d4de2 1726 * @brief Disable PLL2
<> 154:37f96f9d4de2 1727 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
<> 154:37f96f9d4de2 1728 * @retval None
<> 154:37f96f9d4de2 1729 */
<> 154:37f96f9d4de2 1730 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
<> 154:37f96f9d4de2 1731 {
<> 154:37f96f9d4de2 1732 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
<> 154:37f96f9d4de2 1733 }
<> 154:37f96f9d4de2 1734
<> 154:37f96f9d4de2 1735 /**
<> 154:37f96f9d4de2 1736 * @brief Check if PLL2 Ready
<> 154:37f96f9d4de2 1737 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
<> 154:37f96f9d4de2 1738 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1739 */
<> 154:37f96f9d4de2 1740 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
<> 154:37f96f9d4de2 1741 {
<> 154:37f96f9d4de2 1742 return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
<> 154:37f96f9d4de2 1743 }
<> 154:37f96f9d4de2 1744
<> 154:37f96f9d4de2 1745 /**
<> 154:37f96f9d4de2 1746 * @brief Configure PLL2 used for PLL2 Domain
<> 154:37f96f9d4de2 1747 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
<> 154:37f96f9d4de2 1748 * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
<> 154:37f96f9d4de2 1749 * @param Divider This parameter can be one of the following values:
<> 154:37f96f9d4de2 1750 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<> 154:37f96f9d4de2 1751 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<> 154:37f96f9d4de2 1752 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<> 154:37f96f9d4de2 1753 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<> 154:37f96f9d4de2 1754 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<> 154:37f96f9d4de2 1755 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<> 154:37f96f9d4de2 1756 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<> 154:37f96f9d4de2 1757 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<> 154:37f96f9d4de2 1758 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<> 154:37f96f9d4de2 1759 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<> 154:37f96f9d4de2 1760 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<> 154:37f96f9d4de2 1761 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<> 154:37f96f9d4de2 1762 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<> 154:37f96f9d4de2 1763 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<> 154:37f96f9d4de2 1764 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<> 154:37f96f9d4de2 1765 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<> 154:37f96f9d4de2 1766 * @param Multiplicator This parameter can be one of the following values:
<> 154:37f96f9d4de2 1767 * @arg @ref LL_RCC_PLL2_MUL_8
<> 154:37f96f9d4de2 1768 * @arg @ref LL_RCC_PLL2_MUL_9
<> 154:37f96f9d4de2 1769 * @arg @ref LL_RCC_PLL2_MUL_10
<> 154:37f96f9d4de2 1770 * @arg @ref LL_RCC_PLL2_MUL_11
<> 154:37f96f9d4de2 1771 * @arg @ref LL_RCC_PLL2_MUL_12
<> 154:37f96f9d4de2 1772 * @arg @ref LL_RCC_PLL2_MUL_13
<> 154:37f96f9d4de2 1773 * @arg @ref LL_RCC_PLL2_MUL_14
<> 154:37f96f9d4de2 1774 * @arg @ref LL_RCC_PLL2_MUL_16
<> 154:37f96f9d4de2 1775 * @arg @ref LL_RCC_PLL2_MUL_20
<> 154:37f96f9d4de2 1776 * @retval None
<> 154:37f96f9d4de2 1777 */
<> 154:37f96f9d4de2 1778 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
<> 154:37f96f9d4de2 1779 {
<> 154:37f96f9d4de2 1780 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator);
<> 154:37f96f9d4de2 1781 }
<> 154:37f96f9d4de2 1782
<> 154:37f96f9d4de2 1783 /**
<> 154:37f96f9d4de2 1784 * @brief Get PLL2 Multiplication Factor
<> 154:37f96f9d4de2 1785 * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
<> 154:37f96f9d4de2 1786 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 1787 * @arg @ref LL_RCC_PLL2_MUL_8
<> 154:37f96f9d4de2 1788 * @arg @ref LL_RCC_PLL2_MUL_9
<> 154:37f96f9d4de2 1789 * @arg @ref LL_RCC_PLL2_MUL_10
<> 154:37f96f9d4de2 1790 * @arg @ref LL_RCC_PLL2_MUL_11
<> 154:37f96f9d4de2 1791 * @arg @ref LL_RCC_PLL2_MUL_12
<> 154:37f96f9d4de2 1792 * @arg @ref LL_RCC_PLL2_MUL_13
<> 154:37f96f9d4de2 1793 * @arg @ref LL_RCC_PLL2_MUL_14
<> 154:37f96f9d4de2 1794 * @arg @ref LL_RCC_PLL2_MUL_16
<> 154:37f96f9d4de2 1795 * @arg @ref LL_RCC_PLL2_MUL_20
<> 154:37f96f9d4de2 1796 */
<> 154:37f96f9d4de2 1797 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
<> 154:37f96f9d4de2 1798 {
<> 154:37f96f9d4de2 1799 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
<> 154:37f96f9d4de2 1800 }
<> 154:37f96f9d4de2 1801
<> 154:37f96f9d4de2 1802 /**
<> 154:37f96f9d4de2 1803 * @}
<> 154:37f96f9d4de2 1804 */
<> 154:37f96f9d4de2 1805 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 1806
<> 154:37f96f9d4de2 1807 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
<> 154:37f96f9d4de2 1808 * @{
<> 154:37f96f9d4de2 1809 */
<> 154:37f96f9d4de2 1810
<> 154:37f96f9d4de2 1811 /**
<> 154:37f96f9d4de2 1812 * @brief Clear LSI ready interrupt flag
<> 154:37f96f9d4de2 1813 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
<> 154:37f96f9d4de2 1814 * @retval None
<> 154:37f96f9d4de2 1815 */
<> 154:37f96f9d4de2 1816 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
<> 154:37f96f9d4de2 1817 {
<> 154:37f96f9d4de2 1818 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
<> 154:37f96f9d4de2 1819 }
<> 154:37f96f9d4de2 1820
<> 154:37f96f9d4de2 1821 /**
<> 154:37f96f9d4de2 1822 * @brief Clear LSE ready interrupt flag
<> 154:37f96f9d4de2 1823 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
<> 154:37f96f9d4de2 1824 * @retval None
<> 154:37f96f9d4de2 1825 */
<> 154:37f96f9d4de2 1826 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
<> 154:37f96f9d4de2 1827 {
<> 154:37f96f9d4de2 1828 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
<> 154:37f96f9d4de2 1829 }
<> 154:37f96f9d4de2 1830
<> 154:37f96f9d4de2 1831 /**
<> 154:37f96f9d4de2 1832 * @brief Clear HSI ready interrupt flag
<> 154:37f96f9d4de2 1833 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
<> 154:37f96f9d4de2 1834 * @retval None
<> 154:37f96f9d4de2 1835 */
<> 154:37f96f9d4de2 1836 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
<> 154:37f96f9d4de2 1837 {
<> 154:37f96f9d4de2 1838 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
<> 154:37f96f9d4de2 1839 }
<> 154:37f96f9d4de2 1840
<> 154:37f96f9d4de2 1841 /**
<> 154:37f96f9d4de2 1842 * @brief Clear HSE ready interrupt flag
<> 154:37f96f9d4de2 1843 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
<> 154:37f96f9d4de2 1844 * @retval None
<> 154:37f96f9d4de2 1845 */
<> 154:37f96f9d4de2 1846 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
<> 154:37f96f9d4de2 1847 {
<> 154:37f96f9d4de2 1848 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
<> 154:37f96f9d4de2 1849 }
<> 154:37f96f9d4de2 1850
<> 154:37f96f9d4de2 1851 /**
<> 154:37f96f9d4de2 1852 * @brief Clear PLL ready interrupt flag
<> 154:37f96f9d4de2 1853 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
<> 154:37f96f9d4de2 1854 * @retval None
<> 154:37f96f9d4de2 1855 */
<> 154:37f96f9d4de2 1856 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
<> 154:37f96f9d4de2 1857 {
<> 154:37f96f9d4de2 1858 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
<> 154:37f96f9d4de2 1859 }
<> 154:37f96f9d4de2 1860
<> 154:37f96f9d4de2 1861 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 1862 /**
<> 154:37f96f9d4de2 1863 * @brief Clear PLLI2S ready interrupt flag
<> 154:37f96f9d4de2 1864 * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
<> 154:37f96f9d4de2 1865 * @retval None
<> 154:37f96f9d4de2 1866 */
<> 154:37f96f9d4de2 1867 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
<> 154:37f96f9d4de2 1868 {
<> 154:37f96f9d4de2 1869 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
<> 154:37f96f9d4de2 1870 }
<> 154:37f96f9d4de2 1871 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 1872
<> 154:37f96f9d4de2 1873 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 1874 /**
<> 154:37f96f9d4de2 1875 * @brief Clear PLL2 ready interrupt flag
<> 154:37f96f9d4de2 1876 * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
<> 154:37f96f9d4de2 1877 * @retval None
<> 154:37f96f9d4de2 1878 */
<> 154:37f96f9d4de2 1879 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
<> 154:37f96f9d4de2 1880 {
<> 154:37f96f9d4de2 1881 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
<> 154:37f96f9d4de2 1882 }
<> 154:37f96f9d4de2 1883 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 1884
<> 154:37f96f9d4de2 1885 /**
<> 154:37f96f9d4de2 1886 * @brief Clear Clock security system interrupt flag
<> 154:37f96f9d4de2 1887 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
<> 154:37f96f9d4de2 1888 * @retval None
<> 154:37f96f9d4de2 1889 */
<> 154:37f96f9d4de2 1890 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
<> 154:37f96f9d4de2 1891 {
<> 154:37f96f9d4de2 1892 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
<> 154:37f96f9d4de2 1893 }
<> 154:37f96f9d4de2 1894
<> 154:37f96f9d4de2 1895 /**
<> 154:37f96f9d4de2 1896 * @brief Check if LSI ready interrupt occurred or not
<> 154:37f96f9d4de2 1897 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
<> 154:37f96f9d4de2 1898 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1899 */
<> 154:37f96f9d4de2 1900 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
<> 154:37f96f9d4de2 1901 {
<> 154:37f96f9d4de2 1902 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
<> 154:37f96f9d4de2 1903 }
<> 154:37f96f9d4de2 1904
<> 154:37f96f9d4de2 1905 /**
<> 154:37f96f9d4de2 1906 * @brief Check if LSE ready interrupt occurred or not
<> 154:37f96f9d4de2 1907 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
<> 154:37f96f9d4de2 1908 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1909 */
<> 154:37f96f9d4de2 1910 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
<> 154:37f96f9d4de2 1911 {
<> 154:37f96f9d4de2 1912 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
<> 154:37f96f9d4de2 1913 }
<> 154:37f96f9d4de2 1914
<> 154:37f96f9d4de2 1915 /**
<> 154:37f96f9d4de2 1916 * @brief Check if HSI ready interrupt occurred or not
<> 154:37f96f9d4de2 1917 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
<> 154:37f96f9d4de2 1918 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1919 */
<> 154:37f96f9d4de2 1920 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
<> 154:37f96f9d4de2 1921 {
<> 154:37f96f9d4de2 1922 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
<> 154:37f96f9d4de2 1923 }
<> 154:37f96f9d4de2 1924
<> 154:37f96f9d4de2 1925 /**
<> 154:37f96f9d4de2 1926 * @brief Check if HSE ready interrupt occurred or not
<> 154:37f96f9d4de2 1927 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
<> 154:37f96f9d4de2 1928 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1929 */
<> 154:37f96f9d4de2 1930 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
<> 154:37f96f9d4de2 1931 {
<> 154:37f96f9d4de2 1932 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
<> 154:37f96f9d4de2 1933 }
<> 154:37f96f9d4de2 1934
<> 154:37f96f9d4de2 1935 /**
<> 154:37f96f9d4de2 1936 * @brief Check if PLL ready interrupt occurred or not
<> 154:37f96f9d4de2 1937 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
<> 154:37f96f9d4de2 1938 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1939 */
<> 154:37f96f9d4de2 1940 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
<> 154:37f96f9d4de2 1941 {
<> 154:37f96f9d4de2 1942 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
<> 154:37f96f9d4de2 1943 }
<> 154:37f96f9d4de2 1944
<> 154:37f96f9d4de2 1945 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 1946 /**
<> 154:37f96f9d4de2 1947 * @brief Check if PLLI2S ready interrupt occurred or not
<> 154:37f96f9d4de2 1948 * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
<> 154:37f96f9d4de2 1949 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1950 */
<> 154:37f96f9d4de2 1951 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
<> 154:37f96f9d4de2 1952 {
<> 154:37f96f9d4de2 1953 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
<> 154:37f96f9d4de2 1954 }
<> 154:37f96f9d4de2 1955 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 1956
<> 154:37f96f9d4de2 1957 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 1958 /**
<> 154:37f96f9d4de2 1959 * @brief Check if PLL2 ready interrupt occurred or not
<> 154:37f96f9d4de2 1960 * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
<> 154:37f96f9d4de2 1961 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1962 */
<> 154:37f96f9d4de2 1963 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
<> 154:37f96f9d4de2 1964 {
<> 154:37f96f9d4de2 1965 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
<> 154:37f96f9d4de2 1966 }
<> 154:37f96f9d4de2 1967 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 1968
<> 154:37f96f9d4de2 1969 /**
<> 154:37f96f9d4de2 1970 * @brief Check if Clock security system interrupt occurred or not
<> 154:37f96f9d4de2 1971 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
<> 154:37f96f9d4de2 1972 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1973 */
<> 154:37f96f9d4de2 1974 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
<> 154:37f96f9d4de2 1975 {
<> 154:37f96f9d4de2 1976 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
<> 154:37f96f9d4de2 1977 }
<> 154:37f96f9d4de2 1978
<> 154:37f96f9d4de2 1979 /**
<> 154:37f96f9d4de2 1980 * @brief Check if RCC flag Independent Watchdog reset is set or not.
<> 154:37f96f9d4de2 1981 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
<> 154:37f96f9d4de2 1982 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1983 */
<> 154:37f96f9d4de2 1984 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
<> 154:37f96f9d4de2 1985 {
<> 154:37f96f9d4de2 1986 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
<> 154:37f96f9d4de2 1987 }
<> 154:37f96f9d4de2 1988
<> 154:37f96f9d4de2 1989 /**
<> 154:37f96f9d4de2 1990 * @brief Check if RCC flag Low Power reset is set or not.
<> 154:37f96f9d4de2 1991 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
<> 154:37f96f9d4de2 1992 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 1993 */
<> 154:37f96f9d4de2 1994 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
<> 154:37f96f9d4de2 1995 {
<> 154:37f96f9d4de2 1996 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
<> 154:37f96f9d4de2 1997 }
<> 154:37f96f9d4de2 1998
<> 154:37f96f9d4de2 1999 /**
<> 154:37f96f9d4de2 2000 * @brief Check if RCC flag Pin reset is set or not.
<> 154:37f96f9d4de2 2001 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
<> 154:37f96f9d4de2 2002 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2003 */
<> 154:37f96f9d4de2 2004 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
<> 154:37f96f9d4de2 2005 {
<> 154:37f96f9d4de2 2006 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
<> 154:37f96f9d4de2 2007 }
<> 154:37f96f9d4de2 2008
<> 154:37f96f9d4de2 2009 /**
<> 154:37f96f9d4de2 2010 * @brief Check if RCC flag POR/PDR reset is set or not.
<> 154:37f96f9d4de2 2011 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
<> 154:37f96f9d4de2 2012 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2013 */
<> 154:37f96f9d4de2 2014 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
<> 154:37f96f9d4de2 2015 {
<> 154:37f96f9d4de2 2016 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
<> 154:37f96f9d4de2 2017 }
<> 154:37f96f9d4de2 2018
<> 154:37f96f9d4de2 2019 /**
<> 154:37f96f9d4de2 2020 * @brief Check if RCC flag Software reset is set or not.
<> 154:37f96f9d4de2 2021 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
<> 154:37f96f9d4de2 2022 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2023 */
<> 154:37f96f9d4de2 2024 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
<> 154:37f96f9d4de2 2025 {
<> 154:37f96f9d4de2 2026 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
<> 154:37f96f9d4de2 2027 }
<> 154:37f96f9d4de2 2028
<> 154:37f96f9d4de2 2029 /**
<> 154:37f96f9d4de2 2030 * @brief Check if RCC flag Window Watchdog reset is set or not.
<> 154:37f96f9d4de2 2031 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
<> 154:37f96f9d4de2 2032 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2033 */
<> 154:37f96f9d4de2 2034 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
<> 154:37f96f9d4de2 2035 {
<> 154:37f96f9d4de2 2036 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
<> 154:37f96f9d4de2 2037 }
<> 154:37f96f9d4de2 2038
<> 154:37f96f9d4de2 2039 /**
<> 154:37f96f9d4de2 2040 * @brief Set RMVF bit to clear the reset flags.
<> 154:37f96f9d4de2 2041 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
<> 154:37f96f9d4de2 2042 * @retval None
<> 154:37f96f9d4de2 2043 */
<> 154:37f96f9d4de2 2044 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
<> 154:37f96f9d4de2 2045 {
<> 154:37f96f9d4de2 2046 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<> 154:37f96f9d4de2 2047 }
<> 154:37f96f9d4de2 2048
<> 154:37f96f9d4de2 2049 /**
<> 154:37f96f9d4de2 2050 * @}
<> 154:37f96f9d4de2 2051 */
<> 154:37f96f9d4de2 2052
<> 154:37f96f9d4de2 2053 /** @defgroup RCC_LL_EF_IT_Management IT Management
<> 154:37f96f9d4de2 2054 * @{
<> 154:37f96f9d4de2 2055 */
<> 154:37f96f9d4de2 2056
<> 154:37f96f9d4de2 2057 /**
<> 154:37f96f9d4de2 2058 * @brief Enable LSI ready interrupt
<> 154:37f96f9d4de2 2059 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
<> 154:37f96f9d4de2 2060 * @retval None
<> 154:37f96f9d4de2 2061 */
<> 154:37f96f9d4de2 2062 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
<> 154:37f96f9d4de2 2063 {
<> 154:37f96f9d4de2 2064 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<> 154:37f96f9d4de2 2065 }
<> 154:37f96f9d4de2 2066
<> 154:37f96f9d4de2 2067 /**
<> 154:37f96f9d4de2 2068 * @brief Enable LSE ready interrupt
<> 154:37f96f9d4de2 2069 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
<> 154:37f96f9d4de2 2070 * @retval None
<> 154:37f96f9d4de2 2071 */
<> 154:37f96f9d4de2 2072 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
<> 154:37f96f9d4de2 2073 {
<> 154:37f96f9d4de2 2074 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<> 154:37f96f9d4de2 2075 }
<> 154:37f96f9d4de2 2076
<> 154:37f96f9d4de2 2077 /**
<> 154:37f96f9d4de2 2078 * @brief Enable HSI ready interrupt
<> 154:37f96f9d4de2 2079 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
<> 154:37f96f9d4de2 2080 * @retval None
<> 154:37f96f9d4de2 2081 */
<> 154:37f96f9d4de2 2082 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
<> 154:37f96f9d4de2 2083 {
<> 154:37f96f9d4de2 2084 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<> 154:37f96f9d4de2 2085 }
<> 154:37f96f9d4de2 2086
<> 154:37f96f9d4de2 2087 /**
<> 154:37f96f9d4de2 2088 * @brief Enable HSE ready interrupt
<> 154:37f96f9d4de2 2089 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
<> 154:37f96f9d4de2 2090 * @retval None
<> 154:37f96f9d4de2 2091 */
<> 154:37f96f9d4de2 2092 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
<> 154:37f96f9d4de2 2093 {
<> 154:37f96f9d4de2 2094 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<> 154:37f96f9d4de2 2095 }
<> 154:37f96f9d4de2 2096
<> 154:37f96f9d4de2 2097 /**
<> 154:37f96f9d4de2 2098 * @brief Enable PLL ready interrupt
<> 154:37f96f9d4de2 2099 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
<> 154:37f96f9d4de2 2100 * @retval None
<> 154:37f96f9d4de2 2101 */
<> 154:37f96f9d4de2 2102 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
<> 154:37f96f9d4de2 2103 {
<> 154:37f96f9d4de2 2104 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<> 154:37f96f9d4de2 2105 }
<> 154:37f96f9d4de2 2106
<> 154:37f96f9d4de2 2107 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 2108 /**
<> 154:37f96f9d4de2 2109 * @brief Enable PLLI2S ready interrupt
<> 154:37f96f9d4de2 2110 * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
<> 154:37f96f9d4de2 2111 * @retval None
<> 154:37f96f9d4de2 2112 */
<> 154:37f96f9d4de2 2113 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
<> 154:37f96f9d4de2 2114 {
<> 154:37f96f9d4de2 2115 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
<> 154:37f96f9d4de2 2116 }
<> 154:37f96f9d4de2 2117 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 2118
<> 154:37f96f9d4de2 2119 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 2120 /**
<> 154:37f96f9d4de2 2121 * @brief Enable PLL2 ready interrupt
<> 154:37f96f9d4de2 2122 * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
<> 154:37f96f9d4de2 2123 * @retval None
<> 154:37f96f9d4de2 2124 */
<> 154:37f96f9d4de2 2125 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
<> 154:37f96f9d4de2 2126 {
<> 154:37f96f9d4de2 2127 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
<> 154:37f96f9d4de2 2128 }
<> 154:37f96f9d4de2 2129 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 2130
<> 154:37f96f9d4de2 2131 /**
<> 154:37f96f9d4de2 2132 * @brief Disable LSI ready interrupt
<> 154:37f96f9d4de2 2133 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
<> 154:37f96f9d4de2 2134 * @retval None
<> 154:37f96f9d4de2 2135 */
<> 154:37f96f9d4de2 2136 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
<> 154:37f96f9d4de2 2137 {
<> 154:37f96f9d4de2 2138 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<> 154:37f96f9d4de2 2139 }
<> 154:37f96f9d4de2 2140
<> 154:37f96f9d4de2 2141 /**
<> 154:37f96f9d4de2 2142 * @brief Disable LSE ready interrupt
<> 154:37f96f9d4de2 2143 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
<> 154:37f96f9d4de2 2144 * @retval None
<> 154:37f96f9d4de2 2145 */
<> 154:37f96f9d4de2 2146 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
<> 154:37f96f9d4de2 2147 {
<> 154:37f96f9d4de2 2148 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<> 154:37f96f9d4de2 2149 }
<> 154:37f96f9d4de2 2150
<> 154:37f96f9d4de2 2151 /**
<> 154:37f96f9d4de2 2152 * @brief Disable HSI ready interrupt
<> 154:37f96f9d4de2 2153 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
<> 154:37f96f9d4de2 2154 * @retval None
<> 154:37f96f9d4de2 2155 */
<> 154:37f96f9d4de2 2156 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
<> 154:37f96f9d4de2 2157 {
<> 154:37f96f9d4de2 2158 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<> 154:37f96f9d4de2 2159 }
<> 154:37f96f9d4de2 2160
<> 154:37f96f9d4de2 2161 /**
<> 154:37f96f9d4de2 2162 * @brief Disable HSE ready interrupt
<> 154:37f96f9d4de2 2163 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
<> 154:37f96f9d4de2 2164 * @retval None
<> 154:37f96f9d4de2 2165 */
<> 154:37f96f9d4de2 2166 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
<> 154:37f96f9d4de2 2167 {
<> 154:37f96f9d4de2 2168 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<> 154:37f96f9d4de2 2169 }
<> 154:37f96f9d4de2 2170
<> 154:37f96f9d4de2 2171 /**
<> 154:37f96f9d4de2 2172 * @brief Disable PLL ready interrupt
<> 154:37f96f9d4de2 2173 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
<> 154:37f96f9d4de2 2174 * @retval None
<> 154:37f96f9d4de2 2175 */
<> 154:37f96f9d4de2 2176 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
<> 154:37f96f9d4de2 2177 {
<> 154:37f96f9d4de2 2178 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<> 154:37f96f9d4de2 2179 }
<> 154:37f96f9d4de2 2180
<> 154:37f96f9d4de2 2181 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 2182 /**
<> 154:37f96f9d4de2 2183 * @brief Disable PLLI2S ready interrupt
<> 154:37f96f9d4de2 2184 * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
<> 154:37f96f9d4de2 2185 * @retval None
<> 154:37f96f9d4de2 2186 */
<> 154:37f96f9d4de2 2187 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
<> 154:37f96f9d4de2 2188 {
<> 154:37f96f9d4de2 2189 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
<> 154:37f96f9d4de2 2190 }
<> 154:37f96f9d4de2 2191 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 2192
<> 154:37f96f9d4de2 2193 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 2194 /**
<> 154:37f96f9d4de2 2195 * @brief Disable PLL2 ready interrupt
<> 154:37f96f9d4de2 2196 * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
<> 154:37f96f9d4de2 2197 * @retval None
<> 154:37f96f9d4de2 2198 */
<> 154:37f96f9d4de2 2199 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
<> 154:37f96f9d4de2 2200 {
<> 154:37f96f9d4de2 2201 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
<> 154:37f96f9d4de2 2202 }
<> 154:37f96f9d4de2 2203 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 2204
<> 154:37f96f9d4de2 2205 /**
<> 154:37f96f9d4de2 2206 * @brief Checks if LSI ready interrupt source is enabled or disabled.
<> 154:37f96f9d4de2 2207 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
<> 154:37f96f9d4de2 2208 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2209 */
<> 154:37f96f9d4de2 2210 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
<> 154:37f96f9d4de2 2211 {
<> 154:37f96f9d4de2 2212 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
<> 154:37f96f9d4de2 2213 }
<> 154:37f96f9d4de2 2214
<> 154:37f96f9d4de2 2215 /**
<> 154:37f96f9d4de2 2216 * @brief Checks if LSE ready interrupt source is enabled or disabled.
<> 154:37f96f9d4de2 2217 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
<> 154:37f96f9d4de2 2218 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2219 */
<> 154:37f96f9d4de2 2220 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
<> 154:37f96f9d4de2 2221 {
<> 154:37f96f9d4de2 2222 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
<> 154:37f96f9d4de2 2223 }
<> 154:37f96f9d4de2 2224
<> 154:37f96f9d4de2 2225 /**
<> 154:37f96f9d4de2 2226 * @brief Checks if HSI ready interrupt source is enabled or disabled.
<> 154:37f96f9d4de2 2227 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
<> 154:37f96f9d4de2 2228 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2229 */
<> 154:37f96f9d4de2 2230 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
<> 154:37f96f9d4de2 2231 {
<> 154:37f96f9d4de2 2232 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
<> 154:37f96f9d4de2 2233 }
<> 154:37f96f9d4de2 2234
<> 154:37f96f9d4de2 2235 /**
<> 154:37f96f9d4de2 2236 * @brief Checks if HSE ready interrupt source is enabled or disabled.
<> 154:37f96f9d4de2 2237 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
<> 154:37f96f9d4de2 2238 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2239 */
<> 154:37f96f9d4de2 2240 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
<> 154:37f96f9d4de2 2241 {
<> 154:37f96f9d4de2 2242 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
<> 154:37f96f9d4de2 2243 }
<> 154:37f96f9d4de2 2244
<> 154:37f96f9d4de2 2245 /**
<> 154:37f96f9d4de2 2246 * @brief Checks if PLL ready interrupt source is enabled or disabled.
<> 154:37f96f9d4de2 2247 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
<> 154:37f96f9d4de2 2248 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2249 */
<> 154:37f96f9d4de2 2250 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
<> 154:37f96f9d4de2 2251 {
<> 154:37f96f9d4de2 2252 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
<> 154:37f96f9d4de2 2253 }
<> 154:37f96f9d4de2 2254
<> 154:37f96f9d4de2 2255 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 2256 /**
<> 154:37f96f9d4de2 2257 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
<> 154:37f96f9d4de2 2258 * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
<> 154:37f96f9d4de2 2259 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2260 */
<> 154:37f96f9d4de2 2261 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
<> 154:37f96f9d4de2 2262 {
<> 154:37f96f9d4de2 2263 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
<> 154:37f96f9d4de2 2264 }
<> 154:37f96f9d4de2 2265 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 2266
<> 154:37f96f9d4de2 2267 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 2268 /**
<> 154:37f96f9d4de2 2269 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
<> 154:37f96f9d4de2 2270 * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
<> 154:37f96f9d4de2 2271 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 2272 */
<> 154:37f96f9d4de2 2273 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
<> 154:37f96f9d4de2 2274 {
<> 154:37f96f9d4de2 2275 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
<> 154:37f96f9d4de2 2276 }
<> 154:37f96f9d4de2 2277 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 2278
<> 154:37f96f9d4de2 2279 /**
<> 154:37f96f9d4de2 2280 * @}
<> 154:37f96f9d4de2 2281 */
<> 154:37f96f9d4de2 2282
<> 154:37f96f9d4de2 2283 #if defined(USE_FULL_LL_DRIVER)
<> 154:37f96f9d4de2 2284 /** @defgroup RCC_LL_EF_Init De-initialization function
<> 154:37f96f9d4de2 2285 * @{
<> 154:37f96f9d4de2 2286 */
<> 154:37f96f9d4de2 2287 ErrorStatus LL_RCC_DeInit(void);
<> 154:37f96f9d4de2 2288 /**
<> 154:37f96f9d4de2 2289 * @}
<> 154:37f96f9d4de2 2290 */
<> 154:37f96f9d4de2 2291
<> 154:37f96f9d4de2 2292 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
<> 154:37f96f9d4de2 2293 * @{
<> 154:37f96f9d4de2 2294 */
<> 154:37f96f9d4de2 2295 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge 165:e614a9f1c9e2 2296 #if defined(RCC_CFGR2_I2S2SRC)
<> 154:37f96f9d4de2 2297 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
<> 154:37f96f9d4de2 2298 #endif /* RCC_CFGR2_I2S2SRC */
<> 154:37f96f9d4de2 2299 #if defined(USB_OTG_FS) || defined(USB)
<> 154:37f96f9d4de2 2300 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
<> 154:37f96f9d4de2 2301 #endif /* USB_OTG_FS || USB */
<> 154:37f96f9d4de2 2302 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
<> 154:37f96f9d4de2 2303 /**
<> 154:37f96f9d4de2 2304 * @}
<> 154:37f96f9d4de2 2305 */
<> 154:37f96f9d4de2 2306 #endif /* USE_FULL_LL_DRIVER */
<> 154:37f96f9d4de2 2307
<> 154:37f96f9d4de2 2308 /**
<> 154:37f96f9d4de2 2309 * @}
<> 154:37f96f9d4de2 2310 */
<> 154:37f96f9d4de2 2311
<> 154:37f96f9d4de2 2312 /**
<> 154:37f96f9d4de2 2313 * @}
<> 154:37f96f9d4de2 2314 */
<> 154:37f96f9d4de2 2315
<> 154:37f96f9d4de2 2316 #endif /* RCC */
<> 154:37f96f9d4de2 2317
<> 154:37f96f9d4de2 2318 /**
<> 154:37f96f9d4de2 2319 * @}
<> 154:37f96f9d4de2 2320 */
<> 154:37f96f9d4de2 2321
<> 154:37f96f9d4de2 2322 #ifdef __cplusplus
<> 154:37f96f9d4de2 2323 }
<> 154:37f96f9d4de2 2324 #endif
<> 154:37f96f9d4de2 2325
<> 154:37f96f9d4de2 2326 #endif /* __STM32F1xx_LL_RCC_H */
<> 154:37f96f9d4de2 2327
<> 154:37f96f9d4de2 2328 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/