mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /**
<> 154:37f96f9d4de2 2 ******************************************************************************
<> 154:37f96f9d4de2 3 * @file stm32f1xx_ll_rcc.c
<> 154:37f96f9d4de2 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @brief RCC LL module driver.
<> 154:37f96f9d4de2 6 ******************************************************************************
<> 154:37f96f9d4de2 7 * @attention
<> 154:37f96f9d4de2 8 *
<> 154:37f96f9d4de2 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 12 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 14 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 16 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 17 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 19 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 20 * without specific prior written permission.
<> 154:37f96f9d4de2 21 *
<> 154:37f96f9d4de2 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 32 *
<> 154:37f96f9d4de2 33 ******************************************************************************
<> 154:37f96f9d4de2 34 */
<> 154:37f96f9d4de2 35 #if defined(USE_FULL_LL_DRIVER)
<> 154:37f96f9d4de2 36
<> 154:37f96f9d4de2 37 /* Includes ------------------------------------------------------------------*/
<> 154:37f96f9d4de2 38 #include "stm32f1xx_ll_rcc.h"
<> 154:37f96f9d4de2 39 #ifdef USE_FULL_ASSERT
<> 154:37f96f9d4de2 40 #include "stm32_assert.h"
<> 154:37f96f9d4de2 41 #else
<> 154:37f96f9d4de2 42 #define assert_param(expr) ((void)0U)
<> 154:37f96f9d4de2 43 #endif /* USE_FULL_ASSERT */
<> 154:37f96f9d4de2 44 /** @addtogroup STM32F1xx_LL_Driver
<> 154:37f96f9d4de2 45 * @{
<> 154:37f96f9d4de2 46 */
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 #if defined(RCC)
<> 154:37f96f9d4de2 49
<> 154:37f96f9d4de2 50 /** @defgroup RCC_LL RCC
<> 154:37f96f9d4de2 51 * @{
<> 154:37f96f9d4de2 52 */
<> 154:37f96f9d4de2 53
<> 154:37f96f9d4de2 54 /* Private types -------------------------------------------------------------*/
<> 154:37f96f9d4de2 55 /* Private variables ---------------------------------------------------------*/
<> 154:37f96f9d4de2 56 /* Private constants ---------------------------------------------------------*/
<> 154:37f96f9d4de2 57 /* Private macros ------------------------------------------------------------*/
<> 154:37f96f9d4de2 58 /** @addtogroup RCC_LL_Private_Macros
<> 154:37f96f9d4de2 59 * @{
<> 154:37f96f9d4de2 60 */
<> 154:37f96f9d4de2 61 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 62 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
<> 154:37f96f9d4de2 63 || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
<> 154:37f96f9d4de2 64 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 65
<> 154:37f96f9d4de2 66 #if defined(USB) || defined(USB_OTG_FS)
<> 154:37f96f9d4de2 67 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
<> 154:37f96f9d4de2 68 #endif /* USB */
<> 154:37f96f9d4de2 69
<> 154:37f96f9d4de2 70 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
<> 154:37f96f9d4de2 71 /**
<> 154:37f96f9d4de2 72 * @}
<> 154:37f96f9d4de2 73 */
<> 154:37f96f9d4de2 74
<> 154:37f96f9d4de2 75 /* Private function prototypes -----------------------------------------------*/
<> 154:37f96f9d4de2 76 /** @defgroup RCC_LL_Private_Functions RCC Private functions
<> 154:37f96f9d4de2 77 * @{
<> 154:37f96f9d4de2 78 */
<> 154:37f96f9d4de2 79 uint32_t RCC_GetSystemClockFreq(void);
<> 154:37f96f9d4de2 80 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
<> 154:37f96f9d4de2 81 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
<> 154:37f96f9d4de2 82 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
<> 154:37f96f9d4de2 83 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
<> 154:37f96f9d4de2 84 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 85 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
<> 154:37f96f9d4de2 86 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 87 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 88 uint32_t RCC_PLL2_GetFreqClockFreq(void);
<> 154:37f96f9d4de2 89 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 90 /**
<> 154:37f96f9d4de2 91 * @}
<> 154:37f96f9d4de2 92 */
<> 154:37f96f9d4de2 93
<> 154:37f96f9d4de2 94 /* Exported functions --------------------------------------------------------*/
<> 154:37f96f9d4de2 95 /** @addtogroup RCC_LL_Exported_Functions
<> 154:37f96f9d4de2 96 * @{
<> 154:37f96f9d4de2 97 */
<> 154:37f96f9d4de2 98
<> 154:37f96f9d4de2 99 /** @addtogroup RCC_LL_EF_Init
<> 154:37f96f9d4de2 100 * @{
<> 154:37f96f9d4de2 101 */
<> 154:37f96f9d4de2 102
<> 154:37f96f9d4de2 103 /**
<> 154:37f96f9d4de2 104 * @brief Reset the RCC clock configuration to the default reset state.
<> 154:37f96f9d4de2 105 * @note The default reset state of the clock configuration is given below:
<> 154:37f96f9d4de2 106 * - HSI ON and used as system clock source
AnnaBridge 187:0387e8f68319 107 * - HSE PLL, PLL2 & PLL3 are OFF
<> 154:37f96f9d4de2 108 * - AHB, APB1 and APB2 prescaler set to 1.
<> 154:37f96f9d4de2 109 * - CSS, MCO OFF
<> 154:37f96f9d4de2 110 * - All interrupts disabled
<> 154:37f96f9d4de2 111 * @note This function doesn't modify the configuration of the
<> 154:37f96f9d4de2 112 * - Peripheral clocks
<> 154:37f96f9d4de2 113 * - LSI, LSE and RTC clocks
<> 154:37f96f9d4de2 114 * @retval An ErrorStatus enumeration value:
AnnaBridge 187:0387e8f68319 115 * - SUCCESS: RCC registers are de-initialized
AnnaBridge 187:0387e8f68319 116 * - ERROR: not applicable
<> 154:37f96f9d4de2 117 */
<> 154:37f96f9d4de2 118 ErrorStatus LL_RCC_DeInit(void)
<> 154:37f96f9d4de2 119 {
<> 154:37f96f9d4de2 120 /* Set HSION bit */
<> 154:37f96f9d4de2 121 LL_RCC_HSI_Enable();
<> 154:37f96f9d4de2 122
AnnaBridge 187:0387e8f68319 123 /* Wait for HSI READY bit */
AnnaBridge 187:0387e8f68319 124 while(LL_RCC_HSI_IsReady() != 1U)
AnnaBridge 187:0387e8f68319 125 {}
<> 154:37f96f9d4de2 126
AnnaBridge 187:0387e8f68319 127 /* Configure HSI as system clock source */
AnnaBridge 187:0387e8f68319 128 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
AnnaBridge 187:0387e8f68319 129
AnnaBridge 187:0387e8f68319 130 /* Wait till clock switch is ready */
AnnaBridge 187:0387e8f68319 131 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
AnnaBridge 187:0387e8f68319 132 {}
<> 154:37f96f9d4de2 133
AnnaBridge 187:0387e8f68319 134 /* Reset PLLON bit */
AnnaBridge 187:0387e8f68319 135 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<> 154:37f96f9d4de2 136
AnnaBridge 187:0387e8f68319 137 /* Wait for PLL READY bit to be reset */
AnnaBridge 187:0387e8f68319 138 while(LL_RCC_PLL_IsReady() != 0U)
AnnaBridge 187:0387e8f68319 139 {}
<> 154:37f96f9d4de2 140
AnnaBridge 187:0387e8f68319 141 /* Reset CFGR register */
AnnaBridge 187:0387e8f68319 142 LL_RCC_WriteReg(CFGR, 0x00000000U);
AnnaBridge 187:0387e8f68319 143
AnnaBridge 187:0387e8f68319 144 /* Reset HSEON, HSEBYP & CSSON bits */
AnnaBridge 187:0387e8f68319 145 CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
<> 154:37f96f9d4de2 146
<> 154:37f96f9d4de2 147 #if defined(RCC_CR_PLL2ON)
<> 154:37f96f9d4de2 148 /* Reset PLL2ON bit */
AnnaBridge 187:0387e8f68319 149 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
<> 154:37f96f9d4de2 150 #endif /* RCC_CR_PLL2ON */
<> 154:37f96f9d4de2 151
<> 154:37f96f9d4de2 152 #if defined(RCC_CR_PLL3ON)
<> 154:37f96f9d4de2 153 /* Reset PLL3ON bit */
AnnaBridge 187:0387e8f68319 154 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
<> 154:37f96f9d4de2 155 #endif /* RCC_CR_PLL3ON */
AnnaBridge 165:e614a9f1c9e2 156
<> 154:37f96f9d4de2 157 /* Set HSITRIM bits to the reset value */
<> 154:37f96f9d4de2 158 LL_RCC_HSI_SetCalibTrimming(0x10U);
<> 154:37f96f9d4de2 159
AnnaBridge 165:e614a9f1c9e2 160 #if defined(RCC_CFGR2_PREDIV1)
<> 154:37f96f9d4de2 161 /* Reset CFGR2 register */
AnnaBridge 187:0387e8f68319 162 LL_RCC_WriteReg(CFGR2, 0x00000000U);
AnnaBridge 165:e614a9f1c9e2 163 #endif /* RCC_CFGR2_PREDIV1 */
<> 154:37f96f9d4de2 164
<> 154:37f96f9d4de2 165 /* Disable all interrupts */
<> 154:37f96f9d4de2 166 LL_RCC_WriteReg(CIR, 0x00000000U);
<> 154:37f96f9d4de2 167
AnnaBridge 187:0387e8f68319 168 /* Clear reset flags */
AnnaBridge 187:0387e8f68319 169 LL_RCC_ClearResetFlags();
AnnaBridge 187:0387e8f68319 170
<> 154:37f96f9d4de2 171 return SUCCESS;
<> 154:37f96f9d4de2 172 }
<> 154:37f96f9d4de2 173
<> 154:37f96f9d4de2 174 /**
<> 154:37f96f9d4de2 175 * @}
<> 154:37f96f9d4de2 176 */
<> 154:37f96f9d4de2 177
<> 154:37f96f9d4de2 178 /** @addtogroup RCC_LL_EF_Get_Freq
<> 154:37f96f9d4de2 179 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<> 154:37f96f9d4de2 180 * and different peripheral clocks available on the device.
<> 154:37f96f9d4de2 181 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
<> 154:37f96f9d4de2 182 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
<> 154:37f96f9d4de2 183 * @note If SYSCLK source is PLL, function returns values based on
<> 154:37f96f9d4de2 184 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
<> 154:37f96f9d4de2 185 * @note (**) HSI_VALUE is a defined constant but the real value may vary
<> 154:37f96f9d4de2 186 * depending on the variations in voltage and temperature.
<> 154:37f96f9d4de2 187 * @note (***) HSE_VALUE is a defined constant, user has to ensure that
<> 154:37f96f9d4de2 188 * HSE_VALUE is same as the real frequency of the crystal used.
<> 154:37f96f9d4de2 189 * Otherwise, this function may have wrong result.
<> 154:37f96f9d4de2 190 * @note The result of this function could be incorrect when using fractional
<> 154:37f96f9d4de2 191 * value for HSE crystal.
<> 154:37f96f9d4de2 192 * @note This function can be used by the user application to compute the
<> 154:37f96f9d4de2 193 * baud-rate for the communication peripherals or configure other parameters.
<> 154:37f96f9d4de2 194 * @{
<> 154:37f96f9d4de2 195 */
<> 154:37f96f9d4de2 196
<> 154:37f96f9d4de2 197 /**
<> 154:37f96f9d4de2 198 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<> 154:37f96f9d4de2 199 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
<> 154:37f96f9d4de2 200 * must be called to update structure fields. Otherwise, any
<> 154:37f96f9d4de2 201 * configuration based on this function will be incorrect.
<> 154:37f96f9d4de2 202 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
<> 154:37f96f9d4de2 203 * @retval None
<> 154:37f96f9d4de2 204 */
<> 154:37f96f9d4de2 205 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
<> 154:37f96f9d4de2 206 {
<> 154:37f96f9d4de2 207 /* Get SYSCLK frequency */
<> 154:37f96f9d4de2 208 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
<> 154:37f96f9d4de2 209
<> 154:37f96f9d4de2 210 /* HCLK clock frequency */
<> 154:37f96f9d4de2 211 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
<> 154:37f96f9d4de2 212
<> 154:37f96f9d4de2 213 /* PCLK1 clock frequency */
<> 154:37f96f9d4de2 214 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
<> 154:37f96f9d4de2 215
<> 154:37f96f9d4de2 216 /* PCLK2 clock frequency */
<> 154:37f96f9d4de2 217 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
<> 154:37f96f9d4de2 218 }
<> 154:37f96f9d4de2 219
<> 154:37f96f9d4de2 220 #if defined(RCC_CFGR2_I2S2SRC)
<> 154:37f96f9d4de2 221 /**
<> 154:37f96f9d4de2 222 * @brief Return I2Sx clock frequency
<> 154:37f96f9d4de2 223 * @param I2SxSource This parameter can be one of the following values:
<> 154:37f96f9d4de2 224 * @arg @ref LL_RCC_I2S2_CLKSOURCE
<> 154:37f96f9d4de2 225 * @arg @ref LL_RCC_I2S3_CLKSOURCE
<> 154:37f96f9d4de2 226 * @retval I2S clock frequency (in Hz)
AnnaBridge 165:e614a9f1c9e2 227 */
<> 154:37f96f9d4de2 228 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
<> 154:37f96f9d4de2 229 {
<> 154:37f96f9d4de2 230 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 154:37f96f9d4de2 231
<> 154:37f96f9d4de2 232 /* Check parameter */
<> 154:37f96f9d4de2 233 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
<> 154:37f96f9d4de2 234
<> 154:37f96f9d4de2 235 /* I2S1CLK clock frequency */
<> 154:37f96f9d4de2 236 switch (LL_RCC_GetI2SClockSource(I2SxSource))
<> 154:37f96f9d4de2 237 {
<> 154:37f96f9d4de2 238 case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
<> 154:37f96f9d4de2 239 case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
<> 154:37f96f9d4de2 240 i2s_frequency = RCC_GetSystemClockFreq();
<> 154:37f96f9d4de2 241 break;
<> 154:37f96f9d4de2 242
<> 154:37f96f9d4de2 243 case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
<> 154:37f96f9d4de2 244 case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
<> 154:37f96f9d4de2 245 default:
AnnaBridge 165:e614a9f1c9e2 246 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
<> 154:37f96f9d4de2 247 break;
<> 154:37f96f9d4de2 248 }
<> 154:37f96f9d4de2 249
<> 154:37f96f9d4de2 250 return i2s_frequency;
<> 154:37f96f9d4de2 251 }
<> 154:37f96f9d4de2 252 #endif /* RCC_CFGR2_I2S2SRC */
AnnaBridge 165:e614a9f1c9e2 253
<> 154:37f96f9d4de2 254 #if defined(USB) || defined(USB_OTG_FS)
<> 154:37f96f9d4de2 255 /**
<> 154:37f96f9d4de2 256 * @brief Return USBx clock frequency
<> 154:37f96f9d4de2 257 * @param USBxSource This parameter can be one of the following values:
<> 154:37f96f9d4de2 258 * @arg @ref LL_RCC_USB_CLKSOURCE
<> 154:37f96f9d4de2 259 * @retval USB clock frequency (in Hz)
<> 154:37f96f9d4de2 260 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
<> 154:37f96f9d4de2 261 */
<> 154:37f96f9d4de2 262 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
<> 154:37f96f9d4de2 263 {
<> 154:37f96f9d4de2 264 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 154:37f96f9d4de2 265
<> 154:37f96f9d4de2 266 /* Check parameter */
<> 154:37f96f9d4de2 267 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
<> 154:37f96f9d4de2 268
<> 154:37f96f9d4de2 269 /* USBCLK clock frequency */
<> 154:37f96f9d4de2 270 switch (LL_RCC_GetUSBClockSource(USBxSource))
<> 154:37f96f9d4de2 271 {
<> 154:37f96f9d4de2 272 #if defined(RCC_CFGR_USBPRE)
<> 154:37f96f9d4de2 273 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
<> 154:37f96f9d4de2 274 if (LL_RCC_PLL_IsReady())
<> 154:37f96f9d4de2 275 {
<> 154:37f96f9d4de2 276 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
<> 154:37f96f9d4de2 277 }
<> 154:37f96f9d4de2 278 break;
<> 154:37f96f9d4de2 279
<> 154:37f96f9d4de2 280 case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
<> 154:37f96f9d4de2 281 default:
<> 154:37f96f9d4de2 282 if (LL_RCC_PLL_IsReady())
<> 154:37f96f9d4de2 283 {
AnnaBridge 165:e614a9f1c9e2 284 usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
<> 154:37f96f9d4de2 285 }
<> 154:37f96f9d4de2 286 break;
<> 154:37f96f9d4de2 287 #endif /* RCC_CFGR_USBPRE */
<> 154:37f96f9d4de2 288 #if defined(RCC_CFGR_OTGFSPRE)
<> 154:37f96f9d4de2 289 /* USBCLK = PLLVCO/2
<> 154:37f96f9d4de2 290 = (2 x PLLCLK) / 2
<> 154:37f96f9d4de2 291 = PLLCLK */
<> 154:37f96f9d4de2 292 case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
<> 154:37f96f9d4de2 293 if (LL_RCC_PLL_IsReady())
<> 154:37f96f9d4de2 294 {
<> 154:37f96f9d4de2 295 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
<> 154:37f96f9d4de2 296 }
<> 154:37f96f9d4de2 297 break;
<> 154:37f96f9d4de2 298
<> 154:37f96f9d4de2 299 /* USBCLK = PLLVCO/3
<> 154:37f96f9d4de2 300 = (2 x PLLCLK) / 3 */
AnnaBridge 165:e614a9f1c9e2 301 case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
<> 154:37f96f9d4de2 302 default:
<> 154:37f96f9d4de2 303 if (LL_RCC_PLL_IsReady())
<> 154:37f96f9d4de2 304 {
AnnaBridge 165:e614a9f1c9e2 305 usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
<> 154:37f96f9d4de2 306 }
<> 154:37f96f9d4de2 307 break;
<> 154:37f96f9d4de2 308 #endif /* RCC_CFGR_OTGFSPRE */
<> 154:37f96f9d4de2 309 }
<> 154:37f96f9d4de2 310
<> 154:37f96f9d4de2 311 return usb_frequency;
<> 154:37f96f9d4de2 312 }
<> 154:37f96f9d4de2 313 #endif /* USB */
<> 154:37f96f9d4de2 314
<> 154:37f96f9d4de2 315 /**
<> 154:37f96f9d4de2 316 * @brief Return ADCx clock frequency
<> 154:37f96f9d4de2 317 * @param ADCxSource This parameter can be one of the following values:
<> 154:37f96f9d4de2 318 * @arg @ref LL_RCC_ADC_CLKSOURCE
<> 154:37f96f9d4de2 319 * @retval ADC clock frequency (in Hz)
<> 154:37f96f9d4de2 320 */
<> 154:37f96f9d4de2 321 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
<> 154:37f96f9d4de2 322 {
<> 154:37f96f9d4de2 323 uint32_t adc_prescaler = 0U;
AnnaBridge 165:e614a9f1c9e2 324 uint32_t adc_frequency = 0U;
<> 154:37f96f9d4de2 325
<> 154:37f96f9d4de2 326 /* Check parameter */
<> 154:37f96f9d4de2 327 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
AnnaBridge 165:e614a9f1c9e2 328
<> 154:37f96f9d4de2 329 /* Get ADC prescaler */
<> 154:37f96f9d4de2 330 adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
<> 154:37f96f9d4de2 331
<> 154:37f96f9d4de2 332 /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
<> 154:37f96f9d4de2 333 adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
<> 154:37f96f9d4de2 334 / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
<> 154:37f96f9d4de2 335
<> 154:37f96f9d4de2 336 return adc_frequency;
<> 154:37f96f9d4de2 337 }
<> 154:37f96f9d4de2 338
<> 154:37f96f9d4de2 339 /**
<> 154:37f96f9d4de2 340 * @}
<> 154:37f96f9d4de2 341 */
<> 154:37f96f9d4de2 342
<> 154:37f96f9d4de2 343 /**
<> 154:37f96f9d4de2 344 * @}
<> 154:37f96f9d4de2 345 */
<> 154:37f96f9d4de2 346
<> 154:37f96f9d4de2 347 /** @addtogroup RCC_LL_Private_Functions
<> 154:37f96f9d4de2 348 * @{
<> 154:37f96f9d4de2 349 */
<> 154:37f96f9d4de2 350
<> 154:37f96f9d4de2 351 /**
<> 154:37f96f9d4de2 352 * @brief Return SYSTEM clock frequency
<> 154:37f96f9d4de2 353 * @retval SYSTEM clock frequency (in Hz)
<> 154:37f96f9d4de2 354 */
<> 154:37f96f9d4de2 355 uint32_t RCC_GetSystemClockFreq(void)
<> 154:37f96f9d4de2 356 {
<> 154:37f96f9d4de2 357 uint32_t frequency = 0U;
<> 154:37f96f9d4de2 358
<> 154:37f96f9d4de2 359 /* Get SYSCLK source -------------------------------------------------------*/
<> 154:37f96f9d4de2 360 switch (LL_RCC_GetSysClkSource())
<> 154:37f96f9d4de2 361 {
<> 154:37f96f9d4de2 362 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 154:37f96f9d4de2 363 frequency = HSI_VALUE;
<> 154:37f96f9d4de2 364 break;
<> 154:37f96f9d4de2 365
<> 154:37f96f9d4de2 366 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
<> 154:37f96f9d4de2 367 frequency = HSE_VALUE;
<> 154:37f96f9d4de2 368 break;
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
<> 154:37f96f9d4de2 371 frequency = RCC_PLL_GetFreqDomain_SYS();
<> 154:37f96f9d4de2 372 break;
<> 154:37f96f9d4de2 373
<> 154:37f96f9d4de2 374 default:
<> 154:37f96f9d4de2 375 frequency = HSI_VALUE;
<> 154:37f96f9d4de2 376 break;
<> 154:37f96f9d4de2 377 }
<> 154:37f96f9d4de2 378
<> 154:37f96f9d4de2 379 return frequency;
<> 154:37f96f9d4de2 380 }
<> 154:37f96f9d4de2 381
<> 154:37f96f9d4de2 382 /**
<> 154:37f96f9d4de2 383 * @brief Return HCLK clock frequency
<> 154:37f96f9d4de2 384 * @param SYSCLK_Frequency SYSCLK clock frequency
<> 154:37f96f9d4de2 385 * @retval HCLK clock frequency (in Hz)
<> 154:37f96f9d4de2 386 */
<> 154:37f96f9d4de2 387 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
<> 154:37f96f9d4de2 388 {
<> 154:37f96f9d4de2 389 /* HCLK clock frequency */
<> 154:37f96f9d4de2 390 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
<> 154:37f96f9d4de2 391 }
<> 154:37f96f9d4de2 392
<> 154:37f96f9d4de2 393 /**
<> 154:37f96f9d4de2 394 * @brief Return PCLK1 clock frequency
<> 154:37f96f9d4de2 395 * @param HCLK_Frequency HCLK clock frequency
<> 154:37f96f9d4de2 396 * @retval PCLK1 clock frequency (in Hz)
<> 154:37f96f9d4de2 397 */
<> 154:37f96f9d4de2 398 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
<> 154:37f96f9d4de2 399 {
<> 154:37f96f9d4de2 400 /* PCLK1 clock frequency */
<> 154:37f96f9d4de2 401 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
<> 154:37f96f9d4de2 402 }
<> 154:37f96f9d4de2 403
<> 154:37f96f9d4de2 404 /**
<> 154:37f96f9d4de2 405 * @brief Return PCLK2 clock frequency
<> 154:37f96f9d4de2 406 * @param HCLK_Frequency HCLK clock frequency
<> 154:37f96f9d4de2 407 * @retval PCLK2 clock frequency (in Hz)
<> 154:37f96f9d4de2 408 */
<> 154:37f96f9d4de2 409 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
<> 154:37f96f9d4de2 410 {
<> 154:37f96f9d4de2 411 /* PCLK2 clock frequency */
<> 154:37f96f9d4de2 412 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
<> 154:37f96f9d4de2 413 }
<> 154:37f96f9d4de2 414
<> 154:37f96f9d4de2 415 /**
<> 154:37f96f9d4de2 416 * @brief Return PLL clock frequency used for system domain
<> 154:37f96f9d4de2 417 * @retval PLL clock frequency (in Hz)
<> 154:37f96f9d4de2 418 */
<> 154:37f96f9d4de2 419 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
<> 154:37f96f9d4de2 420 {
<> 154:37f96f9d4de2 421 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 154:37f96f9d4de2 422
<> 154:37f96f9d4de2 423 /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
<> 154:37f96f9d4de2 424
<> 154:37f96f9d4de2 425 /* Get PLL source */
<> 154:37f96f9d4de2 426 pllsource = LL_RCC_PLL_GetMainSource();
<> 154:37f96f9d4de2 427
<> 154:37f96f9d4de2 428 switch (pllsource)
<> 154:37f96f9d4de2 429 {
<> 154:37f96f9d4de2 430 case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
AnnaBridge 165:e614a9f1c9e2 431 pllinputfreq = HSI_VALUE / 2U;
<> 154:37f96f9d4de2 432 break;
<> 154:37f96f9d4de2 433
<> 154:37f96f9d4de2 434 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
AnnaBridge 165:e614a9f1c9e2 435 pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
<> 154:37f96f9d4de2 436 break;
<> 154:37f96f9d4de2 437
<> 154:37f96f9d4de2 438 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 439 case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
AnnaBridge 165:e614a9f1c9e2 440 pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
<> 154:37f96f9d4de2 441 break;
<> 154:37f96f9d4de2 442 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 443
<> 154:37f96f9d4de2 444 default:
AnnaBridge 165:e614a9f1c9e2 445 pllinputfreq = HSI_VALUE / 2U;
<> 154:37f96f9d4de2 446 break;
<> 154:37f96f9d4de2 447 }
<> 154:37f96f9d4de2 448 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
<> 154:37f96f9d4de2 449 }
<> 154:37f96f9d4de2 450
<> 154:37f96f9d4de2 451 #if defined(RCC_PLL2_SUPPORT)
<> 154:37f96f9d4de2 452 /**
<> 154:37f96f9d4de2 453 * @brief Return PLL clock frequency used for system domain
<> 154:37f96f9d4de2 454 * @retval PLL clock frequency (in Hz)
<> 154:37f96f9d4de2 455 */
<> 154:37f96f9d4de2 456 uint32_t RCC_PLL2_GetFreqClockFreq(void)
<> 154:37f96f9d4de2 457 {
<> 154:37f96f9d4de2 458 return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
<> 154:37f96f9d4de2 459 }
<> 154:37f96f9d4de2 460 #endif /* RCC_PLL2_SUPPORT */
<> 154:37f96f9d4de2 461
<> 154:37f96f9d4de2 462 #if defined(RCC_PLLI2S_SUPPORT)
<> 154:37f96f9d4de2 463 /**
<> 154:37f96f9d4de2 464 * @brief Return PLL clock frequency used for system domain
<> 154:37f96f9d4de2 465 * @retval PLL clock frequency (in Hz)
<> 154:37f96f9d4de2 466 */
<> 154:37f96f9d4de2 467 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
<> 154:37f96f9d4de2 468 {
<> 154:37f96f9d4de2 469 return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
<> 154:37f96f9d4de2 470 }
<> 154:37f96f9d4de2 471 #endif /* RCC_PLLI2S_SUPPORT */
<> 154:37f96f9d4de2 472
<> 154:37f96f9d4de2 473 /**
<> 154:37f96f9d4de2 474 * @}
<> 154:37f96f9d4de2 475 */
<> 154:37f96f9d4de2 476
<> 154:37f96f9d4de2 477 /**
<> 154:37f96f9d4de2 478 * @}
<> 154:37f96f9d4de2 479 */
<> 154:37f96f9d4de2 480
<> 154:37f96f9d4de2 481 #endif /* defined(RCC) */
<> 154:37f96f9d4de2 482
<> 154:37f96f9d4de2 483 /**
<> 154:37f96f9d4de2 484 * @}
<> 154:37f96f9d4de2 485 */
<> 154:37f96f9d4de2 486
<> 154:37f96f9d4de2 487 #endif /* USE_FULL_LL_DRIVER */
<> 154:37f96f9d4de2 488
<> 154:37f96f9d4de2 489 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/