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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /**
<> 154:37f96f9d4de2 2 ******************************************************************************
<> 154:37f96f9d4de2 3 * @file stm32f1xx_ll_pwr.h
<> 154:37f96f9d4de2 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @brief Header file of PWR LL module.
<> 154:37f96f9d4de2 6 ******************************************************************************
<> 154:37f96f9d4de2 7 * @attention
<> 154:37f96f9d4de2 8 *
<> 154:37f96f9d4de2 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 12 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 14 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 16 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 17 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 19 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 20 * without specific prior written permission.
<> 154:37f96f9d4de2 21 *
<> 154:37f96f9d4de2 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 32 *
<> 154:37f96f9d4de2 33 ******************************************************************************
<> 154:37f96f9d4de2 34 */
<> 154:37f96f9d4de2 35
<> 154:37f96f9d4de2 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 154:37f96f9d4de2 37 #ifndef __STM32F1xx_LL_PWR_H
<> 154:37f96f9d4de2 38 #define __STM32F1xx_LL_PWR_H
<> 154:37f96f9d4de2 39
<> 154:37f96f9d4de2 40 #ifdef __cplusplus
<> 154:37f96f9d4de2 41 extern "C" {
<> 154:37f96f9d4de2 42 #endif
<> 154:37f96f9d4de2 43
<> 154:37f96f9d4de2 44 /* Includes ------------------------------------------------------------------*/
<> 154:37f96f9d4de2 45 #include "stm32f1xx.h"
<> 154:37f96f9d4de2 46
<> 154:37f96f9d4de2 47 /** @addtogroup STM32F1xx_LL_Driver
<> 154:37f96f9d4de2 48 * @{
<> 154:37f96f9d4de2 49 */
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 #if defined(PWR)
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 /** @defgroup PWR_LL PWR
<> 154:37f96f9d4de2 54 * @{
<> 154:37f96f9d4de2 55 */
<> 154:37f96f9d4de2 56
<> 154:37f96f9d4de2 57 /* Private types -------------------------------------------------------------*/
<> 154:37f96f9d4de2 58 /* Private variables ---------------------------------------------------------*/
<> 154:37f96f9d4de2 59 /* Private constants ---------------------------------------------------------*/
<> 154:37f96f9d4de2 60 /* Private macros ------------------------------------------------------------*/
<> 154:37f96f9d4de2 61 /* Exported types ------------------------------------------------------------*/
<> 154:37f96f9d4de2 62 /* Exported constants --------------------------------------------------------*/
<> 154:37f96f9d4de2 63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
<> 154:37f96f9d4de2 64 * @{
<> 154:37f96f9d4de2 65 */
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 154:37f96f9d4de2 68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
<> 154:37f96f9d4de2 69 * @{
<> 154:37f96f9d4de2 70 */
<> 154:37f96f9d4de2 71 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
<> 154:37f96f9d4de2 72 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
<> 154:37f96f9d4de2 73 /**
<> 154:37f96f9d4de2 74 * @}
<> 154:37f96f9d4de2 75 */
<> 154:37f96f9d4de2 76
<> 154:37f96f9d4de2 77 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
<> 154:37f96f9d4de2 78 * @brief Flags defines which can be used with LL_PWR_ReadReg function
<> 154:37f96f9d4de2 79 * @{
<> 154:37f96f9d4de2 80 */
<> 154:37f96f9d4de2 81 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
<> 154:37f96f9d4de2 82 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
<> 154:37f96f9d4de2 83 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
<> 154:37f96f9d4de2 84 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
<> 154:37f96f9d4de2 85 /**
<> 154:37f96f9d4de2 86 * @}
<> 154:37f96f9d4de2 87 */
<> 154:37f96f9d4de2 88
<> 154:37f96f9d4de2 89
<> 154:37f96f9d4de2 90 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
<> 154:37f96f9d4de2 91 * @{
<> 154:37f96f9d4de2 92 */
<> 154:37f96f9d4de2 93 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
AnnaBridge 165:e614a9f1c9e2 94 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
<> 154:37f96f9d4de2 95 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
<> 154:37f96f9d4de2 96 /**
<> 154:37f96f9d4de2 97 * @}
<> 154:37f96f9d4de2 98 */
<> 154:37f96f9d4de2 99
<> 154:37f96f9d4de2 100 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
<> 154:37f96f9d4de2 101 * @{
<> 154:37f96f9d4de2 102 */
AnnaBridge 165:e614a9f1c9e2 103 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
AnnaBridge 165:e614a9f1c9e2 104 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
<> 154:37f96f9d4de2 105 /**
<> 154:37f96f9d4de2 106 * @}
<> 154:37f96f9d4de2 107 */
<> 154:37f96f9d4de2 108
<> 154:37f96f9d4de2 109 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
<> 154:37f96f9d4de2 110 * @{
<> 154:37f96f9d4de2 111 */
<> 154:37f96f9d4de2 112 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
<> 154:37f96f9d4de2 113 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
<> 154:37f96f9d4de2 114 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
<> 154:37f96f9d4de2 115 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
<> 154:37f96f9d4de2 116 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
<> 154:37f96f9d4de2 117 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
<> 154:37f96f9d4de2 118 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
<> 154:37f96f9d4de2 119 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
<> 154:37f96f9d4de2 120 /**
<> 154:37f96f9d4de2 121 * @}
<> 154:37f96f9d4de2 122 */
<> 154:37f96f9d4de2 123 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
<> 154:37f96f9d4de2 124 * @{
<> 154:37f96f9d4de2 125 */
AnnaBridge 165:e614a9f1c9e2 126 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
<> 154:37f96f9d4de2 127 /**
<> 154:37f96f9d4de2 128 * @}
<> 154:37f96f9d4de2 129 */
<> 154:37f96f9d4de2 130
<> 154:37f96f9d4de2 131 /**
<> 154:37f96f9d4de2 132 * @}
<> 154:37f96f9d4de2 133 */
<> 154:37f96f9d4de2 134
<> 154:37f96f9d4de2 135
<> 154:37f96f9d4de2 136 /* Exported macro ------------------------------------------------------------*/
<> 154:37f96f9d4de2 137 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
<> 154:37f96f9d4de2 138 * @{
<> 154:37f96f9d4de2 139 */
<> 154:37f96f9d4de2 140
<> 154:37f96f9d4de2 141 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
<> 154:37f96f9d4de2 142 * @{
<> 154:37f96f9d4de2 143 */
<> 154:37f96f9d4de2 144
<> 154:37f96f9d4de2 145 /**
<> 154:37f96f9d4de2 146 * @brief Write a value in PWR register
<> 154:37f96f9d4de2 147 * @param __REG__ Register to be written
<> 154:37f96f9d4de2 148 * @param __VALUE__ Value to be written in the register
<> 154:37f96f9d4de2 149 * @retval None
<> 154:37f96f9d4de2 150 */
<> 154:37f96f9d4de2 151 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
<> 154:37f96f9d4de2 152
<> 154:37f96f9d4de2 153 /**
<> 154:37f96f9d4de2 154 * @brief Read a value in PWR register
<> 154:37f96f9d4de2 155 * @param __REG__ Register to be read
<> 154:37f96f9d4de2 156 * @retval Register value
<> 154:37f96f9d4de2 157 */
<> 154:37f96f9d4de2 158 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
<> 154:37f96f9d4de2 159 /**
<> 154:37f96f9d4de2 160 * @}
<> 154:37f96f9d4de2 161 */
<> 154:37f96f9d4de2 162
<> 154:37f96f9d4de2 163 /**
<> 154:37f96f9d4de2 164 * @}
<> 154:37f96f9d4de2 165 */
<> 154:37f96f9d4de2 166
<> 154:37f96f9d4de2 167 /* Exported functions --------------------------------------------------------*/
<> 154:37f96f9d4de2 168 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
<> 154:37f96f9d4de2 169 * @{
<> 154:37f96f9d4de2 170 */
<> 154:37f96f9d4de2 171
<> 154:37f96f9d4de2 172 /** @defgroup PWR_LL_EF_Configuration Configuration
<> 154:37f96f9d4de2 173 * @{
<> 154:37f96f9d4de2 174 */
<> 154:37f96f9d4de2 175
<> 154:37f96f9d4de2 176 /**
<> 154:37f96f9d4de2 177 * @brief Enable access to the backup domain
<> 154:37f96f9d4de2 178 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
<> 154:37f96f9d4de2 179 * @retval None
<> 154:37f96f9d4de2 180 */
<> 154:37f96f9d4de2 181 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
<> 154:37f96f9d4de2 182 {
<> 154:37f96f9d4de2 183 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 154:37f96f9d4de2 184 }
<> 154:37f96f9d4de2 185
<> 154:37f96f9d4de2 186 /**
<> 154:37f96f9d4de2 187 * @brief Disable access to the backup domain
<> 154:37f96f9d4de2 188 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
<> 154:37f96f9d4de2 189 * @retval None
<> 154:37f96f9d4de2 190 */
<> 154:37f96f9d4de2 191 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
<> 154:37f96f9d4de2 192 {
<> 154:37f96f9d4de2 193 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
<> 154:37f96f9d4de2 194 }
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 /**
<> 154:37f96f9d4de2 197 * @brief Check if the backup domain is enabled
<> 154:37f96f9d4de2 198 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
<> 154:37f96f9d4de2 199 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 200 */
<> 154:37f96f9d4de2 201 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
<> 154:37f96f9d4de2 202 {
<> 154:37f96f9d4de2 203 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
<> 154:37f96f9d4de2 204 }
<> 154:37f96f9d4de2 205
<> 154:37f96f9d4de2 206 /**
AnnaBridge 165:e614a9f1c9e2 207 * @brief Set voltage Regulator mode during deep sleep mode
<> 154:37f96f9d4de2 208 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
<> 154:37f96f9d4de2 209 * @param RegulMode This parameter can be one of the following values:
<> 154:37f96f9d4de2 210 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 154:37f96f9d4de2 211 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 154:37f96f9d4de2 212 * @retval None
<> 154:37f96f9d4de2 213 */
<> 154:37f96f9d4de2 214 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
<> 154:37f96f9d4de2 215 {
<> 154:37f96f9d4de2 216 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
<> 154:37f96f9d4de2 217 }
<> 154:37f96f9d4de2 218
<> 154:37f96f9d4de2 219 /**
AnnaBridge 165:e614a9f1c9e2 220 * @brief Get voltage Regulator mode during deep sleep mode
<> 154:37f96f9d4de2 221 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
<> 154:37f96f9d4de2 222 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 223 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 154:37f96f9d4de2 224 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 154:37f96f9d4de2 225 */
<> 154:37f96f9d4de2 226 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
<> 154:37f96f9d4de2 227 {
<> 154:37f96f9d4de2 228 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
<> 154:37f96f9d4de2 229 }
<> 154:37f96f9d4de2 230
<> 154:37f96f9d4de2 231 /**
AnnaBridge 165:e614a9f1c9e2 232 * @brief Set Power Down mode when CPU enters deepsleep
<> 154:37f96f9d4de2 233 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
<> 154:37f96f9d4de2 234 * @rmtoll CR LPDS LL_PWR_SetPowerMode
<> 154:37f96f9d4de2 235 * @param PDMode This parameter can be one of the following values:
<> 154:37f96f9d4de2 236 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
<> 154:37f96f9d4de2 237 * @arg @ref LL_PWR_MODE_STOP_LPREGU
<> 154:37f96f9d4de2 238 * @arg @ref LL_PWR_MODE_STANDBY
<> 154:37f96f9d4de2 239 * @retval None
<> 154:37f96f9d4de2 240 */
<> 154:37f96f9d4de2 241 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
<> 154:37f96f9d4de2 242 {
<> 154:37f96f9d4de2 243 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
<> 154:37f96f9d4de2 244 }
<> 154:37f96f9d4de2 245
<> 154:37f96f9d4de2 246 /**
AnnaBridge 165:e614a9f1c9e2 247 * @brief Get Power Down mode when CPU enters deepsleep
<> 154:37f96f9d4de2 248 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
<> 154:37f96f9d4de2 249 * @rmtoll CR LPDS LL_PWR_GetPowerMode
<> 154:37f96f9d4de2 250 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 251 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
<> 154:37f96f9d4de2 252 * @arg @ref LL_PWR_MODE_STOP_LPREGU
<> 154:37f96f9d4de2 253 * @arg @ref LL_PWR_MODE_STANDBY
<> 154:37f96f9d4de2 254 */
<> 154:37f96f9d4de2 255 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
<> 154:37f96f9d4de2 256 {
<> 154:37f96f9d4de2 257 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
<> 154:37f96f9d4de2 258 }
<> 154:37f96f9d4de2 259
<> 154:37f96f9d4de2 260 /**
<> 154:37f96f9d4de2 261 * @brief Configure the voltage threshold detected by the Power Voltage Detector
<> 154:37f96f9d4de2 262 * @rmtoll CR PLS LL_PWR_SetPVDLevel
<> 154:37f96f9d4de2 263 * @param PVDLevel This parameter can be one of the following values:
<> 154:37f96f9d4de2 264 * @arg @ref LL_PWR_PVDLEVEL_0
<> 154:37f96f9d4de2 265 * @arg @ref LL_PWR_PVDLEVEL_1
<> 154:37f96f9d4de2 266 * @arg @ref LL_PWR_PVDLEVEL_2
<> 154:37f96f9d4de2 267 * @arg @ref LL_PWR_PVDLEVEL_3
<> 154:37f96f9d4de2 268 * @arg @ref LL_PWR_PVDLEVEL_4
<> 154:37f96f9d4de2 269 * @arg @ref LL_PWR_PVDLEVEL_5
<> 154:37f96f9d4de2 270 * @arg @ref LL_PWR_PVDLEVEL_6
<> 154:37f96f9d4de2 271 * @arg @ref LL_PWR_PVDLEVEL_7
<> 154:37f96f9d4de2 272 * @retval None
<> 154:37f96f9d4de2 273 */
<> 154:37f96f9d4de2 274 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
<> 154:37f96f9d4de2 275 {
<> 154:37f96f9d4de2 276 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
<> 154:37f96f9d4de2 277 }
<> 154:37f96f9d4de2 278
<> 154:37f96f9d4de2 279 /**
<> 154:37f96f9d4de2 280 * @brief Get the voltage threshold detection
<> 154:37f96f9d4de2 281 * @rmtoll CR PLS LL_PWR_GetPVDLevel
<> 154:37f96f9d4de2 282 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 283 * @arg @ref LL_PWR_PVDLEVEL_0
<> 154:37f96f9d4de2 284 * @arg @ref LL_PWR_PVDLEVEL_1
<> 154:37f96f9d4de2 285 * @arg @ref LL_PWR_PVDLEVEL_2
<> 154:37f96f9d4de2 286 * @arg @ref LL_PWR_PVDLEVEL_3
<> 154:37f96f9d4de2 287 * @arg @ref LL_PWR_PVDLEVEL_4
<> 154:37f96f9d4de2 288 * @arg @ref LL_PWR_PVDLEVEL_5
<> 154:37f96f9d4de2 289 * @arg @ref LL_PWR_PVDLEVEL_6
<> 154:37f96f9d4de2 290 * @arg @ref LL_PWR_PVDLEVEL_7
<> 154:37f96f9d4de2 291 */
<> 154:37f96f9d4de2 292 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
<> 154:37f96f9d4de2 293 {
<> 154:37f96f9d4de2 294 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
<> 154:37f96f9d4de2 295 }
<> 154:37f96f9d4de2 296
<> 154:37f96f9d4de2 297 /**
<> 154:37f96f9d4de2 298 * @brief Enable Power Voltage Detector
<> 154:37f96f9d4de2 299 * @rmtoll CR PVDE LL_PWR_EnablePVD
<> 154:37f96f9d4de2 300 * @retval None
<> 154:37f96f9d4de2 301 */
<> 154:37f96f9d4de2 302 __STATIC_INLINE void LL_PWR_EnablePVD(void)
<> 154:37f96f9d4de2 303 {
<> 154:37f96f9d4de2 304 SET_BIT(PWR->CR, PWR_CR_PVDE);
<> 154:37f96f9d4de2 305 }
<> 154:37f96f9d4de2 306
<> 154:37f96f9d4de2 307 /**
<> 154:37f96f9d4de2 308 * @brief Disable Power Voltage Detector
<> 154:37f96f9d4de2 309 * @rmtoll CR PVDE LL_PWR_DisablePVD
<> 154:37f96f9d4de2 310 * @retval None
<> 154:37f96f9d4de2 311 */
<> 154:37f96f9d4de2 312 __STATIC_INLINE void LL_PWR_DisablePVD(void)
<> 154:37f96f9d4de2 313 {
<> 154:37f96f9d4de2 314 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
<> 154:37f96f9d4de2 315 }
<> 154:37f96f9d4de2 316
<> 154:37f96f9d4de2 317 /**
<> 154:37f96f9d4de2 318 * @brief Check if Power Voltage Detector is enabled
<> 154:37f96f9d4de2 319 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
<> 154:37f96f9d4de2 320 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 321 */
<> 154:37f96f9d4de2 322 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
<> 154:37f96f9d4de2 323 {
<> 154:37f96f9d4de2 324 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
<> 154:37f96f9d4de2 325 }
<> 154:37f96f9d4de2 326
<> 154:37f96f9d4de2 327 /**
<> 154:37f96f9d4de2 328 * @brief Enable the WakeUp PINx functionality
<> 154:37f96f9d4de2 329 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
<> 154:37f96f9d4de2 330 * @param WakeUpPin This parameter can be one of the following values:
<> 154:37f96f9d4de2 331 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 154:37f96f9d4de2 332 * @retval None
<> 154:37f96f9d4de2 333 */
<> 154:37f96f9d4de2 334 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
<> 154:37f96f9d4de2 335 {
<> 154:37f96f9d4de2 336 SET_BIT(PWR->CSR, WakeUpPin);
<> 154:37f96f9d4de2 337 }
<> 154:37f96f9d4de2 338
<> 154:37f96f9d4de2 339 /**
<> 154:37f96f9d4de2 340 * @brief Disable the WakeUp PINx functionality
<> 154:37f96f9d4de2 341 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
<> 154:37f96f9d4de2 342 * @param WakeUpPin This parameter can be one of the following values:
<> 154:37f96f9d4de2 343 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 154:37f96f9d4de2 344 * @retval None
<> 154:37f96f9d4de2 345 */
<> 154:37f96f9d4de2 346 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
<> 154:37f96f9d4de2 347 {
<> 154:37f96f9d4de2 348 CLEAR_BIT(PWR->CSR, WakeUpPin);
<> 154:37f96f9d4de2 349 }
<> 154:37f96f9d4de2 350
<> 154:37f96f9d4de2 351 /**
<> 154:37f96f9d4de2 352 * @brief Check if the WakeUp PINx functionality is enabled
<> 154:37f96f9d4de2 353 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
<> 154:37f96f9d4de2 354 * @param WakeUpPin This parameter can be one of the following values:
<> 154:37f96f9d4de2 355 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 154:37f96f9d4de2 356 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 357 */
<> 154:37f96f9d4de2 358 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
<> 154:37f96f9d4de2 359 {
<> 154:37f96f9d4de2 360 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
<> 154:37f96f9d4de2 361 }
<> 154:37f96f9d4de2 362
<> 154:37f96f9d4de2 363
<> 154:37f96f9d4de2 364 /**
<> 154:37f96f9d4de2 365 * @}
<> 154:37f96f9d4de2 366 */
<> 154:37f96f9d4de2 367
<> 154:37f96f9d4de2 368 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
<> 154:37f96f9d4de2 369 * @{
<> 154:37f96f9d4de2 370 */
<> 154:37f96f9d4de2 371
<> 154:37f96f9d4de2 372 /**
<> 154:37f96f9d4de2 373 * @brief Get Wake-up Flag
<> 154:37f96f9d4de2 374 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
<> 154:37f96f9d4de2 375 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 376 */
<> 154:37f96f9d4de2 377 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
<> 154:37f96f9d4de2 378 {
<> 154:37f96f9d4de2 379 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
<> 154:37f96f9d4de2 380 }
<> 154:37f96f9d4de2 381
<> 154:37f96f9d4de2 382 /**
<> 154:37f96f9d4de2 383 * @brief Get Standby Flag
<> 154:37f96f9d4de2 384 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
<> 154:37f96f9d4de2 385 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 386 */
<> 154:37f96f9d4de2 387 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
<> 154:37f96f9d4de2 388 {
<> 154:37f96f9d4de2 389 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
<> 154:37f96f9d4de2 390 }
<> 154:37f96f9d4de2 391
<> 154:37f96f9d4de2 392 /**
<> 154:37f96f9d4de2 393 * @brief Indicate whether VDD voltage is below the selected PVD threshold
<> 154:37f96f9d4de2 394 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
<> 154:37f96f9d4de2 395 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 396 */
<> 154:37f96f9d4de2 397 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
<> 154:37f96f9d4de2 398 {
<> 154:37f96f9d4de2 399 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
<> 154:37f96f9d4de2 400 }
<> 154:37f96f9d4de2 401
<> 154:37f96f9d4de2 402 /**
<> 154:37f96f9d4de2 403 * @brief Clear Standby Flag
<> 154:37f96f9d4de2 404 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
<> 154:37f96f9d4de2 405 * @retval None
<> 154:37f96f9d4de2 406 */
<> 154:37f96f9d4de2 407 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
<> 154:37f96f9d4de2 408 {
<> 154:37f96f9d4de2 409 SET_BIT(PWR->CR, PWR_CR_CSBF);
<> 154:37f96f9d4de2 410 }
<> 154:37f96f9d4de2 411
<> 154:37f96f9d4de2 412 /**
<> 154:37f96f9d4de2 413 * @brief Clear Wake-up Flags
<> 154:37f96f9d4de2 414 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
<> 154:37f96f9d4de2 415 * @retval None
<> 154:37f96f9d4de2 416 */
<> 154:37f96f9d4de2 417 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
<> 154:37f96f9d4de2 418 {
<> 154:37f96f9d4de2 419 SET_BIT(PWR->CR, PWR_CR_CWUF);
<> 154:37f96f9d4de2 420 }
AnnaBridge 165:e614a9f1c9e2 421
AnnaBridge 165:e614a9f1c9e2 422 /**
AnnaBridge 165:e614a9f1c9e2 423 * @}
AnnaBridge 165:e614a9f1c9e2 424 */
AnnaBridge 165:e614a9f1c9e2 425
<> 154:37f96f9d4de2 426 #if defined(USE_FULL_LL_DRIVER)
<> 154:37f96f9d4de2 427 /** @defgroup PWR_LL_EF_Init De-initialization function
<> 154:37f96f9d4de2 428 * @{
<> 154:37f96f9d4de2 429 */
<> 154:37f96f9d4de2 430 ErrorStatus LL_PWR_DeInit(void);
<> 154:37f96f9d4de2 431 /**
<> 154:37f96f9d4de2 432 * @}
<> 154:37f96f9d4de2 433 */
<> 154:37f96f9d4de2 434 #endif /* USE_FULL_LL_DRIVER */
<> 154:37f96f9d4de2 435
<> 154:37f96f9d4de2 436 /**
<> 154:37f96f9d4de2 437 * @}
<> 154:37f96f9d4de2 438 */
<> 154:37f96f9d4de2 439
<> 154:37f96f9d4de2 440 /**
<> 154:37f96f9d4de2 441 * @}
<> 154:37f96f9d4de2 442 */
<> 154:37f96f9d4de2 443
<> 154:37f96f9d4de2 444 #endif /* defined(PWR) */
<> 154:37f96f9d4de2 445
<> 154:37f96f9d4de2 446 /**
<> 154:37f96f9d4de2 447 * @}
<> 154:37f96f9d4de2 448 */
<> 154:37f96f9d4de2 449
<> 154:37f96f9d4de2 450 #ifdef __cplusplus
<> 154:37f96f9d4de2 451 }
<> 154:37f96f9d4de2 452 #endif
<> 154:37f96f9d4de2 453
<> 154:37f96f9d4de2 454 #endif /* __STM32F1xx_LL_PWR_H */
<> 154:37f96f9d4de2 455
<> 154:37f96f9d4de2 456 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/