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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	154:37f96f9d4de2	1	/**
<>	154:37f96f9d4de2	2	******************************************************************************
<>	154:37f96f9d4de2	3	* @file stm32f1xx_ll_gpio.h
<>	154:37f96f9d4de2	4	* @author MCD Application Team
<>	154:37f96f9d4de2	5	* @brief Header file of GPIO LL module.
<>	154:37f96f9d4de2	6	******************************************************************************
<>	154:37f96f9d4de2	7	* @attention
<>	154:37f96f9d4de2	8	*
<>	154:37f96f9d4de2	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	154:37f96f9d4de2	10	*
<>	154:37f96f9d4de2	11	* Redistribution and use in source and binary forms, with or without modification,
<>	154:37f96f9d4de2	12	* are permitted provided that the following conditions are met:
<>	154:37f96f9d4de2	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	154:37f96f9d4de2	14	* this list of conditions and the following disclaimer.
<>	154:37f96f9d4de2	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	154:37f96f9d4de2	16	* this list of conditions and the following disclaimer in the documentation
<>	154:37f96f9d4de2	17	* and/or other materials provided with the distribution.
<>	154:37f96f9d4de2	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	154:37f96f9d4de2	19	* may be used to endorse or promote products derived from this software
<>	154:37f96f9d4de2	20	* without specific prior written permission.
<>	154:37f96f9d4de2	21	*
<>	154:37f96f9d4de2	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	154:37f96f9d4de2	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	154:37f96f9d4de2	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	154:37f96f9d4de2	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	154:37f96f9d4de2	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	154:37f96f9d4de2	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	154:37f96f9d4de2	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	154:37f96f9d4de2	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	154:37f96f9d4de2	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	154:37f96f9d4de2	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	154:37f96f9d4de2	32	*
<>	154:37f96f9d4de2	33	******************************************************************************
<>	154:37f96f9d4de2	34	*/
<>	154:37f96f9d4de2	35
<>	154:37f96f9d4de2	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	154:37f96f9d4de2	37	#ifndef __STM32F1xx_LL_GPIO_H
<>	154:37f96f9d4de2	38	#define __STM32F1xx_LL_GPIO_H
<>	154:37f96f9d4de2	39
<>	154:37f96f9d4de2	40	#ifdef __cplusplus
<>	154:37f96f9d4de2	41	extern "C" {
<>	154:37f96f9d4de2	42	#endif
<>	154:37f96f9d4de2	43
<>	154:37f96f9d4de2	44	/* Includes ------------------------------------------------------------------*/
<>	154:37f96f9d4de2	45	#include "stm32f1xx.h"
<>	154:37f96f9d4de2	46
<>	154:37f96f9d4de2	47	/** @addtogroup STM32F1xx_LL_Driver
<>	154:37f96f9d4de2	48	* @{
<>	154:37f96f9d4de2	49	*/
<>	154:37f96f9d4de2	50
<>	154:37f96f9d4de2	51	#if defined (GPIOA) \|\| defined (GPIOB) \|\| defined (GPIOC) \|\| defined (GPIOD) \|\| defined (GPIOE) \|\| defined (GPIOF) \|\| defined (GPIOG)
<>	154:37f96f9d4de2	52
<>	154:37f96f9d4de2	53	/** @defgroup GPIO_LL GPIO
<>	154:37f96f9d4de2	54	* @{
<>	154:37f96f9d4de2	55	*/
<>	154:37f96f9d4de2	56
<>	154:37f96f9d4de2	57	/* Private types -------------------------------------------------------------*/
<>	154:37f96f9d4de2	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	187:0387e8f68319	59	/* Private constants ---------------------------------------------------------*/
<>	154:37f96f9d4de2	60
<>	154:37f96f9d4de2	61	/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
<>	154:37f96f9d4de2	62	* @{
<>	154:37f96f9d4de2	63	*/
AnnaBridge	187:0387e8f68319	64	/* Defines used for Pin Mask Initialization */
AnnaBridge	187:0387e8f68319	65	#define GPIO_PIN_MASK_POS 8U
AnnaBridge	187:0387e8f68319	66	#define GPIO_PIN_NB 16U
<>	154:37f96f9d4de2	67	/**
<>	154:37f96f9d4de2	68	* @}
<>	154:37f96f9d4de2	69	*/
<>	154:37f96f9d4de2	70
<>	154:37f96f9d4de2	71	/* Private macros ------------------------------------------------------------*/
<>	154:37f96f9d4de2	72	#if defined(USE_FULL_LL_DRIVER)
<>	154:37f96f9d4de2	73	/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
<>	154:37f96f9d4de2	74	* @{
<>	154:37f96f9d4de2	75	*/
<>	154:37f96f9d4de2	76
<>	154:37f96f9d4de2	77	/**
<>	154:37f96f9d4de2	78	* @}
<>	154:37f96f9d4de2	79	*/
<>	154:37f96f9d4de2	80	#endif /USE_FULL_LL_DRIVER/
<>	154:37f96f9d4de2	81
<>	154:37f96f9d4de2	82	/* Exported types ------------------------------------------------------------*/
<>	154:37f96f9d4de2	83	#if defined(USE_FULL_LL_DRIVER)
<>	154:37f96f9d4de2	84	/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
<>	154:37f96f9d4de2	85	* @{
<>	154:37f96f9d4de2	86	*/
<>	154:37f96f9d4de2	87
<>	154:37f96f9d4de2	88	/**
<>	154:37f96f9d4de2	89	* @brief LL GPIO Init Structure definition
<>	154:37f96f9d4de2	90	*/
<>	154:37f96f9d4de2	91	typedef struct
<>	154:37f96f9d4de2	92	{
<>	154:37f96f9d4de2	93	uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
<>	154:37f96f9d4de2	94	This parameter can be any value of @ref GPIO_LL_EC_PIN */
<>	154:37f96f9d4de2	95
<>	154:37f96f9d4de2	96	uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
<>	154:37f96f9d4de2	97	This parameter can be a value of @ref GPIO_LL_EC_MODE.
<>	154:37f96f9d4de2	98
<>	154:37f96f9d4de2	99	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
<>	154:37f96f9d4de2	100
<>	154:37f96f9d4de2	101	uint32_t Speed; /*!< Specifies the speed for the selected pins.
<>	154:37f96f9d4de2	102	This parameter can be a value of @ref GPIO_LL_EC_SPEED.
<>	154:37f96f9d4de2	103
<>	154:37f96f9d4de2	104	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
<>	154:37f96f9d4de2	105
<>	154:37f96f9d4de2	106	uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
<>	154:37f96f9d4de2	107	This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
<>	154:37f96f9d4de2	108
<>	154:37f96f9d4de2	109	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
<>	154:37f96f9d4de2	110
<>	154:37f96f9d4de2	111	uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
<>	154:37f96f9d4de2	112	This parameter can be a value of @ref GPIO_LL_EC_PULL.
<>	154:37f96f9d4de2	113
<>	154:37f96f9d4de2	114	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
AnnaBridge	187:0387e8f68319	115	} LL_GPIO_InitTypeDef;
<>	154:37f96f9d4de2	116
<>	154:37f96f9d4de2	117	/**
<>	154:37f96f9d4de2	118	* @}
<>	154:37f96f9d4de2	119	*/
<>	154:37f96f9d4de2	120	#endif /* USE_FULL_LL_DRIVER */
<>	154:37f96f9d4de2	121
<>	154:37f96f9d4de2	122	/* Exported constants --------------------------------------------------------*/
<>	154:37f96f9d4de2	123	/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
<>	154:37f96f9d4de2	124	* @{
<>	154:37f96f9d4de2	125	*/
<>	154:37f96f9d4de2	126
<>	154:37f96f9d4de2	127	/** @defgroup GPIO_LL_EC_PIN PIN
<>	154:37f96f9d4de2	128	* @{
<>	154:37f96f9d4de2	129	*/
AnnaBridge	187:0387e8f68319	130	#define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) \| 0x00000001U) /!< Select pin 0 /
AnnaBridge	187:0387e8f68319	131	#define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) \| 0x00000002U) /!< Select pin 1 /
AnnaBridge	187:0387e8f68319	132	#define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) \| 0x00000004U) /!< Select pin 2 /
AnnaBridge	187:0387e8f68319	133	#define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) \| 0x00000008U) /!< Select pin 3 /
AnnaBridge	187:0387e8f68319	134	#define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) \| 0x00000010U) /!< Select pin 4 /
AnnaBridge	187:0387e8f68319	135	#define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) \| 0x00000020U) /!< Select pin 5 /
AnnaBridge	187:0387e8f68319	136	#define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) \| 0x00000040U) /!< Select pin 6 /
AnnaBridge	187:0387e8f68319	137	#define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) \| 0x00000080U) /!< Select pin 7 /
AnnaBridge	187:0387e8f68319	138	#define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) \| 0x04000001U) /!< Select pin 8 /
AnnaBridge	187:0387e8f68319	139	#define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) \| 0x04000002U) /!< Select pin 9 /
AnnaBridge	187:0387e8f68319	140	#define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) \| 0x04000004U) /!< Select pin 10 /
AnnaBridge	187:0387e8f68319	141	#define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) \| 0x04000008U) /!< Select pin 11 /
AnnaBridge	187:0387e8f68319	142	#define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) \| 0x04000010U) /!< Select pin 12 /
AnnaBridge	187:0387e8f68319	143	#define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) \| 0x04000020U) /!< Select pin 13 /
AnnaBridge	187:0387e8f68319	144	#define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) \| 0x04000040U) /!< Select pin 14 /
AnnaBridge	187:0387e8f68319	145	#define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) \| 0x04000080U) /!< Select pin 15 /
AnnaBridge	165:e614a9f1c9e2	146	#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 \| LL_GPIO_PIN_1 \| LL_GPIO_PIN_2 \| \
AnnaBridge	165:e614a9f1c9e2	147	LL_GPIO_PIN_3 \| LL_GPIO_PIN_4 \| LL_GPIO_PIN_5 \| \
AnnaBridge	165:e614a9f1c9e2	148	LL_GPIO_PIN_6 \| LL_GPIO_PIN_7 \| LL_GPIO_PIN_8 \| \
AnnaBridge	165:e614a9f1c9e2	149	LL_GPIO_PIN_9 \| LL_GPIO_PIN_10 \| LL_GPIO_PIN_11 \| \
AnnaBridge	165:e614a9f1c9e2	150	LL_GPIO_PIN_12 \| LL_GPIO_PIN_13 \| LL_GPIO_PIN_14 \| \
AnnaBridge	187:0387e8f68319	151	LL_GPIO_PIN_15) /!< Select all pins /
<>	154:37f96f9d4de2	152	/**
<>	154:37f96f9d4de2	153	* @}
<>	154:37f96f9d4de2	154	*/
<>	154:37f96f9d4de2	155
<>	154:37f96f9d4de2	156	/** @defgroup GPIO_LL_EC_MODE Mode
<>	154:37f96f9d4de2	157	* @{
<>	154:37f96f9d4de2	158	*/
AnnaBridge	187:0387e8f68319	159	#define LL_GPIO_MODE_ANALOG 0x00000000U /!< Select analog mode /
AnnaBridge	187:0387e8f68319	160	#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /!< Select floating mode /
AnnaBridge	187:0387e8f68319	161	#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /!< Select input mode /
AnnaBridge	187:0387e8f68319	162	#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /!< Select general purpose output mode /
AnnaBridge	187:0387e8f68319	163	#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 \| GPIO_CRL_MODE0_0) /!< Select alternate function mode /
<>	154:37f96f9d4de2	164	/**
<>	154:37f96f9d4de2	165	* @}
<>	154:37f96f9d4de2	166	*/
<>	154:37f96f9d4de2	167
<>	154:37f96f9d4de2	168	/** @defgroup GPIO_LL_EC_OUTPUT Output Type
<>	154:37f96f9d4de2	169	* @{
<>	154:37f96f9d4de2	170	*/
AnnaBridge	187:0387e8f68319	171	#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /!< Select push-pull as output type /
AnnaBridge	187:0387e8f68319	172	#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /!< Select open-drain as output type /
<>	154:37f96f9d4de2	173	/**
<>	154:37f96f9d4de2	174	* @}
<>	154:37f96f9d4de2	175	*/
<>	154:37f96f9d4de2	176
<>	154:37f96f9d4de2	177	/** @defgroup GPIO_LL_EC_SPEED Output Speed
<>	154:37f96f9d4de2	178	* @{
<>	154:37f96f9d4de2	179	*/
AnnaBridge	187:0387e8f68319	180	#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /!< Select Output mode, max speed 10 MHz /
AnnaBridge	187:0387e8f68319	181	#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /!< Select Output mode, max speed 20 MHz /
AnnaBridge	187:0387e8f68319	182	#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /!< Select Output mode, max speed 50 MHz /
<>	154:37f96f9d4de2	183	/**
<>	154:37f96f9d4de2	184	* @}
<>	154:37f96f9d4de2	185	*/
AnnaBridge	187:0387e8f68319	186
<>	154:37f96f9d4de2	187	#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /!< Select I/O low output speed /
<>	154:37f96f9d4de2	188	#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /!< Select I/O medium output speed /
<>	154:37f96f9d4de2	189	#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /!< Select I/O high output speed /
<>	154:37f96f9d4de2	190
<>	154:37f96f9d4de2	191	/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
<>	154:37f96f9d4de2	192	* @{
<>	154:37f96f9d4de2	193	*/
AnnaBridge	187:0387e8f68319	194	#define LL_GPIO_PULL_DOWN 0x00000000U /!< Select I/O pull down /
AnnaBridge	187:0387e8f68319	195	#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /!< Select I/O pull up /
<>	154:37f96f9d4de2	196
<>	154:37f96f9d4de2	197	/**
<>	154:37f96f9d4de2	198	* @}
<>	154:37f96f9d4de2	199	*/
AnnaBridge	187:0387e8f68319	200
<>	154:37f96f9d4de2	201	/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
<>	154:37f96f9d4de2	202	* @{
<>	154:37f96f9d4de2	203	*/
<>	154:37f96f9d4de2	204
AnnaBridge	165:e614a9f1c9e2	205	#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /!< EVENTOUT on pin 0 /
AnnaBridge	165:e614a9f1c9e2	206	#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /!< EVENTOUT on pin 1 /
AnnaBridge	165:e614a9f1c9e2	207	#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /!< EVENTOUT on pin 2 /
AnnaBridge	165:e614a9f1c9e2	208	#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /!< EVENTOUT on pin 3 /
AnnaBridge	165:e614a9f1c9e2	209	#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /!< EVENTOUT on pin 4 /
AnnaBridge	165:e614a9f1c9e2	210	#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /!< EVENTOUT on pin 5 /
AnnaBridge	165:e614a9f1c9e2	211	#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /!< EVENTOUT on pin 6 /
AnnaBridge	165:e614a9f1c9e2	212	#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /!< EVENTOUT on pin 7 /
AnnaBridge	165:e614a9f1c9e2	213	#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /!< EVENTOUT on pin 8 /
AnnaBridge	165:e614a9f1c9e2	214	#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /!< EVENTOUT on pin 9 /
AnnaBridge	165:e614a9f1c9e2	215	#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /!< EVENTOUT on pin 10 /
AnnaBridge	165:e614a9f1c9e2	216	#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /!< EVENTOUT on pin 11 /
AnnaBridge	165:e614a9f1c9e2	217	#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /!< EVENTOUT on pin 12 /
AnnaBridge	165:e614a9f1c9e2	218	#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /!< EVENTOUT on pin 13 /
AnnaBridge	165:e614a9f1c9e2	219	#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /!< EVENTOUT on pin 14 /
AnnaBridge	165:e614a9f1c9e2	220	#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /!< EVENTOUT on pin 15 /
<>	154:37f96f9d4de2	221
<>	154:37f96f9d4de2	222	/**
<>	154:37f96f9d4de2	223	* @}
<>	154:37f96f9d4de2	224	*/
<>	154:37f96f9d4de2	225
<>	154:37f96f9d4de2	226	/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
<>	154:37f96f9d4de2	227	* @{
<>	154:37f96f9d4de2	228	*/
<>	154:37f96f9d4de2	229
AnnaBridge	165:e614a9f1c9e2	230	#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /!< EVENTOUT on port A /
AnnaBridge	165:e614a9f1c9e2	231	#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /!< EVENTOUT on port B /
AnnaBridge	165:e614a9f1c9e2	232	#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /!< EVENTOUT on port C /
AnnaBridge	165:e614a9f1c9e2	233	#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /!< EVENTOUT on port D /
AnnaBridge	165:e614a9f1c9e2	234	#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /!< EVENTOUT on port E /
<>	154:37f96f9d4de2	235
<>	154:37f96f9d4de2	236	/**
<>	154:37f96f9d4de2	237	* @}
<>	154:37f96f9d4de2	238	*/
<>	154:37f96f9d4de2	239
<>	154:37f96f9d4de2	240	/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
<>	154:37f96f9d4de2	241	* @{
<>	154:37f96f9d4de2	242	*/
AnnaBridge	187:0387e8f68319	243	#define LL_GPIO_AF_EXTI_PORTA 0U /!< EXTI PORT A /
AnnaBridge	187:0387e8f68319	244	#define LL_GPIO_AF_EXTI_PORTB 1U /!< EXTI PORT B /
AnnaBridge	187:0387e8f68319	245	#define LL_GPIO_AF_EXTI_PORTC 2U /!< EXTI PORT C /
AnnaBridge	187:0387e8f68319	246	#define LL_GPIO_AF_EXTI_PORTD 3U /!< EXTI PORT D /
AnnaBridge	187:0387e8f68319	247	#define LL_GPIO_AF_EXTI_PORTE 4U /!< EXTI PORT E /
AnnaBridge	187:0387e8f68319	248	#define LL_GPIO_AF_EXTI_PORTF 5U /!< EXTI PORT F /
AnnaBridge	187:0387e8f68319	249	#define LL_GPIO_AF_EXTI_PORTG 6U /!< EXTI PORT G /
<>	154:37f96f9d4de2	250	/**
<>	154:37f96f9d4de2	251	* @}
<>	154:37f96f9d4de2	252	*/
<>	154:37f96f9d4de2	253
<>	154:37f96f9d4de2	254	/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
<>	154:37f96f9d4de2	255	* @{
<>	154:37f96f9d4de2	256	*/
AnnaBridge	187:0387e8f68319	257	#define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
AnnaBridge	187:0387e8f68319	258	#define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
AnnaBridge	187:0387e8f68319	259	#define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
AnnaBridge	187:0387e8f68319	260	#define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
AnnaBridge	187:0387e8f68319	261	#define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
AnnaBridge	187:0387e8f68319	262	#define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
AnnaBridge	187:0387e8f68319	263	#define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
AnnaBridge	187:0387e8f68319	264	#define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
AnnaBridge	187:0387e8f68319	265	#define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
AnnaBridge	187:0387e8f68319	266	#define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
AnnaBridge	187:0387e8f68319	267	#define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
AnnaBridge	187:0387e8f68319	268	#define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
AnnaBridge	187:0387e8f68319	269	#define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
AnnaBridge	187:0387e8f68319	270	#define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
AnnaBridge	187:0387e8f68319	271	#define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
AnnaBridge	187:0387e8f68319	272	#define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
<>	154:37f96f9d4de2	273	/**
<>	154:37f96f9d4de2	274	* @}
<>	154:37f96f9d4de2	275	*/
<>	154:37f96f9d4de2	276
<>	154:37f96f9d4de2	277	/**
<>	154:37f96f9d4de2	278	* @}
<>	154:37f96f9d4de2	279	*/
<>	154:37f96f9d4de2	280
<>	154:37f96f9d4de2	281	/* Exported macro ------------------------------------------------------------*/
<>	154:37f96f9d4de2	282	/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
<>	154:37f96f9d4de2	283	* @{
<>	154:37f96f9d4de2	284	*/
<>	154:37f96f9d4de2	285
<>	154:37f96f9d4de2	286	/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
<>	154:37f96f9d4de2	287	* @{
<>	154:37f96f9d4de2	288	*/
<>	154:37f96f9d4de2	289
<>	154:37f96f9d4de2	290	/**
<>	154:37f96f9d4de2	291	* @brief Write a value in GPIO register
<>	154:37f96f9d4de2	292	* @param __INSTANCE__ GPIO Instance
<>	154:37f96f9d4de2	293	* @param __REG__ Register to be written
<>	154:37f96f9d4de2	294	* @param __VALUE__ Value to be written in the register
<>	154:37f96f9d4de2	295	* @retval None
<>	154:37f96f9d4de2	296	*/
<>	154:37f96f9d4de2	297	#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	154:37f96f9d4de2	298
<>	154:37f96f9d4de2	299	/**
<>	154:37f96f9d4de2	300	* @brief Read a value in GPIO register
<>	154:37f96f9d4de2	301	* @param __INSTANCE__ GPIO Instance
<>	154:37f96f9d4de2	302	* @param __REG__ Register to be read
<>	154:37f96f9d4de2	303	* @retval Register value
<>	154:37f96f9d4de2	304	*/
<>	154:37f96f9d4de2	305	#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	154:37f96f9d4de2	306	/**
<>	154:37f96f9d4de2	307	* @}
<>	154:37f96f9d4de2	308	*/
<>	154:37f96f9d4de2	309
<>	154:37f96f9d4de2	310	/**
<>	154:37f96f9d4de2	311	* @}
<>	154:37f96f9d4de2	312	*/
<>	154:37f96f9d4de2	313
<>	154:37f96f9d4de2	314	/* Exported functions --------------------------------------------------------*/
<>	154:37f96f9d4de2	315	/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
<>	154:37f96f9d4de2	316	* @{
<>	154:37f96f9d4de2	317	*/
<>	154:37f96f9d4de2	318
<>	154:37f96f9d4de2	319	/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
<>	154:37f96f9d4de2	320	* @{
<>	154:37f96f9d4de2	321	*/
<>	154:37f96f9d4de2	322
<>	154:37f96f9d4de2	323	/**
<>	154:37f96f9d4de2	324	* @brief Configure gpio mode for a dedicated pin on dedicated port.
<>	154:37f96f9d4de2	325	* @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
<>	154:37f96f9d4de2	326	* Alternate function Output.
<>	154:37f96f9d4de2	327	* @note Warning: only one pin can be passed as parameter.
<>	154:37f96f9d4de2	328	* @rmtoll CRL CNFy LL_GPIO_SetPinMode
<>	154:37f96f9d4de2	329	* @rmtoll CRL MODEy LL_GPIO_SetPinMode
<>	154:37f96f9d4de2	330	* @rmtoll CRH CNFy LL_GPIO_SetPinMode
<>	154:37f96f9d4de2	331	* @rmtoll CRH MODEy LL_GPIO_SetPinMode
<>	154:37f96f9d4de2	332	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	333	* @param Pin This parameter can be one of the following values:
<>	154:37f96f9d4de2	334	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	335	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	336	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	337	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	338	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	339	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	340	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	341	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	342	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	343	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	344	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	345	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	346	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	347	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	348	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	349	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	350	* @param Mode This parameter can be one of the following values:
<>	154:37f96f9d4de2	351	* @arg @ref LL_GPIO_MODE_ANALOG
<>	154:37f96f9d4de2	352	* @arg @ref LL_GPIO_MODE_FLOATING
<>	154:37f96f9d4de2	353	* @arg @ref LL_GPIO_MODE_INPUT
<>	154:37f96f9d4de2	354	* @arg @ref LL_GPIO_MODE_OUTPUT
<>	154:37f96f9d4de2	355	* @arg @ref LL_GPIO_MODE_ALTERNATE
<>	154:37f96f9d4de2	356	* @retval None
<>	154:37f96f9d4de2	357	*/
<>	154:37f96f9d4de2	358	__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
<>	154:37f96f9d4de2	359	{
AnnaBridge	187:0387e8f68319	360	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	187:0387e8f68319	361	MODIFY_REG(pReg, ((GPIO_CRL_CNF0 \| GPIO_CRL_MODE0) << (POSITION_VAL(Pin) 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
<>	154:37f96f9d4de2	362	}
<>	154:37f96f9d4de2	363
<>	154:37f96f9d4de2	364	/**
<>	154:37f96f9d4de2	365	* @brief Return gpio mode for a dedicated pin on dedicated port.
<>	154:37f96f9d4de2	366	* @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
<>	154:37f96f9d4de2	367	* Alternate function Output.
<>	154:37f96f9d4de2	368	* @note Warning: only one pin can be passed as parameter.
<>	154:37f96f9d4de2	369	* @rmtoll CRL CNFy LL_GPIO_GetPinMode
<>	154:37f96f9d4de2	370	* @rmtoll CRL MODEy LL_GPIO_GetPinMode
<>	154:37f96f9d4de2	371	* @rmtoll CRH CNFy LL_GPIO_GetPinMode
<>	154:37f96f9d4de2	372	* @rmtoll CRH MODEy LL_GPIO_GetPinMode
<>	154:37f96f9d4de2	373	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	374	* @param Pin This parameter can be one of the following values:
<>	154:37f96f9d4de2	375	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	376	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	377	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	378	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	379	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	380	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	381	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	382	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	383	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	384	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	385	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	386	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	387	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	388	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	389	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	390	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	391	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	392	* @arg @ref LL_GPIO_MODE_ANALOG
<>	154:37f96f9d4de2	393	* @arg @ref LL_GPIO_MODE_FLOATING
<>	154:37f96f9d4de2	394	* @arg @ref LL_GPIO_MODE_INPUT
<>	154:37f96f9d4de2	395	* @arg @ref LL_GPIO_MODE_OUTPUT
<>	154:37f96f9d4de2	396	* @arg @ref LL_GPIO_MODE_ALTERNATE
<>	154:37f96f9d4de2	397	*/
<>	154:37f96f9d4de2	398	__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
<>	154:37f96f9d4de2	399	{
AnnaBridge	187:0387e8f68319	400	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	187:0387e8f68319	401	return (READ_BIT(pReg, ((GPIO_CRL_CNF0 \| GPIO_CRL_MODE0) << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
<>	154:37f96f9d4de2	402	}
<>	154:37f96f9d4de2	403
<>	154:37f96f9d4de2	404	/**
<>	154:37f96f9d4de2	405	* @brief Configure gpio speed for a dedicated pin on dedicated port.
<>	154:37f96f9d4de2	406	* @note I/O speed can be Low, Medium or Fast speed.
<>	154:37f96f9d4de2	407	* @note Warning: only one pin can be passed as parameter.
<>	154:37f96f9d4de2	408	* @note Refer to datasheet for frequency specifications and the power
<>	154:37f96f9d4de2	409	* supply and load conditions for each speed.
<>	154:37f96f9d4de2	410	* @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
<>	154:37f96f9d4de2	411	* @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
<>	154:37f96f9d4de2	412	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	413	* @param Pin This parameter can be one of the following values:
<>	154:37f96f9d4de2	414	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	415	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	416	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	417	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	418	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	419	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	420	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	421	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	422	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	423	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	424	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	425	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	426	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	427	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	428	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	429	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	430	* @param Speed This parameter can be one of the following values:
<>	154:37f96f9d4de2	431	* @arg @ref LL_GPIO_SPEED_FREQ_LOW
<>	154:37f96f9d4de2	432	* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
<>	154:37f96f9d4de2	433	* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
<>	154:37f96f9d4de2	434	* @retval None
<>	154:37f96f9d4de2	435	*/
<>	154:37f96f9d4de2	436	__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
<>	154:37f96f9d4de2	437	{
AnnaBridge	187:0387e8f68319	438	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
<>	154:37f96f9d4de2	439	MODIFY_REG(pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) 4U)),
<>	154:37f96f9d4de2	440	(Speed << (POSITION_VAL(Pin) * 4U)));
<>	154:37f96f9d4de2	441	}
<>	154:37f96f9d4de2	442
<>	154:37f96f9d4de2	443	/**
<>	154:37f96f9d4de2	444	* @brief Return gpio speed for a dedicated pin on dedicated port.
<>	154:37f96f9d4de2	445	* @note I/O speed can be Low, Medium, Fast or High speed.
<>	154:37f96f9d4de2	446	* @note Warning: only one pin can be passed as parameter.
<>	154:37f96f9d4de2	447	* @note Refer to datasheet for frequency specifications and the power
<>	154:37f96f9d4de2	448	* supply and load conditions for each speed.
<>	154:37f96f9d4de2	449	* @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
<>	154:37f96f9d4de2	450	* @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
<>	154:37f96f9d4de2	451	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	452	* @param Pin This parameter can be one of the following values:
<>	154:37f96f9d4de2	453	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	454	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	455	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	456	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	457	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	458	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	459	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	460	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	461	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	462	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	463	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	464	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	465	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	466	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	467	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	468	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	469	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	470	* @arg @ref LL_GPIO_SPEED_FREQ_LOW
<>	154:37f96f9d4de2	471	* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
<>	154:37f96f9d4de2	472	* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
<>	154:37f96f9d4de2	473	*/
<>	154:37f96f9d4de2	474	__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
<>	154:37f96f9d4de2	475	{
AnnaBridge	187:0387e8f68319	476	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	187:0387e8f68319	477	return (READ_BIT(pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
<>	154:37f96f9d4de2	478	}
<>	154:37f96f9d4de2	479
<>	154:37f96f9d4de2	480	/**
<>	154:37f96f9d4de2	481	* @brief Configure gpio output type for several pins on dedicated port.
<>	154:37f96f9d4de2	482	* @note Output type as to be set when gpio pin is in output or
<>	154:37f96f9d4de2	483	* alternate modes. Possible type are Push-pull or Open-drain.
<>	154:37f96f9d4de2	484	* @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
<>	154:37f96f9d4de2	485	* @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
<>	154:37f96f9d4de2	486	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	487	* @param Pin This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	488	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	489	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	490	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	491	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	492	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	493	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	494	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	495	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	496	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	497	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	498	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	499	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	500	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	501	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	502	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	503	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	504	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	505	* @param OutputType This parameter can be one of the following values:
<>	154:37f96f9d4de2	506	* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
<>	154:37f96f9d4de2	507	* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
<>	154:37f96f9d4de2	508	* @retval None
<>	154:37f96f9d4de2	509	*/
<>	154:37f96f9d4de2	510	__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
<>	154:37f96f9d4de2	511	{
AnnaBridge	187:0387e8f68319	512	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
<>	154:37f96f9d4de2	513	MODIFY_REG(pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) 4U)),
<>	154:37f96f9d4de2	514	(OutputType << (POSITION_VAL(Pin) * 4U)));
<>	154:37f96f9d4de2	515	}
<>	154:37f96f9d4de2	516
<>	154:37f96f9d4de2	517	/**
<>	154:37f96f9d4de2	518	* @brief Return gpio output type for several pins on dedicated port.
<>	154:37f96f9d4de2	519	* @note Output type as to be set when gpio pin is in output or
<>	154:37f96f9d4de2	520	* alternate modes. Possible type are Push-pull or Open-drain.
<>	154:37f96f9d4de2	521	* @note Warning: only one pin can be passed as parameter.
<>	154:37f96f9d4de2	522	* @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
<>	154:37f96f9d4de2	523	* @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
<>	154:37f96f9d4de2	524	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	525	* @param Pin This parameter can be one of the following values:
<>	154:37f96f9d4de2	526	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	527	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	528	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	529	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	530	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	531	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	532	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	533	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	534	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	535	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	536	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	537	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	538	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	539	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	540	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	541	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	542	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	543	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	544	* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
<>	154:37f96f9d4de2	545	* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
<>	154:37f96f9d4de2	546	*/
<>	154:37f96f9d4de2	547	__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
<>	154:37f96f9d4de2	548	{
AnnaBridge	187:0387e8f68319	549	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	187:0387e8f68319	550	return (READ_BIT(pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
<>	154:37f96f9d4de2	551
<>	154:37f96f9d4de2	552	}
<>	154:37f96f9d4de2	553
<>	154:37f96f9d4de2	554	/**
<>	154:37f96f9d4de2	555	* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
<>	154:37f96f9d4de2	556	* @note Warning: only one pin can be passed as parameter.
<>	154:37f96f9d4de2	557	* @rmtoll ODR ODR LL_GPIO_SetPinPull
<>	154:37f96f9d4de2	558	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	559	* @param Pin This parameter can be one of the following values:
<>	154:37f96f9d4de2	560	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	561	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	562	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	563	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	564	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	565	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	566	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	567	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	568	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	569	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	570	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	571	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	572	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	573	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	574	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	575	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	576	* @param Pull This parameter can be one of the following values:
<>	154:37f96f9d4de2	577	* @arg @ref LL_GPIO_PULL_DOWN
<>	154:37f96f9d4de2	578	* @arg @ref LL_GPIO_PULL_UP
<>	154:37f96f9d4de2	579	* @retval None
<>	154:37f96f9d4de2	580	*/
<>	154:37f96f9d4de2	581	__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
<>	154:37f96f9d4de2	582	{
AnnaBridge	187:0387e8f68319	583	MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
<>	154:37f96f9d4de2	584	}
<>	154:37f96f9d4de2	585
<>	154:37f96f9d4de2	586	/**
<>	154:37f96f9d4de2	587	* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
<>	154:37f96f9d4de2	588	* @note Warning: only one pin can be passed as parameter.
<>	154:37f96f9d4de2	589	* @rmtoll ODR ODR LL_GPIO_GetPinPull
<>	154:37f96f9d4de2	590	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	591	* @param Pin This parameter can be one of the following values:
<>	154:37f96f9d4de2	592	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	593	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	594	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	595	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	596	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	597	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	598	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	599	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	600	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	601	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	602	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	603	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	604	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	605	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	606	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	607	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	608	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	609	* @arg @ref LL_GPIO_PULL_DOWN
<>	154:37f96f9d4de2	610	* @arg @ref LL_GPIO_PULL_UP
<>	154:37f96f9d4de2	611	*/
<>	154:37f96f9d4de2	612	__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
<>	154:37f96f9d4de2	613	{
AnnaBridge	187:0387e8f68319	614	return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
<>	154:37f96f9d4de2	615	}
<>	154:37f96f9d4de2	616
<>	154:37f96f9d4de2	617	/**
<>	154:37f96f9d4de2	618	* @brief Lock configuration of several pins for a dedicated port.
<>	154:37f96f9d4de2	619	* @note When the lock sequence has been applied on a port bit, the
<>	154:37f96f9d4de2	620	* value of this port bit can no longer be modified until the
<>	154:37f96f9d4de2	621	* next reset.
<>	154:37f96f9d4de2	622	* @note Each lock bit freezes a specific configuration register
<>	154:37f96f9d4de2	623	* (control and alternate function registers).
<>	154:37f96f9d4de2	624	* @rmtoll LCKR LCKK LL_GPIO_LockPin
<>	154:37f96f9d4de2	625	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	626	* @param PinMask This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	627	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	628	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	629	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	630	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	631	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	632	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	633	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	634	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	635	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	636	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	637	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	638	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	639	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	640	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	641	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	642	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	643	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	644	* @retval None
<>	154:37f96f9d4de2	645	*/
<>	154:37f96f9d4de2	646	__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
<>	154:37f96f9d4de2	647	{
<>	154:37f96f9d4de2	648	__IO uint32_t temp;
AnnaBridge	187:0387e8f68319	649	WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK \| ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	187:0387e8f68319	650	WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	187:0387e8f68319	651	WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK \| ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
<>	154:37f96f9d4de2	652	temp = READ_REG(GPIOx->LCKR);
<>	154:37f96f9d4de2	653	(void) temp;
<>	154:37f96f9d4de2	654	}
<>	154:37f96f9d4de2	655
<>	154:37f96f9d4de2	656	/**
<>	154:37f96f9d4de2	657	* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
<>	154:37f96f9d4de2	658	* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
<>	154:37f96f9d4de2	659	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	660	* @param PinMask This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	661	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	662	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	663	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	664	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	665	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	666	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	667	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	668	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	669	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	670	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	671	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	672	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	673	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	674	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	675	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	676	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	677	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	678	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	679	*/
<>	154:37f96f9d4de2	680	__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
<>	154:37f96f9d4de2	681	{
AnnaBridge	187:0387e8f68319	682	return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
<>	154:37f96f9d4de2	683	}
<>	154:37f96f9d4de2	684
<>	154:37f96f9d4de2	685	/**
<>	154:37f96f9d4de2	686	* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
<>	154:37f96f9d4de2	687	* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
<>	154:37f96f9d4de2	688	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	689	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	690	*/
<>	154:37f96f9d4de2	691	__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
<>	154:37f96f9d4de2	692	{
<>	154:37f96f9d4de2	693	return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
<>	154:37f96f9d4de2	694	}
<>	154:37f96f9d4de2	695
<>	154:37f96f9d4de2	696	/**
<>	154:37f96f9d4de2	697	* @}
<>	154:37f96f9d4de2	698	*/
<>	154:37f96f9d4de2	699
<>	154:37f96f9d4de2	700	/** @defgroup GPIO_LL_EF_Data_Access Data Access
<>	154:37f96f9d4de2	701	* @{
<>	154:37f96f9d4de2	702	*/
<>	154:37f96f9d4de2	703
<>	154:37f96f9d4de2	704	/**
<>	154:37f96f9d4de2	705	* @brief Return full input data register value for a dedicated port.
<>	154:37f96f9d4de2	706	* @rmtoll IDR IDy LL_GPIO_ReadInputPort
<>	154:37f96f9d4de2	707	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	708	* @retval Input data register value of port
<>	154:37f96f9d4de2	709	*/
<>	154:37f96f9d4de2	710	__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
<>	154:37f96f9d4de2	711	{
AnnaBridge	187:0387e8f68319	712	return (READ_REG(GPIOx->IDR));
<>	154:37f96f9d4de2	713	}
<>	154:37f96f9d4de2	714
<>	154:37f96f9d4de2	715	/**
<>	154:37f96f9d4de2	716	* @brief Return if input data level for several pins of dedicated port is high or low.
<>	154:37f96f9d4de2	717	* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
<>	154:37f96f9d4de2	718	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	719	* @param PinMask This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	720	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	721	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	722	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	723	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	724	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	725	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	726	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	727	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	728	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	729	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	730	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	731	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	732	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	733	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	734	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	735	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	736	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	737	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	738	*/
<>	154:37f96f9d4de2	739	__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
<>	154:37f96f9d4de2	740	{
AnnaBridge	187:0387e8f68319	741	return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
<>	154:37f96f9d4de2	742	}
<>	154:37f96f9d4de2	743
<>	154:37f96f9d4de2	744	/**
<>	154:37f96f9d4de2	745	* @brief Write output data register for the port.
<>	154:37f96f9d4de2	746	* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
<>	154:37f96f9d4de2	747	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	748	* @param PortValue Level value for each pin of the port
<>	154:37f96f9d4de2	749	* @retval None
<>	154:37f96f9d4de2	750	*/
<>	154:37f96f9d4de2	751	__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
<>	154:37f96f9d4de2	752	{
<>	154:37f96f9d4de2	753	WRITE_REG(GPIOx->ODR, PortValue);
<>	154:37f96f9d4de2	754	}
<>	154:37f96f9d4de2	755
<>	154:37f96f9d4de2	756	/**
<>	154:37f96f9d4de2	757	* @brief Return full output data register value for a dedicated port.
<>	154:37f96f9d4de2	758	* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
<>	154:37f96f9d4de2	759	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	760	* @retval Output data register value of port
<>	154:37f96f9d4de2	761	*/
<>	154:37f96f9d4de2	762	__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
<>	154:37f96f9d4de2	763	{
<>	154:37f96f9d4de2	764	return (uint32_t)(READ_REG(GPIOx->ODR));
<>	154:37f96f9d4de2	765	}
<>	154:37f96f9d4de2	766
<>	154:37f96f9d4de2	767	/**
<>	154:37f96f9d4de2	768	* @brief Return if input data level for several pins of dedicated port is high or low.
<>	154:37f96f9d4de2	769	* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
<>	154:37f96f9d4de2	770	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	771	* @param PinMask This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	772	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	773	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	774	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	775	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	776	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	777	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	778	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	779	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	780	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	781	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	782	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	783	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	784	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	785	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	786	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	787	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	788	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	789	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	790	*/
<>	154:37f96f9d4de2	791	__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
<>	154:37f96f9d4de2	792	{
AnnaBridge	187:0387e8f68319	793	return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
<>	154:37f96f9d4de2	794	}
<>	154:37f96f9d4de2	795
<>	154:37f96f9d4de2	796	/**
<>	154:37f96f9d4de2	797	* @brief Set several pins to high level on dedicated gpio port.
<>	154:37f96f9d4de2	798	* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
<>	154:37f96f9d4de2	799	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	800	* @param PinMask This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	801	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	802	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	803	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	804	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	805	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	806	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	807	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	808	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	809	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	810	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	811	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	812	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	813	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	814	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	815	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	816	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	817	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	818	* @retval None
<>	154:37f96f9d4de2	819	*/
<>	154:37f96f9d4de2	820	__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
<>	154:37f96f9d4de2	821	{
AnnaBridge	187:0387e8f68319	822	WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
<>	154:37f96f9d4de2	823	}
<>	154:37f96f9d4de2	824
<>	154:37f96f9d4de2	825	/**
<>	154:37f96f9d4de2	826	* @brief Set several pins to low level on dedicated gpio port.
<>	154:37f96f9d4de2	827	* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
<>	154:37f96f9d4de2	828	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	829	* @param PinMask This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	830	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	831	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	832	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	833	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	834	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	835	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	836	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	837	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	838	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	839	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	840	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	841	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	842	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	843	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	844	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	845	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	846	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	847	* @retval None
<>	154:37f96f9d4de2	848	*/
<>	154:37f96f9d4de2	849	__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
<>	154:37f96f9d4de2	850	{
AnnaBridge	187:0387e8f68319	851	WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
<>	154:37f96f9d4de2	852	}
<>	154:37f96f9d4de2	853
<>	154:37f96f9d4de2	854	/**
<>	154:37f96f9d4de2	855	* @brief Toggle data value for several pin of dedicated port.
<>	154:37f96f9d4de2	856	* @rmtoll ODR ODy LL_GPIO_TogglePin
<>	154:37f96f9d4de2	857	* @param GPIOx GPIO Port
<>	154:37f96f9d4de2	858	* @param PinMask This parameter can be a combination of the following values:
<>	154:37f96f9d4de2	859	* @arg @ref LL_GPIO_PIN_0
<>	154:37f96f9d4de2	860	* @arg @ref LL_GPIO_PIN_1
<>	154:37f96f9d4de2	861	* @arg @ref LL_GPIO_PIN_2
<>	154:37f96f9d4de2	862	* @arg @ref LL_GPIO_PIN_3
<>	154:37f96f9d4de2	863	* @arg @ref LL_GPIO_PIN_4
<>	154:37f96f9d4de2	864	* @arg @ref LL_GPIO_PIN_5
<>	154:37f96f9d4de2	865	* @arg @ref LL_GPIO_PIN_6
<>	154:37f96f9d4de2	866	* @arg @ref LL_GPIO_PIN_7
<>	154:37f96f9d4de2	867	* @arg @ref LL_GPIO_PIN_8
<>	154:37f96f9d4de2	868	* @arg @ref LL_GPIO_PIN_9
<>	154:37f96f9d4de2	869	* @arg @ref LL_GPIO_PIN_10
<>	154:37f96f9d4de2	870	* @arg @ref LL_GPIO_PIN_11
<>	154:37f96f9d4de2	871	* @arg @ref LL_GPIO_PIN_12
<>	154:37f96f9d4de2	872	* @arg @ref LL_GPIO_PIN_13
<>	154:37f96f9d4de2	873	* @arg @ref LL_GPIO_PIN_14
<>	154:37f96f9d4de2	874	* @arg @ref LL_GPIO_PIN_15
<>	154:37f96f9d4de2	875	* @arg @ref LL_GPIO_PIN_ALL
<>	154:37f96f9d4de2	876	* @retval None
<>	154:37f96f9d4de2	877	*/
<>	154:37f96f9d4de2	878	__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
<>	154:37f96f9d4de2	879	{
AnnaBridge	187:0387e8f68319	880	WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
<>	154:37f96f9d4de2	881	}
<>	154:37f96f9d4de2	882
<>	154:37f96f9d4de2	883	/**
<>	154:37f96f9d4de2	884	* @}
<>	154:37f96f9d4de2	885	*/
<>	154:37f96f9d4de2	886
AnnaBridge	165:e614a9f1c9e2	887	/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
<>	154:37f96f9d4de2	888	* @brief This section propose definition to remap the alternate function to some other port/pins.
<>	154:37f96f9d4de2	889	* @{
<>	154:37f96f9d4de2	890	*/
<>	154:37f96f9d4de2	891
<>	154:37f96f9d4de2	892	/**
<>	154:37f96f9d4de2	893	* @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
AnnaBridge	165:e614a9f1c9e2	894	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
<>	154:37f96f9d4de2	895	* @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
<>	154:37f96f9d4de2	896	* @retval None
<>	154:37f96f9d4de2	897	*/
AnnaBridge	165:e614a9f1c9e2	898	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
<>	154:37f96f9d4de2	899	{
<>	154:37f96f9d4de2	900	SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
<>	154:37f96f9d4de2	901	}
<>	154:37f96f9d4de2	902
<>	154:37f96f9d4de2	903	/**
<>	154:37f96f9d4de2	904	* @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
AnnaBridge	165:e614a9f1c9e2	905	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
<>	154:37f96f9d4de2	906	* @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
<>	154:37f96f9d4de2	907	* @retval None
<>	154:37f96f9d4de2	908	*/
AnnaBridge	165:e614a9f1c9e2	909	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
<>	154:37f96f9d4de2	910	{
<>	154:37f96f9d4de2	911	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
<>	154:37f96f9d4de2	912	}
<>	154:37f96f9d4de2	913
<>	154:37f96f9d4de2	914	/**
AnnaBridge	165:e614a9f1c9e2	915	* @brief Check if SPI1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	916	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
AnnaBridge	165:e614a9f1c9e2	917	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	918	*/
AnnaBridge	165:e614a9f1c9e2	919	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
AnnaBridge	165:e614a9f1c9e2	920	{
AnnaBridge	165:e614a9f1c9e2	921	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
AnnaBridge	165:e614a9f1c9e2	922	}
AnnaBridge	165:e614a9f1c9e2	923
AnnaBridge	165:e614a9f1c9e2	924	/**
<>	154:37f96f9d4de2	925	* @brief Enable the remapping of I2C1 alternate function SCL and SDA.
AnnaBridge	165:e614a9f1c9e2	926	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
<>	154:37f96f9d4de2	927	* @note ENABLE: Remap (SCL/PB8, SDA/PB9)
<>	154:37f96f9d4de2	928	* @retval None
<>	154:37f96f9d4de2	929	*/
AnnaBridge	165:e614a9f1c9e2	930	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
<>	154:37f96f9d4de2	931	{
<>	154:37f96f9d4de2	932	SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
<>	154:37f96f9d4de2	933	}
<>	154:37f96f9d4de2	934
<>	154:37f96f9d4de2	935	/**
<>	154:37f96f9d4de2	936	* @brief Disable the remapping of I2C1 alternate function SCL and SDA.
AnnaBridge	165:e614a9f1c9e2	937	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
<>	154:37f96f9d4de2	938	* @note DISABLE: No remap (SCL/PB6, SDA/PB7)
<>	154:37f96f9d4de2	939	* @retval None
<>	154:37f96f9d4de2	940	*/
AnnaBridge	165:e614a9f1c9e2	941	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
<>	154:37f96f9d4de2	942	{
<>	154:37f96f9d4de2	943	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
<>	154:37f96f9d4de2	944	}
<>	154:37f96f9d4de2	945
<>	154:37f96f9d4de2	946	/**
AnnaBridge	165:e614a9f1c9e2	947	* @brief Check if I2C1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	948	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
AnnaBridge	165:e614a9f1c9e2	949	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	950	*/
AnnaBridge	165:e614a9f1c9e2	951	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
AnnaBridge	165:e614a9f1c9e2	952	{
AnnaBridge	165:e614a9f1c9e2	953	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
AnnaBridge	165:e614a9f1c9e2	954	}
AnnaBridge	165:e614a9f1c9e2	955
AnnaBridge	165:e614a9f1c9e2	956	/**
<>	154:37f96f9d4de2	957	* @brief Enable the remapping of USART1 alternate function TX and RX.
AnnaBridge	165:e614a9f1c9e2	958	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
<>	154:37f96f9d4de2	959	* @note ENABLE: Remap (TX/PB6, RX/PB7)
<>	154:37f96f9d4de2	960	* @retval None
<>	154:37f96f9d4de2	961	*/
AnnaBridge	165:e614a9f1c9e2	962	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
<>	154:37f96f9d4de2	963	{
<>	154:37f96f9d4de2	964	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
<>	154:37f96f9d4de2	965	}
<>	154:37f96f9d4de2	966
<>	154:37f96f9d4de2	967	/**
<>	154:37f96f9d4de2	968	* @brief Disable the remapping of USART1 alternate function TX and RX.
AnnaBridge	165:e614a9f1c9e2	969	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
<>	154:37f96f9d4de2	970	* @note DISABLE: No remap (TX/PA9, RX/PA10)
<>	154:37f96f9d4de2	971	* @retval None
<>	154:37f96f9d4de2	972	*/
AnnaBridge	165:e614a9f1c9e2	973	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
<>	154:37f96f9d4de2	974	{
<>	154:37f96f9d4de2	975	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
<>	154:37f96f9d4de2	976	}
<>	154:37f96f9d4de2	977
<>	154:37f96f9d4de2	978	/**
AnnaBridge	165:e614a9f1c9e2	979	* @brief Check if USART1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	980	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
AnnaBridge	165:e614a9f1c9e2	981	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	982	*/
AnnaBridge	165:e614a9f1c9e2	983	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
AnnaBridge	165:e614a9f1c9e2	984	{
AnnaBridge	165:e614a9f1c9e2	985	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
AnnaBridge	165:e614a9f1c9e2	986	}
AnnaBridge	165:e614a9f1c9e2	987
AnnaBridge	165:e614a9f1c9e2	988	/**
<>	154:37f96f9d4de2	989	* @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	165:e614a9f1c9e2	990	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
<>	154:37f96f9d4de2	991	* @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
<>	154:37f96f9d4de2	992	* @retval None
<>	154:37f96f9d4de2	993	*/
AnnaBridge	165:e614a9f1c9e2	994	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
<>	154:37f96f9d4de2	995	{
<>	154:37f96f9d4de2	996	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
<>	154:37f96f9d4de2	997	}
<>	154:37f96f9d4de2	998
<>	154:37f96f9d4de2	999	/**
<>	154:37f96f9d4de2	1000	* @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	165:e614a9f1c9e2	1001	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
<>	154:37f96f9d4de2	1002	* @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
<>	154:37f96f9d4de2	1003	* @retval None
<>	154:37f96f9d4de2	1004	*/
AnnaBridge	165:e614a9f1c9e2	1005	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
<>	154:37f96f9d4de2	1006	{
<>	154:37f96f9d4de2	1007	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
<>	154:37f96f9d4de2	1008	}
<>	154:37f96f9d4de2	1009
AnnaBridge	165:e614a9f1c9e2	1010	/**
AnnaBridge	165:e614a9f1c9e2	1011	* @brief Check if USART2 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1012	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
AnnaBridge	165:e614a9f1c9e2	1013	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1014	*/
AnnaBridge	165:e614a9f1c9e2	1015	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
AnnaBridge	165:e614a9f1c9e2	1016	{
AnnaBridge	165:e614a9f1c9e2	1017	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
AnnaBridge	165:e614a9f1c9e2	1018	}
AnnaBridge	165:e614a9f1c9e2	1019
<>	154:37f96f9d4de2	1020	#if defined (AFIO_MAPR_USART3_REMAP)
<>	154:37f96f9d4de2	1021	/**
<>	154:37f96f9d4de2	1022	* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	165:e614a9f1c9e2	1023	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
<>	154:37f96f9d4de2	1024	* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
<>	154:37f96f9d4de2	1025	* @retval None
<>	154:37f96f9d4de2	1026	*/
AnnaBridge	165:e614a9f1c9e2	1027	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
<>	154:37f96f9d4de2	1028	{
AnnaBridge	165:e614a9f1c9e2	1029	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
AnnaBridge	187:0387e8f68319	1030	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
<>	154:37f96f9d4de2	1031	}
<>	154:37f96f9d4de2	1032
<>	154:37f96f9d4de2	1033	/**
<>	154:37f96f9d4de2	1034	* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	165:e614a9f1c9e2	1035	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
<>	154:37f96f9d4de2	1036	* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
<>	154:37f96f9d4de2	1037	* @retval None
<>	154:37f96f9d4de2	1038	*/
AnnaBridge	165:e614a9f1c9e2	1039	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
<>	154:37f96f9d4de2	1040	{
AnnaBridge	165:e614a9f1c9e2	1041	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
AnnaBridge	187:0387e8f68319	1042	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
<>	154:37f96f9d4de2	1043	}
<>	154:37f96f9d4de2	1044
<>	154:37f96f9d4de2	1045	/**
<>	154:37f96f9d4de2	1046	* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	165:e614a9f1c9e2	1047	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
<>	154:37f96f9d4de2	1048	* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
<>	154:37f96f9d4de2	1049	* @retval None
<>	154:37f96f9d4de2	1050	*/
AnnaBridge	165:e614a9f1c9e2	1051	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
<>	154:37f96f9d4de2	1052	{
AnnaBridge	165:e614a9f1c9e2	1053	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
AnnaBridge	187:0387e8f68319	1054	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
<>	154:37f96f9d4de2	1055	}
<>	154:37f96f9d4de2	1056	#endif
<>	154:37f96f9d4de2	1057
<>	154:37f96f9d4de2	1058	/**
<>	154:37f96f9d4de2	1059	* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
AnnaBridge	165:e614a9f1c9e2	1060	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
<>	154:37f96f9d4de2	1061	* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
<>	154:37f96f9d4de2	1062	* @retval None
<>	154:37f96f9d4de2	1063	*/
AnnaBridge	165:e614a9f1c9e2	1064	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
<>	154:37f96f9d4de2	1065	{
AnnaBridge	165:e614a9f1c9e2	1066	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
AnnaBridge	187:0387e8f68319	1067	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
<>	154:37f96f9d4de2	1068	}
<>	154:37f96f9d4de2	1069
<>	154:37f96f9d4de2	1070	/**
<>	154:37f96f9d4de2	1071	* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
AnnaBridge	165:e614a9f1c9e2	1072	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
<>	154:37f96f9d4de2	1073	* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
<>	154:37f96f9d4de2	1074	* @retval None
<>	154:37f96f9d4de2	1075	*/
AnnaBridge	165:e614a9f1c9e2	1076	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
<>	154:37f96f9d4de2	1077	{
AnnaBridge	165:e614a9f1c9e2	1078	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
AnnaBridge	187:0387e8f68319	1079	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
<>	154:37f96f9d4de2	1080	}
<>	154:37f96f9d4de2	1081
<>	154:37f96f9d4de2	1082	/**
<>	154:37f96f9d4de2	1083	* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
AnnaBridge	165:e614a9f1c9e2	1084	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
<>	154:37f96f9d4de2	1085	* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
<>	154:37f96f9d4de2	1086	* @retval None
<>	154:37f96f9d4de2	1087	*/
AnnaBridge	165:e614a9f1c9e2	1088	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
<>	154:37f96f9d4de2	1089	{
AnnaBridge	165:e614a9f1c9e2	1090	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
AnnaBridge	187:0387e8f68319	1091	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
<>	154:37f96f9d4de2	1092	}
<>	154:37f96f9d4de2	1093
<>	154:37f96f9d4de2	1094	/**
<>	154:37f96f9d4de2	1095	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	165:e614a9f1c9e2	1096	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
<>	154:37f96f9d4de2	1097	* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
<>	154:37f96f9d4de2	1098	* @retval None
<>	154:37f96f9d4de2	1099	*/
AnnaBridge	165:e614a9f1c9e2	1100	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
<>	154:37f96f9d4de2	1101	{
AnnaBridge	165:e614a9f1c9e2	1102	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	187:0387e8f68319	1103	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
<>	154:37f96f9d4de2	1104	}
<>	154:37f96f9d4de2	1105
<>	154:37f96f9d4de2	1106	/**
<>	154:37f96f9d4de2	1107	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	165:e614a9f1c9e2	1108	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
<>	154:37f96f9d4de2	1109	* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
<>	154:37f96f9d4de2	1110	* @retval None
<>	154:37f96f9d4de2	1111	*/
AnnaBridge	165:e614a9f1c9e2	1112	__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
<>	154:37f96f9d4de2	1113	{
AnnaBridge	165:e614a9f1c9e2	1114	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	187:0387e8f68319	1115	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
<>	154:37f96f9d4de2	1116	}
<>	154:37f96f9d4de2	1117
<>	154:37f96f9d4de2	1118	/**
<>	154:37f96f9d4de2	1119	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	165:e614a9f1c9e2	1120	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
<>	154:37f96f9d4de2	1121	* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
<>	154:37f96f9d4de2	1122	* @retval None
<>	154:37f96f9d4de2	1123	*/
AnnaBridge	165:e614a9f1c9e2	1124	__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
<>	154:37f96f9d4de2	1125	{
AnnaBridge	165:e614a9f1c9e2	1126	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	187:0387e8f68319	1127	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
<>	154:37f96f9d4de2	1128	}
<>	154:37f96f9d4de2	1129
<>	154:37f96f9d4de2	1130	/**
<>	154:37f96f9d4de2	1131	* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	165:e614a9f1c9e2	1132	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
<>	154:37f96f9d4de2	1133	* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
<>	154:37f96f9d4de2	1134	* @retval None
<>	154:37f96f9d4de2	1135	*/
AnnaBridge	165:e614a9f1c9e2	1136	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
<>	154:37f96f9d4de2	1137	{
AnnaBridge	165:e614a9f1c9e2	1138	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	187:0387e8f68319	1139	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
<>	154:37f96f9d4de2	1140	}
<>	154:37f96f9d4de2	1141
<>	154:37f96f9d4de2	1142	/**
<>	154:37f96f9d4de2	1143	* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
AnnaBridge	165:e614a9f1c9e2	1144	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
<>	154:37f96f9d4de2	1145	* @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
<>	154:37f96f9d4de2	1146	* @note TIM3_ETR on PE0 is not re-mapped.
<>	154:37f96f9d4de2	1147	* @retval None
<>	154:37f96f9d4de2	1148	*/
AnnaBridge	165:e614a9f1c9e2	1149	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
<>	154:37f96f9d4de2	1150	{
AnnaBridge	165:e614a9f1c9e2	1151	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
AnnaBridge	187:0387e8f68319	1152	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
<>	154:37f96f9d4de2	1153	}
<>	154:37f96f9d4de2	1154
<>	154:37f96f9d4de2	1155	/**
<>	154:37f96f9d4de2	1156	* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
AnnaBridge	165:e614a9f1c9e2	1157	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
<>	154:37f96f9d4de2	1158	* @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
<>	154:37f96f9d4de2	1159	* @note TIM3_ETR on PE0 is not re-mapped.
<>	154:37f96f9d4de2	1160	* @retval None
<>	154:37f96f9d4de2	1161	*/
AnnaBridge	165:e614a9f1c9e2	1162	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
<>	154:37f96f9d4de2	1163	{
AnnaBridge	165:e614a9f1c9e2	1164	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
AnnaBridge	187:0387e8f68319	1165	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
<>	154:37f96f9d4de2	1166	}
<>	154:37f96f9d4de2	1167
<>	154:37f96f9d4de2	1168	/**
<>	154:37f96f9d4de2	1169	* @brief Disable the remapping of TIM3 alternate function channels 1 to 4
AnnaBridge	165:e614a9f1c9e2	1170	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
<>	154:37f96f9d4de2	1171	* @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
<>	154:37f96f9d4de2	1172	* @note TIM3_ETR on PE0 is not re-mapped.
<>	154:37f96f9d4de2	1173	* @retval None
<>	154:37f96f9d4de2	1174	*/
AnnaBridge	165:e614a9f1c9e2	1175	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
<>	154:37f96f9d4de2	1176	{
AnnaBridge	165:e614a9f1c9e2	1177	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
AnnaBridge	187:0387e8f68319	1178	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
<>	154:37f96f9d4de2	1179	}
<>	154:37f96f9d4de2	1180
<>	154:37f96f9d4de2	1181	#if defined(AFIO_MAPR_TIM4_REMAP)
<>	154:37f96f9d4de2	1182	/**
<>	154:37f96f9d4de2	1183	* @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
AnnaBridge	165:e614a9f1c9e2	1184	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
<>	154:37f96f9d4de2	1185	* @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
<>	154:37f96f9d4de2	1186	* @note TIM4_ETR on PE0 is not re-mapped.
<>	154:37f96f9d4de2	1187	* @retval None
<>	154:37f96f9d4de2	1188	*/
AnnaBridge	165:e614a9f1c9e2	1189	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
<>	154:37f96f9d4de2	1190	{
<>	154:37f96f9d4de2	1191	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
<>	154:37f96f9d4de2	1192	}
<>	154:37f96f9d4de2	1193	/**
<>	154:37f96f9d4de2	1194	* @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
AnnaBridge	165:e614a9f1c9e2	1195	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
<>	154:37f96f9d4de2	1196	* @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
<>	154:37f96f9d4de2	1197	* @note TIM4_ETR on PE0 is not re-mapped.
<>	154:37f96f9d4de2	1198	* @retval None
<>	154:37f96f9d4de2	1199	*/
AnnaBridge	165:e614a9f1c9e2	1200	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
<>	154:37f96f9d4de2	1201	{
<>	154:37f96f9d4de2	1202	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
<>	154:37f96f9d4de2	1203	}
AnnaBridge	165:e614a9f1c9e2	1204
AnnaBridge	165:e614a9f1c9e2	1205	/**
AnnaBridge	165:e614a9f1c9e2	1206	* @brief Check if TIM4 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1207	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
AnnaBridge	165:e614a9f1c9e2	1208	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1209	*/
AnnaBridge	165:e614a9f1c9e2	1210	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
AnnaBridge	165:e614a9f1c9e2	1211	{
AnnaBridge	165:e614a9f1c9e2	1212	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
AnnaBridge	165:e614a9f1c9e2	1213	}
<>	154:37f96f9d4de2	1214	#endif
<>	154:37f96f9d4de2	1215
<>	154:37f96f9d4de2	1216	#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
<>	154:37f96f9d4de2	1217
<>	154:37f96f9d4de2	1218	/**
<>	154:37f96f9d4de2	1219	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
AnnaBridge	165:e614a9f1c9e2	1220	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
<>	154:37f96f9d4de2	1221	* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
<>	154:37f96f9d4de2	1222	* @retval None
<>	154:37f96f9d4de2	1223	*/
AnnaBridge	165:e614a9f1c9e2	1224	__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
<>	154:37f96f9d4de2	1225	{
AnnaBridge	165:e614a9f1c9e2	1226	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
AnnaBridge	187:0387e8f68319	1227	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
<>	154:37f96f9d4de2	1228	}
<>	154:37f96f9d4de2	1229
<>	154:37f96f9d4de2	1230	/**
<>	154:37f96f9d4de2	1231	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
AnnaBridge	165:e614a9f1c9e2	1232	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
<>	154:37f96f9d4de2	1233	* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
<>	154:37f96f9d4de2	1234	* @retval None
<>	154:37f96f9d4de2	1235	*/
AnnaBridge	165:e614a9f1c9e2	1236	__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
<>	154:37f96f9d4de2	1237	{
AnnaBridge	165:e614a9f1c9e2	1238	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
AnnaBridge	187:0387e8f68319	1239	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
<>	154:37f96f9d4de2	1240	}
<>	154:37f96f9d4de2	1241
<>	154:37f96f9d4de2	1242	/**
<>	154:37f96f9d4de2	1243	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
AnnaBridge	165:e614a9f1c9e2	1244	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
<>	154:37f96f9d4de2	1245	* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
<>	154:37f96f9d4de2	1246	* @retval None
<>	154:37f96f9d4de2	1247	*/
AnnaBridge	165:e614a9f1c9e2	1248	__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
<>	154:37f96f9d4de2	1249	{
AnnaBridge	165:e614a9f1c9e2	1250	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
AnnaBridge	187:0387e8f68319	1251	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
<>	154:37f96f9d4de2	1252	}
<>	154:37f96f9d4de2	1253	#endif
<>	154:37f96f9d4de2	1254
<>	154:37f96f9d4de2	1255	/**
<>	154:37f96f9d4de2	1256	* @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
<>	154:37f96f9d4de2	1257	* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
<>	154:37f96f9d4de2	1258	* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
<>	154:37f96f9d4de2	1259	* on 100-pin and 144-pin packages, no need for remapping).
AnnaBridge	165:e614a9f1c9e2	1260	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
<>	154:37f96f9d4de2	1261	* @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
<>	154:37f96f9d4de2	1262	* @retval None
<>	154:37f96f9d4de2	1263	*/
AnnaBridge	165:e614a9f1c9e2	1264	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
<>	154:37f96f9d4de2	1265	{
<>	154:37f96f9d4de2	1266	SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
<>	154:37f96f9d4de2	1267	}
<>	154:37f96f9d4de2	1268
<>	154:37f96f9d4de2	1269	/**
<>	154:37f96f9d4de2	1270	* @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
<>	154:37f96f9d4de2	1271	* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
<>	154:37f96f9d4de2	1272	* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
<>	154:37f96f9d4de2	1273	* on 100-pin and 144-pin packages, no need for remapping).
AnnaBridge	165:e614a9f1c9e2	1274	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
<>	154:37f96f9d4de2	1275	* @note DISABLE: No remapping of PD0 and PD1
<>	154:37f96f9d4de2	1276	* @retval None
<>	154:37f96f9d4de2	1277	*/
AnnaBridge	165:e614a9f1c9e2	1278	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
<>	154:37f96f9d4de2	1279	{
<>	154:37f96f9d4de2	1280	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
<>	154:37f96f9d4de2	1281	}
<>	154:37f96f9d4de2	1282
AnnaBridge	165:e614a9f1c9e2	1283	/**
AnnaBridge	165:e614a9f1c9e2	1284	* @brief Check if PD01 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1285	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
AnnaBridge	165:e614a9f1c9e2	1286	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1287	*/
AnnaBridge	165:e614a9f1c9e2	1288	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
AnnaBridge	165:e614a9f1c9e2	1289	{
AnnaBridge	165:e614a9f1c9e2	1290	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
AnnaBridge	165:e614a9f1c9e2	1291	}
AnnaBridge	165:e614a9f1c9e2	1292
<>	154:37f96f9d4de2	1293	#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
<>	154:37f96f9d4de2	1294	/**
<>	154:37f96f9d4de2	1295	* @brief Enable the remapping of TIM5CH4.
AnnaBridge	165:e614a9f1c9e2	1296	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
<>	154:37f96f9d4de2	1297	* @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
<>	154:37f96f9d4de2	1298	* @note This function is available only in high density value line devices.
<>	154:37f96f9d4de2	1299	* @retval None
<>	154:37f96f9d4de2	1300	*/
AnnaBridge	165:e614a9f1c9e2	1301	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
<>	154:37f96f9d4de2	1302	{
<>	154:37f96f9d4de2	1303	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
<>	154:37f96f9d4de2	1304	}
<>	154:37f96f9d4de2	1305
<>	154:37f96f9d4de2	1306	/**
<>	154:37f96f9d4de2	1307	* @brief Disable the remapping of TIM5CH4.
AnnaBridge	165:e614a9f1c9e2	1308	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
<>	154:37f96f9d4de2	1309	* @note DISABLE: TIM5_CH4 is connected to PA3
<>	154:37f96f9d4de2	1310	* @note This function is available only in high density value line devices.
<>	154:37f96f9d4de2	1311	* @retval None
<>	154:37f96f9d4de2	1312	*/
AnnaBridge	165:e614a9f1c9e2	1313	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
<>	154:37f96f9d4de2	1314	{
<>	154:37f96f9d4de2	1315	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
<>	154:37f96f9d4de2	1316	}
AnnaBridge	165:e614a9f1c9e2	1317
AnnaBridge	165:e614a9f1c9e2	1318	/**
AnnaBridge	165:e614a9f1c9e2	1319	* @brief Check if TIM5CH4 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1320	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
AnnaBridge	165:e614a9f1c9e2	1321	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1322	*/
AnnaBridge	165:e614a9f1c9e2	1323	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
AnnaBridge	165:e614a9f1c9e2	1324	{
AnnaBridge	165:e614a9f1c9e2	1325	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
AnnaBridge	165:e614a9f1c9e2	1326	}
<>	154:37f96f9d4de2	1327	#endif
<>	154:37f96f9d4de2	1328
<>	154:37f96f9d4de2	1329	#if defined(AFIO_MAPR_ETH_REMAP)
<>	154:37f96f9d4de2	1330	/**
<>	154:37f96f9d4de2	1331	* @brief Enable the remapping of Ethernet MAC connections with the PHY.
AnnaBridge	165:e614a9f1c9e2	1332	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
<>	154:37f96f9d4de2	1333	* @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
<>	154:37f96f9d4de2	1334	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1335	* @retval None
<>	154:37f96f9d4de2	1336	*/
AnnaBridge	165:e614a9f1c9e2	1337	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
<>	154:37f96f9d4de2	1338	{
<>	154:37f96f9d4de2	1339	SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
<>	154:37f96f9d4de2	1340	}
<>	154:37f96f9d4de2	1341
<>	154:37f96f9d4de2	1342	/**
<>	154:37f96f9d4de2	1343	* @brief Disable the remapping of Ethernet MAC connections with the PHY.
AnnaBridge	165:e614a9f1c9e2	1344	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
<>	154:37f96f9d4de2	1345	* @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
<>	154:37f96f9d4de2	1346	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1347	* @retval None
<>	154:37f96f9d4de2	1348	*/
AnnaBridge	165:e614a9f1c9e2	1349	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
<>	154:37f96f9d4de2	1350	{
<>	154:37f96f9d4de2	1351	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
<>	154:37f96f9d4de2	1352	}
AnnaBridge	165:e614a9f1c9e2	1353
AnnaBridge	165:e614a9f1c9e2	1354	/**
AnnaBridge	165:e614a9f1c9e2	1355	* @brief Check if ETH has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1356	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
AnnaBridge	165:e614a9f1c9e2	1357	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1358	*/
AnnaBridge	165:e614a9f1c9e2	1359	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
AnnaBridge	165:e614a9f1c9e2	1360	{
AnnaBridge	165:e614a9f1c9e2	1361	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
AnnaBridge	165:e614a9f1c9e2	1362	}
<>	154:37f96f9d4de2	1363	#endif
<>	154:37f96f9d4de2	1364
<>	154:37f96f9d4de2	1365	#if defined(AFIO_MAPR_CAN2_REMAP)
<>	154:37f96f9d4de2	1366
<>	154:37f96f9d4de2	1367	/**
<>	154:37f96f9d4de2	1368	* @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
AnnaBridge	165:e614a9f1c9e2	1369	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
<>	154:37f96f9d4de2	1370	* @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
<>	154:37f96f9d4de2	1371	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1372	* @retval None
<>	154:37f96f9d4de2	1373	*/
AnnaBridge	165:e614a9f1c9e2	1374	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
<>	154:37f96f9d4de2	1375	{
<>	154:37f96f9d4de2	1376	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
<>	154:37f96f9d4de2	1377	}
<>	154:37f96f9d4de2	1378	/**
<>	154:37f96f9d4de2	1379	* @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
AnnaBridge	165:e614a9f1c9e2	1380	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
<>	154:37f96f9d4de2	1381	* @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
<>	154:37f96f9d4de2	1382	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1383	* @retval None
<>	154:37f96f9d4de2	1384	*/
AnnaBridge	165:e614a9f1c9e2	1385	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
<>	154:37f96f9d4de2	1386	{
<>	154:37f96f9d4de2	1387	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
<>	154:37f96f9d4de2	1388	}
AnnaBridge	165:e614a9f1c9e2	1389
AnnaBridge	165:e614a9f1c9e2	1390	/**
AnnaBridge	165:e614a9f1c9e2	1391	* @brief Check if CAN2 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1392	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
AnnaBridge	165:e614a9f1c9e2	1393	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1394	*/
AnnaBridge	165:e614a9f1c9e2	1395	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
AnnaBridge	165:e614a9f1c9e2	1396	{
AnnaBridge	165:e614a9f1c9e2	1397	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
AnnaBridge	165:e614a9f1c9e2	1398	}
<>	154:37f96f9d4de2	1399	#endif
<>	154:37f96f9d4de2	1400
<>	154:37f96f9d4de2	1401	#if defined(AFIO_MAPR_MII_RMII_SEL)
<>	154:37f96f9d4de2	1402	/**
<>	154:37f96f9d4de2	1403	* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
AnnaBridge	165:e614a9f1c9e2	1404	* @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
<>	154:37f96f9d4de2	1405	* @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
<>	154:37f96f9d4de2	1406	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1407	* @retval None
<>	154:37f96f9d4de2	1408	*/
AnnaBridge	165:e614a9f1c9e2	1409	__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
<>	154:37f96f9d4de2	1410	{
<>	154:37f96f9d4de2	1411	SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
<>	154:37f96f9d4de2	1412	}
<>	154:37f96f9d4de2	1413
<>	154:37f96f9d4de2	1414	/**
<>	154:37f96f9d4de2	1415	* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
AnnaBridge	165:e614a9f1c9e2	1416	* @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
<>	154:37f96f9d4de2	1417	* @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
<>	154:37f96f9d4de2	1418	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1419	* @retval None
<>	154:37f96f9d4de2	1420	*/
AnnaBridge	165:e614a9f1c9e2	1421	__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
<>	154:37f96f9d4de2	1422	{
<>	154:37f96f9d4de2	1423	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
<>	154:37f96f9d4de2	1424	}
<>	154:37f96f9d4de2	1425	#endif
<>	154:37f96f9d4de2	1426
<>	154:37f96f9d4de2	1427	#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
<>	154:37f96f9d4de2	1428	/**
<>	154:37f96f9d4de2	1429	* @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
AnnaBridge	165:e614a9f1c9e2	1430	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
<>	154:37f96f9d4de2	1431	* @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
<>	154:37f96f9d4de2	1432	* @retval None
<>	154:37f96f9d4de2	1433	*/
AnnaBridge	165:e614a9f1c9e2	1434	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
<>	154:37f96f9d4de2	1435	{
<>	154:37f96f9d4de2	1436	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
<>	154:37f96f9d4de2	1437	}
<>	154:37f96f9d4de2	1438
<>	154:37f96f9d4de2	1439	/**
<>	154:37f96f9d4de2	1440	* @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
AnnaBridge	165:e614a9f1c9e2	1441	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
<>	154:37f96f9d4de2	1442	* @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
<>	154:37f96f9d4de2	1443	* @retval None
<>	154:37f96f9d4de2	1444	*/
AnnaBridge	165:e614a9f1c9e2	1445	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
<>	154:37f96f9d4de2	1446	{
<>	154:37f96f9d4de2	1447	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
<>	154:37f96f9d4de2	1448	}
AnnaBridge	165:e614a9f1c9e2	1449
AnnaBridge	165:e614a9f1c9e2	1450	/**
AnnaBridge	165:e614a9f1c9e2	1451	* @brief Check if ADC1_ETRGINJ has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1452	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
AnnaBridge	165:e614a9f1c9e2	1453	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1454	*/
AnnaBridge	165:e614a9f1c9e2	1455	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
AnnaBridge	165:e614a9f1c9e2	1456	{
AnnaBridge	165:e614a9f1c9e2	1457	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
AnnaBridge	165:e614a9f1c9e2	1458	}
<>	154:37f96f9d4de2	1459	#endif
<>	154:37f96f9d4de2	1460
<>	154:37f96f9d4de2	1461	#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
<>	154:37f96f9d4de2	1462	/**
<>	154:37f96f9d4de2	1463	* @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
AnnaBridge	165:e614a9f1c9e2	1464	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
<>	154:37f96f9d4de2	1465	* @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
<>	154:37f96f9d4de2	1466	* @retval None
<>	154:37f96f9d4de2	1467	*/
AnnaBridge	165:e614a9f1c9e2	1468	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
<>	154:37f96f9d4de2	1469	{
<>	154:37f96f9d4de2	1470	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
<>	154:37f96f9d4de2	1471	}
<>	154:37f96f9d4de2	1472
<>	154:37f96f9d4de2	1473	/**
<>	154:37f96f9d4de2	1474	* @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
AnnaBridge	165:e614a9f1c9e2	1475	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
<>	154:37f96f9d4de2	1476	* @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
<>	154:37f96f9d4de2	1477	* @retval None
<>	154:37f96f9d4de2	1478	*/
AnnaBridge	165:e614a9f1c9e2	1479	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
<>	154:37f96f9d4de2	1480	{
<>	154:37f96f9d4de2	1481	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
<>	154:37f96f9d4de2	1482	}
AnnaBridge	165:e614a9f1c9e2	1483
AnnaBridge	165:e614a9f1c9e2	1484	/**
AnnaBridge	165:e614a9f1c9e2	1485	* @brief Check if ADC1_ETRGREG has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1486	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
AnnaBridge	165:e614a9f1c9e2	1487	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1488	*/
AnnaBridge	165:e614a9f1c9e2	1489	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
AnnaBridge	165:e614a9f1c9e2	1490	{
AnnaBridge	165:e614a9f1c9e2	1491	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
AnnaBridge	165:e614a9f1c9e2	1492	}
<>	154:37f96f9d4de2	1493	#endif
<>	154:37f96f9d4de2	1494
<>	154:37f96f9d4de2	1495	#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
<>	154:37f96f9d4de2	1496
<>	154:37f96f9d4de2	1497	/**
<>	154:37f96f9d4de2	1498	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
AnnaBridge	165:e614a9f1c9e2	1499	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
<>	154:37f96f9d4de2	1500	* @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
<>	154:37f96f9d4de2	1501	* @retval None
<>	154:37f96f9d4de2	1502	*/
AnnaBridge	165:e614a9f1c9e2	1503	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
<>	154:37f96f9d4de2	1504	{
<>	154:37f96f9d4de2	1505	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
<>	154:37f96f9d4de2	1506	}
<>	154:37f96f9d4de2	1507
<>	154:37f96f9d4de2	1508	/**
<>	154:37f96f9d4de2	1509	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
AnnaBridge	165:e614a9f1c9e2	1510	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
<>	154:37f96f9d4de2	1511	* @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
<>	154:37f96f9d4de2	1512	* @retval None
<>	154:37f96f9d4de2	1513	*/
AnnaBridge	165:e614a9f1c9e2	1514	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
<>	154:37f96f9d4de2	1515	{
<>	154:37f96f9d4de2	1516	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
<>	154:37f96f9d4de2	1517	}
AnnaBridge	165:e614a9f1c9e2	1518
AnnaBridge	165:e614a9f1c9e2	1519	/**
AnnaBridge	165:e614a9f1c9e2	1520	* @brief Check if ADC2_ETRGINJ has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1521	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
AnnaBridge	165:e614a9f1c9e2	1522	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1523	*/
AnnaBridge	165:e614a9f1c9e2	1524	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
AnnaBridge	165:e614a9f1c9e2	1525	{
AnnaBridge	165:e614a9f1c9e2	1526	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
AnnaBridge	165:e614a9f1c9e2	1527	}
<>	154:37f96f9d4de2	1528	#endif
<>	154:37f96f9d4de2	1529
<>	154:37f96f9d4de2	1530	#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
<>	154:37f96f9d4de2	1531
<>	154:37f96f9d4de2	1532	/**
<>	154:37f96f9d4de2	1533	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	165:e614a9f1c9e2	1534	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
<>	154:37f96f9d4de2	1535	* @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
<>	154:37f96f9d4de2	1536	* @retval None
<>	154:37f96f9d4de2	1537	*/
AnnaBridge	165:e614a9f1c9e2	1538	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
<>	154:37f96f9d4de2	1539	{
<>	154:37f96f9d4de2	1540	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
<>	154:37f96f9d4de2	1541	}
<>	154:37f96f9d4de2	1542
<>	154:37f96f9d4de2	1543	/**
<>	154:37f96f9d4de2	1544	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	165:e614a9f1c9e2	1545	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
<>	154:37f96f9d4de2	1546	* @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
<>	154:37f96f9d4de2	1547	* @retval None
<>	154:37f96f9d4de2	1548	*/
AnnaBridge	165:e614a9f1c9e2	1549	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
<>	154:37f96f9d4de2	1550	{
<>	154:37f96f9d4de2	1551	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
<>	154:37f96f9d4de2	1552	}
AnnaBridge	165:e614a9f1c9e2	1553
AnnaBridge	165:e614a9f1c9e2	1554	/**
AnnaBridge	165:e614a9f1c9e2	1555	* @brief Check if ADC2_ETRGREG has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1556	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
AnnaBridge	165:e614a9f1c9e2	1557	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1558	*/
AnnaBridge	165:e614a9f1c9e2	1559	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
AnnaBridge	165:e614a9f1c9e2	1560	{
AnnaBridge	165:e614a9f1c9e2	1561	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
AnnaBridge	165:e614a9f1c9e2	1562	}
<>	154:37f96f9d4de2	1563	#endif
<>	154:37f96f9d4de2	1564
<>	154:37f96f9d4de2	1565	/**
<>	154:37f96f9d4de2	1566	* @brief Enable the Serial wire JTAG configuration
AnnaBridge	165:e614a9f1c9e2	1567	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
<>	154:37f96f9d4de2	1568	* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
<>	154:37f96f9d4de2	1569	* @retval None
<>	154:37f96f9d4de2	1570	*/
AnnaBridge	165:e614a9f1c9e2	1571	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
<>	154:37f96f9d4de2	1572	{
AnnaBridge	165:e614a9f1c9e2	1573	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	187:0387e8f68319	1574	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
<>	154:37f96f9d4de2	1575	}
<>	154:37f96f9d4de2	1576
<>	154:37f96f9d4de2	1577	/**
<>	154:37f96f9d4de2	1578	* @brief Enable the Serial wire JTAG configuration
AnnaBridge	165:e614a9f1c9e2	1579	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
<>	154:37f96f9d4de2	1580	* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
<>	154:37f96f9d4de2	1581	* @retval None
<>	154:37f96f9d4de2	1582	*/
AnnaBridge	165:e614a9f1c9e2	1583	__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
<>	154:37f96f9d4de2	1584	{
AnnaBridge	165:e614a9f1c9e2	1585	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	165:e614a9f1c9e2	1586	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
<>	154:37f96f9d4de2	1587	}
<>	154:37f96f9d4de2	1588
<>	154:37f96f9d4de2	1589	/**
<>	154:37f96f9d4de2	1590	* @brief Enable the Serial wire JTAG configuration
AnnaBridge	165:e614a9f1c9e2	1591	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
<>	154:37f96f9d4de2	1592	* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
<>	154:37f96f9d4de2	1593	* @retval None
<>	154:37f96f9d4de2	1594	*/
AnnaBridge	165:e614a9f1c9e2	1595	__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
<>	154:37f96f9d4de2	1596	{
AnnaBridge	165:e614a9f1c9e2	1597	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	165:e614a9f1c9e2	1598	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
<>	154:37f96f9d4de2	1599	}
<>	154:37f96f9d4de2	1600
<>	154:37f96f9d4de2	1601	/**
<>	154:37f96f9d4de2	1602	* @brief Disable the Serial wire JTAG configuration
AnnaBridge	165:e614a9f1c9e2	1603	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
<>	154:37f96f9d4de2	1604	* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
<>	154:37f96f9d4de2	1605	* @retval None
<>	154:37f96f9d4de2	1606	*/
AnnaBridge	165:e614a9f1c9e2	1607	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
<>	154:37f96f9d4de2	1608	{
AnnaBridge	165:e614a9f1c9e2	1609	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	187:0387e8f68319	1610	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
<>	154:37f96f9d4de2	1611	}
<>	154:37f96f9d4de2	1612
<>	154:37f96f9d4de2	1613	#if defined(AFIO_MAPR_SPI3_REMAP)
<>	154:37f96f9d4de2	1614
<>	154:37f96f9d4de2	1615	/**
<>	154:37f96f9d4de2	1616	* @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
AnnaBridge	165:e614a9f1c9e2	1617	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
<>	154:37f96f9d4de2	1618	* @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
<>	154:37f96f9d4de2	1619	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1620	* @retval None
<>	154:37f96f9d4de2	1621	*/
AnnaBridge	165:e614a9f1c9e2	1622	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
<>	154:37f96f9d4de2	1623	{
<>	154:37f96f9d4de2	1624	SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
<>	154:37f96f9d4de2	1625	}
<>	154:37f96f9d4de2	1626
<>	154:37f96f9d4de2	1627	/**
<>	154:37f96f9d4de2	1628	* @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
AnnaBridge	165:e614a9f1c9e2	1629	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
<>	154:37f96f9d4de2	1630	* @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
<>	154:37f96f9d4de2	1631	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1632	* @retval None
<>	154:37f96f9d4de2	1633	*/
AnnaBridge	165:e614a9f1c9e2	1634	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
<>	154:37f96f9d4de2	1635	{
<>	154:37f96f9d4de2	1636	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
<>	154:37f96f9d4de2	1637	}
AnnaBridge	165:e614a9f1c9e2	1638
AnnaBridge	165:e614a9f1c9e2	1639	/**
AnnaBridge	165:e614a9f1c9e2	1640	* @brief Check if SPI3 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1641	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
AnnaBridge	165:e614a9f1c9e2	1642	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1643	*/
AnnaBridge	165:e614a9f1c9e2	1644	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
AnnaBridge	165:e614a9f1c9e2	1645	{
AnnaBridge	165:e614a9f1c9e2	1646	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
AnnaBridge	165:e614a9f1c9e2	1647	}
<>	154:37f96f9d4de2	1648	#endif
<>	154:37f96f9d4de2	1649
<>	154:37f96f9d4de2	1650	#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
<>	154:37f96f9d4de2	1651
<>	154:37f96f9d4de2	1652	/**
<>	154:37f96f9d4de2	1653	* @brief Control of TIM2_ITR1 internal mapping.
AnnaBridge	165:e614a9f1c9e2	1654	* @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
<>	154:37f96f9d4de2	1655	* @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
<>	154:37f96f9d4de2	1656	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1657	* @retval None
<>	154:37f96f9d4de2	1658	*/
AnnaBridge	165:e614a9f1c9e2	1659	__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
<>	154:37f96f9d4de2	1660	{
<>	154:37f96f9d4de2	1661	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
<>	154:37f96f9d4de2	1662	}
<>	154:37f96f9d4de2	1663
<>	154:37f96f9d4de2	1664	/**
<>	154:37f96f9d4de2	1665	* @brief Control of TIM2_ITR1 internal mapping.
AnnaBridge	165:e614a9f1c9e2	1666	* @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
<>	154:37f96f9d4de2	1667	* @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
<>	154:37f96f9d4de2	1668	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1669	* @retval None
<>	154:37f96f9d4de2	1670	*/
AnnaBridge	165:e614a9f1c9e2	1671	__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
<>	154:37f96f9d4de2	1672	{
<>	154:37f96f9d4de2	1673	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
<>	154:37f96f9d4de2	1674	}
<>	154:37f96f9d4de2	1675	#endif
<>	154:37f96f9d4de2	1676
<>	154:37f96f9d4de2	1677	#if defined(AFIO_MAPR_PTP_PPS_REMAP)
<>	154:37f96f9d4de2	1678
<>	154:37f96f9d4de2	1679	/**
<>	154:37f96f9d4de2	1680	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	165:e614a9f1c9e2	1681	* @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
<>	154:37f96f9d4de2	1682	* @note ENABLE: PTP_PPS is output on PB5 pin.
<>	154:37f96f9d4de2	1683	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1684	* @retval None
<>	154:37f96f9d4de2	1685	*/
AnnaBridge	165:e614a9f1c9e2	1686	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
<>	154:37f96f9d4de2	1687	{
<>	154:37f96f9d4de2	1688	SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
<>	154:37f96f9d4de2	1689	}
<>	154:37f96f9d4de2	1690
<>	154:37f96f9d4de2	1691	/**
<>	154:37f96f9d4de2	1692	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	165:e614a9f1c9e2	1693	* @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
<>	154:37f96f9d4de2	1694	* @note DISABLE: PTP_PPS not output on PB5 pin.
<>	154:37f96f9d4de2	1695	* @note This bit is available only in connectivity line devices and is reserved otherwise.
<>	154:37f96f9d4de2	1696	* @retval None
<>	154:37f96f9d4de2	1697	*/
AnnaBridge	165:e614a9f1c9e2	1698	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
<>	154:37f96f9d4de2	1699	{
<>	154:37f96f9d4de2	1700	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
<>	154:37f96f9d4de2	1701	}
<>	154:37f96f9d4de2	1702	#endif
<>	154:37f96f9d4de2	1703
<>	154:37f96f9d4de2	1704	#if defined(AFIO_MAPR2_TIM9_REMAP)
<>	154:37f96f9d4de2	1705
<>	154:37f96f9d4de2	1706	/**
<>	154:37f96f9d4de2	1707	* @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
AnnaBridge	165:e614a9f1c9e2	1708	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
<>	154:37f96f9d4de2	1709	* @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
<>	154:37f96f9d4de2	1710	* @retval None
<>	154:37f96f9d4de2	1711	*/
AnnaBridge	165:e614a9f1c9e2	1712	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
<>	154:37f96f9d4de2	1713	{
<>	154:37f96f9d4de2	1714	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
<>	154:37f96f9d4de2	1715	}
<>	154:37f96f9d4de2	1716
<>	154:37f96f9d4de2	1717	/**
<>	154:37f96f9d4de2	1718	* @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
AnnaBridge	165:e614a9f1c9e2	1719	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
<>	154:37f96f9d4de2	1720	* @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
<>	154:37f96f9d4de2	1721	* @retval None
<>	154:37f96f9d4de2	1722	*/
AnnaBridge	165:e614a9f1c9e2	1723	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
<>	154:37f96f9d4de2	1724	{
<>	154:37f96f9d4de2	1725	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
<>	154:37f96f9d4de2	1726	}
AnnaBridge	165:e614a9f1c9e2	1727
AnnaBridge	165:e614a9f1c9e2	1728	/**
AnnaBridge	165:e614a9f1c9e2	1729	* @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
AnnaBridge	165:e614a9f1c9e2	1730	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
AnnaBridge	165:e614a9f1c9e2	1731	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1732	*/
AnnaBridge	165:e614a9f1c9e2	1733	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
AnnaBridge	165:e614a9f1c9e2	1734	{
AnnaBridge	165:e614a9f1c9e2	1735	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
AnnaBridge	165:e614a9f1c9e2	1736	}
<>	154:37f96f9d4de2	1737	#endif
<>	154:37f96f9d4de2	1738
<>	154:37f96f9d4de2	1739	#if defined(AFIO_MAPR2_TIM10_REMAP)
<>	154:37f96f9d4de2	1740
<>	154:37f96f9d4de2	1741	/**
<>	154:37f96f9d4de2	1742	* @brief Enable the remapping of TIM10_CH1.
AnnaBridge	165:e614a9f1c9e2	1743	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
<>	154:37f96f9d4de2	1744	* @note ENABLE: Remap (TIM10_CH1 on PF6).
<>	154:37f96f9d4de2	1745	* @retval None
<>	154:37f96f9d4de2	1746	*/
AnnaBridge	165:e614a9f1c9e2	1747	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
<>	154:37f96f9d4de2	1748	{
<>	154:37f96f9d4de2	1749	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
<>	154:37f96f9d4de2	1750	}
<>	154:37f96f9d4de2	1751
<>	154:37f96f9d4de2	1752	/**
<>	154:37f96f9d4de2	1753	* @brief Disable the remapping of TIM10_CH1.
AnnaBridge	165:e614a9f1c9e2	1754	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
<>	154:37f96f9d4de2	1755	* @note DISABLE: No remap (TIM10_CH1 on PB8).
<>	154:37f96f9d4de2	1756	* @retval None
<>	154:37f96f9d4de2	1757	*/
AnnaBridge	165:e614a9f1c9e2	1758	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
<>	154:37f96f9d4de2	1759	{
<>	154:37f96f9d4de2	1760	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
<>	154:37f96f9d4de2	1761	}
AnnaBridge	165:e614a9f1c9e2	1762
AnnaBridge	165:e614a9f1c9e2	1763	/**
AnnaBridge	165:e614a9f1c9e2	1764	* @brief Check if TIM10_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1765	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
AnnaBridge	165:e614a9f1c9e2	1766	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1767	*/
AnnaBridge	165:e614a9f1c9e2	1768	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
AnnaBridge	165:e614a9f1c9e2	1769	{
AnnaBridge	165:e614a9f1c9e2	1770	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
AnnaBridge	165:e614a9f1c9e2	1771	}
<>	154:37f96f9d4de2	1772	#endif
<>	154:37f96f9d4de2	1773
<>	154:37f96f9d4de2	1774	#if defined(AFIO_MAPR2_TIM11_REMAP)
<>	154:37f96f9d4de2	1775	/**
<>	154:37f96f9d4de2	1776	* @brief Enable the remapping of TIM11_CH1.
AnnaBridge	165:e614a9f1c9e2	1777	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
<>	154:37f96f9d4de2	1778	* @note ENABLE: Remap (TIM11_CH1 on PF7).
<>	154:37f96f9d4de2	1779	* @retval None
<>	154:37f96f9d4de2	1780	*/
AnnaBridge	165:e614a9f1c9e2	1781	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
<>	154:37f96f9d4de2	1782	{
<>	154:37f96f9d4de2	1783	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
<>	154:37f96f9d4de2	1784	}
<>	154:37f96f9d4de2	1785
<>	154:37f96f9d4de2	1786	/**
<>	154:37f96f9d4de2	1787	* @brief Disable the remapping of TIM11_CH1.
AnnaBridge	165:e614a9f1c9e2	1788	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
<>	154:37f96f9d4de2	1789	* @note DISABLE: No remap (TIM11_CH1 on PB9).
<>	154:37f96f9d4de2	1790	* @retval None
<>	154:37f96f9d4de2	1791	*/
AnnaBridge	165:e614a9f1c9e2	1792	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
<>	154:37f96f9d4de2	1793	{
<>	154:37f96f9d4de2	1794	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
<>	154:37f96f9d4de2	1795	}
AnnaBridge	165:e614a9f1c9e2	1796
AnnaBridge	165:e614a9f1c9e2	1797	/**
AnnaBridge	165:e614a9f1c9e2	1798	* @brief Check if TIM11_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1799	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
AnnaBridge	165:e614a9f1c9e2	1800	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1801	*/
AnnaBridge	165:e614a9f1c9e2	1802	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
AnnaBridge	165:e614a9f1c9e2	1803	{
AnnaBridge	165:e614a9f1c9e2	1804	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
AnnaBridge	165:e614a9f1c9e2	1805	}
<>	154:37f96f9d4de2	1806	#endif
<>	154:37f96f9d4de2	1807
<>	154:37f96f9d4de2	1808	#if defined(AFIO_MAPR2_TIM13_REMAP)
<>	154:37f96f9d4de2	1809
<>	154:37f96f9d4de2	1810	/**
<>	154:37f96f9d4de2	1811	* @brief Enable the remapping of TIM13_CH1.
AnnaBridge	165:e614a9f1c9e2	1812	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
<>	154:37f96f9d4de2	1813	* @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
<>	154:37f96f9d4de2	1814	* @retval None
<>	154:37f96f9d4de2	1815	*/
AnnaBridge	165:e614a9f1c9e2	1816	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
<>	154:37f96f9d4de2	1817	{
<>	154:37f96f9d4de2	1818	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
<>	154:37f96f9d4de2	1819	}
<>	154:37f96f9d4de2	1820
<>	154:37f96f9d4de2	1821	/**
<>	154:37f96f9d4de2	1822	* @brief Disable the remapping of TIM13_CH1.
AnnaBridge	165:e614a9f1c9e2	1823	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
<>	154:37f96f9d4de2	1824	* @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
<>	154:37f96f9d4de2	1825	* @retval None
<>	154:37f96f9d4de2	1826	*/
AnnaBridge	165:e614a9f1c9e2	1827	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
<>	154:37f96f9d4de2	1828	{
<>	154:37f96f9d4de2	1829	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
<>	154:37f96f9d4de2	1830	}
AnnaBridge	165:e614a9f1c9e2	1831
AnnaBridge	165:e614a9f1c9e2	1832	/**
AnnaBridge	165:e614a9f1c9e2	1833	* @brief Check if TIM13_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1834	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
AnnaBridge	165:e614a9f1c9e2	1835	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1836	*/
AnnaBridge	165:e614a9f1c9e2	1837	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
AnnaBridge	165:e614a9f1c9e2	1838	{
AnnaBridge	165:e614a9f1c9e2	1839	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
AnnaBridge	165:e614a9f1c9e2	1840	}
<>	154:37f96f9d4de2	1841	#endif
<>	154:37f96f9d4de2	1842
<>	154:37f96f9d4de2	1843	#if defined(AFIO_MAPR2_TIM14_REMAP)
<>	154:37f96f9d4de2	1844
<>	154:37f96f9d4de2	1845	/**
<>	154:37f96f9d4de2	1846	* @brief Enable the remapping of TIM14_CH1.
AnnaBridge	165:e614a9f1c9e2	1847	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
<>	154:37f96f9d4de2	1848	* @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
<>	154:37f96f9d4de2	1849	* @retval None
<>	154:37f96f9d4de2	1850	*/
AnnaBridge	165:e614a9f1c9e2	1851	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
<>	154:37f96f9d4de2	1852	{
<>	154:37f96f9d4de2	1853	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
<>	154:37f96f9d4de2	1854	}
<>	154:37f96f9d4de2	1855
<>	154:37f96f9d4de2	1856	/**
<>	154:37f96f9d4de2	1857	* @brief Disable the remapping of TIM14_CH1.
AnnaBridge	165:e614a9f1c9e2	1858	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
<>	154:37f96f9d4de2	1859	* @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
<>	154:37f96f9d4de2	1860	* @retval None
<>	154:37f96f9d4de2	1861	*/
AnnaBridge	165:e614a9f1c9e2	1862	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
<>	154:37f96f9d4de2	1863	{
<>	154:37f96f9d4de2	1864	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
<>	154:37f96f9d4de2	1865	}
AnnaBridge	165:e614a9f1c9e2	1866
AnnaBridge	165:e614a9f1c9e2	1867	/**
AnnaBridge	165:e614a9f1c9e2	1868	* @brief Check if TIM14_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1869	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
AnnaBridge	165:e614a9f1c9e2	1870	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1871	*/
AnnaBridge	165:e614a9f1c9e2	1872	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
AnnaBridge	165:e614a9f1c9e2	1873	{
AnnaBridge	165:e614a9f1c9e2	1874	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
AnnaBridge	165:e614a9f1c9e2	1875	}
<>	154:37f96f9d4de2	1876	#endif
<>	154:37f96f9d4de2	1877
<>	154:37f96f9d4de2	1878	#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
<>	154:37f96f9d4de2	1879
<>	154:37f96f9d4de2	1880	/**
<>	154:37f96f9d4de2	1881	* @brief Controls the use of the optional FSMC_NADV signal.
AnnaBridge	165:e614a9f1c9e2	1882	* @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
<>	154:37f96f9d4de2	1883	* @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
<>	154:37f96f9d4de2	1884	* @retval None
<>	154:37f96f9d4de2	1885	*/
AnnaBridge	165:e614a9f1c9e2	1886	__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
<>	154:37f96f9d4de2	1887	{
<>	154:37f96f9d4de2	1888	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
<>	154:37f96f9d4de2	1889	}
<>	154:37f96f9d4de2	1890
<>	154:37f96f9d4de2	1891	/**
<>	154:37f96f9d4de2	1892	* @brief Controls the use of the optional FSMC_NADV signal.
AnnaBridge	165:e614a9f1c9e2	1893	* @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
<>	154:37f96f9d4de2	1894	* @note CONNECTED: The NADV signal is connected to the output (default).
<>	154:37f96f9d4de2	1895	* @retval None
<>	154:37f96f9d4de2	1896	*/
AnnaBridge	165:e614a9f1c9e2	1897	__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
<>	154:37f96f9d4de2	1898	{
<>	154:37f96f9d4de2	1899	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
<>	154:37f96f9d4de2	1900	}
<>	154:37f96f9d4de2	1901	#endif
<>	154:37f96f9d4de2	1902
<>	154:37f96f9d4de2	1903	#if defined(AFIO_MAPR2_TIM15_REMAP)
<>	154:37f96f9d4de2	1904
<>	154:37f96f9d4de2	1905	/**
<>	154:37f96f9d4de2	1906	* @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
AnnaBridge	165:e614a9f1c9e2	1907	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
<>	154:37f96f9d4de2	1908	* @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
<>	154:37f96f9d4de2	1909	* @retval None
<>	154:37f96f9d4de2	1910	*/
AnnaBridge	165:e614a9f1c9e2	1911	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
<>	154:37f96f9d4de2	1912	{
<>	154:37f96f9d4de2	1913	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
<>	154:37f96f9d4de2	1914	}
<>	154:37f96f9d4de2	1915	/**
<>	154:37f96f9d4de2	1916	* @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
AnnaBridge	165:e614a9f1c9e2	1917	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
<>	154:37f96f9d4de2	1918	* @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
<>	154:37f96f9d4de2	1919	* @retval None
<>	154:37f96f9d4de2	1920	*/
AnnaBridge	165:e614a9f1c9e2	1921	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
<>	154:37f96f9d4de2	1922	{
<>	154:37f96f9d4de2	1923	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
<>	154:37f96f9d4de2	1924	}
AnnaBridge	165:e614a9f1c9e2	1925
AnnaBridge	165:e614a9f1c9e2	1926	/**
AnnaBridge	165:e614a9f1c9e2	1927	* @brief Check if TIM15_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1928	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
AnnaBridge	165:e614a9f1c9e2	1929	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1930	*/
AnnaBridge	165:e614a9f1c9e2	1931	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
AnnaBridge	165:e614a9f1c9e2	1932	{
AnnaBridge	165:e614a9f1c9e2	1933	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
AnnaBridge	165:e614a9f1c9e2	1934	}
<>	154:37f96f9d4de2	1935	#endif
<>	154:37f96f9d4de2	1936
<>	154:37f96f9d4de2	1937	#if defined(AFIO_MAPR2_TIM16_REMAP)
<>	154:37f96f9d4de2	1938
<>	154:37f96f9d4de2	1939	/**
<>	154:37f96f9d4de2	1940	* @brief Enable the remapping of TIM16_CH1.
AnnaBridge	165:e614a9f1c9e2	1941	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
<>	154:37f96f9d4de2	1942	* @note ENABLE: Remap (TIM16_CH1 on PA6).
<>	154:37f96f9d4de2	1943	* @retval None
<>	154:37f96f9d4de2	1944	*/
AnnaBridge	165:e614a9f1c9e2	1945	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
<>	154:37f96f9d4de2	1946	{
<>	154:37f96f9d4de2	1947	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
<>	154:37f96f9d4de2	1948	}
<>	154:37f96f9d4de2	1949
<>	154:37f96f9d4de2	1950	/**
<>	154:37f96f9d4de2	1951	* @brief Disable the remapping of TIM16_CH1.
AnnaBridge	165:e614a9f1c9e2	1952	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
<>	154:37f96f9d4de2	1953	* @note DISABLE: No remap (TIM16_CH1 on PB8).
<>	154:37f96f9d4de2	1954	* @retval None
<>	154:37f96f9d4de2	1955	*/
AnnaBridge	165:e614a9f1c9e2	1956	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
<>	154:37f96f9d4de2	1957	{
<>	154:37f96f9d4de2	1958	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
<>	154:37f96f9d4de2	1959	}
AnnaBridge	165:e614a9f1c9e2	1960
AnnaBridge	165:e614a9f1c9e2	1961	/**
AnnaBridge	165:e614a9f1c9e2	1962	* @brief Check if TIM16_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1963	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
AnnaBridge	165:e614a9f1c9e2	1964	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1965	*/
AnnaBridge	165:e614a9f1c9e2	1966	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
AnnaBridge	165:e614a9f1c9e2	1967	{
AnnaBridge	165:e614a9f1c9e2	1968	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
AnnaBridge	165:e614a9f1c9e2	1969	}
<>	154:37f96f9d4de2	1970	#endif
<>	154:37f96f9d4de2	1971
<>	154:37f96f9d4de2	1972	#if defined(AFIO_MAPR2_TIM17_REMAP)
<>	154:37f96f9d4de2	1973
<>	154:37f96f9d4de2	1974	/**
<>	154:37f96f9d4de2	1975	* @brief Enable the remapping of TIM17_CH1.
AnnaBridge	165:e614a9f1c9e2	1976	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
<>	154:37f96f9d4de2	1977	* @note ENABLE: Remap (TIM17_CH1 on PA7).
<>	154:37f96f9d4de2	1978	* @retval None
<>	154:37f96f9d4de2	1979	*/
AnnaBridge	165:e614a9f1c9e2	1980	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
<>	154:37f96f9d4de2	1981	{
<>	154:37f96f9d4de2	1982	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
<>	154:37f96f9d4de2	1983	}
<>	154:37f96f9d4de2	1984
<>	154:37f96f9d4de2	1985	/**
<>	154:37f96f9d4de2	1986	* @brief Disable the remapping of TIM17_CH1.
AnnaBridge	165:e614a9f1c9e2	1987	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
<>	154:37f96f9d4de2	1988	* @note DISABLE: No remap (TIM17_CH1 on PB9).
<>	154:37f96f9d4de2	1989	* @retval None
<>	154:37f96f9d4de2	1990	*/
AnnaBridge	165:e614a9f1c9e2	1991	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
<>	154:37f96f9d4de2	1992	{
<>	154:37f96f9d4de2	1993	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
<>	154:37f96f9d4de2	1994	}
AnnaBridge	165:e614a9f1c9e2	1995
AnnaBridge	165:e614a9f1c9e2	1996	/**
AnnaBridge	165:e614a9f1c9e2	1997	* @brief Check if TIM17_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	1998	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
AnnaBridge	165:e614a9f1c9e2	1999	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2000	*/
AnnaBridge	165:e614a9f1c9e2	2001	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
AnnaBridge	165:e614a9f1c9e2	2002	{
AnnaBridge	165:e614a9f1c9e2	2003	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
AnnaBridge	165:e614a9f1c9e2	2004	}
<>	154:37f96f9d4de2	2005	#endif
<>	154:37f96f9d4de2	2006
<>	154:37f96f9d4de2	2007	#if defined(AFIO_MAPR2_CEC_REMAP)
<>	154:37f96f9d4de2	2008
<>	154:37f96f9d4de2	2009	/**
<>	154:37f96f9d4de2	2010	* @brief Enable the remapping of CEC.
AnnaBridge	165:e614a9f1c9e2	2011	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
<>	154:37f96f9d4de2	2012	* @note ENABLE: Remap (CEC on PB10).
<>	154:37f96f9d4de2	2013	* @retval None
<>	154:37f96f9d4de2	2014	*/
AnnaBridge	165:e614a9f1c9e2	2015	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
<>	154:37f96f9d4de2	2016	{
<>	154:37f96f9d4de2	2017	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
<>	154:37f96f9d4de2	2018	}
<>	154:37f96f9d4de2	2019
<>	154:37f96f9d4de2	2020	/**
<>	154:37f96f9d4de2	2021	* @brief Disable the remapping of CEC.
AnnaBridge	165:e614a9f1c9e2	2022	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
<>	154:37f96f9d4de2	2023	* @note DISABLE: No remap (CEC on PB8).
<>	154:37f96f9d4de2	2024	* @retval None
<>	154:37f96f9d4de2	2025	*/
AnnaBridge	165:e614a9f1c9e2	2026	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
<>	154:37f96f9d4de2	2027	{
<>	154:37f96f9d4de2	2028	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
<>	154:37f96f9d4de2	2029	}
AnnaBridge	165:e614a9f1c9e2	2030
AnnaBridge	165:e614a9f1c9e2	2031	/**
AnnaBridge	165:e614a9f1c9e2	2032	* @brief Check if CEC has been remaped or not
AnnaBridge	165:e614a9f1c9e2	2033	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
AnnaBridge	165:e614a9f1c9e2	2034	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2035	*/
AnnaBridge	165:e614a9f1c9e2	2036	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
AnnaBridge	165:e614a9f1c9e2	2037	{
AnnaBridge	165:e614a9f1c9e2	2038	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
AnnaBridge	165:e614a9f1c9e2	2039	}
<>	154:37f96f9d4de2	2040	#endif
<>	154:37f96f9d4de2	2041
<>	154:37f96f9d4de2	2042	#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
<>	154:37f96f9d4de2	2043
<>	154:37f96f9d4de2	2044	/**
<>	154:37f96f9d4de2	2045	* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
AnnaBridge	165:e614a9f1c9e2	2046	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
<>	154:37f96f9d4de2	2047	* @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
<>	154:37f96f9d4de2	2048	* @retval None
<>	154:37f96f9d4de2	2049	*/
AnnaBridge	165:e614a9f1c9e2	2050	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
<>	154:37f96f9d4de2	2051	{
<>	154:37f96f9d4de2	2052	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
<>	154:37f96f9d4de2	2053	}
<>	154:37f96f9d4de2	2054
<>	154:37f96f9d4de2	2055	/**
<>	154:37f96f9d4de2	2056	* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
AnnaBridge	165:e614a9f1c9e2	2057	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
<>	154:37f96f9d4de2	2058	* @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
<>	154:37f96f9d4de2	2059	* @retval None
<>	154:37f96f9d4de2	2060	*/
AnnaBridge	165:e614a9f1c9e2	2061	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
<>	154:37f96f9d4de2	2062	{
<>	154:37f96f9d4de2	2063	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
<>	154:37f96f9d4de2	2064	}
AnnaBridge	165:e614a9f1c9e2	2065
AnnaBridge	165:e614a9f1c9e2	2066	/**
AnnaBridge	165:e614a9f1c9e2	2067	* @brief Check if TIM1DMA has been remaped or not
AnnaBridge	165:e614a9f1c9e2	2068	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
AnnaBridge	165:e614a9f1c9e2	2069	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2070	*/
AnnaBridge	165:e614a9f1c9e2	2071	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
AnnaBridge	165:e614a9f1c9e2	2072	{
AnnaBridge	165:e614a9f1c9e2	2073	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
AnnaBridge	165:e614a9f1c9e2	2074	}
<>	154:37f96f9d4de2	2075	#endif
<>	154:37f96f9d4de2	2076
<>	154:37f96f9d4de2	2077	#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
<>	154:37f96f9d4de2	2078
<>	154:37f96f9d4de2	2079	/**
<>	154:37f96f9d4de2	2080	* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
AnnaBridge	165:e614a9f1c9e2	2081	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
<>	154:37f96f9d4de2	2082	* @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
<>	154:37f96f9d4de2	2083	* @retval None
<>	154:37f96f9d4de2	2084	*/
AnnaBridge	165:e614a9f1c9e2	2085	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
<>	154:37f96f9d4de2	2086	{
<>	154:37f96f9d4de2	2087	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
<>	154:37f96f9d4de2	2088	}
<>	154:37f96f9d4de2	2089
<>	154:37f96f9d4de2	2090	/**
<>	154:37f96f9d4de2	2091	* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
AnnaBridge	165:e614a9f1c9e2	2092	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
<>	154:37f96f9d4de2	2093	* @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
<>	154:37f96f9d4de2	2094	* @retval None
<>	154:37f96f9d4de2	2095	*/
AnnaBridge	165:e614a9f1c9e2	2096	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
<>	154:37f96f9d4de2	2097	{
<>	154:37f96f9d4de2	2098	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
<>	154:37f96f9d4de2	2099	}
AnnaBridge	165:e614a9f1c9e2	2100
AnnaBridge	165:e614a9f1c9e2	2101	/**
AnnaBridge	165:e614a9f1c9e2	2102	* @brief Check if TIM67DACDMA has been remaped or not
AnnaBridge	165:e614a9f1c9e2	2103	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
AnnaBridge	165:e614a9f1c9e2	2104	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2105	*/
AnnaBridge	165:e614a9f1c9e2	2106	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
AnnaBridge	165:e614a9f1c9e2	2107	{
AnnaBridge	165:e614a9f1c9e2	2108	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
AnnaBridge	165:e614a9f1c9e2	2109	}
<>	154:37f96f9d4de2	2110	#endif
<>	154:37f96f9d4de2	2111
<>	154:37f96f9d4de2	2112	#if defined(AFIO_MAPR2_TIM12_REMAP)
<>	154:37f96f9d4de2	2113
<>	154:37f96f9d4de2	2114	/**
<>	154:37f96f9d4de2	2115	* @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
AnnaBridge	165:e614a9f1c9e2	2116	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
<>	154:37f96f9d4de2	2117	* @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
<>	154:37f96f9d4de2	2118	* @note This bit is available only in high density value line devices.
<>	154:37f96f9d4de2	2119	* @retval None
<>	154:37f96f9d4de2	2120	*/
AnnaBridge	165:e614a9f1c9e2	2121	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
<>	154:37f96f9d4de2	2122	{
<>	154:37f96f9d4de2	2123	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
<>	154:37f96f9d4de2	2124	}
<>	154:37f96f9d4de2	2125
<>	154:37f96f9d4de2	2126	/**
<>	154:37f96f9d4de2	2127	* @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
AnnaBridge	165:e614a9f1c9e2	2128	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
<>	154:37f96f9d4de2	2129	* @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
<>	154:37f96f9d4de2	2130	* @note This bit is available only in high density value line devices.
<>	154:37f96f9d4de2	2131	* @retval None
<>	154:37f96f9d4de2	2132	*/
AnnaBridge	165:e614a9f1c9e2	2133	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
<>	154:37f96f9d4de2	2134	{
<>	154:37f96f9d4de2	2135	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
<>	154:37f96f9d4de2	2136	}
AnnaBridge	165:e614a9f1c9e2	2137
AnnaBridge	165:e614a9f1c9e2	2138	/**
AnnaBridge	165:e614a9f1c9e2	2139	* @brief Check if TIM12_CH1 has been remaped or not
AnnaBridge	165:e614a9f1c9e2	2140	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
AnnaBridge	165:e614a9f1c9e2	2141	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2142	*/
AnnaBridge	165:e614a9f1c9e2	2143	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
AnnaBridge	165:e614a9f1c9e2	2144	{
AnnaBridge	165:e614a9f1c9e2	2145	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
AnnaBridge	165:e614a9f1c9e2	2146	}
<>	154:37f96f9d4de2	2147	#endif
<>	154:37f96f9d4de2	2148
<>	154:37f96f9d4de2	2149	#if defined(AFIO_MAPR2_MISC_REMAP)
<>	154:37f96f9d4de2	2150
<>	154:37f96f9d4de2	2151	/**
<>	154:37f96f9d4de2	2152	* @brief Miscellaneous features remapping.
<>	154:37f96f9d4de2	2153	* This bit is set and cleared by software. It controls miscellaneous features.
<>	154:37f96f9d4de2	2154	* The DMA2 channel 5 interrupt position in the vector table.
<>	154:37f96f9d4de2	2155	* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
AnnaBridge	165:e614a9f1c9e2	2156	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
<>	154:37f96f9d4de2	2157	* @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
<>	154:37f96f9d4de2	2158	* selected as DAC Trigger 3, TIM15 triggers TIM1/3.
<>	154:37f96f9d4de2	2159	* @note This bit is available only in high density value line devices.
<>	154:37f96f9d4de2	2160	* @retval None
<>	154:37f96f9d4de2	2161	*/
AnnaBridge	165:e614a9f1c9e2	2162	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
<>	154:37f96f9d4de2	2163	{
<>	154:37f96f9d4de2	2164	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
<>	154:37f96f9d4de2	2165	}
<>	154:37f96f9d4de2	2166
<>	154:37f96f9d4de2	2167	/**
<>	154:37f96f9d4de2	2168	* @brief Miscellaneous features remapping.
<>	154:37f96f9d4de2	2169	* This bit is set and cleared by software. It controls miscellaneous features.
<>	154:37f96f9d4de2	2170	* The DMA2 channel 5 interrupt position in the vector table.
<>	154:37f96f9d4de2	2171	* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
AnnaBridge	165:e614a9f1c9e2	2172	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
<>	154:37f96f9d4de2	2173	* @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
<>	154:37f96f9d4de2	2174	* event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
<>	154:37f96f9d4de2	2175	* @note This bit is available only in high density value line devices.
<>	154:37f96f9d4de2	2176	* @retval None
<>	154:37f96f9d4de2	2177	*/
AnnaBridge	165:e614a9f1c9e2	2178	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
<>	154:37f96f9d4de2	2179	{
<>	154:37f96f9d4de2	2180	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
<>	154:37f96f9d4de2	2181	}
AnnaBridge	165:e614a9f1c9e2	2182
AnnaBridge	165:e614a9f1c9e2	2183	/**
AnnaBridge	165:e614a9f1c9e2	2184	* @brief Check if MISC has been remaped or not
AnnaBridge	165:e614a9f1c9e2	2185	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
AnnaBridge	165:e614a9f1c9e2	2186	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	2187	*/
AnnaBridge	165:e614a9f1c9e2	2188	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
AnnaBridge	165:e614a9f1c9e2	2189	{
AnnaBridge	165:e614a9f1c9e2	2190	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
AnnaBridge	165:e614a9f1c9e2	2191	}
<>	154:37f96f9d4de2	2192	#endif
<>	154:37f96f9d4de2	2193
<>	154:37f96f9d4de2	2194	/**
<>	154:37f96f9d4de2	2195	* @}
<>	154:37f96f9d4de2	2196	*/
<>	154:37f96f9d4de2	2197
AnnaBridge	165:e614a9f1c9e2	2198	/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
<>	154:37f96f9d4de2	2199	* @brief This section propose definition to Configure EVENTOUT Cortex feature .
<>	154:37f96f9d4de2	2200	* @{
<>	154:37f96f9d4de2	2201	*/
<>	154:37f96f9d4de2	2202
<>	154:37f96f9d4de2	2203	/**
<>	154:37f96f9d4de2	2204	* @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
AnnaBridge	165:e614a9f1c9e2	2205	* @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
AnnaBridge	165:e614a9f1c9e2	2206	* EVCR PIN LL_GPIO_AF_ConfigEventout
<>	154:37f96f9d4de2	2207	* @param LL_GPIO_PortSource This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2208	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
AnnaBridge	165:e614a9f1c9e2	2209	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
AnnaBridge	165:e614a9f1c9e2	2210	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
AnnaBridge	165:e614a9f1c9e2	2211	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
AnnaBridge	165:e614a9f1c9e2	2212	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
<>	154:37f96f9d4de2	2213	* @param LL_GPIO_PinSource This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2214	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
AnnaBridge	165:e614a9f1c9e2	2215	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
AnnaBridge	165:e614a9f1c9e2	2216	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
AnnaBridge	165:e614a9f1c9e2	2217	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
AnnaBridge	165:e614a9f1c9e2	2218	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
AnnaBridge	165:e614a9f1c9e2	2219	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
AnnaBridge	165:e614a9f1c9e2	2220	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
AnnaBridge	165:e614a9f1c9e2	2221	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
AnnaBridge	165:e614a9f1c9e2	2222	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
AnnaBridge	165:e614a9f1c9e2	2223	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
AnnaBridge	165:e614a9f1c9e2	2224	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
AnnaBridge	165:e614a9f1c9e2	2225	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
AnnaBridge	165:e614a9f1c9e2	2226	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
AnnaBridge	165:e614a9f1c9e2	2227	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
AnnaBridge	165:e614a9f1c9e2	2228	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
AnnaBridge	165:e614a9f1c9e2	2229	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
<>	154:37f96f9d4de2	2230	* @retval None
<>	154:37f96f9d4de2	2231	*/
AnnaBridge	165:e614a9f1c9e2	2232	__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
<>	154:37f96f9d4de2	2233	{
<>	154:37f96f9d4de2	2234	MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) \| (AFIO_EVCR_PIN), (LL_GPIO_PortSource) \| (LL_GPIO_PinSource));
<>	154:37f96f9d4de2	2235	}
<>	154:37f96f9d4de2	2236
<>	154:37f96f9d4de2	2237	/**
<>	154:37f96f9d4de2	2238	* @brief Enables the Event Output.
AnnaBridge	165:e614a9f1c9e2	2239	* @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
<>	154:37f96f9d4de2	2240	* @retval None
<>	154:37f96f9d4de2	2241	*/
AnnaBridge	165:e614a9f1c9e2	2242	__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
<>	154:37f96f9d4de2	2243	{
<>	154:37f96f9d4de2	2244	SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
<>	154:37f96f9d4de2	2245	}
<>	154:37f96f9d4de2	2246
<>	154:37f96f9d4de2	2247	/**
<>	154:37f96f9d4de2	2248	* @brief Disables the Event Output.
AnnaBridge	165:e614a9f1c9e2	2249	* @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
<>	154:37f96f9d4de2	2250	* @retval None
<>	154:37f96f9d4de2	2251	*/
AnnaBridge	165:e614a9f1c9e2	2252	__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
<>	154:37f96f9d4de2	2253	{
<>	154:37f96f9d4de2	2254	CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
<>	154:37f96f9d4de2	2255	}
<>	154:37f96f9d4de2	2256
<>	154:37f96f9d4de2	2257	/**
<>	154:37f96f9d4de2	2258	* @}
<>	154:37f96f9d4de2	2259	*/
AnnaBridge	165:e614a9f1c9e2	2260	/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
<>	154:37f96f9d4de2	2261	* @brief This section Configure source input for the EXTI external interrupt .
<>	154:37f96f9d4de2	2262	* @{
<>	154:37f96f9d4de2	2263	*/
<>	154:37f96f9d4de2	2264
<>	154:37f96f9d4de2	2265	/**
<>	154:37f96f9d4de2	2266	* @brief Configure source input for the EXTI external interrupt.
AnnaBridge	165:e614a9f1c9e2	2267	* @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
AnnaBridge	165:e614a9f1c9e2	2268	* AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
AnnaBridge	165:e614a9f1c9e2	2269	* AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
AnnaBridge	165:e614a9f1c9e2	2270	* AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
<>	154:37f96f9d4de2	2271	* @param Port This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2272	* @arg @ref LL_GPIO_AF_EXTI_PORTA
AnnaBridge	165:e614a9f1c9e2	2273	* @arg @ref LL_GPIO_AF_EXTI_PORTB
AnnaBridge	165:e614a9f1c9e2	2274	* @arg @ref LL_GPIO_AF_EXTI_PORTC
AnnaBridge	165:e614a9f1c9e2	2275	* @arg @ref LL_GPIO_AF_EXTI_PORTD
AnnaBridge	165:e614a9f1c9e2	2276	* @arg @ref LL_GPIO_AF_EXTI_PORTE
AnnaBridge	165:e614a9f1c9e2	2277	* @arg @ref LL_GPIO_AF_EXTI_PORTF
AnnaBridge	165:e614a9f1c9e2	2278	* @arg @ref LL_GPIO_AF_EXTI_PORTG
<>	154:37f96f9d4de2	2279	* @param Line This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2280	* @arg @ref LL_GPIO_AF_EXTI_LINE0
AnnaBridge	165:e614a9f1c9e2	2281	* @arg @ref LL_GPIO_AF_EXTI_LINE1
AnnaBridge	165:e614a9f1c9e2	2282	* @arg @ref LL_GPIO_AF_EXTI_LINE2
AnnaBridge	165:e614a9f1c9e2	2283	* @arg @ref LL_GPIO_AF_EXTI_LINE3
AnnaBridge	165:e614a9f1c9e2	2284	* @arg @ref LL_GPIO_AF_EXTI_LINE4
AnnaBridge	165:e614a9f1c9e2	2285	* @arg @ref LL_GPIO_AF_EXTI_LINE5
AnnaBridge	165:e614a9f1c9e2	2286	* @arg @ref LL_GPIO_AF_EXTI_LINE6
AnnaBridge	165:e614a9f1c9e2	2287	* @arg @ref LL_GPIO_AF_EXTI_LINE7
AnnaBridge	165:e614a9f1c9e2	2288	* @arg @ref LL_GPIO_AF_EXTI_LINE8
AnnaBridge	165:e614a9f1c9e2	2289	* @arg @ref LL_GPIO_AF_EXTI_LINE9
AnnaBridge	165:e614a9f1c9e2	2290	* @arg @ref LL_GPIO_AF_EXTI_LINE10
AnnaBridge	165:e614a9f1c9e2	2291	* @arg @ref LL_GPIO_AF_EXTI_LINE11
AnnaBridge	165:e614a9f1c9e2	2292	* @arg @ref LL_GPIO_AF_EXTI_LINE12
AnnaBridge	165:e614a9f1c9e2	2293	* @arg @ref LL_GPIO_AF_EXTI_LINE13
AnnaBridge	165:e614a9f1c9e2	2294	* @arg @ref LL_GPIO_AF_EXTI_LINE14
AnnaBridge	165:e614a9f1c9e2	2295	* @arg @ref LL_GPIO_AF_EXTI_LINE15
<>	154:37f96f9d4de2	2296	* @retval None
<>	154:37f96f9d4de2	2297	*/
AnnaBridge	165:e614a9f1c9e2	2298	__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
<>	154:37f96f9d4de2	2299	{
<>	154:37f96f9d4de2	2300	MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
<>	154:37f96f9d4de2	2301	}
<>	154:37f96f9d4de2	2302
<>	154:37f96f9d4de2	2303	/**
<>	154:37f96f9d4de2	2304	* @brief Get the configured defined for specific EXTI Line
AnnaBridge	165:e614a9f1c9e2	2305	* @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
AnnaBridge	165:e614a9f1c9e2	2306	* AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
AnnaBridge	165:e614a9f1c9e2	2307	* AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
AnnaBridge	165:e614a9f1c9e2	2308	* AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
<>	154:37f96f9d4de2	2309	* @param Line This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2310	* @arg @ref LL_GPIO_AF_EXTI_LINE0
AnnaBridge	165:e614a9f1c9e2	2311	* @arg @ref LL_GPIO_AF_EXTI_LINE1
AnnaBridge	165:e614a9f1c9e2	2312	* @arg @ref LL_GPIO_AF_EXTI_LINE2
AnnaBridge	165:e614a9f1c9e2	2313	* @arg @ref LL_GPIO_AF_EXTI_LINE3
AnnaBridge	165:e614a9f1c9e2	2314	* @arg @ref LL_GPIO_AF_EXTI_LINE4
AnnaBridge	165:e614a9f1c9e2	2315	* @arg @ref LL_GPIO_AF_EXTI_LINE5
AnnaBridge	165:e614a9f1c9e2	2316	* @arg @ref LL_GPIO_AF_EXTI_LINE6
AnnaBridge	165:e614a9f1c9e2	2317	* @arg @ref LL_GPIO_AF_EXTI_LINE7
AnnaBridge	165:e614a9f1c9e2	2318	* @arg @ref LL_GPIO_AF_EXTI_LINE8
AnnaBridge	165:e614a9f1c9e2	2319	* @arg @ref LL_GPIO_AF_EXTI_LINE9
AnnaBridge	165:e614a9f1c9e2	2320	* @arg @ref LL_GPIO_AF_EXTI_LINE10
AnnaBridge	165:e614a9f1c9e2	2321	* @arg @ref LL_GPIO_AF_EXTI_LINE11
AnnaBridge	165:e614a9f1c9e2	2322	* @arg @ref LL_GPIO_AF_EXTI_LINE12
AnnaBridge	165:e614a9f1c9e2	2323	* @arg @ref LL_GPIO_AF_EXTI_LINE13
AnnaBridge	165:e614a9f1c9e2	2324	* @arg @ref LL_GPIO_AF_EXTI_LINE14
AnnaBridge	165:e614a9f1c9e2	2325	* @arg @ref LL_GPIO_AF_EXTI_LINE15
<>	154:37f96f9d4de2	2326	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	2327	* @arg @ref LL_GPIO_AF_EXTI_PORTA
AnnaBridge	165:e614a9f1c9e2	2328	* @arg @ref LL_GPIO_AF_EXTI_PORTB
AnnaBridge	165:e614a9f1c9e2	2329	* @arg @ref LL_GPIO_AF_EXTI_PORTC
AnnaBridge	165:e614a9f1c9e2	2330	* @arg @ref LL_GPIO_AF_EXTI_PORTD
AnnaBridge	165:e614a9f1c9e2	2331	* @arg @ref LL_GPIO_AF_EXTI_PORTE
AnnaBridge	165:e614a9f1c9e2	2332	* @arg @ref LL_GPIO_AF_EXTI_PORTF
AnnaBridge	165:e614a9f1c9e2	2333	* @arg @ref LL_GPIO_AF_EXTI_PORTG
<>	154:37f96f9d4de2	2334	*/
AnnaBridge	165:e614a9f1c9e2	2335	__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
<>	154:37f96f9d4de2	2336	{
<>	154:37f96f9d4de2	2337	return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
<>	154:37f96f9d4de2	2338	}
<>	154:37f96f9d4de2	2339
<>	154:37f96f9d4de2	2340	/**
<>	154:37f96f9d4de2	2341	* @}
<>	154:37f96f9d4de2	2342	*/
<>	154:37f96f9d4de2	2343
<>	154:37f96f9d4de2	2344	#if defined(USE_FULL_LL_DRIVER)
<>	154:37f96f9d4de2	2345	/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
<>	154:37f96f9d4de2	2346	* @{
<>	154:37f96f9d4de2	2347	*/
<>	154:37f96f9d4de2	2348
<>	154:37f96f9d4de2	2349	ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
<>	154:37f96f9d4de2	2350	ErrorStatus LL_GPIO_Init(GPIO_TypeDef GPIOx, LL_GPIO_InitTypeDef GPIO_InitStruct);
<>	154:37f96f9d4de2	2351	void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
<>	154:37f96f9d4de2	2352
<>	154:37f96f9d4de2	2353	/**
<>	154:37f96f9d4de2	2354	* @}
<>	154:37f96f9d4de2	2355	*/
<>	154:37f96f9d4de2	2356	#endif /* USE_FULL_LL_DRIVER */
<>	154:37f96f9d4de2	2357
<>	154:37f96f9d4de2	2358	/**
<>	154:37f96f9d4de2	2359	* @}
<>	154:37f96f9d4de2	2360	*/
<>	154:37f96f9d4de2	2361
<>	154:37f96f9d4de2	2362	/**
<>	154:37f96f9d4de2	2363	* @}
<>	154:37f96f9d4de2	2364	*/
<>	154:37f96f9d4de2	2365
<>	154:37f96f9d4de2	2366	#endif /* defined (GPIOA) \|\| defined (GPIOB) \|\| defined (GPIOC) \|\| defined (GPIOD) \|\| defined (GPIOE) \|\| defined (GPIOF) \|\| defined (GPIOG) */
<>	154:37f96f9d4de2	2367	/**
<>	154:37f96f9d4de2	2368	* @}
<>	154:37f96f9d4de2	2369	*/
<>	154:37f96f9d4de2	2370
<>	154:37f96f9d4de2	2371	#ifdef __cplusplus
<>	154:37f96f9d4de2	2372	}
<>	154:37f96f9d4de2	2373	#endif
<>	154:37f96f9d4de2	2374
<>	154:37f96f9d4de2	2375	#endif /* __STM32F1xx_LL_GPIO_H */
<>	154:37f96f9d4de2	2376
<>	154:37f96f9d4de2	2377	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/