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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:e614a9f1c9e2	1	/**
AnnaBridge	165:e614a9f1c9e2	2	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	3	* @file stm32f1xx_ll_dma.c
AnnaBridge	165:e614a9f1c9e2	4	* @author MCD Application Team
AnnaBridge	165:e614a9f1c9e2	5	* @brief DMA LL module driver.
AnnaBridge	165:e614a9f1c9e2	6	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	7	* @attention
AnnaBridge	165:e614a9f1c9e2	8	*
AnnaBridge	165:e614a9f1c9e2	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	165:e614a9f1c9e2	10	*
AnnaBridge	165:e614a9f1c9e2	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:e614a9f1c9e2	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:e614a9f1c9e2	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:e614a9f1c9e2	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:e614a9f1c9e2	17	* and/or other materials provided with the distribution.
AnnaBridge	165:e614a9f1c9e2	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:e614a9f1c9e2	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:e614a9f1c9e2	20	* without specific prior written permission.
AnnaBridge	165:e614a9f1c9e2	21	*
AnnaBridge	165:e614a9f1c9e2	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:e614a9f1c9e2	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:e614a9f1c9e2	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:e614a9f1c9e2	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:e614a9f1c9e2	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:e614a9f1c9e2	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:e614a9f1c9e2	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:e614a9f1c9e2	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:e614a9f1c9e2	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:e614a9f1c9e2	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:e614a9f1c9e2	32	*
AnnaBridge	165:e614a9f1c9e2	33	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	34	*/
AnnaBridge	165:e614a9f1c9e2	35	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	36
AnnaBridge	165:e614a9f1c9e2	37	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	38	#include "stm32f1xx_ll_dma.h"
AnnaBridge	165:e614a9f1c9e2	39	#include "stm32f1xx_ll_bus.h"
AnnaBridge	165:e614a9f1c9e2	40	#ifdef USE_FULL_ASSERT
AnnaBridge	165:e614a9f1c9e2	41	#include "stm32_assert.h"
AnnaBridge	165:e614a9f1c9e2	42	#else
AnnaBridge	165:e614a9f1c9e2	43	#define assert_param(expr) ((void)0U)
AnnaBridge	165:e614a9f1c9e2	44	#endif
AnnaBridge	165:e614a9f1c9e2	45
AnnaBridge	165:e614a9f1c9e2	46	/** @addtogroup STM32F1xx_LL_Driver
AnnaBridge	165:e614a9f1c9e2	47	* @{
AnnaBridge	165:e614a9f1c9e2	48	*/
AnnaBridge	165:e614a9f1c9e2	49
AnnaBridge	165:e614a9f1c9e2	50	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	165:e614a9f1c9e2	51
AnnaBridge	165:e614a9f1c9e2	52	/** @defgroup DMA_LL DMA
AnnaBridge	165:e614a9f1c9e2	53	* @{
AnnaBridge	165:e614a9f1c9e2	54	*/
AnnaBridge	165:e614a9f1c9e2	55
AnnaBridge	165:e614a9f1c9e2	56	/* Private types -------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	57	/* Private variables ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	58	/* Private constants ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	59	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	60	/** @addtogroup DMA_LL_Private_Macros
AnnaBridge	165:e614a9f1c9e2	61	* @{
AnnaBridge	165:e614a9f1c9e2	62	*/
AnnaBridge	165:e614a9f1c9e2	63	#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) \|\| \
AnnaBridge	165:e614a9f1c9e2	64	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) \|\| \
AnnaBridge	165:e614a9f1c9e2	65	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
AnnaBridge	165:e614a9f1c9e2	66
AnnaBridge	165:e614a9f1c9e2	67	#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) \|\| \
AnnaBridge	165:e614a9f1c9e2	68	((__VALUE__) == LL_DMA_MODE_CIRCULAR))
AnnaBridge	165:e614a9f1c9e2	69
AnnaBridge	165:e614a9f1c9e2	70	#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) \|\| \
AnnaBridge	165:e614a9f1c9e2	71	((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
AnnaBridge	165:e614a9f1c9e2	72
AnnaBridge	165:e614a9f1c9e2	73	#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) \|\| \
AnnaBridge	165:e614a9f1c9e2	74	((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
AnnaBridge	165:e614a9f1c9e2	75
AnnaBridge	165:e614a9f1c9e2	76	#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) \|\| \
AnnaBridge	165:e614a9f1c9e2	77	((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) \|\| \
AnnaBridge	165:e614a9f1c9e2	78	((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
AnnaBridge	165:e614a9f1c9e2	79
AnnaBridge	165:e614a9f1c9e2	80	#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) \|\| \
AnnaBridge	165:e614a9f1c9e2	81	((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) \|\| \
AnnaBridge	165:e614a9f1c9e2	82	((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
AnnaBridge	165:e614a9f1c9e2	83
AnnaBridge	165:e614a9f1c9e2	84	#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
AnnaBridge	165:e614a9f1c9e2	85
AnnaBridge	165:e614a9f1c9e2	86	#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) \|\| \
AnnaBridge	165:e614a9f1c9e2	87	((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) \|\| \
AnnaBridge	165:e614a9f1c9e2	88	((__VALUE__) == LL_DMA_PRIORITY_HIGH) \|\| \
AnnaBridge	165:e614a9f1c9e2	89	((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
AnnaBridge	165:e614a9f1c9e2	90
AnnaBridge	165:e614a9f1c9e2	91	#if defined (DMA2)
AnnaBridge	165:e614a9f1c9e2	92	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
AnnaBridge	165:e614a9f1c9e2	93	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
AnnaBridge	165:e614a9f1c9e2	94	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
AnnaBridge	165:e614a9f1c9e2	95	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
AnnaBridge	165:e614a9f1c9e2	96	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
AnnaBridge	165:e614a9f1c9e2	97	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
AnnaBridge	165:e614a9f1c9e2	98	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
AnnaBridge	165:e614a9f1c9e2	99	((CHANNEL) == LL_DMA_CHANNEL_7))) \|\| \
AnnaBridge	165:e614a9f1c9e2	100	(((INSTANCE) == DMA2) && \
AnnaBridge	165:e614a9f1c9e2	101	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
AnnaBridge	165:e614a9f1c9e2	102	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
AnnaBridge	165:e614a9f1c9e2	103	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
AnnaBridge	165:e614a9f1c9e2	104	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
AnnaBridge	165:e614a9f1c9e2	105	((CHANNEL) == LL_DMA_CHANNEL_5))))
AnnaBridge	165:e614a9f1c9e2	106	#else
AnnaBridge	165:e614a9f1c9e2	107	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
AnnaBridge	165:e614a9f1c9e2	108	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
AnnaBridge	165:e614a9f1c9e2	109	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
AnnaBridge	165:e614a9f1c9e2	110	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
AnnaBridge	165:e614a9f1c9e2	111	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
AnnaBridge	165:e614a9f1c9e2	112	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
AnnaBridge	165:e614a9f1c9e2	113	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
AnnaBridge	165:e614a9f1c9e2	114	((CHANNEL) == LL_DMA_CHANNEL_7))))
AnnaBridge	165:e614a9f1c9e2	115	#endif
AnnaBridge	165:e614a9f1c9e2	116	/**
AnnaBridge	165:e614a9f1c9e2	117	* @}
AnnaBridge	165:e614a9f1c9e2	118	*/
AnnaBridge	165:e614a9f1c9e2	119
AnnaBridge	165:e614a9f1c9e2	120	/* Private function prototypes -----------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	121	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	122	/** @addtogroup DMA_LL_Exported_Functions
AnnaBridge	165:e614a9f1c9e2	123	* @{
AnnaBridge	165:e614a9f1c9e2	124	*/
AnnaBridge	165:e614a9f1c9e2	125
AnnaBridge	165:e614a9f1c9e2	126	/** @addtogroup DMA_LL_EF_Init
AnnaBridge	165:e614a9f1c9e2	127	* @{
AnnaBridge	165:e614a9f1c9e2	128	*/
AnnaBridge	165:e614a9f1c9e2	129
AnnaBridge	165:e614a9f1c9e2	130	/**
AnnaBridge	165:e614a9f1c9e2	131	* @brief De-initialize the DMA registers to their default reset values.
AnnaBridge	165:e614a9f1c9e2	132	* @param DMAx DMAx Instance
AnnaBridge	165:e614a9f1c9e2	133	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	134	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	165:e614a9f1c9e2	135	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	165:e614a9f1c9e2	136	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	165:e614a9f1c9e2	137	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	165:e614a9f1c9e2	138	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	165:e614a9f1c9e2	139	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	165:e614a9f1c9e2	140	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	165:e614a9f1c9e2	141	* @retval An ErrorStatus enumeration value:
AnnaBridge	165:e614a9f1c9e2	142	* - SUCCESS: DMA registers are de-initialized
AnnaBridge	165:e614a9f1c9e2	143	* - ERROR: DMA registers are not de-initialized
AnnaBridge	165:e614a9f1c9e2	144	*/
AnnaBridge	165:e614a9f1c9e2	145	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	165:e614a9f1c9e2	146	{
AnnaBridge	165:e614a9f1c9e2	147	DMA_Channel_TypeDef tmp = (DMA_Channel_TypeDef )DMA1_Channel1;
AnnaBridge	165:e614a9f1c9e2	148	ErrorStatus status = SUCCESS;
AnnaBridge	165:e614a9f1c9e2	149
AnnaBridge	165:e614a9f1c9e2	150	/* Check the DMA Instance DMAx and Channel parameters*/
AnnaBridge	165:e614a9f1c9e2	151	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
AnnaBridge	165:e614a9f1c9e2	152
AnnaBridge	165:e614a9f1c9e2	153	tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
AnnaBridge	165:e614a9f1c9e2	154
AnnaBridge	165:e614a9f1c9e2	155	/* Disable the selected DMAx_Channely */
AnnaBridge	165:e614a9f1c9e2	156	CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
AnnaBridge	165:e614a9f1c9e2	157
AnnaBridge	165:e614a9f1c9e2	158	/* Reset DMAx_Channely control register */
AnnaBridge	165:e614a9f1c9e2	159	LL_DMA_WriteReg(tmp, CCR, 0U);
AnnaBridge	165:e614a9f1c9e2	160
AnnaBridge	165:e614a9f1c9e2	161	/* Reset DMAx_Channely remaining bytes register */
AnnaBridge	165:e614a9f1c9e2	162	LL_DMA_WriteReg(tmp, CNDTR, 0U);
AnnaBridge	165:e614a9f1c9e2	163
AnnaBridge	165:e614a9f1c9e2	164	/* Reset DMAx_Channely peripheral address register */
AnnaBridge	165:e614a9f1c9e2	165	LL_DMA_WriteReg(tmp, CPAR, 0U);
AnnaBridge	165:e614a9f1c9e2	166
AnnaBridge	165:e614a9f1c9e2	167	/* Reset DMAx_Channely memory address register */
AnnaBridge	165:e614a9f1c9e2	168	LL_DMA_WriteReg(tmp, CMAR, 0U);
AnnaBridge	165:e614a9f1c9e2	169
AnnaBridge	165:e614a9f1c9e2	170	if (Channel == LL_DMA_CHANNEL_1)
AnnaBridge	165:e614a9f1c9e2	171	{
AnnaBridge	165:e614a9f1c9e2	172	/* Reset interrupt pending bits for DMAx Channel1 */
AnnaBridge	165:e614a9f1c9e2	173	LL_DMA_ClearFlag_GI1(DMAx);
AnnaBridge	165:e614a9f1c9e2	174	}
AnnaBridge	165:e614a9f1c9e2	175	else if (Channel == LL_DMA_CHANNEL_2)
AnnaBridge	165:e614a9f1c9e2	176	{
AnnaBridge	165:e614a9f1c9e2	177	/* Reset interrupt pending bits for DMAx Channel2 */
AnnaBridge	165:e614a9f1c9e2	178	LL_DMA_ClearFlag_GI2(DMAx);
AnnaBridge	165:e614a9f1c9e2	179	}
AnnaBridge	165:e614a9f1c9e2	180	else if (Channel == LL_DMA_CHANNEL_3)
AnnaBridge	165:e614a9f1c9e2	181	{
AnnaBridge	165:e614a9f1c9e2	182	/* Reset interrupt pending bits for DMAx Channel3 */
AnnaBridge	165:e614a9f1c9e2	183	LL_DMA_ClearFlag_GI3(DMAx);
AnnaBridge	165:e614a9f1c9e2	184	}
AnnaBridge	165:e614a9f1c9e2	185	else if (Channel == LL_DMA_CHANNEL_4)
AnnaBridge	165:e614a9f1c9e2	186	{
AnnaBridge	165:e614a9f1c9e2	187	/* Reset interrupt pending bits for DMAx Channel4 */
AnnaBridge	165:e614a9f1c9e2	188	LL_DMA_ClearFlag_GI4(DMAx);
AnnaBridge	165:e614a9f1c9e2	189	}
AnnaBridge	165:e614a9f1c9e2	190	else if (Channel == LL_DMA_CHANNEL_5)
AnnaBridge	165:e614a9f1c9e2	191	{
AnnaBridge	165:e614a9f1c9e2	192	/* Reset interrupt pending bits for DMAx Channel5 */
AnnaBridge	165:e614a9f1c9e2	193	LL_DMA_ClearFlag_GI5(DMAx);
AnnaBridge	165:e614a9f1c9e2	194	}
AnnaBridge	165:e614a9f1c9e2	195
AnnaBridge	165:e614a9f1c9e2	196	else if (Channel == LL_DMA_CHANNEL_6)
AnnaBridge	165:e614a9f1c9e2	197	{
AnnaBridge	165:e614a9f1c9e2	198	/* Reset interrupt pending bits for DMAx Channel6 */
AnnaBridge	165:e614a9f1c9e2	199	LL_DMA_ClearFlag_GI6(DMAx);
AnnaBridge	165:e614a9f1c9e2	200	}
AnnaBridge	165:e614a9f1c9e2	201	else if (Channel == LL_DMA_CHANNEL_7)
AnnaBridge	165:e614a9f1c9e2	202	{
AnnaBridge	165:e614a9f1c9e2	203	/* Reset interrupt pending bits for DMAx Channel7 */
AnnaBridge	165:e614a9f1c9e2	204	LL_DMA_ClearFlag_GI7(DMAx);
AnnaBridge	165:e614a9f1c9e2	205	}
AnnaBridge	165:e614a9f1c9e2	206	else
AnnaBridge	165:e614a9f1c9e2	207	{
AnnaBridge	165:e614a9f1c9e2	208	status = ERROR;
AnnaBridge	165:e614a9f1c9e2	209	}
AnnaBridge	165:e614a9f1c9e2	210
AnnaBridge	165:e614a9f1c9e2	211	return status;
AnnaBridge	165:e614a9f1c9e2	212	}
AnnaBridge	165:e614a9f1c9e2	213
AnnaBridge	165:e614a9f1c9e2	214	/**
AnnaBridge	165:e614a9f1c9e2	215	* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
AnnaBridge	165:e614a9f1c9e2	216	* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
AnnaBridge	165:e614a9f1c9e2	217	* @arg @ref __LL_DMA_GET_INSTANCE
AnnaBridge	165:e614a9f1c9e2	218	* @arg @ref __LL_DMA_GET_CHANNEL
AnnaBridge	165:e614a9f1c9e2	219	* @param DMAx DMAx Instance
AnnaBridge	165:e614a9f1c9e2	220	* @param Channel This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	221	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	165:e614a9f1c9e2	222	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	165:e614a9f1c9e2	223	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	165:e614a9f1c9e2	224	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	165:e614a9f1c9e2	225	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	165:e614a9f1c9e2	226	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	165:e614a9f1c9e2	227	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	165:e614a9f1c9e2	228	* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
AnnaBridge	165:e614a9f1c9e2	229	* @retval An ErrorStatus enumeration value:
AnnaBridge	165:e614a9f1c9e2	230	* - SUCCESS: DMA registers are initialized
AnnaBridge	165:e614a9f1c9e2	231	* - ERROR: Not applicable
AnnaBridge	165:e614a9f1c9e2	232	*/
AnnaBridge	165:e614a9f1c9e2	233	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct)
AnnaBridge	165:e614a9f1c9e2	234	{
AnnaBridge	165:e614a9f1c9e2	235	/* Check the DMA Instance DMAx and Channel parameters*/
AnnaBridge	165:e614a9f1c9e2	236	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
AnnaBridge	165:e614a9f1c9e2	237
AnnaBridge	165:e614a9f1c9e2	238	/* Check the DMA parameters from DMA_InitStruct */
AnnaBridge	165:e614a9f1c9e2	239	assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
AnnaBridge	165:e614a9f1c9e2	240	assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
AnnaBridge	165:e614a9f1c9e2	241	assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
AnnaBridge	165:e614a9f1c9e2	242	assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
AnnaBridge	165:e614a9f1c9e2	243	assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
AnnaBridge	165:e614a9f1c9e2	244	assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
AnnaBridge	165:e614a9f1c9e2	245	assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
AnnaBridge	165:e614a9f1c9e2	246	assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
AnnaBridge	165:e614a9f1c9e2	247
AnnaBridge	165:e614a9f1c9e2	248	/*---------------------------- DMAx CCR Configuration ------------------------
AnnaBridge	165:e614a9f1c9e2	249	* Configure DMAx_Channely: data transfer direction, data transfer mode,
AnnaBridge	165:e614a9f1c9e2	250	* peripheral and memory increment mode,
AnnaBridge	165:e614a9f1c9e2	251	* data size alignment and priority level with parameters :
AnnaBridge	165:e614a9f1c9e2	252	* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
AnnaBridge	165:e614a9f1c9e2	253	* - Mode: DMA_CCR_CIRC bit
AnnaBridge	165:e614a9f1c9e2	254	* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
AnnaBridge	165:e614a9f1c9e2	255	* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
AnnaBridge	165:e614a9f1c9e2	256	* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
AnnaBridge	165:e614a9f1c9e2	257	* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
AnnaBridge	165:e614a9f1c9e2	258	* - Priority: DMA_CCR_PL[1:0] bits
AnnaBridge	165:e614a9f1c9e2	259	*/
AnnaBridge	165:e614a9f1c9e2	260	LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction \| \
AnnaBridge	165:e614a9f1c9e2	261	DMA_InitStruct->Mode \| \
AnnaBridge	165:e614a9f1c9e2	262	DMA_InitStruct->PeriphOrM2MSrcIncMode \| \
AnnaBridge	165:e614a9f1c9e2	263	DMA_InitStruct->MemoryOrM2MDstIncMode \| \
AnnaBridge	165:e614a9f1c9e2	264	DMA_InitStruct->PeriphOrM2MSrcDataSize \| \
AnnaBridge	165:e614a9f1c9e2	265	DMA_InitStruct->MemoryOrM2MDstDataSize \| \
AnnaBridge	165:e614a9f1c9e2	266	DMA_InitStruct->Priority);
AnnaBridge	165:e614a9f1c9e2	267
AnnaBridge	165:e614a9f1c9e2	268	/*-------------------------- DMAx CMAR Configuration -------------------------
AnnaBridge	165:e614a9f1c9e2	269	* Configure the memory or destination base address with parameter :
AnnaBridge	165:e614a9f1c9e2	270	* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
AnnaBridge	165:e614a9f1c9e2	271	*/
AnnaBridge	165:e614a9f1c9e2	272	LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
AnnaBridge	165:e614a9f1c9e2	273
AnnaBridge	165:e614a9f1c9e2	274	/*-------------------------- DMAx CPAR Configuration -------------------------
AnnaBridge	165:e614a9f1c9e2	275	* Configure the peripheral or source base address with parameter :
AnnaBridge	165:e614a9f1c9e2	276	* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
AnnaBridge	165:e614a9f1c9e2	277	*/
AnnaBridge	165:e614a9f1c9e2	278	LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
AnnaBridge	165:e614a9f1c9e2	279
AnnaBridge	165:e614a9f1c9e2	280	/*--------------------------- DMAx CNDTR Configuration -----------------------
AnnaBridge	165:e614a9f1c9e2	281	* Configure the peripheral base address with parameter :
AnnaBridge	165:e614a9f1c9e2	282	* - NbData: DMA_CNDTR_NDT[15:0] bits
AnnaBridge	165:e614a9f1c9e2	283	*/
AnnaBridge	165:e614a9f1c9e2	284	LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
AnnaBridge	165:e614a9f1c9e2	285
AnnaBridge	165:e614a9f1c9e2	286	return SUCCESS;
AnnaBridge	165:e614a9f1c9e2	287	}
AnnaBridge	165:e614a9f1c9e2	288
AnnaBridge	165:e614a9f1c9e2	289	/**
AnnaBridge	165:e614a9f1c9e2	290	* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
AnnaBridge	165:e614a9f1c9e2	291	* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
AnnaBridge	165:e614a9f1c9e2	292	* @retval None
AnnaBridge	165:e614a9f1c9e2	293	*/
AnnaBridge	165:e614a9f1c9e2	294	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
AnnaBridge	165:e614a9f1c9e2	295	{
AnnaBridge	165:e614a9f1c9e2	296	/* Set DMA_InitStruct fields to default values */
AnnaBridge	165:e614a9f1c9e2	297	DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
AnnaBridge	165:e614a9f1c9e2	298	DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
AnnaBridge	165:e614a9f1c9e2	299	DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
AnnaBridge	165:e614a9f1c9e2	300	DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
AnnaBridge	165:e614a9f1c9e2	301	DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
AnnaBridge	165:e614a9f1c9e2	302	DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
AnnaBridge	165:e614a9f1c9e2	303	DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
AnnaBridge	165:e614a9f1c9e2	304	DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
AnnaBridge	165:e614a9f1c9e2	305	DMA_InitStruct->NbData = 0x00000000U;
AnnaBridge	165:e614a9f1c9e2	306	DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
AnnaBridge	165:e614a9f1c9e2	307	}
AnnaBridge	165:e614a9f1c9e2	308
AnnaBridge	165:e614a9f1c9e2	309	/**
AnnaBridge	165:e614a9f1c9e2	310	* @}
AnnaBridge	165:e614a9f1c9e2	311	*/
AnnaBridge	165:e614a9f1c9e2	312
AnnaBridge	165:e614a9f1c9e2	313	/**
AnnaBridge	165:e614a9f1c9e2	314	* @}
AnnaBridge	165:e614a9f1c9e2	315	*/
AnnaBridge	165:e614a9f1c9e2	316
AnnaBridge	165:e614a9f1c9e2	317	/**
AnnaBridge	165:e614a9f1c9e2	318	* @}
AnnaBridge	165:e614a9f1c9e2	319	*/
AnnaBridge	165:e614a9f1c9e2	320
AnnaBridge	165:e614a9f1c9e2	321	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	165:e614a9f1c9e2	322
AnnaBridge	165:e614a9f1c9e2	323	/**
AnnaBridge	165:e614a9f1c9e2	324	* @}
AnnaBridge	165:e614a9f1c9e2	325	*/
AnnaBridge	165:e614a9f1c9e2	326
AnnaBridge	165:e614a9f1c9e2	327	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	328
AnnaBridge	165:e614a9f1c9e2	329	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/