mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /**
<> 154:37f96f9d4de2 2 ******************************************************************************
<> 154:37f96f9d4de2 3 * @file stm32f1xx_ll_cortex.h
<> 154:37f96f9d4de2 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @brief Header file of CORTEX LL module.
<> 154:37f96f9d4de2 6 @verbatim
<> 154:37f96f9d4de2 7 ==============================================================================
<> 154:37f96f9d4de2 8 ##### How to use this driver #####
<> 154:37f96f9d4de2 9 ==============================================================================
<> 154:37f96f9d4de2 10 [..]
<> 154:37f96f9d4de2 11 The LL CORTEX driver contains a set of generic APIs that can be
<> 154:37f96f9d4de2 12 used by user:
<> 154:37f96f9d4de2 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
<> 154:37f96f9d4de2 14 functions
<> 154:37f96f9d4de2 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
<> 154:37f96f9d4de2 16 (+) MPU API to configure and enable regions
<> 154:37f96f9d4de2 17 (MPU services provided only on some devices)
<> 154:37f96f9d4de2 18 (+) API to access to MCU info (CPUID register)
<> 154:37f96f9d4de2 19 (+) API to enable fault handler (SHCSR accesses)
<> 154:37f96f9d4de2 20
<> 154:37f96f9d4de2 21 @endverbatim
<> 154:37f96f9d4de2 22 ******************************************************************************
<> 154:37f96f9d4de2 23 * @attention
<> 154:37f96f9d4de2 24 *
<> 154:37f96f9d4de2 25 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 154:37f96f9d4de2 26 *
<> 154:37f96f9d4de2 27 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 28 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 29 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 30 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 31 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 32 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 33 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 34 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 35 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 36 * without specific prior written permission.
<> 154:37f96f9d4de2 37 *
<> 154:37f96f9d4de2 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 41 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 44 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 45 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 46 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 48 *
<> 154:37f96f9d4de2 49 ******************************************************************************
<> 154:37f96f9d4de2 50 */
<> 154:37f96f9d4de2 51
<> 154:37f96f9d4de2 52 /* Define to prevent recursive inclusion -------------------------------------*/
<> 154:37f96f9d4de2 53 #ifndef __STM32F1xx_LL_CORTEX_H
<> 154:37f96f9d4de2 54 #define __STM32F1xx_LL_CORTEX_H
<> 154:37f96f9d4de2 55
<> 154:37f96f9d4de2 56 #ifdef __cplusplus
<> 154:37f96f9d4de2 57 extern "C" {
<> 154:37f96f9d4de2 58 #endif
<> 154:37f96f9d4de2 59
<> 154:37f96f9d4de2 60 /* Includes ------------------------------------------------------------------*/
<> 154:37f96f9d4de2 61 #include "stm32f1xx.h"
<> 154:37f96f9d4de2 62
<> 154:37f96f9d4de2 63 /** @addtogroup STM32F1xx_LL_Driver
<> 154:37f96f9d4de2 64 * @{
<> 154:37f96f9d4de2 65 */
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 /** @defgroup CORTEX_LL CORTEX
<> 154:37f96f9d4de2 68 * @{
<> 154:37f96f9d4de2 69 */
<> 154:37f96f9d4de2 70
<> 154:37f96f9d4de2 71 /* Private types -------------------------------------------------------------*/
<> 154:37f96f9d4de2 72 /* Private variables ---------------------------------------------------------*/
<> 154:37f96f9d4de2 73
<> 154:37f96f9d4de2 74 /* Private constants ---------------------------------------------------------*/
<> 154:37f96f9d4de2 75
<> 154:37f96f9d4de2 76 /* Private macros ------------------------------------------------------------*/
<> 154:37f96f9d4de2 77
<> 154:37f96f9d4de2 78 /* Exported types ------------------------------------------------------------*/
<> 154:37f96f9d4de2 79 /* Exported constants --------------------------------------------------------*/
<> 154:37f96f9d4de2 80 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
<> 154:37f96f9d4de2 81 * @{
<> 154:37f96f9d4de2 82 */
<> 154:37f96f9d4de2 83
<> 154:37f96f9d4de2 84 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
<> 154:37f96f9d4de2 85 * @{
<> 154:37f96f9d4de2 86 */
AnnaBridge 165:e614a9f1c9e2 87 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 165:e614a9f1c9e2 88 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
<> 154:37f96f9d4de2 89 /**
<> 154:37f96f9d4de2 90 * @}
<> 154:37f96f9d4de2 91 */
<> 154:37f96f9d4de2 92
<> 154:37f96f9d4de2 93 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
<> 154:37f96f9d4de2 94 * @{
<> 154:37f96f9d4de2 95 */
<> 154:37f96f9d4de2 96 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
<> 154:37f96f9d4de2 97 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
<> 154:37f96f9d4de2 98 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
<> 154:37f96f9d4de2 99 /**
<> 154:37f96f9d4de2 100 * @}
<> 154:37f96f9d4de2 101 */
<> 154:37f96f9d4de2 102
<> 154:37f96f9d4de2 103 #if __MPU_PRESENT
<> 154:37f96f9d4de2 104
<> 154:37f96f9d4de2 105 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
<> 154:37f96f9d4de2 106 * @{
<> 154:37f96f9d4de2 107 */
AnnaBridge 165:e614a9f1c9e2 108 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
<> 154:37f96f9d4de2 109 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
<> 154:37f96f9d4de2 110 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
<> 154:37f96f9d4de2 111 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
<> 154:37f96f9d4de2 112 /**
<> 154:37f96f9d4de2 113 * @}
<> 154:37f96f9d4de2 114 */
<> 154:37f96f9d4de2 115
<> 154:37f96f9d4de2 116 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
<> 154:37f96f9d4de2 117 * @{
<> 154:37f96f9d4de2 118 */
AnnaBridge 165:e614a9f1c9e2 119 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 165:e614a9f1c9e2 120 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 165:e614a9f1c9e2 121 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 165:e614a9f1c9e2 122 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 165:e614a9f1c9e2 123 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 165:e614a9f1c9e2 124 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 165:e614a9f1c9e2 125 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 165:e614a9f1c9e2 126 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
<> 154:37f96f9d4de2 127 /**
<> 154:37f96f9d4de2 128 * @}
<> 154:37f96f9d4de2 129 */
<> 154:37f96f9d4de2 130
<> 154:37f96f9d4de2 131 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
<> 154:37f96f9d4de2 132 * @{
<> 154:37f96f9d4de2 133 */
AnnaBridge 165:e614a9f1c9e2 134 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 135 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 136 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 137 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 138 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 139 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 140 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 141 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 142 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 143 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 144 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 145 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 146 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 147 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 148 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 149 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 150 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 151 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 152 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 153 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 154 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 155 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 156 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 157 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 158 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 159 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 160 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 165:e614a9f1c9e2 161 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
<> 154:37f96f9d4de2 162 /**
<> 154:37f96f9d4de2 163 * @}
<> 154:37f96f9d4de2 164 */
<> 154:37f96f9d4de2 165
<> 154:37f96f9d4de2 166 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
<> 154:37f96f9d4de2 167 * @{
<> 154:37f96f9d4de2 168 */
AnnaBridge 165:e614a9f1c9e2 169 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 165:e614a9f1c9e2 170 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 165:e614a9f1c9e2 171 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 165:e614a9f1c9e2 172 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 165:e614a9f1c9e2 173 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 165:e614a9f1c9e2 174 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
<> 154:37f96f9d4de2 175 /**
<> 154:37f96f9d4de2 176 * @}
<> 154:37f96f9d4de2 177 */
<> 154:37f96f9d4de2 178
<> 154:37f96f9d4de2 179 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
<> 154:37f96f9d4de2 180 * @{
<> 154:37f96f9d4de2 181 */
AnnaBridge 165:e614a9f1c9e2 182 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 165:e614a9f1c9e2 183 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 165:e614a9f1c9e2 184 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 165:e614a9f1c9e2 185 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
<> 154:37f96f9d4de2 186 /**
<> 154:37f96f9d4de2 187 * @}
<> 154:37f96f9d4de2 188 */
<> 154:37f96f9d4de2 189
<> 154:37f96f9d4de2 190 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
<> 154:37f96f9d4de2 191 * @{
<> 154:37f96f9d4de2 192 */
AnnaBridge 165:e614a9f1c9e2 193 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
<> 154:37f96f9d4de2 194 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
<> 154:37f96f9d4de2 195 /**
<> 154:37f96f9d4de2 196 * @}
<> 154:37f96f9d4de2 197 */
<> 154:37f96f9d4de2 198
<> 154:37f96f9d4de2 199 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
<> 154:37f96f9d4de2 200 * @{
<> 154:37f96f9d4de2 201 */
<> 154:37f96f9d4de2 202 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 165:e614a9f1c9e2 203 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
<> 154:37f96f9d4de2 204 /**
<> 154:37f96f9d4de2 205 * @}
<> 154:37f96f9d4de2 206 */
<> 154:37f96f9d4de2 207
<> 154:37f96f9d4de2 208 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
<> 154:37f96f9d4de2 209 * @{
<> 154:37f96f9d4de2 210 */
<> 154:37f96f9d4de2 211 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 165:e614a9f1c9e2 212 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
<> 154:37f96f9d4de2 213 /**
<> 154:37f96f9d4de2 214 * @}
<> 154:37f96f9d4de2 215 */
<> 154:37f96f9d4de2 216
<> 154:37f96f9d4de2 217 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
<> 154:37f96f9d4de2 218 * @{
<> 154:37f96f9d4de2 219 */
<> 154:37f96f9d4de2 220 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 165:e614a9f1c9e2 221 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
<> 154:37f96f9d4de2 222 /**
<> 154:37f96f9d4de2 223 * @}
<> 154:37f96f9d4de2 224 */
<> 154:37f96f9d4de2 225 #endif /* __MPU_PRESENT */
<> 154:37f96f9d4de2 226 /**
<> 154:37f96f9d4de2 227 * @}
<> 154:37f96f9d4de2 228 */
<> 154:37f96f9d4de2 229
<> 154:37f96f9d4de2 230 /* Exported macro ------------------------------------------------------------*/
<> 154:37f96f9d4de2 231
<> 154:37f96f9d4de2 232 /* Exported functions --------------------------------------------------------*/
<> 154:37f96f9d4de2 233 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
<> 154:37f96f9d4de2 234 * @{
<> 154:37f96f9d4de2 235 */
<> 154:37f96f9d4de2 236
<> 154:37f96f9d4de2 237 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
<> 154:37f96f9d4de2 238 * @{
<> 154:37f96f9d4de2 239 */
<> 154:37f96f9d4de2 240
<> 154:37f96f9d4de2 241 /**
<> 154:37f96f9d4de2 242 * @brief This function checks if the Systick counter flag is active or not.
<> 154:37f96f9d4de2 243 * @note It can be used in timeout function on application side.
<> 154:37f96f9d4de2 244 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
<> 154:37f96f9d4de2 245 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 246 */
<> 154:37f96f9d4de2 247 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
<> 154:37f96f9d4de2 248 {
<> 154:37f96f9d4de2 249 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
<> 154:37f96f9d4de2 250 }
<> 154:37f96f9d4de2 251
<> 154:37f96f9d4de2 252 /**
<> 154:37f96f9d4de2 253 * @brief Configures the SysTick clock source
<> 154:37f96f9d4de2 254 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
<> 154:37f96f9d4de2 255 * @param Source This parameter can be one of the following values:
<> 154:37f96f9d4de2 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 154:37f96f9d4de2 257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 154:37f96f9d4de2 258 * @retval None
<> 154:37f96f9d4de2 259 */
<> 154:37f96f9d4de2 260 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
<> 154:37f96f9d4de2 261 {
<> 154:37f96f9d4de2 262 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
<> 154:37f96f9d4de2 263 {
<> 154:37f96f9d4de2 264 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 154:37f96f9d4de2 265 }
<> 154:37f96f9d4de2 266 else
<> 154:37f96f9d4de2 267 {
<> 154:37f96f9d4de2 268 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 154:37f96f9d4de2 269 }
<> 154:37f96f9d4de2 270 }
<> 154:37f96f9d4de2 271
<> 154:37f96f9d4de2 272 /**
<> 154:37f96f9d4de2 273 * @brief Get the SysTick clock source
<> 154:37f96f9d4de2 274 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
<> 154:37f96f9d4de2 275 * @retval Returned value can be one of the following values:
<> 154:37f96f9d4de2 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 154:37f96f9d4de2 277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 154:37f96f9d4de2 278 */
<> 154:37f96f9d4de2 279 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
<> 154:37f96f9d4de2 280 {
<> 154:37f96f9d4de2 281 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 154:37f96f9d4de2 282 }
<> 154:37f96f9d4de2 283
<> 154:37f96f9d4de2 284 /**
<> 154:37f96f9d4de2 285 * @brief Enable SysTick exception request
<> 154:37f96f9d4de2 286 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
<> 154:37f96f9d4de2 287 * @retval None
<> 154:37f96f9d4de2 288 */
<> 154:37f96f9d4de2 289 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
<> 154:37f96f9d4de2 290 {
<> 154:37f96f9d4de2 291 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 154:37f96f9d4de2 292 }
<> 154:37f96f9d4de2 293
<> 154:37f96f9d4de2 294 /**
<> 154:37f96f9d4de2 295 * @brief Disable SysTick exception request
<> 154:37f96f9d4de2 296 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
<> 154:37f96f9d4de2 297 * @retval None
<> 154:37f96f9d4de2 298 */
<> 154:37f96f9d4de2 299 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
<> 154:37f96f9d4de2 300 {
<> 154:37f96f9d4de2 301 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 154:37f96f9d4de2 302 }
<> 154:37f96f9d4de2 303
<> 154:37f96f9d4de2 304 /**
<> 154:37f96f9d4de2 305 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
<> 154:37f96f9d4de2 306 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
<> 154:37f96f9d4de2 307 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 308 */
<> 154:37f96f9d4de2 309 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
<> 154:37f96f9d4de2 310 {
<> 154:37f96f9d4de2 311 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
<> 154:37f96f9d4de2 312 }
<> 154:37f96f9d4de2 313
<> 154:37f96f9d4de2 314 /**
<> 154:37f96f9d4de2 315 * @}
<> 154:37f96f9d4de2 316 */
<> 154:37f96f9d4de2 317
<> 154:37f96f9d4de2 318 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
<> 154:37f96f9d4de2 319 * @{
<> 154:37f96f9d4de2 320 */
<> 154:37f96f9d4de2 321
<> 154:37f96f9d4de2 322 /**
<> 154:37f96f9d4de2 323 * @brief Processor uses sleep as its low power mode
<> 154:37f96f9d4de2 324 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
<> 154:37f96f9d4de2 325 * @retval None
<> 154:37f96f9d4de2 326 */
<> 154:37f96f9d4de2 327 __STATIC_INLINE void LL_LPM_EnableSleep(void)
<> 154:37f96f9d4de2 328 {
<> 154:37f96f9d4de2 329 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 154:37f96f9d4de2 330 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 154:37f96f9d4de2 331 }
<> 154:37f96f9d4de2 332
<> 154:37f96f9d4de2 333 /**
<> 154:37f96f9d4de2 334 * @brief Processor uses deep sleep as its low power mode
<> 154:37f96f9d4de2 335 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
<> 154:37f96f9d4de2 336 * @retval None
<> 154:37f96f9d4de2 337 */
<> 154:37f96f9d4de2 338 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
<> 154:37f96f9d4de2 339 {
<> 154:37f96f9d4de2 340 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 154:37f96f9d4de2 341 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 154:37f96f9d4de2 342 }
<> 154:37f96f9d4de2 343
<> 154:37f96f9d4de2 344 /**
<> 154:37f96f9d4de2 345 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
<> 154:37f96f9d4de2 346 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
<> 154:37f96f9d4de2 347 * empty main application.
<> 154:37f96f9d4de2 348 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
<> 154:37f96f9d4de2 349 * @retval None
<> 154:37f96f9d4de2 350 */
<> 154:37f96f9d4de2 351 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
<> 154:37f96f9d4de2 352 {
<> 154:37f96f9d4de2 353 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 154:37f96f9d4de2 354 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 154:37f96f9d4de2 355 }
<> 154:37f96f9d4de2 356
<> 154:37f96f9d4de2 357 /**
<> 154:37f96f9d4de2 358 * @brief Do not sleep when returning to Thread mode.
<> 154:37f96f9d4de2 359 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
<> 154:37f96f9d4de2 360 * @retval None
<> 154:37f96f9d4de2 361 */
<> 154:37f96f9d4de2 362 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
<> 154:37f96f9d4de2 363 {
<> 154:37f96f9d4de2 364 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 154:37f96f9d4de2 365 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 154:37f96f9d4de2 366 }
<> 154:37f96f9d4de2 367
<> 154:37f96f9d4de2 368 /**
<> 154:37f96f9d4de2 369 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
<> 154:37f96f9d4de2 370 * processor.
<> 154:37f96f9d4de2 371 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
<> 154:37f96f9d4de2 372 * @retval None
<> 154:37f96f9d4de2 373 */
<> 154:37f96f9d4de2 374 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
<> 154:37f96f9d4de2 375 {
<> 154:37f96f9d4de2 376 /* Set SEVEONPEND bit of Cortex System Control Register */
<> 154:37f96f9d4de2 377 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 154:37f96f9d4de2 378 }
<> 154:37f96f9d4de2 379
<> 154:37f96f9d4de2 380 /**
<> 154:37f96f9d4de2 381 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
<> 154:37f96f9d4de2 382 * excluded
<> 154:37f96f9d4de2 383 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
<> 154:37f96f9d4de2 384 * @retval None
<> 154:37f96f9d4de2 385 */
<> 154:37f96f9d4de2 386 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
<> 154:37f96f9d4de2 387 {
<> 154:37f96f9d4de2 388 /* Clear SEVEONPEND bit of Cortex System Control Register */
<> 154:37f96f9d4de2 389 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 154:37f96f9d4de2 390 }
<> 154:37f96f9d4de2 391
<> 154:37f96f9d4de2 392 /**
<> 154:37f96f9d4de2 393 * @}
<> 154:37f96f9d4de2 394 */
<> 154:37f96f9d4de2 395
<> 154:37f96f9d4de2 396 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
<> 154:37f96f9d4de2 397 * @{
<> 154:37f96f9d4de2 398 */
<> 154:37f96f9d4de2 399
<> 154:37f96f9d4de2 400 /**
<> 154:37f96f9d4de2 401 * @brief Enable a fault in System handler control register (SHCSR)
<> 154:37f96f9d4de2 402 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
<> 154:37f96f9d4de2 403 * @param Fault This parameter can be a combination of the following values:
<> 154:37f96f9d4de2 404 * @arg @ref LL_HANDLER_FAULT_USG
<> 154:37f96f9d4de2 405 * @arg @ref LL_HANDLER_FAULT_BUS
<> 154:37f96f9d4de2 406 * @arg @ref LL_HANDLER_FAULT_MEM
<> 154:37f96f9d4de2 407 * @retval None
<> 154:37f96f9d4de2 408 */
<> 154:37f96f9d4de2 409 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
<> 154:37f96f9d4de2 410 {
<> 154:37f96f9d4de2 411 /* Enable the system handler fault */
<> 154:37f96f9d4de2 412 SET_BIT(SCB->SHCSR, Fault);
<> 154:37f96f9d4de2 413 }
<> 154:37f96f9d4de2 414
<> 154:37f96f9d4de2 415 /**
<> 154:37f96f9d4de2 416 * @brief Disable a fault in System handler control register (SHCSR)
<> 154:37f96f9d4de2 417 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
<> 154:37f96f9d4de2 418 * @param Fault This parameter can be a combination of the following values:
<> 154:37f96f9d4de2 419 * @arg @ref LL_HANDLER_FAULT_USG
<> 154:37f96f9d4de2 420 * @arg @ref LL_HANDLER_FAULT_BUS
<> 154:37f96f9d4de2 421 * @arg @ref LL_HANDLER_FAULT_MEM
<> 154:37f96f9d4de2 422 * @retval None
<> 154:37f96f9d4de2 423 */
<> 154:37f96f9d4de2 424 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
<> 154:37f96f9d4de2 425 {
<> 154:37f96f9d4de2 426 /* Disable the system handler fault */
<> 154:37f96f9d4de2 427 CLEAR_BIT(SCB->SHCSR, Fault);
<> 154:37f96f9d4de2 428 }
<> 154:37f96f9d4de2 429
<> 154:37f96f9d4de2 430 /**
<> 154:37f96f9d4de2 431 * @}
<> 154:37f96f9d4de2 432 */
<> 154:37f96f9d4de2 433
<> 154:37f96f9d4de2 434 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
<> 154:37f96f9d4de2 435 * @{
<> 154:37f96f9d4de2 436 */
<> 154:37f96f9d4de2 437
<> 154:37f96f9d4de2 438 /**
<> 154:37f96f9d4de2 439 * @brief Get Implementer code
<> 154:37f96f9d4de2 440 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
<> 154:37f96f9d4de2 441 * @retval Value should be equal to 0x41 for ARM
<> 154:37f96f9d4de2 442 */
<> 154:37f96f9d4de2 443 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
<> 154:37f96f9d4de2 444 {
<> 154:37f96f9d4de2 445 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
<> 154:37f96f9d4de2 446 }
<> 154:37f96f9d4de2 447
<> 154:37f96f9d4de2 448 /**
<> 154:37f96f9d4de2 449 * @brief Get Variant number (The r value in the rnpn product revision identifier)
<> 154:37f96f9d4de2 450 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
<> 154:37f96f9d4de2 451 * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
<> 154:37f96f9d4de2 452 */
<> 154:37f96f9d4de2 453 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
<> 154:37f96f9d4de2 454 {
<> 154:37f96f9d4de2 455 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
<> 154:37f96f9d4de2 456 }
<> 154:37f96f9d4de2 457
<> 154:37f96f9d4de2 458 /**
<> 154:37f96f9d4de2 459 * @brief Get Constant number
<> 154:37f96f9d4de2 460 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
<> 154:37f96f9d4de2 461 * @retval Value should be equal to 0xF for Cortex-M3 devices
<> 154:37f96f9d4de2 462 */
<> 154:37f96f9d4de2 463 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
<> 154:37f96f9d4de2 464 {
<> 154:37f96f9d4de2 465 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
<> 154:37f96f9d4de2 466 }
<> 154:37f96f9d4de2 467
<> 154:37f96f9d4de2 468 /**
<> 154:37f96f9d4de2 469 * @brief Get Part number
<> 154:37f96f9d4de2 470 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
<> 154:37f96f9d4de2 471 * @retval Value should be equal to 0xC23 for Cortex-M3
<> 154:37f96f9d4de2 472 */
<> 154:37f96f9d4de2 473 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
<> 154:37f96f9d4de2 474 {
<> 154:37f96f9d4de2 475 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
<> 154:37f96f9d4de2 476 }
<> 154:37f96f9d4de2 477
<> 154:37f96f9d4de2 478 /**
<> 154:37f96f9d4de2 479 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
<> 154:37f96f9d4de2 480 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
<> 154:37f96f9d4de2 481 * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
<> 154:37f96f9d4de2 482 */
<> 154:37f96f9d4de2 483 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
<> 154:37f96f9d4de2 484 {
<> 154:37f96f9d4de2 485 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
<> 154:37f96f9d4de2 486 }
<> 154:37f96f9d4de2 487
<> 154:37f96f9d4de2 488 /**
<> 154:37f96f9d4de2 489 * @}
<> 154:37f96f9d4de2 490 */
<> 154:37f96f9d4de2 491
<> 154:37f96f9d4de2 492 #if __MPU_PRESENT
<> 154:37f96f9d4de2 493 /** @defgroup CORTEX_LL_EF_MPU MPU
<> 154:37f96f9d4de2 494 * @{
<> 154:37f96f9d4de2 495 */
<> 154:37f96f9d4de2 496
<> 154:37f96f9d4de2 497 /**
<> 154:37f96f9d4de2 498 * @brief Enable MPU with input options
<> 154:37f96f9d4de2 499 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
<> 154:37f96f9d4de2 500 * @param Options This parameter can be one of the following values:
<> 154:37f96f9d4de2 501 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
<> 154:37f96f9d4de2 502 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
<> 154:37f96f9d4de2 503 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
<> 154:37f96f9d4de2 504 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
<> 154:37f96f9d4de2 505 * @retval None
<> 154:37f96f9d4de2 506 */
<> 154:37f96f9d4de2 507 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
<> 154:37f96f9d4de2 508 {
<> 154:37f96f9d4de2 509 /* Enable the MPU*/
<> 154:37f96f9d4de2 510 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
<> 154:37f96f9d4de2 511 /* Ensure MPU settings take effects */
<> 154:37f96f9d4de2 512 __DSB();
<> 154:37f96f9d4de2 513 /* Sequence instruction fetches using update settings */
<> 154:37f96f9d4de2 514 __ISB();
<> 154:37f96f9d4de2 515 }
<> 154:37f96f9d4de2 516
<> 154:37f96f9d4de2 517 /**
<> 154:37f96f9d4de2 518 * @brief Disable MPU
<> 154:37f96f9d4de2 519 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
<> 154:37f96f9d4de2 520 * @retval None
<> 154:37f96f9d4de2 521 */
<> 154:37f96f9d4de2 522 __STATIC_INLINE void LL_MPU_Disable(void)
<> 154:37f96f9d4de2 523 {
<> 154:37f96f9d4de2 524 /* Make sure outstanding transfers are done */
<> 154:37f96f9d4de2 525 __DMB();
<> 154:37f96f9d4de2 526 /* Disable MPU*/
<> 154:37f96f9d4de2 527 WRITE_REG(MPU->CTRL, 0U);
<> 154:37f96f9d4de2 528 }
<> 154:37f96f9d4de2 529
<> 154:37f96f9d4de2 530 /**
<> 154:37f96f9d4de2 531 * @brief Check if MPU is enabled or not
<> 154:37f96f9d4de2 532 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
<> 154:37f96f9d4de2 533 * @retval State of bit (1 or 0).
<> 154:37f96f9d4de2 534 */
<> 154:37f96f9d4de2 535 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
<> 154:37f96f9d4de2 536 {
<> 154:37f96f9d4de2 537 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
<> 154:37f96f9d4de2 538 }
<> 154:37f96f9d4de2 539
<> 154:37f96f9d4de2 540 /**
<> 154:37f96f9d4de2 541 * @brief Enable a MPU region
<> 154:37f96f9d4de2 542 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
<> 154:37f96f9d4de2 543 * @param Region This parameter can be one of the following values:
<> 154:37f96f9d4de2 544 * @arg @ref LL_MPU_REGION_NUMBER0
<> 154:37f96f9d4de2 545 * @arg @ref LL_MPU_REGION_NUMBER1
<> 154:37f96f9d4de2 546 * @arg @ref LL_MPU_REGION_NUMBER2
<> 154:37f96f9d4de2 547 * @arg @ref LL_MPU_REGION_NUMBER3
<> 154:37f96f9d4de2 548 * @arg @ref LL_MPU_REGION_NUMBER4
<> 154:37f96f9d4de2 549 * @arg @ref LL_MPU_REGION_NUMBER5
<> 154:37f96f9d4de2 550 * @arg @ref LL_MPU_REGION_NUMBER6
<> 154:37f96f9d4de2 551 * @arg @ref LL_MPU_REGION_NUMBER7
<> 154:37f96f9d4de2 552 * @retval None
<> 154:37f96f9d4de2 553 */
<> 154:37f96f9d4de2 554 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
<> 154:37f96f9d4de2 555 {
<> 154:37f96f9d4de2 556 /* Set Region number */
<> 154:37f96f9d4de2 557 WRITE_REG(MPU->RNR, Region);
<> 154:37f96f9d4de2 558 /* Enable the MPU region */
<> 154:37f96f9d4de2 559 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 154:37f96f9d4de2 560 }
<> 154:37f96f9d4de2 561
<> 154:37f96f9d4de2 562 /**
<> 154:37f96f9d4de2 563 * @brief Configure and enable a region
<> 154:37f96f9d4de2 564 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 565 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 566 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 567 * MPU_RASR XN LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 568 * MPU_RASR AP LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 569 * MPU_RASR S LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 570 * MPU_RASR C LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 571 * MPU_RASR B LL_MPU_ConfigRegion\n
<> 154:37f96f9d4de2 572 * MPU_RASR SIZE LL_MPU_ConfigRegion
<> 154:37f96f9d4de2 573 * @param Region This parameter can be one of the following values:
<> 154:37f96f9d4de2 574 * @arg @ref LL_MPU_REGION_NUMBER0
<> 154:37f96f9d4de2 575 * @arg @ref LL_MPU_REGION_NUMBER1
<> 154:37f96f9d4de2 576 * @arg @ref LL_MPU_REGION_NUMBER2
<> 154:37f96f9d4de2 577 * @arg @ref LL_MPU_REGION_NUMBER3
<> 154:37f96f9d4de2 578 * @arg @ref LL_MPU_REGION_NUMBER4
<> 154:37f96f9d4de2 579 * @arg @ref LL_MPU_REGION_NUMBER5
<> 154:37f96f9d4de2 580 * @arg @ref LL_MPU_REGION_NUMBER6
<> 154:37f96f9d4de2 581 * @arg @ref LL_MPU_REGION_NUMBER7
<> 154:37f96f9d4de2 582 * @param Address Value of region base address
<> 154:37f96f9d4de2 583 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
<> 154:37f96f9d4de2 584 * @param Attributes This parameter can be a combination of the following values:
<> 154:37f96f9d4de2 585 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
<> 154:37f96f9d4de2 586 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
<> 154:37f96f9d4de2 587 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
<> 154:37f96f9d4de2 588 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
<> 154:37f96f9d4de2 589 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
<> 154:37f96f9d4de2 590 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
<> 154:37f96f9d4de2 591 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
<> 154:37f96f9d4de2 592 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
<> 154:37f96f9d4de2 593 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
<> 154:37f96f9d4de2 594 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
<> 154:37f96f9d4de2 595 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
<> 154:37f96f9d4de2 596 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
<> 154:37f96f9d4de2 597 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
<> 154:37f96f9d4de2 598 * @retval None
<> 154:37f96f9d4de2 599 */
<> 154:37f96f9d4de2 600 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
<> 154:37f96f9d4de2 601 {
<> 154:37f96f9d4de2 602 /* Set Region number */
<> 154:37f96f9d4de2 603 WRITE_REG(MPU->RNR, Region);
<> 154:37f96f9d4de2 604 /* Set base address */
<> 154:37f96f9d4de2 605 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
<> 154:37f96f9d4de2 606 /* Configure MPU */
<> 154:37f96f9d4de2 607 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
<> 154:37f96f9d4de2 608 }
<> 154:37f96f9d4de2 609
<> 154:37f96f9d4de2 610 /**
<> 154:37f96f9d4de2 611 * @brief Disable a region
<> 154:37f96f9d4de2 612 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
<> 154:37f96f9d4de2 613 * MPU_RASR ENABLE LL_MPU_DisableRegion
<> 154:37f96f9d4de2 614 * @param Region This parameter can be one of the following values:
<> 154:37f96f9d4de2 615 * @arg @ref LL_MPU_REGION_NUMBER0
<> 154:37f96f9d4de2 616 * @arg @ref LL_MPU_REGION_NUMBER1
<> 154:37f96f9d4de2 617 * @arg @ref LL_MPU_REGION_NUMBER2
<> 154:37f96f9d4de2 618 * @arg @ref LL_MPU_REGION_NUMBER3
<> 154:37f96f9d4de2 619 * @arg @ref LL_MPU_REGION_NUMBER4
<> 154:37f96f9d4de2 620 * @arg @ref LL_MPU_REGION_NUMBER5
<> 154:37f96f9d4de2 621 * @arg @ref LL_MPU_REGION_NUMBER6
<> 154:37f96f9d4de2 622 * @arg @ref LL_MPU_REGION_NUMBER7
<> 154:37f96f9d4de2 623 * @retval None
<> 154:37f96f9d4de2 624 */
<> 154:37f96f9d4de2 625 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
<> 154:37f96f9d4de2 626 {
<> 154:37f96f9d4de2 627 /* Set Region number */
<> 154:37f96f9d4de2 628 WRITE_REG(MPU->RNR, Region);
<> 154:37f96f9d4de2 629 /* Disable the MPU region */
<> 154:37f96f9d4de2 630 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 154:37f96f9d4de2 631 }
<> 154:37f96f9d4de2 632
<> 154:37f96f9d4de2 633 /**
<> 154:37f96f9d4de2 634 * @}
<> 154:37f96f9d4de2 635 */
<> 154:37f96f9d4de2 636
<> 154:37f96f9d4de2 637 #endif /* __MPU_PRESENT */
<> 154:37f96f9d4de2 638 /**
<> 154:37f96f9d4de2 639 * @}
<> 154:37f96f9d4de2 640 */
<> 154:37f96f9d4de2 641
<> 154:37f96f9d4de2 642 /**
<> 154:37f96f9d4de2 643 * @}
<> 154:37f96f9d4de2 644 */
<> 154:37f96f9d4de2 645
<> 154:37f96f9d4de2 646 /**
<> 154:37f96f9d4de2 647 * @}
<> 154:37f96f9d4de2 648 */
<> 154:37f96f9d4de2 649
<> 154:37f96f9d4de2 650 #ifdef __cplusplus
<> 154:37f96f9d4de2 651 }
<> 154:37f96f9d4de2 652 #endif
<> 154:37f96f9d4de2 653
<> 154:37f96f9d4de2 654 #endif /* __STM32F1xx_LL_CORTEX_H */
<> 154:37f96f9d4de2 655
<> 154:37f96f9d4de2 656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/