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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_sram.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief SRAM HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides a generic firmware to drive SRAM memories
<> 144:ef7eb2e8f9f7 7 * mounted as external device.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 @verbatim
<> 144:ef7eb2e8f9f7 10 ==============================================================================
<> 144:ef7eb2e8f9f7 11 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 [..]
<> 144:ef7eb2e8f9f7 14 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 15 control SRAM memories. It uses the FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 16 with SRAM devices.
<> 144:ef7eb2e8f9f7 17 The following sequence should be followed to configure the FSMC to interface
<> 144:ef7eb2e8f9f7 18 with SRAM/PSRAM memories:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 21 SRAM_HandleTypeDef hsram; and:
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
<> 144:ef7eb2e8f9f7 24 values of the structure member.
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
<> 144:ef7eb2e8f9f7 27 base register instance for NOR or SRAM device
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
<> 144:ef7eb2e8f9f7 30 base register instance for NOR or SRAM extended mode
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
<> 144:ef7eb2e8f9f7 33 mode timings; for example:
<> 144:ef7eb2e8f9f7 34 FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
<> 144:ef7eb2e8f9f7 35 and fill its fields with the allowed values of the structure member.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
<> 144:ef7eb2e8f9f7 38 performs the following sequence:
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
<> 144:ef7eb2e8f9f7 41 (##) Control register configuration using the FSMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 42 FSMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 43 (##) Timing register configuration using the FSMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 44 FSMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 45 (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 46 FSMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 47 (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 (#) At this stage you can perform read/write accesses from/to the memory connected
<> 144:ef7eb2e8f9f7 50 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
<> 144:ef7eb2e8f9f7 51 following APIs:
<> 144:ef7eb2e8f9f7 52 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
<> 144:ef7eb2e8f9f7 53 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 56 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (#) You can continuously monitor the SRAM device HAL state by calling the function
<> 144:ef7eb2e8f9f7 59 HAL_SRAM_GetState()
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 @endverbatim
<> 144:ef7eb2e8f9f7 62 ******************************************************************************
<> 144:ef7eb2e8f9f7 63 * @attention
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 68 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 69 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 70 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 71 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 72 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 73 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 74 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 75 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 76 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 79 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 80 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 81 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 82 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 83 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 84 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 85 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 86 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 ******************************************************************************
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 93 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 96 * @{
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #ifdef HAL_SRAM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @defgroup SRAM SRAM
<> 144:ef7eb2e8f9f7 104 * @brief SRAM driver modules
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 108 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 109 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 111 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 119 * @brief Initialization and Configuration functions.
<> 144:ef7eb2e8f9f7 120 *
<> 144:ef7eb2e8f9f7 121 @verbatim
<> 144:ef7eb2e8f9f7 122 ==============================================================================
<> 144:ef7eb2e8f9f7 123 ##### SRAM Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 124 ==============================================================================
<> 144:ef7eb2e8f9f7 125 [..] This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 126 the SRAM memory
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 @endverbatim
<> 144:ef7eb2e8f9f7 129 * @{
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief Performs the SRAM device initialization sequence
<> 144:ef7eb2e8f9f7 134 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 135 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 136 * @param Timing: Pointer to SRAM control timing structure
<> 144:ef7eb2e8f9f7 137 * @param ExtTiming: Pointer to SRAM extended mode timing structure
<> 144:ef7eb2e8f9f7 138 * @retval HAL status
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 144:ef7eb2e8f9f7 141 {
<> 144:ef7eb2e8f9f7 142 /* Check the SRAM handle parameter */
<> 144:ef7eb2e8f9f7 143 if(hsram == NULL)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 if(hsram->State == HAL_SRAM_STATE_RESET)
<> 144:ef7eb2e8f9f7 149 {
<> 144:ef7eb2e8f9f7 150 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 151 hsram->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 154 HAL_SRAM_MspInit(hsram);
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Initialize SRAM control Interface */
<> 144:ef7eb2e8f9f7 158 FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Initialize SRAM timing Interface */
<> 144:ef7eb2e8f9f7 161 FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Initialize SRAM extended mode timing Interface */
<> 144:ef7eb2e8f9f7 164 FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Enable the NORSRAM device */
<> 144:ef7eb2e8f9f7 167 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 return HAL_OK;
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @brief Performs the SRAM device De-initialization sequence.
<> 144:ef7eb2e8f9f7 174 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 175 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 176 * @retval HAL status
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 /* De-Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 181 HAL_SRAM_MspDeInit(hsram);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Configure the SRAM registers with their reset values */
<> 144:ef7eb2e8f9f7 184 FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 hsram->State = HAL_SRAM_STATE_RESET;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Release Lock */
<> 144:ef7eb2e8f9f7 189 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 return HAL_OK;
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @brief SRAM MSP Init.
<> 144:ef7eb2e8f9f7 196 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 197 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 198 * @retval None
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 203 UNUSED(hsram);
<> 144:ef7eb2e8f9f7 204 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 205 the HAL_SRAM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @brief SRAM MSP DeInit.
<> 144:ef7eb2e8f9f7 211 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 212 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 213 * @retval None
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 218 UNUSED(hsram);
<> 144:ef7eb2e8f9f7 219 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 220 the HAL_SRAM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 226 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 227 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 228 * @retval None
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 233 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 234 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 235 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /**
<> 144:ef7eb2e8f9f7 240 * @brief DMA transfer complete error callback.
<> 144:ef7eb2e8f9f7 241 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 242 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 243 * @retval None
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 248 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 249 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 250 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @}
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
<> 144:ef7eb2e8f9f7 259 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 260 *
<> 144:ef7eb2e8f9f7 261 @verbatim
<> 144:ef7eb2e8f9f7 262 ==============================================================================
<> 144:ef7eb2e8f9f7 263 ##### SRAM Input and Output functions #####
<> 144:ef7eb2e8f9f7 264 ==============================================================================
<> 144:ef7eb2e8f9f7 265 [..]
<> 144:ef7eb2e8f9f7 266 This section provides functions allowing to use and control the SRAM memory
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 @endverbatim
<> 144:ef7eb2e8f9f7 269 * @{
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief Reads 8-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 274 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 275 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 276 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 277 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 278 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 279 * @retval HAL status
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Process Locked */
<> 144:ef7eb2e8f9f7 286 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 289 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Read data from memory */
AnnaBridge 165:e614a9f1c9e2 292 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 *pDstBuffer = *(__IO uint8_t *)psramaddress;
<> 144:ef7eb2e8f9f7 295 pDstBuffer++;
<> 144:ef7eb2e8f9f7 296 psramaddress++;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 300 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Process unlocked */
<> 144:ef7eb2e8f9f7 303 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 return HAL_OK;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @brief Writes 8-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 310 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 311 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 312 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 313 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 314 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 315 * @retval HAL status
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 322 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Process Locked */
<> 144:ef7eb2e8f9f7 328 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 331 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Write data to memory */
AnnaBridge 165:e614a9f1c9e2 334 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 337 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 338 psramaddress++;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 342 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Process unlocked */
<> 144:ef7eb2e8f9f7 345 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 return HAL_OK;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @brief Reads 16-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 352 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 353 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 354 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 355 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 356 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 357 * @retval HAL status
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Process Locked */
<> 144:ef7eb2e8f9f7 364 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 367 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Read data from memory */
AnnaBridge 165:e614a9f1c9e2 370 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 *pDstBuffer = *(__IO uint16_t *)psramaddress;
<> 144:ef7eb2e8f9f7 373 pDstBuffer++;
<> 144:ef7eb2e8f9f7 374 psramaddress++;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 378 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Process unlocked */
<> 144:ef7eb2e8f9f7 381 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 return HAL_OK;
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @brief Writes 16-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 388 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 389 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 390 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 391 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 392 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 393 * @retval HAL status
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 400 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Process Locked */
<> 144:ef7eb2e8f9f7 406 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 409 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Write data to memory */
AnnaBridge 165:e614a9f1c9e2 412 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 415 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 416 psramaddress++;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 420 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Process unlocked */
<> 144:ef7eb2e8f9f7 423 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 return HAL_OK;
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @brief Reads 32-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 430 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 431 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 432 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 433 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 434 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 435 * @retval HAL status
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 438 {
<> 144:ef7eb2e8f9f7 439 /* Process Locked */
<> 144:ef7eb2e8f9f7 440 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 443 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Read data from memory */
AnnaBridge 165:e614a9f1c9e2 446 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 *pDstBuffer = *(__IO uint32_t *)pAddress;
<> 144:ef7eb2e8f9f7 449 pDstBuffer++;
<> 144:ef7eb2e8f9f7 450 pAddress++;
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 454 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Process unlocked */
<> 144:ef7eb2e8f9f7 457 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 return HAL_OK;
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @brief Writes 32-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 464 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 465 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 466 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 467 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 468 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 469 * @retval HAL status
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 474 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Process Locked */
<> 144:ef7eb2e8f9f7 480 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 483 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Write data to memory */
AnnaBridge 165:e614a9f1c9e2 486 for(; BufferSize != 0U; BufferSize--)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 *(__IO uint32_t *)pAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 489 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 490 pAddress++;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 494 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Process unlocked */
<> 144:ef7eb2e8f9f7 497 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 return HAL_OK;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /**
<> 144:ef7eb2e8f9f7 503 * @brief Reads a Words data from the SRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 504 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 505 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 506 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 507 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 508 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 509 * @retval HAL status
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 /* Process Locked */
<> 144:ef7eb2e8f9f7 514 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 517 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 520 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 521 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Enable the DMA Channel */
<> 144:ef7eb2e8f9f7 524 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 527 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Process unlocked */
<> 144:ef7eb2e8f9f7 530 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 return HAL_OK;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /**
<> 144:ef7eb2e8f9f7 536 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 537 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 538 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 539 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 540 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 541 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 542 * @retval HAL status
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 547 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Process Locked */
<> 144:ef7eb2e8f9f7 553 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 556 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 559 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 560 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Enable the DMA Channel */
<> 144:ef7eb2e8f9f7 563 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 566 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Process unlocked */
<> 144:ef7eb2e8f9f7 569 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 return HAL_OK;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /**
<> 144:ef7eb2e8f9f7 575 * @}
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
<> 144:ef7eb2e8f9f7 579 * @brief Control functions
<> 144:ef7eb2e8f9f7 580 *
<> 144:ef7eb2e8f9f7 581 @verbatim
<> 144:ef7eb2e8f9f7 582 ==============================================================================
<> 144:ef7eb2e8f9f7 583 ##### SRAM Control functions #####
<> 144:ef7eb2e8f9f7 584 ==============================================================================
<> 144:ef7eb2e8f9f7 585 [..]
<> 144:ef7eb2e8f9f7 586 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 587 the SRAM interface.
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 @endverbatim
<> 144:ef7eb2e8f9f7 590 * @{
<> 144:ef7eb2e8f9f7 591 */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /**
<> 144:ef7eb2e8f9f7 594 * @brief Enables dynamically SRAM write operation.
<> 144:ef7eb2e8f9f7 595 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 596 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 597 * @retval HAL status
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Process Locked */
<> 144:ef7eb2e8f9f7 602 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Enable write operation */
<> 144:ef7eb2e8f9f7 605 FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 608 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Process unlocked */
<> 144:ef7eb2e8f9f7 611 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 return HAL_OK;
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @brief Disables dynamically SRAM write operation.
<> 144:ef7eb2e8f9f7 618 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 619 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 620 * @retval HAL status
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 /* Process Locked */
<> 144:ef7eb2e8f9f7 625 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 628 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Disable write operation */
<> 144:ef7eb2e8f9f7 631 FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 634 hsram->State = HAL_SRAM_STATE_PROTECTED;
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Process unlocked */
<> 144:ef7eb2e8f9f7 637 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 return HAL_OK;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /**
<> 144:ef7eb2e8f9f7 643 * @}
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 647 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 648 *
<> 144:ef7eb2e8f9f7 649 @verbatim
<> 144:ef7eb2e8f9f7 650 ==============================================================================
<> 144:ef7eb2e8f9f7 651 ##### SRAM State functions #####
<> 144:ef7eb2e8f9f7 652 ==============================================================================
<> 144:ef7eb2e8f9f7 653 [..]
<> 144:ef7eb2e8f9f7 654 This subsection permits to get in run-time the status of the SRAM controller
<> 144:ef7eb2e8f9f7 655 and the data flow.
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 @endverbatim
<> 144:ef7eb2e8f9f7 658 * @{
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /**
<> 144:ef7eb2e8f9f7 662 * @brief Returns the SRAM controller state
<> 144:ef7eb2e8f9f7 663 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 664 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 665 * @retval HAL state
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 return hsram->State;
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @}
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @}
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /**
<> 144:ef7eb2e8f9f7 681 * @}
<> 144:ef7eb2e8f9f7 682 */
<> 144:ef7eb2e8f9f7 683 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
<> 144:ef7eb2e8f9f7 684 #endif /* HAL_SRAM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @}
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/