mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_spi_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Extended SPI HAL module driver.
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities SPI extension peripheral:
<> 144:ef7eb2e8f9f7 9 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 ******************************************************************************
<> 144:ef7eb2e8f9f7 12 * @attention
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 17 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 18 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 20 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 22 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 24 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 25 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 *
<> 144:ef7eb2e8f9f7 38 ******************************************************************************
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 42 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 45 * @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup SPI_Private_Variables SPI Private Variables
AnnaBridge 165:e614a9f1c9e2 54 * @{
AnnaBridge 165:e614a9f1c9e2 55 */
AnnaBridge 165:e614a9f1c9e2 56 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 57 /* Variable used to determine if device is impacted by implementation of workaround
<> 144:ef7eb2e8f9f7 58 related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
<> 144:ef7eb2e8f9f7 59 - STM32F101CDE/STM32F103CDE
<> 144:ef7eb2e8f9f7 60 - Revision ID : Z
<> 144:ef7eb2e8f9f7 61 - SPI2
<> 144:ef7eb2e8f9f7 62 - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
<> 144:ef7eb2e8f9f7 63 the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
<> 144:ef7eb2e8f9f7 64 + If the value is 0, the complete data transfer is successful.
<> 144:ef7eb2e8f9f7 65 + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
<> 144:ef7eb2e8f9f7 66 If CRCERR is found reset, the complete data transfer is considered successful.
<> 144:ef7eb2e8f9f7 67 */
AnnaBridge 165:e614a9f1c9e2 68 uint8_t uCRCErrorWorkaroundCheck = 0U;
AnnaBridge 165:e614a9f1c9e2 69 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 70 /**
<> 144:ef7eb2e8f9f7 71 * @}
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @addtogroup SPI_Exported_Functions
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @addtogroup SPI_Exported_Functions_Group1
AnnaBridge 165:e614a9f1c9e2 87 *
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @brief Initializes the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 93 * in the SPI_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 94 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 95 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 96 * @retval HAL status
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 101 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 102 {
<> 144:ef7eb2e8f9f7 103 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* Check the parameters */
<> 144:ef7eb2e8f9f7 107 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 108 assert_param(IS_SPI_MODE(hspi->Init.Mode));
AnnaBridge 165:e614a9f1c9e2 109 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 110 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 111 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 144:ef7eb2e8f9f7 112 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 144:ef7eb2e8f9f7 113 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 114 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 115 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
AnnaBridge 165:e614a9f1c9e2 116
AnnaBridge 165:e614a9f1c9e2 117 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 118 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
AnnaBridge 165:e614a9f1c9e2 119 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
AnnaBridge 165:e614a9f1c9e2 120 {
AnnaBridge 165:e614a9f1c9e2 121 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
AnnaBridge 165:e614a9f1c9e2 122 }
AnnaBridge 165:e614a9f1c9e2 123 #else
AnnaBridge 165:e614a9f1c9e2 124 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
AnnaBridge 165:e614a9f1c9e2 125 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 if(hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 130 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* Disble the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 136 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 139 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
<> 144:ef7eb2e8f9f7 140 Communication speed, First bit and CRC calculation state */
<> 144:ef7eb2e8f9f7 141 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
<> 144:ef7eb2e8f9f7 142 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 144:ef7eb2e8f9f7 143 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /* Configure : NSS management */
AnnaBridge 165:e614a9f1c9e2 146 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 149 /* Configure : CRC Polynomial */
<> 144:ef7eb2e8f9f7 150 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<> 144:ef7eb2e8f9f7 151
AnnaBridge 165:e614a9f1c9e2 152 #if defined(SPI_I2SCFGR_I2SMOD)
<> 144:ef7eb2e8f9f7 153 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 144:ef7eb2e8f9f7 154 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
AnnaBridge 165:e614a9f1c9e2 155 #endif /* SPI_I2SCFGR_I2SMOD */
<> 144:ef7eb2e8f9f7 156
AnnaBridge 165:e614a9f1c9e2 157 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 158 #if defined (STM32F101xE) || defined (STM32F103xE)
<> 144:ef7eb2e8f9f7 159 /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
<> 144:ef7eb2e8f9f7 160 CRC errors wrongly detected */
<> 144:ef7eb2e8f9f7 161 /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
<> 144:ef7eb2e8f9f7 162 Revision ID information is only available in Debug mode, so Workaround could not be implemented
<> 144:ef7eb2e8f9f7 163 to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
<> 144:ef7eb2e8f9f7 164 So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
AnnaBridge 165:e614a9f1c9e2 165 uCRCErrorWorkaroundCheck = 0U;
<> 144:ef7eb2e8f9f7 166 #else
AnnaBridge 165:e614a9f1c9e2 167 uCRCErrorWorkaroundCheck = 0U;
AnnaBridge 165:e614a9f1c9e2 168 #endif /* STM32F101xE || STM32F103xE */
AnnaBridge 165:e614a9f1c9e2 169 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 172 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 return HAL_OK;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @}
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /** @addtogroup SPI_Private_Functions
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
AnnaBridge 165:e614a9f1c9e2 188 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
<> 144:ef7eb2e8f9f7 191 * according to SPI instance, Device type, and revision ID.
<> 144:ef7eb2e8f9f7 192 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 193 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 194 * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 197 {
AnnaBridge 165:e614a9f1c9e2 198 #if defined(STM32F101xE) || defined(STM32F103xE)
<> 144:ef7eb2e8f9f7 199 /* Check how to handle this CRC error (workaround to be applied or not) */
<> 144:ef7eb2e8f9f7 200 /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
AnnaBridge 165:e614a9f1c9e2 201 if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2))
<> 144:ef7eb2e8f9f7 202 {
AnnaBridge 165:e614a9f1c9e2 203 if(hspi->Instance->RXCRCR == 0U)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 return (SPI_INVALID_CRC_ERROR);
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208 return (SPI_VALID_CRC_ERROR);
<> 144:ef7eb2e8f9f7 209 #else
AnnaBridge 165:e614a9f1c9e2 210 /* Prevent unused argument(s) compilation warning */
AnnaBridge 165:e614a9f1c9e2 211 UNUSED(hspi);
AnnaBridge 165:e614a9f1c9e2 212
<> 144:ef7eb2e8f9f7 213 return (SPI_VALID_CRC_ERROR);
<> 144:ef7eb2e8f9f7 214 #endif
<> 144:ef7eb2e8f9f7 215 }
AnnaBridge 165:e614a9f1c9e2 216 #endif /* USE_SPI_CRC */
AnnaBridge 165:e614a9f1c9e2 217
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @}
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/