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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_rcc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Extended RCC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities RCC extension peripheral:
<> 144:ef7eb2e8f9f7 8 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 ******************************************************************************
<> 144:ef7eb2e8f9f7 11 * @attention
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 16 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 17 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 19 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 21 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 22 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 23 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 24 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 ******************************************************************************
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 41 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 44 * @{
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @defgroup RCCEx RCCEx
<> 144:ef7eb2e8f9f7 50 * @brief RCC Extension HAL module driver.
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 55 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
AnnaBridge 165:e614a9f1c9e2 57 * @{
AnnaBridge 165:e614a9f1c9e2 58 */
<> 144:ef7eb2e8f9f7 59 /**
<> 144:ef7eb2e8f9f7 60 * @}
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 64 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge 165:e614a9f1c9e2 65 * @{
AnnaBridge 165:e614a9f1c9e2 66 */
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @}
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 72 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 73 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<> 144:ef7eb2e8f9f7 76 * @{
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
AnnaBridge 165:e614a9f1c9e2 80 * @brief Extended Peripheral Control functions
AnnaBridge 165:e614a9f1c9e2 81 *
<> 144:ef7eb2e8f9f7 82 @verbatim
<> 144:ef7eb2e8f9f7 83 ===============================================================================
<> 144:ef7eb2e8f9f7 84 ##### Extended Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 85 ===============================================================================
<> 144:ef7eb2e8f9f7 86 [..]
<> 144:ef7eb2e8f9f7 87 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 88 frequencies.
<> 144:ef7eb2e8f9f7 89 [..]
<> 144:ef7eb2e8f9f7 90 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<> 144:ef7eb2e8f9f7 91 select the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 92 order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 93 the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 @endverbatim
<> 144:ef7eb2e8f9f7 96 * @{
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
<> 144:ef7eb2e8f9f7 101 * RCC_PeriphCLKInitTypeDef.
<> 144:ef7eb2e8f9f7 102 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 103 * contains the configuration information for the Extended Peripherals clocks(RTC clock).
<> 144:ef7eb2e8f9f7 104 *
<> 144:ef7eb2e8f9f7 105 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
<> 144:ef7eb2e8f9f7 106 * the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 107 * order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 108 * the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 109 *
<> 144:ef7eb2e8f9f7 110 * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
<> 144:ef7eb2e8f9f7 111 * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
<> 144:ef7eb2e8f9f7 112 * manually disable it.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * @retval HAL status
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 117 {
AnnaBridge 165:e614a9f1c9e2 118 uint32_t tickstart = 0U, temp_reg = 0U;
<> 144:ef7eb2e8f9f7 119 #if defined(STM32F105xC) || defined(STM32F107xC)
AnnaBridge 165:e614a9f1c9e2 120 uint32_t pllactive = 0U;
<> 144:ef7eb2e8f9f7 121 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Check the parameters */
<> 144:ef7eb2e8f9f7 124 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /*------------------------------- RTC/LCD Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 127 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 /* check for RTC Parameters used to output RTCCLK */
<> 144:ef7eb2e8f9f7 130 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<> 144:ef7eb2e8f9f7 131
AnnaBridge 165:e614a9f1c9e2 132 FlagStatus pwrclkchanged = RESET;
AnnaBridge 165:e614a9f1c9e2 133
AnnaBridge 165:e614a9f1c9e2 134 /* As soon as function is called to change RTC clock source, activation of the
AnnaBridge 165:e614a9f1c9e2 135 power domain is done. */
AnnaBridge 165:e614a9f1c9e2 136 /* Requires to enable write access to Backup Domain of necessary */
AnnaBridge 165:e614a9f1c9e2 137 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
AnnaBridge 165:e614a9f1c9e2 138 {
<> 144:ef7eb2e8f9f7 139 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 165:e614a9f1c9e2 140 pwrclkchanged = SET;
AnnaBridge 165:e614a9f1c9e2 141 }
<> 144:ef7eb2e8f9f7 142
AnnaBridge 165:e614a9f1c9e2 143 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 144 {
AnnaBridge 165:e614a9f1c9e2 145 /* Enable write access to Backup domain */
AnnaBridge 165:e614a9f1c9e2 146 SET_BIT(PWR->CR, PWR_CR_DBP);
AnnaBridge 165:e614a9f1c9e2 147
AnnaBridge 165:e614a9f1c9e2 148 /* Wait for Backup domain Write protection disable */
AnnaBridge 165:e614a9f1c9e2 149 tickstart = HAL_GetTick();
AnnaBridge 165:e614a9f1c9e2 150
AnnaBridge 165:e614a9f1c9e2 151 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 152 {
AnnaBridge 165:e614a9f1c9e2 153 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
AnnaBridge 165:e614a9f1c9e2 154 {
AnnaBridge 165:e614a9f1c9e2 155 return HAL_TIMEOUT;
AnnaBridge 165:e614a9f1c9e2 156 }
AnnaBridge 165:e614a9f1c9e2 157 }
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
<> 144:ef7eb2e8f9f7 161 temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
<> 144:ef7eb2e8f9f7 162 if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 /* Store the content of BDCR register before the reset of Backup Domain */
<> 144:ef7eb2e8f9f7 165 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<> 144:ef7eb2e8f9f7 166 /* RTC Clock selection can be changed only if the Backup Domain is reset */
<> 144:ef7eb2e8f9f7 167 __HAL_RCC_BACKUPRESET_FORCE();
<> 144:ef7eb2e8f9f7 168 __HAL_RCC_BACKUPRESET_RELEASE();
<> 144:ef7eb2e8f9f7 169 /* Restore the Content of BDCR register */
<> 144:ef7eb2e8f9f7 170 RCC->BDCR = temp_reg;
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Wait for LSERDY if LSE was enabled */
<> 144:ef7eb2e8f9f7 173 if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
<> 144:ef7eb2e8f9f7 174 {
AnnaBridge 165:e614a9f1c9e2 175 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 176 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 179 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
AnnaBridge 165:e614a9f1c9e2 189
AnnaBridge 165:e614a9f1c9e2 190 /* Require to disable power clock if necessary */
AnnaBridge 165:e614a9f1c9e2 191 if(pwrclkchanged == SET)
AnnaBridge 165:e614a9f1c9e2 192 {
AnnaBridge 165:e614a9f1c9e2 193 __HAL_RCC_PWR_CLK_DISABLE();
AnnaBridge 165:e614a9f1c9e2 194 }
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /*------------------------------ ADC clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 198 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 /* Check the parameters */
<> 144:ef7eb2e8f9f7 201 assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Configure the ADC clock source */
<> 144:ef7eb2e8f9f7 204 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 208 /*------------------------------ I2S2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 209 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 /* Check the parameters */
<> 144:ef7eb2e8f9f7 212 assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Configure the I2S2 clock source */
<> 144:ef7eb2e8f9f7 215 __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /*------------------------------ I2S3 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 219 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Check the parameters */
<> 144:ef7eb2e8f9f7 222 assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Configure the I2S3 clock source */
<> 144:ef7eb2e8f9f7 225 __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /*------------------------------ PLL I2S Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 229 /* Check that PLLI2S need to be enabled */
<> 144:ef7eb2e8f9f7 230 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Update flag to indicate that PLL I2S should be active */
<> 144:ef7eb2e8f9f7 233 pllactive = 1;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Check if PLL I2S need to be enabled */
<> 144:ef7eb2e8f9f7 237 if (pllactive == 1)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 /* Enable PLL I2S only if not active */
<> 144:ef7eb2e8f9f7 240 if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 /* Check the parameters */
<> 144:ef7eb2e8f9f7 243 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
<> 144:ef7eb2e8f9f7 244 assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Prediv2 can be written only when the PLL2 is disabled. */
<> 144:ef7eb2e8f9f7 247 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 248 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
<> 144:ef7eb2e8f9f7 249 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 255 __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Configure the main PLLI2S multiplication factors. */
<> 144:ef7eb2e8f9f7 258 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Enable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 261 __HAL_RCC_PLLI2S_ENABLE();
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 264 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 267 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275 else
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
<> 144:ef7eb2e8f9f7 278 if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 287 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 288 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 289 /*------------------------------ USB clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 290 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 /* Check the parameters */
<> 144:ef7eb2e8f9f7 293 assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Configure the USB clock source */
<> 144:ef7eb2e8f9f7 296 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 return HAL_OK;
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @brief Get the PeriphClkInit according to the internal
<> 144:ef7eb2e8f9f7 305 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 306 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 307 * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
<> 144:ef7eb2e8f9f7 308 * @retval None
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 311 {
AnnaBridge 165:e614a9f1c9e2 312 uint32_t srcclk = 0U;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Set all possible values for the extended clock type parameter------------*/
<> 144:ef7eb2e8f9f7 315 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Get the RTC configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 318 srcclk = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 319 /* Source clock is LSE or LSI*/
<> 144:ef7eb2e8f9f7 320 PeriphClkInit->RTCClockSelection = srcclk;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Get the ADC clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 323 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
<> 144:ef7eb2e8f9f7 324 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 327 /* Get the I2S2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 328 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
<> 144:ef7eb2e8f9f7 329 PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Get the I2S3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 332 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
<> 144:ef7eb2e8f9f7 333 PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 338 /* Get the I2S2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 339 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
<> 144:ef7eb2e8f9f7 340 PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Get the I2S3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 343 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
<> 144:ef7eb2e8f9f7 344 PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 349 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 350 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 351 /* Get the USB clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 352 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
<> 144:ef7eb2e8f9f7 353 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 354 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief Returns the peripheral clock frequency
<> 144:ef7eb2e8f9f7 359 * @note Returns 0 if peripheral clock is unknown
<> 144:ef7eb2e8f9f7 360 * @param PeriphClk Peripheral clock identifier
<> 144:ef7eb2e8f9f7 361 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 362 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
<> 144:ef7eb2e8f9f7 363 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
<> 144:ef7eb2e8f9f7 364 @if STM32F103xE
<> 144:ef7eb2e8f9f7 365 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 366 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 367 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 368 @endif
<> 144:ef7eb2e8f9f7 369 @if STM32F103xG
<> 144:ef7eb2e8f9f7 370 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 371 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 372 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 373 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 374 @endif
<> 144:ef7eb2e8f9f7 375 @if STM32F105xC
<> 144:ef7eb2e8f9f7 376 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 377 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 378 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 379 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 380 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 381 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 382 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 383 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 384 @endif
<> 144:ef7eb2e8f9f7 385 @if STM32F107xC
<> 144:ef7eb2e8f9f7 386 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 387 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 388 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 389 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 390 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 391 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 392 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 393 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 394 @endif
<> 144:ef7eb2e8f9f7 395 @if STM32F102xx
<> 144:ef7eb2e8f9f7 396 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 397 @endif
<> 144:ef7eb2e8f9f7 398 @if STM32F103xx
<> 144:ef7eb2e8f9f7 399 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 400 @endif
<> 144:ef7eb2e8f9f7 401 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 #if defined(STM32F105xC) || defined(STM32F107xC)
AnnaBridge 165:e614a9f1c9e2 406 const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
AnnaBridge 165:e614a9f1c9e2 407 const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
AnnaBridge 165:e614a9f1c9e2 408
AnnaBridge 165:e614a9f1c9e2 409 uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
AnnaBridge 165:e614a9f1c9e2 410 uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
<> 144:ef7eb2e8f9f7 411 #endif /* STM32F105xC || STM32F107xC */
AnnaBridge 165:e614a9f1c9e2 412 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
AnnaBridge 165:e614a9f1c9e2 413 defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
AnnaBridge 165:e614a9f1c9e2 414 const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
AnnaBridge 165:e614a9f1c9e2 415 const uint8_t aPredivFactorTable[2] = {1, 2};
AnnaBridge 165:e614a9f1c9e2 416
AnnaBridge 165:e614a9f1c9e2 417 uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
AnnaBridge 165:e614a9f1c9e2 418 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
AnnaBridge 165:e614a9f1c9e2 419 uint32_t temp_reg = 0U, frequency = 0U;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Check the parameters */
<> 144:ef7eb2e8f9f7 422 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 switch (PeriphClk)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 427 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 428 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 429 case RCC_PERIPHCLK_USB:
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 /* Get RCC configuration ------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 432 temp_reg = RCC->CFGR;
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* Check if PLL is enabled */
<> 144:ef7eb2e8f9f7 435 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
<> 144:ef7eb2e8f9f7 436 {
AnnaBridge 165:e614a9f1c9e2 437 pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
<> 144:ef7eb2e8f9f7 438 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
<> 144:ef7eb2e8f9f7 441 || defined(STM32F100xE)
AnnaBridge 165:e614a9f1c9e2 442 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
<> 144:ef7eb2e8f9f7 443 #else
AnnaBridge 165:e614a9f1c9e2 444 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
<> 144:ef7eb2e8f9f7 445 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 448 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 /* PLL2 selected as Prediv1 source */
<> 144:ef7eb2e8f9f7 451 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
AnnaBridge 165:e614a9f1c9e2 452 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
AnnaBridge 165:e614a9f1c9e2 453 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
<> 144:ef7eb2e8f9f7 454 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456 else
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 459 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
<> 144:ef7eb2e8f9f7 463 /* In this case need to divide pllclk by 2 */
AnnaBridge 165:e614a9f1c9e2 464 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 pllclk = pllclk / 2;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468 #else
<> 144:ef7eb2e8f9f7 469 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 472 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476 else
<> 144:ef7eb2e8f9f7 477 {
<> 144:ef7eb2e8f9f7 478 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<> 144:ef7eb2e8f9f7 479 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Calcul of the USB frequency*/
<> 144:ef7eb2e8f9f7 483 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 484 /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
<> 144:ef7eb2e8f9f7 485 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 /* Prescaler of 2 selected for USB */
<> 144:ef7eb2e8f9f7 488 frequency = pllclk;
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490 else
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 /* Prescaler of 3 selected for USB */
<> 144:ef7eb2e8f9f7 493 frequency = (2 * pllclk) / 3;
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 #else
<> 144:ef7eb2e8f9f7 496 /* USBCLK = PLLCLK / USB prescaler */
<> 144:ef7eb2e8f9f7 497 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* No prescaler selected for USB */
<> 144:ef7eb2e8f9f7 500 frequency = pllclk;
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502 else
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 /* Prescaler of 1.5 selected for USB */
<> 144:ef7eb2e8f9f7 505 frequency = (pllclk * 2) / 3;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507 #endif
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509 break;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
AnnaBridge 165:e614a9f1c9e2 512 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 513 case RCC_PERIPHCLK_I2S2:
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 516 /* SYSCLK used as source clock for I2S2 */
<> 144:ef7eb2e8f9f7 517 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 518 #else
<> 144:ef7eb2e8f9f7 519 if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 /* SYSCLK used as source clock for I2S2 */
<> 144:ef7eb2e8f9f7 522 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524 else
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 /* Check if PLLI2S is enabled */
<> 144:ef7eb2e8f9f7 527 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
AnnaBridge 165:e614a9f1c9e2 530 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
AnnaBridge 165:e614a9f1c9e2 531 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
<> 144:ef7eb2e8f9f7 532 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 536 break;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 case RCC_PERIPHCLK_I2S3:
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 541 /* SYSCLK used as source clock for I2S3 */
<> 144:ef7eb2e8f9f7 542 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 543 #else
<> 144:ef7eb2e8f9f7 544 if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 /* SYSCLK used as source clock for I2S3 */
<> 144:ef7eb2e8f9f7 547 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549 else
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 /* Check if PLLI2S is enabled */
<> 144:ef7eb2e8f9f7 552 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
AnnaBridge 165:e614a9f1c9e2 555 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
AnnaBridge 165:e614a9f1c9e2 556 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
<> 144:ef7eb2e8f9f7 557 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 561 break;
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 564 case RCC_PERIPHCLK_RTC:
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 /* Get RCC BDCR configuration ------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 567 temp_reg = RCC->BDCR;
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Check if LSE is ready if RTC clock selection is LSE */
<> 144:ef7eb2e8f9f7 570 if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 /* Check if LSI is ready if RTC clock selection is LSI */
<> 144:ef7eb2e8f9f7 575 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
<> 144:ef7eb2e8f9f7 580 {
AnnaBridge 165:e614a9f1c9e2 581 frequency = HSE_VALUE / 128U;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 /* Clock not enabled for RTC*/
<> 144:ef7eb2e8f9f7 584 else
<> 144:ef7eb2e8f9f7 585 {
AnnaBridge 165:e614a9f1c9e2 586 frequency = 0U;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588 break;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 case RCC_PERIPHCLK_ADC:
<> 144:ef7eb2e8f9f7 591 {
AnnaBridge 165:e614a9f1c9e2 592 frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
<> 144:ef7eb2e8f9f7 593 break;
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595 default:
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597 break;
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600 return(frequency);
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @}
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 608 /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
AnnaBridge 165:e614a9f1c9e2 609 * @brief PLLI2S Management functions
AnnaBridge 165:e614a9f1c9e2 610 *
<> 144:ef7eb2e8f9f7 611 @verbatim
<> 144:ef7eb2e8f9f7 612 ===============================================================================
<> 144:ef7eb2e8f9f7 613 ##### Extended PLLI2S Management functions #####
<> 144:ef7eb2e8f9f7 614 ===============================================================================
<> 144:ef7eb2e8f9f7 615 [..]
<> 144:ef7eb2e8f9f7 616 This subsection provides a set of functions allowing to control the PLLI2S
<> 144:ef7eb2e8f9f7 617 activation or deactivation
<> 144:ef7eb2e8f9f7 618 @endverbatim
<> 144:ef7eb2e8f9f7 619 * @{
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /**
<> 144:ef7eb2e8f9f7 623 * @brief Enable PLLI2S
<> 144:ef7eb2e8f9f7 624 * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
<> 144:ef7eb2e8f9f7 625 * contains the configuration information for the PLLI2S
<> 144:ef7eb2e8f9f7 626 * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
<> 144:ef7eb2e8f9f7 627 * @retval HAL status
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
<> 144:ef7eb2e8f9f7 630 {
AnnaBridge 165:e614a9f1c9e2 631 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
<> 144:ef7eb2e8f9f7 634 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 /* Check the parameters */
<> 144:ef7eb2e8f9f7 637 assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
<> 144:ef7eb2e8f9f7 638 assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Prediv2 can be written only when the PLL2 is disabled. */
<> 144:ef7eb2e8f9f7 641 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 642 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
<> 144:ef7eb2e8f9f7 643 (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Disable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 649 __HAL_RCC_PLLI2S_DISABLE();
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 652 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 655 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 664 __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Configure the main PLLI2S multiplication factors. */
<> 144:ef7eb2e8f9f7 668 __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Enable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 671 __HAL_RCC_PLLI2S_ENABLE();
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 674 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 677 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685 else
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
<> 144:ef7eb2e8f9f7 688 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 return HAL_OK;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @brief Disable PLLI2S
<> 144:ef7eb2e8f9f7 696 * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
<> 144:ef7eb2e8f9f7 697 * @retval HAL status
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
<> 144:ef7eb2e8f9f7 700 {
AnnaBridge 165:e614a9f1c9e2 701 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Disable PLL I2S as not requested by I2S2 or I2S3*/
<> 144:ef7eb2e8f9f7 704 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 /* Disable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 707 __HAL_RCC_PLLI2S_DISABLE();
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 710 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 713 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 else
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
<> 144:ef7eb2e8f9f7 724 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 return HAL_OK;
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /**
<> 144:ef7eb2e8f9f7 731 * @}
<> 144:ef7eb2e8f9f7 732 */
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
AnnaBridge 165:e614a9f1c9e2 735 * @brief PLL2 Management functions
AnnaBridge 165:e614a9f1c9e2 736 *
<> 144:ef7eb2e8f9f7 737 @verbatim
<> 144:ef7eb2e8f9f7 738 ===============================================================================
<> 144:ef7eb2e8f9f7 739 ##### Extended PLL2 Management functions #####
<> 144:ef7eb2e8f9f7 740 ===============================================================================
<> 144:ef7eb2e8f9f7 741 [..]
<> 144:ef7eb2e8f9f7 742 This subsection provides a set of functions allowing to control the PLL2
<> 144:ef7eb2e8f9f7 743 activation or deactivation
<> 144:ef7eb2e8f9f7 744 @endverbatim
<> 144:ef7eb2e8f9f7 745 * @{
<> 144:ef7eb2e8f9f7 746 */
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /**
<> 144:ef7eb2e8f9f7 749 * @brief Enable PLL2
<> 144:ef7eb2e8f9f7 750 * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
<> 144:ef7eb2e8f9f7 751 * contains the configuration information for the PLL2
<> 144:ef7eb2e8f9f7 752 * @note The PLL2 configuration not modified if used indirectly as system clock.
<> 144:ef7eb2e8f9f7 753 * @retval HAL status
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
<> 144:ef7eb2e8f9f7 756 {
AnnaBridge 165:e614a9f1c9e2 757 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
<> 144:ef7eb2e8f9f7 760 clock (i.e. it is used as PLL clock entry that is used as system clock). */
<> 144:ef7eb2e8f9f7 761 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
<> 144:ef7eb2e8f9f7 762 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
<> 144:ef7eb2e8f9f7 763 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 766 }
<> 144:ef7eb2e8f9f7 767 else
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 /* Check the parameters */
<> 144:ef7eb2e8f9f7 770 assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
<> 144:ef7eb2e8f9f7 771 assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Prediv2 can be written only when the PLLI2S is disabled. */
<> 144:ef7eb2e8f9f7 774 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 775 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
<> 144:ef7eb2e8f9f7 776 (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 777 {
<> 144:ef7eb2e8f9f7 778 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 782 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 785 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 788 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 797 __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Configure the main PLL2 multiplication factors. */
<> 144:ef7eb2e8f9f7 800 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Enable the main PLL2. */
<> 144:ef7eb2e8f9f7 803 __HAL_RCC_PLL2_ENABLE();
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 806 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Wait till PLL2 is ready */
<> 144:ef7eb2e8f9f7 809 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 return HAL_OK;
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /**
<> 144:ef7eb2e8f9f7 822 * @brief Disable PLL2
<> 144:ef7eb2e8f9f7 823 * @note PLL2 is not disabled if used indirectly as system clock.
<> 144:ef7eb2e8f9f7 824 * @retval HAL status
<> 144:ef7eb2e8f9f7 825 */
<> 144:ef7eb2e8f9f7 826 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
<> 144:ef7eb2e8f9f7 827 {
AnnaBridge 165:e614a9f1c9e2 828 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
<> 144:ef7eb2e8f9f7 831 clock (i.e. it is used as PLL clock entry that is used as system clock). */
<> 144:ef7eb2e8f9f7 832 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
<> 144:ef7eb2e8f9f7 833 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
<> 144:ef7eb2e8f9f7 834 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 else
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 841 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 844 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 847 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 return HAL_OK;
<> 144:ef7eb2e8f9f7 857 }
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /**
<> 144:ef7eb2e8f9f7 860 * @}
<> 144:ef7eb2e8f9f7 861 */
<> 144:ef7eb2e8f9f7 862 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /**
<> 144:ef7eb2e8f9f7 865 * @}
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /**
<> 144:ef7eb2e8f9f7 869 * @}
<> 144:ef7eb2e8f9f7 870 */
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /**
<> 144:ef7eb2e8f9f7 875 * @}
<> 144:ef7eb2e8f9f7 876 */
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 879